Benutzeranleitung / Produktwartung OPL3-SA3 des Produzenten Yamaha
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YMF715E OPL3-SA3 OPL3 Single-chip Audio System 3 YAMAHA CORPORAT ION May 21, 1997 Preliminary ■ ■ ■ ■ OUTLINE YMF715E-S (OPL3-SA 3) is a sin gle au dio chip that.
YMF715E May 21, 1997 -2- ■ ■ ■ ■ PIN CONFIGURATION YMF715E-S 100 pin SQ FP Top View 100 99 98 .
YMF715E May 21, 1997 -3- ■ PIN DESCRIPTION ISA bus interface: 36 p ins name p ins I/O t yp e Size function D7-0 8.
YMF715E May 21, 1997 -4- Multi- p ur p ose p ins : 13 p ins name p ins I/O t yp e size function SEL2-0 3 I+ CMOS - .
YMF715E May 21, 1997 -5- ■ ■ ■ ■ BLOCK DIAGRAM.
YMF715E May 21, 1997 -6- ■ ■ ■ ■ FUNCTION OVERVIEW 1. Multi -purpose pin 1-1. Multi -purpose function OPL3-S A3 can su pport the variou s fun ctions lis ted below by program min g SEL2- 0 pins.
YMF715E May 21, 1997 -7- 1-2. Pin descri ption SEL=0 SEL=1 SEL=2 SEL=3 SEL=4 SEL=5 SEL=6 SEL=7 MP0 .
YMF715E May 21, 1997 -8- 1-3. System Block D iagram (1) SEL=1 ( Sound Card and Co mbo Card Add-in) 1. Extern al PAL(16V8 etc.
YMF715E May 21, 1997 -9- 2. Master Clock Both 33.8688MHz and 24.576MHz are used or 14.31818MHz and clock m odule (ex.MK1420 by Micro Clock) are u sed. 3. O PL4 -ML/M L2 The external DAC (YAC516) is necess ary for w avetable upgrade.
YMF715E May 21, 1997 -10- (3) SEL=3 ( Sound Card fo r Add- in) 1. 16bit Address Decode The sig nal AEN* gen erated by decoding SA 15-12 and A EN needs to be connected to th e AEN of OPL 3-SA3.
YMF715E May 21, 1997 -11- (4) SEL=4 ( for No teboo k PC) 1. 16bit Addres s Decode The sig nal AEN* gen erated by decoding SA 15-12 and A EN needs to be connected to th e AEN of OPL 3-SA3.
YMF715E May 21, 1997 -12- (5) SEL=5 ( for No teboo k PC) 1. Internal DA C The internal OPL3 and the ZV Port shares the internal DAC, w hich is very similar to the case mentioned the previous sectio n.
YMF715E May 21, 1997 -13- (6) SEL=7 ( for No teboo k PC, Desktop PC) AEN RESET DRV YMF715E-S (OPL3-SA3) / IOW , / I.
YMF715E May 21, 1997 -14- 2. ISA Interface OPL3-S A3 su pports ISA Plu g and Pl ay (PnP) th at frees th e users f rom con figuri ng the I/ O address, IRQ and DMA channel.
YMF715E May 21, 1997 -15- 2-2. PnP ISA Configur ation Register OPL3 -SA3 has the following Register s define d in the P nP I SA software.
YMF715E May 21, 1997 -16- Logical Device Num ber = 0 : SA3 Sound System 30h R/W Activate 60h R/W I/O port base address[15..8], Descriptor 0 (SB base) 61h R/W I/O port base address[7.
YMF715E May 21, 1997 -17- Logical Device Num ber = 3 : CD-RO M (Optional) 30h R/W Activate 60h R/W I/O port base address [15..8], Descriptor 0 (/CDCS0) 61h R/W I/O port base address [7.
YMF715E May 21, 1997 -18- IRQ-A : high-active, edg e-sense Index Best Acceptable1 Acceptable2 Acceptable3 IRQ 10 7,.
YMF715E May 21, 1997 -19- (4) LDN=3:CD-ROM I/O (/CDC S0): 16bit address decode Index Best Acceptabl.
YMF715E May 21, 1997 -20- 3. Download Resour ce data When OPL3-SA 3 is in the Configuration state, the host can download th e resources data to EEP R OM and internal SRAM via 2 0h: Resource Data W rite.
YMF715E May 21, 1997 -21- 6. DAC interface OPL3-SA 3 supports two ty pes of DAC in terface format. On e is the conventional DA C interface form at (very comm on for the cons umer audio produ ct) for OPL4-ML/ML 2.
YMF715E May 21, 1997 -22- 8. Power Managem ent Following 4 functionalities are provided for APM(Advanced Po wer Management) com pliance. (1) Partial Power Dow n Mode (2) Power S ave Mode (3) Global Power Dow n Mode (4) Suspen d/Resum e Mode F ig.
YMF715E May 21, 1997 -23- 8-1. Partia l Power Down Mo de Functional blo cks co mprising OPL3-SA3 which are shown in Fig.8-1, are designed so they can be disabled independent of each other.
YMF715E May 21, 1997 -24- 8-4. Suspend/Resume M ode There is no “read only ” or “h idden state” registers in OPL3-SA 3.
YMF715E May 21, 1997 -25- 9. Register descr iption 9-1. SA Sound System 9-1-1. OPL3 Listed below are the OPL3-L register for AdLib com patib ility.
YMF715E May 21, 1997 -26- OPL3 Data Register Array 1 (R/W) Index D7 D 6 D5 D4 D3 D2 D1 D0 00 - 01h LSI TEST 04h - -.
YMF715E May 21, 1997 -27- 9-1-2-1. DSP Command List ed below are the su pported comm ands of DSP defin ed Sound Blaster Pro com patibility.
YMF715E May 21, 1997 -28- 9-1-2-2. Sound Blas ter Pro c ompatibility Mixer The table belo w is the register map of m ixer of Sound B laster Pro co mpatibility. Index D7 D 6 D5 D4 D3 D2 D1 D0 00h Reset Mixer 04h Voice Vol.
YMF715E May 21, 1997 -29- MIDI Vol. ( 26h ) 0123456 7 0 mut e mute mu te mute mut e mute mu te mute 1 mut e -24.0dB -18.0dB -12. 0dB -6.0dB -3.0dB +1.5dB +4.5dB 2 mut e -18.
YMF715E May 21, 1997 -30- 9-1-3. WSS com patible 16-bit CODEC The followings are the I/Os for Window Sound System compatibility.
YMF715E May 21, 1997 -31- WSS CODEC Indirect Reg isters (R/W) : Index D7 D 6 D5 D4 D3 D2 D1 D0 00h LSS1 LSS0 LMGE -.
YMF715E May 21, 1997 -32- Mixer d efault: 02h:A UX1L = 88h (m ute) 03h:A UX1R = 88h (m ute) 04h:A UX2L = 05h (+4.
YMF715E May 21, 1997 -33- Notice) 1) Set D7, D6, D4 and D3 bits to “0”.
YMF715E May 21, 1997 -34- Interrupt Channel configuration (R/W): Index D7 D 6 D5 D4 D3 D2 D1 D0 IRQ-B IRQ-A OPL3 MP.
YMF715E May 21, 1997 -35- Interrupt (IRQ-B) sta tus (RO): Index D7 D 6 D5 D4 D3 D2 D1 D0 05h - MV OPL3 MPU SB TI CI PI This register is the status register that indicates w hich is the interrupt source o f IRQB.
YMF715E May 21, 1997 -36- Master Volume Lch (R/W): Index D7 D 6 D5 D4 D3 D2 D1 D0 07h MVLM - - - MVL3 MVL2 M VL1 MVL0 This register specifies the m aster volum e of left channel.
YMF715E May 21, 1997 -37- Miscellaneous: Index D7 D 6 D5 D4 D3 D2 D1 D0 0Ah VEN - - MCSW MODE VER2 VER1 VER0 VEN... T his bit enables the hardware volume control. Default is VEN=“1”.
YMF715E May 21, 1997 -38- Sound Blaster compatibility Internal State Scan out/in (R/W): Index D7 D 6 D5 D4 D3 D2 D1 D0 10h SBPDA - - - SS SM SE SBPDR SBP DA.
YMF715E May 21, 1997 -39- i) Scan Out SBPDA=0 SBPDR=1 SBPDA=1 SM=1 SS=1 SE=1 → 0 : not r eady for scanning intern.
YMF715E May 21, 1997 -40- Digital Block Partial Power Down (R/W): Index D7 D 6 D5 D4 D3 D2 D1 D0 12h JOY MPU MCLKO FM WSS_R WSS_P SB PnP This register specifies the partial power m anagement of the digital portion.
YMF715E May 21, 1997 -41- Notice) In the partial power down mode, master volume is not m uted, so all analog input sources and enabled digital sources (i.e. FM, SB, WSS etc.
YMF715E May 21, 1997 -42- Hardware Volume Interr upt Channel Configuration (R/W): Index D7 D 6 D5 D4 D3 D2 D1 D0 17h - - IR Q-B MV IRQ-A MV -* * * The Hardware Volume can source interrupt.
YMF715E May 21, 1997 -43- 9-4. CD-ROM The follow ing pins are f or IDE CD-ROM interface w ith PnP supported. /CDCS0... chip select for CD-ROM /CDCS1... chip select for CD-ROM CDIRQ.
YMF715E May 21, 1997 -44- ■ ■ ■ ■ Electrical Characteristics Absolute Maximum Ratin g s .
YMF715E May 21, 1997 -45- Note : DV SS =AV SS =0[V], T OP =0~70 ℃ , AV DD =5.0[V] *1 : A pp licab le to s chmitt input pins w ithout /VOLUP, /VOLDW. *2 : Applicable to /VOLUP and /VOLDW pins.
YMF715E May 21, 1997 -46- AC Character istics CPU Interface & DMA BUS Cycle :Fig.1,2,3,4,5,6,7,8 Note : DV SS =AV SS =0[V], T OP =0~70 ℃ , DV DD =5.0 ± 0.25[V] or 3.
YMF715E May 21, 1997 -47- Miscellaneous Note : DV SS =AV SS =0[V], T OP =0~70 ℃ Duty Search Point is 1/2 DV DD . *... DV DD = 5.0 ± 0.25[V] or 3.3V ± 0.30[V], AV DD = 5.
YMF715E May 21, 1997 -48- F ig.2 I/ O Re ad Cy c l e Valid Valid D7-0 /DACK3,1,0 (A15-12) A11-0 /I OR t AKH t AKS t RDH t ACC t RW t AH t AS F ig.
YMF715E May 21, 1997 -49- F ig.4 Valid 8b it M on o & ADP C M DM A R ea d C ycle D7-0 DRQ3,1,0 /DACK3,1,0 /I OR t DGH t RDH t ACC t RW t HR t SF F ig.
YMF715E May 21, 1997 -50- F ig.6 16b i t S t er eo DM A C ycle DRQ3,1,0 Righ t/ Low Byte L eft/Hig h Byte D7-0 /I O.
YMF715E May 21, 1997 -51- S e ri a l A u d i o I n t e rf a c e L RCK SI N BCLK t LRH t DH t DS 1/f BCK F ig.
YMF715E May 21, 1997 -52- Analog Character istics Analog Input Characteristics Note : DV SS =AV SS =0[V], T OP =25 ℃ , DV DD =AV DD =5.0[V], fs =44.1kHz Analog Output Characteristics Note : DV SS =AV SS =0[V], T OP =25 ℃ , DV DD =AV DD =5.
YMF715E May 21, 1997 -53- ■ ■ ■ ■ External Di mensions Note : The LSIs for surface m ount need especial consideration on storage and soldering conditions. For detailed inform ation, please contact y our nearest agent of y amah a.
YMF715E May 21, 1997 -54- IMPORTANT NOTICE 1. Yamaha reserv es the r ight to make changes to its Produc ts and to this document without notice. The information contained in this doc ument has been car efully chec k ed and is believ ed to be reliable.
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