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2003.9.18 32 SH7709S Group Hardware Manual Renesas 32-Bit RISC Micr ocomputer SuperH RISC engi ne Family /SH7700 Serie s Rev.5.00 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions.
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Renesas 32-B it RISC M icroc om puter SuperH RISC engine Family/SH7700 Se ries SH7709S Group Hardware Manual REJ09B0081-0500O.
Rev. 5.00, 09/0 3, page iv of x liv Cautions Keep safe ty first i n y our circuit des igns! 1. Rene sas T echno log y Corp . p uts t he maxi mum e ffo rt in to mak ing s emic onduc tor product s better and more reliable, but there is always the po ssibility that tr ouble may occur with them.
Rev. 5.00, 09/0 3, page v of xliv General Precautions on Handling o f Product 1. Treatm ent of NC Pins Note: Do not connect an ything to the NC pins. The NC (not con nected) pins are either not con nected to any of the internal circuitry or are used as test pins or to redu ce noise.
Rev. 5.00, 09/0 3, page v i of x liv Configuration of This Manual This manual comprises the f ollo wing items: 1. Gen eral Precaution s on Han dling of Product 2.
Rev. 5.00, 09/0 3, page v ii of x liv Preface This LSI is a microprocessor wi th the 32- bit SH-3 CPU as its core and periphera l functions necessary for conf iguring a u ser system.
Rev. 5.00, 09/0 3, page v iii of xliv • User manuals for develo p ment tools Name of Document Document No. C/C++ Compiler, As sem bler, O pti miz ing Lin kag e Editor User’s M anual ADE-702-246 Si.
Rev. 5.0, 0 9/03, pag e ix of x liv List of Item s Revised or Added for This Version Section Page Description 1.2 Bl ock Diag r am Figure 1.1 Block Diagram 6 ASERAM deleted from figure BRIDGE External bus interface UDI INTC CPG/WDT I bus 2 ASERAM deleted from legend 2.
Rev. 5.0, 0 9/03, pag e x of x liv Section Page Description 5.4.3 Examples of Usage 115, 116 (1) Invalidati ng a Spe cific Entry Descripti on amended A s pecific ca che entry can be inva lidate d by accessi ng the allocated mem ory cac he an d writing a 0 to the ent ry’s U and V bit s .
Rev. 5.0, 0 9/03, pag e xi of x liv Section Page Description 8.3.3 Precaution s when Using t he Sleep Mode 187 Newley added 8.5.1 Transit ion to Module Standby Function 191 Note * 3 added to bit table Note: 3. Before putting t he RTC into module sta ndby status, first access on e or more of the RTC, SCI, and TMU registers.
Rev. 5.0, 0 9/03, pag e xii of x liv Section Page Description 10.2.13 MCS0 Control Register ( MCSCR0) 258 Descripti on added Bit 6—CS2/CS0 S elect (CS2/0) Only 0 sho uld be used for the C S2/0 bit i n MCSCR0. Either 0 or 1 may be u sed for MC SCR1 to MC SCR7.
Rev. 5.0, 0 9/03, pag e xiii of x liv Section Page Description 16.4 SCIF I nterr upts 550 Descripti on amended W hen the TDFE flag i n the serial s tatus register (SCSSR) is set to 1, a TX I interrupt requ est is gen erated. The D MAC can be activated a nd data transfer perfor med when this interrupt is generated.
Rev. 5.0, 0 9/03, pag e xiv of xliv Section Page Description 20.3 Bus Maste r Interface Figure 20.2 A/D Data Register Acce ss Operation (Read ing H'AA40) 622 Figure amend ed Bus interface TEMP [H.
Rev. 5.0, 0 9/03, pag e xv of xliv Section Page Description 23.3.6 Synch r onous DRAM Timing Figure 23.31 Synchronous D RAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Laten cy = 2) 690 Tnop.
Rev. 5.0, 0 9/03, pag e xv i of xliv Section Page Description Function inf orma tion amended for V CC –RTC, V CC –PLL1, V CC – PLL2, and V CC Pin Pin No. (FP-208C, FP-208E) Pin No. (BP- 240A) I/O Function V CC – RTC 3 E2 Pow er supply RT C oscillator p ower supply (2.
Rev. 5.00, 09/0 3, page xv ii of xliv Contents Section 1 Overview and Pin Functions .......................................................................... 1 1.1 SH7709S Feat ure s ...................................................................
Rev. 5.00, 09/0 3, page xv iii of xliv 3.4 MMU Functions ............................................................................................................... .6 9 3.4 .1 M MU Ha rd ware Ma nagemen t .........................................
Rev. 5.00, 09/0 3, page xix of xliv 5.1.2 Cache Structure .................................................................................................... 103 5.1.3 Register Conf i guration .........................................................
Rev. 5.00, 09/0 3, page xx of xliv Section 7 User Break Controller ...................................................................................... 149 7.1 Overview ................................................................................
Rev. 5.00, 09/0 3, page xx i of xliv 8.4.1 Transition to Standby Mode ................................................................................. 188 8.4.2 Canceling Standby Mode ..................................................................
Rev. 5.00, 09/0 3, page xx ii of xliv Section 10 Bus State Cont roller (BSC ) ......................................................................... 223 10.1 Overview .................................................................................
Rev. 5.00, 09/0 3, page xx iii of xliv 11.1.1 Features ................................................................................................................ 3 27 11.1.2 Block Diagram .........................................................
Rev. 5.00, 09/0 3, page xx iv of xliv 12.3 TMU Operation .............................................................................................................. ... 400 12.3.1 General Operation ..................................................
Rev. 5.00, 09/0 3, page xx v of xliv 13.4.3 Precautions w hen Using RTC Module Stan dby ................................................... 426 Section 14 Serial Communication I nterface (SC I) ..................................................... 427 14.
Rev. 5.00, 09/0 3, page xx vi of xliv 15.4.1 Receive Data Timing and Receive Margin in Asynchron ous Mode .................... 507 15.4.2 Retransmission (R eceive and Transmit Modes) ................................................... 509 Section 16 Serial Communication I nterface with F IFO (SCIF) .
Rev. 5.00, 09/0 3, page xx vii of xliv 18.3.1 Port A Cont rol Register (PACR) .......................................................................... 570 18.3.2 Port B Control Regist er (PBCR) .......................................................
Rev. 5.00, 09/0 3, page xx viii of xliv 19.11.1 Register Des cription ............................................................................................. 605 19.11.2 Port K Data Register (PKDR) ...............................................
Rev. 5.00, 09/0 3, page xx ix of xliv Section 22 User Debugging Interface (UD I) ............................................................... 641 22.1 Overview ........................................................................................
Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxx of xl i v A.3 T reatment of Unused Pins ................................................................................................. 724 A.4 Pin States in Access to Each Address Space ........................
Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxi o f xl iv Figu res Figure 1.1 Block Diagram ..................................................................................................... 6 Figure 1.2 Pin As signment (FP-208C, FP-208E) ..................
Rev. 5.00, 09/0 3, page xx xii of x liv Figure 8.3 Manual Reset STATUS Output ............................................................................ 193 Figure 8.4 Standby to Interru pt ST ATUS Output ............................................
Rev. 5.00, 09/0 3, page xx xiii of x liv Figure 10.28 Synchron ous DRAM Mode Write Timing ........................................................... 303 Figure 10.29 Burst RO M Wait Access Timing ......................................................
Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxiv of xl i v Figure 11.23 Tim ing Chart o f Sou rce Address Reload Function............................................... 373 Figure 11.24 Block Diag ram of CMT ....................................................
Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxv o f xl i v Figure 14.17 Data Format in Syn chronous Comm unication ..................................................... 474 Figure 14.18 Sample Flowchart for SCI In itialization .................................
Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxvi of xl i v Figure 19.8 Port H .............................................................................................................. ..... 601 Figure 19.9 Port J ..........................................
Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxvi i o f xl i v Figure 23.19 Burst RO M Bus Cycle (No Wait) ........................................................................ 678 Figure 23.20 Burst RO M Bus Cycle (Two Waits) ...............................
Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxvi ii o f xl i v Figure 23.47 TCLK Inpu t Timing ............................................................................................. 707 Figure 23.48 TCLK Clock Input Timing ..............................
Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxix o f xl iv Tables Table 1.1 SH7709S Features .................................................................................................. 2 Table 1.2 Characteristics.........................................
Rev. 5.00, 09/0 3, page xl of x liv Table 8.2 Pin Conf iguration.................................................................................................... 1 83 Table 8.3 Register Conf i guration...............................................
Rev. 5.00, 09/0 3, page xli of x liv Table 13.2 RT C Register s ........................................................................................................ . 410 Table 13.3 Da y-of- Week Codes (RWKC NT) ...................................
Rev. 5.00, 09/0 3, page xlii of x liv Table 19.1 P ort A Reg ister ...................................................................................................... . 587 Table 19.2 Po r t A Data Register (PADR) Read/Write Operations ............
Rev. 5.00, 09/0 3, page xliii of x liv Table 23.8 P eripheral Module Sig nal Timing ........................................................................... 706 Table 23.9 UDI-Related Pin Timing......................................................
Rev. 5.00, 09/0 3, page xliv of xliv.
Rev. 5.00, 09/0 3, page 1 of 760 Section 1 Overview and Pin Functions 1.1 SH7709S Features This LSI is a single-chip RISC microprocessor that integrates a Renesas Technology-original RISC-t yp e Super.
Rev. 5.00, 09/0 3, page 2 of 760 Table 1.1 SH7709S Featu res Item Features CPU • Origina l Renesas T echnology SuperH archi tecture • Object cod e level w ith SH-1, SH-2, and SH-3 Series • 32-bi.
Rev. 5.00, 09/0 3, page 3 of 760 Item Features Cache memor y • 16-kbyte cache, m ix ed instruction/d ata • 256 entrie s, 4-way set associat ive, 16-byt e block length • Write-bac k, write-thro u.
Rev. 5.00, 09/0 3, page 4 of 760 Item Features Serial communi- cation interf ace 0 (SCI0/SCI) • Asynchronou s mode or cloc k sy nchr onou s mode can be s ele cted • Full-dupl ex communication • .
Rev. 5.00, 09/0 3, page 5 of 760 Table 1.2 Characteristics Item Characteristi cs Power supply voltage • I/O: 3.3 ± 0.3 V Internal: 2.0 ± 0.15 V (200 M Hz model) * , 1.9± 0.15 V (167 MHz model), 1.8 (+0.25, –0.15) V (1 33 MHz model), 1.7(+0 .25, –0.
Rev. 5.00, 09/0 3, page 6 of 760 1.2 Block Diagram MMU TLB SH-3 CPU UBC SCI TMU RTC IrDA SCIF ADC DAC AUD BRIDGE DMAC CMT I/O port External bus interface BSC CCN CACHE UDI INTC CPG/WDT Peripheral bus .
Rev. 5.00, 09/0 3, page 7 of 760 1.3 Pin De scription 1.3.1 Pi n Ass i gnment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44.
Rev. 5.00, 09/0 3, page 8 of 760 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABC DE FG H J K LM N P RTU V W ABC DE FG H J K LM N P RTU V W Note: The pin area enclosed in broken lines is an inner view.
Rev. 5.00, 09/0 3, page 9 of 760 1.3.2 Pi n Functi on Table 1.3 SH7709S Pi n Function Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 1 D2 MD1 I Clock mo de sett ing 2 C2 MD2 I Clock m.
Rev. 5.00, 09/0 3, page 10 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 27 K3 Vss — Pow er supply (0 V) — K4 Vss — Power supply (0 V) 28 K1 D19/PTA[3] I/O Data b u s / input/o utput port A 29 L3 Vcc — Pow er supply (1.
Rev. 5.00, 09/0 3, page 11 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 57 U4 VssQ — Input/output pow er supply (0 V) 58 W5 A4 O Address bus 59 U3 VccQ — Input/output pow er supply (3.
Rev. 5.00, 09/0 3, page 12 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 87 W12 BS /PTK[4] O / I/O Bus cycle start s ignal / input /output port K 88 T13 RD O Read s trobe 89 U.
Rev. 5.00, 09/0 3, page 13 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 106 U18 RAS3L /PTJ[0] O / I/O Lower 32 M / 64 M bytes address (SDRAM) RAS / input/o utput port J 107 U.
Rev. 5.00, 09/0 3, page 14 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 130 L17 AUDATA[3]/PTG[3] I/O / I AUD data / input port G 131 K18 AUDATA[2]/PTG[2] I/O/I AUD data / inp.
Rev. 5.00, 09/0 3, page 15 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description — D19 Vss — Power supply (0 V) 154 E18 Vcc — Power supply ( * 3 ) — C19 Vcc — Power supply (.
Rev. 5.00, 09/0 3, page 16 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 176 A11 CTS2 /IRQ5/SCPT [7] I Transmit cl ear 2 / ex ternal interrupt request / SCI inp ut port 177 B1.
Rev. 5.00, 09/0 3, page 17 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 198 B6 AVss — Analog power supply (0 V) 199 A6 AN[0]/PTL[0] I A/D converter input / input port L 200.
Rev. 5.00, 09/0 3, page 18 of 760.
Rev. 5.00, 09/0 3, page 19 of 760 Section 2 CPU 2.1 Register Configuration 2.1.1 Privileged M ode and B anks Proce ssor M odes: T here are tw o processor modes: user mode and pr ivileged mode. The SH7709S norm all y operates i n user mode, and enters pri v ileged mode when an excepti on occurs or an in terrupt i s accepted.
Rev. 5.00, 09/0 3, page 20 of 760 31 0 R0 _ BANK0 * 1 * 2 R1 _ BANK0 * 2 R2 _ BANK0 * 2 R3 _ BANK0 * 2 R4 _ BANK0 * 2 R5 _ BANK0 * 2 R6 _ BANK0 * 2 R7 _ BANK0 * 2 R8 R9 R10 R1 1 R12 R13 R14 R15 SR GBR MACH MACL PR PC User mode register configuration Notes: 1.
Rev. 5.00, 09/0 3, page 21 of 760 R0_BANK1 * 1 * 2 R1_BANK1 * 2 R2_BANK1 * 2 R3_BANK1 * 2 R4_BANK1 * 2 R5_BANK1 * 2 R6_BANK1 * 2 R7_BANK1 * 2 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR PC SPC GBR MACH MACL PR VBR 31 0 a.
Rev. 5.00, 09/0 3, page 22 of 760 Register v alues after a reset are sh own in table 2.1. Table 2.1 Initial Register Values Type Registers Initial Value * General regi sters R0 to R15 Undefined Contro.
Rev. 5.00, 09/0 3, page 23 of 760 2.1.3 S ystem Registers System re gister s can be accesse d by the LDS and STS i nstructi ons. When an ex ception occurs, t he contents of the program counter (PC) are saved in the saved progr am counter (SPC).
Rev. 5.00, 09/0 3, page 24 of 760 SSR Saved Status Register (SSR) Stores current SR value at time of exception to indicate processor status in return to instruction stream from exception handler. Saved Program Counter (SPC) Stores current PC value at time of exception to indicate return address at completion of exception handling.
Rev. 5.00, 09/0 3, page 25 of 760 2.2 Data Formats 2.2.1 Data Form at in Regi sters Register operan ds are al ways longwords (32 bit s, fig ure 2.6). When a m emory operand is only a byt e (8 bits) or a word (16 bits), it i s sign-extende d into a longword when loaded in to a regis ter.
Rev. 5.00, 09/0 3, page 26 of 760 2.3 Instruction Features 2.3.1 E xecution E nvironment Data Length: T he SH7709S i n struction se t is im plemented with fixed- length 16-bit wide instructions executed in a pipelined s equence with s ingle-cycle executi on for most instructio ns.
Rev. 5.00, 09/0 3, page 27 of 760 T bit: The T bit in the status register (S R) is used to indicate the resu lt of compare operations, and is read as a TRUE/FALSE condition deter mining if a cond itio nal br anch is taken or not. T o improve pro cessin g speed, the T b it logic state is modified only by s p e cific operati ons.
Rev. 5.00, 09/0 3, page 28 of 760 2.3.2 Addressing M odes Address ing modes and effectiv e address calculati on metho ds are shown in table 2.2. Table 2.2 Addressing M odes and Eff ect ive Addresse s Addressing Mode Instruction Format Effective Address C alculation Meth od Calculati on Formula Register di rect Rn Effective address is re gister Rn.
Rev. 5.00, 09/0 3, page 29 of 760 Addressing Mode Instruction Format Effective Address C alculation Meth od Calculati on Formula Register indirect w ith displa cement @(disp:4, Rn) Effective addre ss is register Rn contents w ith 4-bit displace ment disp added .
Rev. 5.00, 09/0 3, page 30 of 760 Addressing Mode Instruction Format Effective Address C alculation Meth od Calculati on Formula PC-relative wit h displa cement @(disp:8, PC) Effective addre ss is regis ter PC cont ents with 8-bit disp lacement disp ad ded.
Rev. 5.00, 09/0 3, page 31 of 760 Addressing Mode Instruction Format Effective Address C alculation Meth od Calculati on Formula PC-relative Rn Effectiv e address is sum of regis ter PC and Rn content s. PC R0 + PC + R0 PC + Rn Immediat e #imm:8 8-bit immed iate data imm of TST , AND, OR , or XOR instruction is zero -extended.
Rev. 5.00, 09/0 3, page 32 of 760 2.3.3 I nstructi on Formats Table 2.3 explains the mean ing of instructio n formats and so urce and des tination operands.
Rev. 5.00, 09/0 3, page 33 of 760 Instruction Format Source Operand Destinatio n Operand Instruction Example nm format nnnn xxxx xxxx 15 0 mmmm mmmm: r egister direct nnnn: regi ster direct ADD Rm,Rn mmmm: r egister indirect nnnn: r egister indirect MOV.
Rev. 5.00, 09/0 3, page 34 of 760 Instruction Format Source Operand Destinatio n Operand Instruction Example nmd format nnnn xxxx dddd 15 0 mmmm mmmm: r egister direct nnnndddd: register indirect w ith displa cement MOV.L Rm,@(disp,Rn) mmmmdddd: register indir ect with dis placement nnnn: regi ster direct MOV.
Rev. 5.00, 09/0 3, page 35 of 760 2.4 Instruction Set 2.4.1 Instruction Set Cla ssified by Function The SH7709S in struct ion set in cludes 68 basic i nstructi on types, a s listed in table 2.4. Table 2.4 Classification of Instructions Classification Ty pes Operation Code Function No.
Rev. 5.00, 09/0 3, page 36 of 760 Classification Ty pes Operation Code Function No. of Instructions 21 MUL Double- prec is ion mul tip lic atio n (32 × 32 bits) 33 Arithmetic operation s (cont) MULS .
Rev. 5.00, 09/0 3, page 37 of 760 Classification Ty pes Operation Code Function No. of Instructions Branch 9 BF Conditional bra nch, delayed con ditional branch (T = 0) 11 BT Conditional branc h, dela.
Rev. 5.00, 09/0 3, page 38 of 760 Table 2.5 lists the SH7709S inst ruction code f ormats. Table 2.5 Instruction Code Fo rmat Item Format Explanation Instructi on mnemonic OP.
Rev. 5.00, 09/0 3, page 39 of 760 Table 2.6 lists the SH 7709S data trans fer inst ructions Table 2.6 Data Transfer Instructions Instruction Operation Code Privile ged Mode C ycles T Bit MOV #imm,Rn imm → Sign exten sion → Rn 1110nnnniiiiiiii —1 — MOV.
Rev. 5.00, 09/0 3, page 40 of 760 Instruction Operation Code Privileged Mode Cy cl es T Bit MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0101 —1 — MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0110 —1 — MOV.B @(R0,Rm),Rn (R0 + Rm) → Sign extension → Rn 0000nnnnmmmm1100 —1 — MOV.
Rev. 5.00, 09/0 3, page 41 of 760 Table 2.7 lists the SH7709S arithm etic instruction s. Table 2.7 Arithmetic Instructions Instruction Operation Code Privileged Mode Cy cl es T Bit ADD Rm,Rn Rn + Rm .
Rev. 5.00, 09/0 3, page 42 of 760 Instructio n Operation Code Pri vileged Mode C ycles T Bit DMULS.L Rm,Rn Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits 0011nnnnmmmm1101 — 2(to 5) * — DMULU.
Rev. 5.00, 09/0 3, page 43 of 760 Instruction Operation Code Privileged Mode Cy cl es T Bit NEG Rm,Rn 0–Rm → Rn 0110nnnnmmmm1011 —1 — NEGC Rm,Rn 0–Rm–T → Rn, Borrow → T 0110nnnnmmmm101.
Rev. 5.00, 09/0 3, page 44 of 760 Table 2.8 lists the SH 7709S logic operat ion in structions. Table 2.8 Logic Operation Instructions Instruction Operation Code Privile ged Mode Cy cl es T Bit AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 —1 — AND #imm,R0 R0 & imm → R0 11001001iiiiiiii —1 — AND.
Rev. 5.00, 09/0 3, page 45 of 760 Table 2.9 lists the S H7709S sh ift inst ructions. Table 2.9 Shift Instr uctions Instruction Operation Code Privileged Mode Cy cles T Bit ROTL Rn T ← Rn ← MSB 010.
Rev. 5.00, 09/0 3, page 46 of 760 Table 2.10 lis ts th e SH7709S branch in structions . Table 2.10 Branch Instructions Instruction Operation Code Privileged Mode C ycles T Bit BF label If T = 0, disp .
Rev. 5.00, 09/0 3, page 47 of 760 Table 2.11 lis ts t he SH7709S sy stem con trol instru ctions. Table 2.11 System Control Instructions Instruction Operation Code Privile ged Mode C ycles T Bit CLRMAC.
Rev. 5.00, 09/0 3, page 48 of 760 Instructio n Operation Code Pri vileged Mode Cy cl es T Bit LDC.L @Rm+, R6_BANK (Rm) → R6_BANK, Rm + 4 → Rm 0100mmmm11100111 √ 5— LDC.
Rev. 5.00, 09/0 3, page 49 of 760 Instruction Operation Code Privile ged Mode C ycles T Bit STC.L SSR,@ – Rn Rn–4 → Rn, SSR → (Rn) 0100nnnn00110011 √ 2— STC.L SPC,@ – Rn Rn–4 → Rn, SPC → (Rn) 0100nnnn01000011 √ 2— STC.L R0_BANK, @ – Rn Rn–4 → Rn, R0_BAN K → (Rn) 0100nnnn10000011 √ 2— STC.
Rev. 5.00, 09/0 3, page 50 of 760 2.4.2 Instruction Code M ap Table 2.12 show s the in struction code map. Table 2.12 Instruction Code Map Inst ruction C ode Fx: 0 000 Fx: 0001 Fx: 0010 Fx: 0 011 to 1.
Rev. 5.00, 09/0 3, page 51 of 760 Inst ruction C ode Fx: 0 000 Fx: 0001 Fx: 0010 Fx: 0 011 to 111 1 MSB LSB MD: 0 0 MD: 01 MD: 10 MD: 11 0100 Rn Fx 0000 SHLL Rn DT Rn SHA L Rn 0100 Rn Fx 0001 SHLR Rn CMP/PZ R n SHAR R n 0100 Rn Fx 00 10 STS.L MACH,@-Rn STS.
Rev. 5.00, 09/0 3, page 52 of 760 Inst ruction C ode Fx: 0 000 Fx: 0001 Fx: 0010 Fx: 0 011 to 111 1 MSB LSB MD: 0 0 MD: 01 MD: 10 MD: 11 1000 00MD Rn disp MOV.
Rev. 5.00, 09/0 3, page 53 of 760 2.5 Processor States and Processor Modes 2.5.1 Proces sor States The SH7709S has fiv e processor states: the reset state, excep ti on-han dling state, bus-release d state, program execution state, and po wer-down state.
Rev. 5.00, 09/0 3, page 54 of 760 From any state when RESETP = 0 From any state but hardware standby mode when RESETM = 0 Note: * The hardware standby mode is entered when the CA pin goes low from any state.
Rev. 5.00, 09/0 3, page 55 of 760 Section 3 Memory Manag ement Uni t (MMU) 3.1 Overview 3.1.1 Features The SH7709S ha s an on -chip memory management uni t (MMU) that implem ents address translation.
Rev. 5.00, 09/0 3, page 56 of 760 case, the MMU will generate a n e xception, change the p hysical memory mapping, and record the new address translation in for matio n.
Rev. 5.00, 09/0 3, page 57 of 760 Process 1 Physical memory MMU (1) (2) (3) (4) Process 1 Physical memory Process 1 Virtual memory MMU Physical memory Process 1 Process 2 Process 3 Physical memory Process 1 Process 2 Process 3 Virtual memory Physical memory Figure 3.
Rev. 5.00, 09/0 3, page 58 of 760 3.1.3 SH7709S MMU Virtual Address Space: T he SH7709S us es 32-bit v i rtual addresses to access a 4- Gbyte virtual address space that is divided into several areas. Address space mapping is shown in f igure 3.2. • Privileged Mode In privileged m od e, t here are fi ve areas, P 0 – P4 .
Rev. 5.00, 09/0 3, page 59 of 760 H'80000000 H'A0000000 H'C0000000 H'E0000000 H'FFFFFFFF 2-Gbyte virtual space, cacheable (write-back/write-through) 2-Gbyte virtual space, cac.
Rev. 5.00, 09/0 3, page 60 of 760 If the virtual address is n ot registered in the TLB, a T LB miss exception occurs an d processing will shift to the TLB miss handler.
Rev. 5.00, 09/0 3, page 61 of 760 3.1.4 Regi ster Configurati on A register that has an u ndefined initial value must be in itialized by software. Table 3.
Rev. 5.00, 09/0 3, page 62 of 760 5. The MMU control register (MMUCR) r esiding at addres s H'FFFFFFE0 , whi ch m akes the MMU settings des cribed in f igure 3.3. Any program that m odif i es MMUCR shoul d reside in the P1 or P2 area. The MMU registers are shown in figure 3.
Rev. 5.00, 09/0 3, page 63 of 760 3.3 TLB Func tions 3.3.1 C on figuration of th e TLB The T LB caches address tran s l ation table information located in the external memory.
Rev. 5.00, 09/0 3, page 64 of 760 31 9 VPN Virtual address (1-kbyte page) Virtual address (4-kbyte page) TLB entry Offs et VPN VPN (31–17) VPN (1 1–10) ASID V PPN D Offs et 0 10 31 1 1 0 (15) (2) (19) (8) SH (1) (1) C PR (2) SZ (1) (1) (1) 12 VPN: Virtual page number.
Rev. 5.00, 09/0 3, page 65 of 760 3.3.2 T LB Indexi ng The TLB uses a 4-way s et associative scheme, so entries must be selected by index. VPN bits 16 to 12 and ASID bits 4 to 0 in P TEH a re us e d as the index nu mb er reg ardl ess of the p age si ze.
Rev. 5.00, 09/0 3, page 66 of 760 31 16 11 12 17 0 Virtual address Ways 0 − 3 VPN(31 − 17) VPN(11 − 10) ASID(7 − 0) V 0 Address array Data array PPN(28 − 10) PR(1 − 0) SZ C D SH Index 31 Figure 3.
Rev. 5.00, 09/0 3, page 67 of 760 The sharing information (SH) determines whether the PT EH.ASID and the ASID in the T LB entry are c om par ed. ASIDs are c ompare d when the re is no sha r ing between processes (SH = 0) bu t not when there is sharing (SH = 1).
Rev. 5.00, 09/0 3, page 68 of 760 3.3.4 Page Man agemen t Inform ation In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and P R bits. The D bit of a TLB entr y indicates whether the page is dirty (i.
Rev. 5.00, 09/0 3, page 69 of 760 3.4 MMU Functions 3.4.1 MMU Hard w are Managem ent There are two k i nds of MMU hardware m an agement as follows: 1. The MMU decodes the virtu al address accessed b y a process and performs address translati on by controlling the T LB in accordance with the MMUCR settings.
Rev. 5.00, 09/0 3, page 70 of 760 3.4.3 MMU In struction (LDTL B) The load TLB instruction (LDTLB) is used to r ecord TLB entries. When the I X bit in M MU CR is 0, the LDTLB instruction changes the T.
Rev. 5.00, 09/0 3, page 71 of 760 VPN(31 − 17) VPN(11 − 10) ASID(7 − 0) V VPN 0 ASID VPN 0 SV 0 0 RC 0 TF IX AT PPN 0 000 V 0 PR SZ C D SH 0 Write PPN(28 − 10) PR(1 − 0) SZ C D SH Write Data array Address array Way selection Ways 0 to 3 31 9 0 MMUCR Index 31 17 12 10 8 0 PTEH register 31 28 29 10 0 PTEL register 0 31 Figure 3.
Rev. 5.00, 09/0 3, page 72 of 760 3.4.4 Avo iding Synony m Proble ms When a 1-k byte page is recorded in a T LB entry, a syn onym problem m ay arise. If a number of virtu al addresses are mapped on to.
Rev. 5.00, 09/0 3, page 73 of 760 When using a 4-kbyte page Virtual address 31 VPN 0 12 11 10 Offset Physical address 31 PPN 0 Offset Virtual address (11 − 4) Physical address (28 − 10) Cache addr.
Rev. 5.00, 09/0 3, page 74 of 760 3.5 MMU Exceptions There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write. 3.5. 1 TLB M iss Exce pt io n A TLB miss results when the vi rtual address and the address arra y of the selected TLB entry are compared an d no match i s found.
Rev. 5.00, 09/0 3, page 75 of 760 2. If using software for way selection for entry replacement, write the desired val ue to the RC field i n MM UC R. 3.
Rev. 5.00, 09/0 3, page 76 of 760 3.5.3 T LB Inval id Exception A TLB invalid exception res ults when the virtu al address is compared to a selected TLB entry address arr ay and a match is fo und but the entry is not v alid (the V bit i s 0) . TLB invalid exception processin g includes both hardware and software operatio n s.
Rev. 5.00, 09/0 3, page 77 of 760 3.5.4 I nitial Page Wri te Excepti on An initial page write e xception r esults in a write a cc ess when the vir tual add ress and the address array of the selected T.
Rev. 5.00, 09/0 3, page 78 of 760 Start TLB miss exception Initial page write exception PR check PR check Yes SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)? VPNs and ASIDs match? VPNs match? No Yes Yes Yes Y.
Rev. 5.00, 09/0 3, page 79 of 760 3.5.5 Processi ng Flow in Event of MMU Exception (Same Processing Flow for Address Error) Figure 3.12 shows the MMU exception signals in the instructio n fetch mode.
Rev. 5.00, 09/0 3, page 80 of 760 Figure 3 . 13 sho ws the MMU e x cep tio n signal s in the da ta access mode . IF ID EX IF ID EX IF ID ID EX M A WB ID EX M A W B ID EX M A W B NOP NOP IF ID EX M A W.
Rev. 5.00, 09/0 3, page 81 of 760 In the addre ss field, specify VPN i n bits 16-12 as the index address that sel ects th e ent ry, W in bit s 9-8 to select the way, and H'F2 in bits 31- 24 to indicate access to the addres s array. Selecti on of the index addres s depends on the MMUCR.
Rev. 5.00, 09/0 3, page 82 of 760 VPN 31 23 1111 0010 * * 16 (1) TLB Address Array Access Read access W 0 * VPN * 31 23 24 24 17 17 17 1111 0010 * ** * 16 Write access Read/write access W 60 * * 0 VPN.
Rev. 5.00, 09/0 3, page 83 of 760 3.6.3 U sage Exam ples Invalidat ing Specif ic Entries: Speci fic TLB entries can be invalidat ed by writ ing 0 to the entry’ s V bit.
Rev. 5.00, 09/0 3, page 84 of 760.
Rev. 5.00, 09/0 3, page 85 of 760 Section 4 Exception Handling 4.1 Overview 4.1.1 Features Exc eption han dling is sepa rat e from norm al progr am proces sin g, an d is pe rform ed by a rou tin e separate f rom the norm al program .
Rev. 5.00, 09/0 3, page 86 of 760 contents of PC an d SR to return to the processor state at the point of inte rruption and the addres s where the exception occurred. A basic exception handli ng sequence consists of the foll owing operat i ons: 1. The contents of PC and SR are saved in SPC and SSR, respectively.
Rev. 5.00, 09/0 3, page 87 of 760 Table 4.2 Exception Event Vectors Exception Ty pe Current Instruction Exception Event Priorit y * 1 Exception Order Vector Address Vector Offset Reset Aborted Power-o.
Rev. 5.00, 09/0 3, page 88 of 760 4.2.3 Acceptance of E xceptions Processo r resets and interrupts are asynchronous events unrelated to the ins truction str eam. All exception ev ents are prioritized to establish an acceptance order w henever two or more exception events occur simultaneously .
Rev. 5.00, 09/0 3, page 89 of 760 IF Instruction n ID EX MA TLB miss (data access) WB IF Instruction n + 1 Instruction n + 2 ID EX MA TLB miss (instruction access) WB IF ID EX MA RIE (reserved instruc.
Rev. 5.00, 09/0 3, page 90 of 760 instruction or d elay slot is accepted after executio n o f the delayed branch inst ru cti on. The del ay slot here refers either to the next instructio n after a delayed uncondit ional branc h instruction or to the next instr uction whe n a dela yed conditional br anch instr uction is true.
Rev. 5.00, 09/0 3, page 91 of 760 Exception Ty pe Exception Ev ent Exception Code General interrupt reque sts External hardw are interrupt s (cont): (cont) IRL3–IRL0 = 001 0 H'240 IRL3–IRL0 =.
Rev. 5.00, 09/0 3, page 92 of 760 4.3 Register Descriptions There are four r egisters related to exception han dling. These are periphe ral module registers, and therefore resid e in area P 4. T hey can be accessed by spe c ifying the address in privileg ed mode only .
Rev. 5.00, 09/0 3, page 93 of 760 4.4 Exception Handling Operation 4.4.1 Reset The res et seq ue nce is us ed t o po wer up o r re sta rt th e S H7709S fr om the in itialization state.
Rev. 5.00, 09/0 3, page 94 of 760 4.4.3 G eneral Exceptions When the SH7709S encounters any exception condition other than a reset or interrupt reques t, it executes the follo wing operations: 1. The contents of PC and SR are saved to SPC and SSR, res pectively.
Rev. 5.00, 09/0 3, page 95 of 760 • UDI Reset Condition s: UDI reset comma nd input (see sect ion 22.4.3, UDI Reset) Operations: EXPEVT set to H'000, VBR and S R initialized, br anch t o PC = H'A 0000000. Initialization sets th e VBR register to H'0000000 .
Rev. 5.00, 09/0 3, page 96 of 760 • TLB invalid exception Conditio ns: Co mpariso n of T LB addr esses shows a ddress match but th e TLB entry v alid bit (V) is 0. Operations : The virtu al address (32 bits) t hat caused the exception is set in T EA and the cor r esp o nding vi r tua l page num be r (22 bit s) is se t in PTEH (31–10).
Rev. 5.00, 09/0 3, page 97 of 760 • CPU address error Condition s: a. Instru c tion fetch from odd address (4n + 1, 4n + 3) b. Word data access ed from addres ses oth er than word boundaries (4 n + 1, 4n + 3) c. Longw ord accessed f rom addresses other than longw ord boundaries (4n + 1, 4n + 2, 4n + 3) d.
Rev. 5.00, 09/0 3, page 98 of 760 • Illegal slot instr uction Condition s: a. When un defined code in a delay slot is decoded Delay br a nc h instruct ions: J MP, JSR, B RA, BRA F, BSR, B SRF, RT S, RT E , BT /S, BF/S b.
Rev. 5.00, 09/0 3, page 99 of 760 4.5.3 Interrupt s 1. NMI — Condit ions: NMI pin edge det ection — Operations: PC after the inst ruction that receives the interru pt is saved to SPC, and SR at the poin t t he interrupt is accepted is s aved to SSR.
Rev. 5.00, 09/0 3, page 100 of 760 5. On-Chip Peri pheral In terrupt s — Co nditi ons: The inter rupt mask bits in SR are l ower than the on-ch ip mo dule ( TMU , RTC, SCI, IrDA, SCIF, A /D, DMAC, WDT, REF) interrupt level and the BL bit in SR is 0.
Rev. 5.00, 09/03, pa ge 101 of 760 • SPC when exception occurs: The PC saved to SPC when an exception occu rs is as shown below: Re-executing-type exceptions: PC of the instruction that caused t he exception is set in SPC and re-execut e d after retu r n from except ion handling.
Rev. 5.00, 09/0 3, page 102 of 760.
Rev. 5.00, 09/03, pa ge 103 of 760 Section 5 Cache 5.1 Overview 5.1.1 Features The cache specificati ons are listed in table 5.1. Table 5.1 Cache Specifications Parameter Specification Capacity 16 k b.
Rev. 5.00, 09/0 3, page 104 of 760 24 (1 + 1 + 22) bits 128 (32 × 4) bits 6 bits LW0 − LW3: Longword data 0 − 3 Entry 0 Entry 1 Entry 255 0 1 255 0 1 255 V U Tag address LW0 LW1 LW2 LW3 Address array (ways 0 − 3) Data array (ways 0 − 3) LRU .
Rev. 5.00, 09/03, pa ge 105 of 760 The LRU bits are initialized to 000000 by a power-on reset, but are not initialize d by a manual reset. Table 5.2 LRU and Way Replace ment (When the cache lock funct.
Rev. 5.00, 09/0 3, page 106 of 760 CE WT CF CB 0 1 2 3 4 5 6 31 …… … …… …… … : Reserved bits. Always 0 when reading. Data written here is also always 0. CF: Cache flush bit. Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all cache entries to 0).
Rev. 5.00, 09/03, pa ge 107 of 760 31 9 8 7 2 1 0 W2 LOAD W3 LOCK W3 LOAD W2 LOCK W2LOCK: W ay 2 lock bit. W2LOAD: W ay 2 load bit. When W2LOCK = 1 & W2LOAD = 1 & SR, CL = 1, the prefetched data will always be loaded into W ay2. In all other conditions the prefetched data will be loaded into the way pointed by LRU.
Rev. 5.00, 09/0 3, page 108 of 760 Table 5.5 Way Repla cement w hen Instructio ns Except for PRE F Instruc tion Ended Up in a Cache Miss DSP bit W3LOAD W3LOCK W2LOAD W2LOCK Wa y to be replaced 0 **** D epends on LRU (table 5.2) 1 * 0 * 0 Depends on LRU (table 5.
Rev. 5.00, 09/03, pa ge 109 of 760 5.3 Cache Operati on 5.3.1 Searching the Cache If the cache is enable d, w henever instructions or data in memory are accessed the cach e w i l l be searched to see if the desired instructio n or data is in the cache.
Rev. 5.00, 09/0 3, page 110 of 760 0 1 255 V U Tag address LW0 LW1 LW2 LW3 Ways 0 − 3 Ways 0 − 3 31 12 11 4 3 2 1 0 Virtual address CMP0 CMP1 CMP2 CMP3 Physical address CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 Hit signal 1 Entry selection Longword (LW) selection MMU Figure 5.
Rev. 5.00, 09/03, pa ge 111 of 760 5.3.2 Read Acces s Read Hit: In a read access, instru ctions and data are transferred from the cache to the CP U. The transfer unit is 32 bits . The LRU is updated. Read M iss: An external bus cycle starts and the entry is updated.
Rev. 5.00, 09/0 3, page 112 of 760 Longword 0 Longword 1 Longword 2 Longword 3 P A (31 − 4) PA (31 − 4): Longword 0 − 3: Physical address written to external memory The line of cache data to be written to external memory Figure 5.5 Writ e-Back Buffer Configuratio n 5.
Rev. 5.00, 09/03, pa ge 113 of 760 The following three operations on the address array are possible. (1) Address Array Read Reads the tag address, LRU, U bit, and V bit fro m the entry that corresp onds to the entry address and w`ay that were specified in the address field.
Rev. 5.00, 09/0 3, page 114 of 760 The following two operations on the data ar ray are possible. Note that these operati ons w ill not change the inf ormation in the address array.
Rev. 5.00, 09/03, pa ge 115 of 760 5.4.3 Examples of Us age (1) Invalidat ing a Specific Entry A specific c ache entry can be invalidate d by access ing the all ocated memor y cache a nd writing a 0 to the ent ry’s U an d V bits. T he A bit is cle a red to 0, an d a n ad d ress is specifi ed f or the entry address and the way.
Rev. 5.00, 09/0 3, page 116 of 760 In the fo llo wing exa mpl e , an add ress (3 2-b it) t o be purged is s pecifi ed in R 0. MOV.L #H'00000FF0, R1 ; AND R0, R1 ; The entry address is fetched. MOV.L #H'F0000008, R2 ; OR R1, R2 ; The start is set to H'F0 and the A bit to 1.
Rev. 5.00, 09/03, pa ge 117 of 760 Section 6 In terrupt Controller (INTC) 6.1 Overview The interrupt controller (INTC) asc e rtains the priori ty of interrupt sourc es and controls interrupt requests to the CPU.
Rev. 5.00, 09/0 3, page 118 of 760 6.1.2 Block Diagra m Figure 6.1 s hows a bl ock diag ram of t he INTC. REF IrDA DMAC ICR Input/output control Com- parator Priority identifier 3 4 6 16 Interrupt req.
Rev. 5.00, 09/03, pa ge 119 of 760 6.1.3 Pi n Configur ation Table 6.1 show s the INTC pi n con figuration . Table 6.1 INTC Pi ns Name Abbrev iation I/O Description Nonmaska ble interrupt input pin NM I I Input of interrupt request s ignal, not maskable b y the interrupt mas k bits in SR.
Rev. 5.00, 09/0 3, page 120 of 760 6.1.4 Regi ster Configurati on The INTC h as th e 12 registers lis ted in t able 6.2. Table 6.2 INTC Registers Name Abbr.
Rev. 5.00, 09/03, pa ge 121 of 760 6.2 Interrup t Sources There are five types of in terrupt s ources: NMI, IRQ, IR L,PI NT , and on -chip peri pheral mod ules. Each interrupt has a priority level (0–16), w ith 0 the lowest and 16 th e highest. Priority level 0 mask s a n interru pt.
Rev. 5.00, 09/0 3, page 122 of 760 Inter rupt s IRQ4 –IRQ 0 c an wake the chip u p fr om the s tandby s tate w hen th e r elev ant i nter rupt level is high er than the s e tting of I3–I0 in the SR regi ster (but only w he n the RTC 32-k Hz oscillator is used).
Rev. 5.00, 09/03, pa ge 123 of 760 Table 6. 3 I I I IR R R RL L L L3 3 3 3 – I I I IR R R RL L L L0 0 0 0 / I I I IR R R RL L L LS S S S3 3 3 3 – I I I IR R R RL L L LS S S S0 0 0 0 Pins and Inter.
Rev. 5.00, 09/0 3, page 124 of 760 6.2.4 PI NT Interru p ts PINT interrupts are input b y level from pins PINT0 – PINT15. The prio rity level can be set by interru pt priority register D (IPRD) in a range from 0 to 15, in groups of PINT0–PI NT7 and PINT8–PIN T15.
Rev. 5.00, 09/03, pa ge 125 of 760 6.2.6 I nterrupt Ex ception Hand ling and Priority Tables 6.4 and 6.5 list the codes for the interrupt event registers (INT EVT and INTEVT2) , and the order of interrupt priority . Each interru pt source is assigned a u n ique code.
Rev. 5.00, 09/0 3, page 126 of 760 Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) Interrupt Source INTEVT Code (INTEVT2 Code) Interrupt Priority (Initial Value) IPR (Bit Number.
Rev. 5.00, 09/03, pa ge 127 of 760 Interrupt Source INTEVT Code (INTEVT2 Code) Interrupt Priority (Initial Value) IPR (Bit Numbers) Priority within IPR Setting Unit Default Priority RTC ATI H'480.
Rev. 5.00, 09/0 3, page 128 of 760 Table 6.5 Interrupt Exception Handling Sources and Priority (IRL Mode) Interrupt Source INTEVT Code (INTEVT2 Code) Interrupt Priority (Initial Value) IPR (Bit Number.
Rev. 5.00, 09/03, pa ge 129 of 760 Interrupt Source INTEVT Code (INTEVT2 Code) Interrupt Priority (Initial Value) IPR (Bit Numbers) Priority within IPR Setting Unit Defa ult Priority SCIF ERI2 H'.
Rev. 5.00, 09/0 3, page 130 of 760 Table 6.6 Interrupt Level s and INTEV T Code s Interrupt level INTEVT Code 15 H'200 14 H'220 13 H'240 12 H'260 11 H'280 10 H'2A0 9H &ap.
Rev. 5.00, 09/03, pa ge 131 of 760 6.3 INTC Registers 6.3.1 Interrupt Priority Registers A to E (IPRA–IPRE) Interrupt prior ity register s A to E (IP RA to IPRE) ar e 1 6-bit readable/writable registers in which priority le vels from 0 to 15 are set for on-c hip periphera l module, IRQ, and P INT in terrupts.
Rev. 5.00, 09/0 3, page 132 of 760 6.3.2 I nterrupt Control Register 0 (ICR0) ICR0 is a regi ster that sets t he input sig nal detection mode of external interrupt input pin NMI, and indicates the input sig nal level at the NMI pin.
Rev. 5.00, 09/03, pa ge 133 of 760 6.3.3 I nterrupt Control Register 1 (ICR1) ICR1 is a 16-bit re gi ster that specifie s the detection mode for extern al interrupt input pins IRQ0 to IRQ5 individually: ris ing edge, f alling edge, or low level.
Rev. 5.00, 09/0 3, page 134 of 760 Bit 12— I I I IR R R RL L L LS S S S Enable (IRLSEN): Enables pins IRLS3 – IR LS0 . This bit is vali d only w hen the IRQLVL bit is 1.
Rev. 5.00, 09/03, pa ge 135 of 760 Bits 5 and 4 —IRQ2 Sense Select (I RQ21S, I RQ20S): Select whether the interr upt signal to the IRQ2 pin is detected at the rising edge, at the fa lling edge, or at the low level.
Rev. 5.00, 09/0 3, page 136 of 760 6.3.4 I nterrupt Control Register 2 (ICR2) ICR2 i s a 1 6-b it re ada ble/ writa ble regi ster tha t sets t he det ectio n mo de fo r e xt erna l int errup t input pins PINT0 to PINT15. This regis ter is in itialized to H' 0000 by a p ower-o n reset or manua l reset, but is not initializ ed in st andby mode.
Rev. 5.00, 09/03, pa ge 137 of 760 6.3.5 PI NT In terrupt Enabl e Register (PI NTER) PINTER is a 1 6-bit readable/ writable register tha t enables interrupt req uests input to external inte rrupt inpu t pins PINT0 t o PINT15.
Rev. 5.00, 09/0 3, page 138 of 760 6.3.6 I nterrupt Request Register 0 (IRR0) IRR0 is a n 8-bit r e gi ster tha t indic a t es inte rrupt r e ques ts f rom e x t e rn al input pins IRQ 0 to IRQ5 and PINT0 to PINT15. T his register is initialized to H '00 by a p ower-on reset or manual reset, but is not initialized i n standb y mode.
Rev. 5.00, 09/03, pa ge 139 of 760 Bit 4—IRQ 4 Interrupt Reques t (IRQ4R): Indi cates whether there i s interru pt request i nput to the IRQ4 pin. When e dge detecti on mod e is set for I R Q4, an interr up t req ue st is cle ared by clearing the IRQ4R bit.
Rev. 5.00, 09/0 3, page 140 of 760 6.3.7 I nterrupt Request Register 1 (IRR1) IRR1 is an 8-bit read- only register that indicates whether DMAC or IrDA interrupt requests have been generated. This register is initialized to H'00 by a p ower- on reset o r manual reset, but is not initialized in standb y mode.
Rev. 5.00, 09/03, pa ge 141 of 760 Bit 3—DEI3 In terrupt Request (DEI3R): Indicates w hether a DEI3 (DMAC) i nterrupt request has be en ge nera ted .
Rev. 5.00, 09/0 3, page 142 of 760 Bits 7 to 5—Reserved: These bits are always read as 0. The write value shoul d always be 0. Bit 4—ADI Interru pt Reques t (ADI R): Indicates whether an ADI (A DC) interrupt reques t has been generated.
Rev. 5.00, 09/03, pa ge 143 of 760 6.4 INTC Operation 6.4.1 Interrupt Sequence The sequen ce of int errupt operation s is described be low. Figure 6.3 i s a f lowchart of the operations. 1. T he interrupt request source s send interrupt request signa ls to th e interrupt contro ller.
Rev. 5.00, 09/0 3, page 144 of 760 No Yes Yes Yes Yes Yes Yes Yes No No No No No Level 15 interrupt? I3 − I0: Interrupt mask bits in status register (SR) Program execution state ICR1.MAI = 1? Interrupt generated? NMI = low? SR.BL= 0 or sleep mode? Yes Yes Yes Yes Yes Yes No No No No No No No ICR1.
Rev. 5.00, 09/03, pa ge 145 of 760 6.4.2 Mult iple Interrupts When handling m ultiple inte rrupts , an inte r ru pt handle r should in clu de th e fol l ow ing procedures: 1. Branch to a specif ic interrupt handler correspondin g to a code set in INTEVT and I NT EVT2.
Rev. 5.00, 09/0 3, page 146 of 760 Table 6.8 Interrupt Response Time Number of States Item NM I IRQ PINT Peripheral Modules Notes 0.5 × Icyc + 1.5 × Pcyc * 5 Time for priori ty decision a nd SR mask bit com pa ris o n 0.5 × Icyc + 0.5 × Bcyc + 0.5 × Pcyc 0.
Rev. 5.00, 09/03, pa ge 147 of 760 Number of States Item NM I IRQ PINT Peripheral Modules Notes Response time Total (5.5 + X) × Icyc + 1.5 × Pcyc * 5 (5.5 + X) × Icyc + 0.5 × Bcyc + 0.5 × Pcy c (5.5 + X) × Icyc + 1 × Bcyc + 4.5 × Pcyc * 4 (5.5 + X) × Icyc + 3.
Rev. 5.00, 09/0 3, page 148 of 760 Interrupt acceptance IRL 0.5 × Icyc + 0.5 × Bcyc + 2 × Pcyc Instruction (instruction replaced by interrupt exception handling) IF ID EX EX EX EX IF IF ID EX 5 × Icyc Start of interrupt handling IF: Instruction fetch: Instruction is fetched from memory in which program is stored.
Rev. 5.00, 09/03, pa ge 149 of 760 Section 7 User Break Controller 7.1 Overview The user break control ler (UBC) pro vides fun ctions that simplify pro gram debugging. This funct ion makes it easy t o design an effective se lf-monitoring de bugger, e n abl ing the c h ip t o debug programs without using an in-circuit emulator .
Rev. 5.00, 09/0 3, page 150 of 760 7.1.2 Block Diagram Figure 7.1 s hows a bl ock diag ram of t he UBC. BBRA BARA BAMRA BASRA ASID comparator CPU state signals IAB LAB MDB Access comparator Address co.
Rev. 5.00, 09/03, pa ge 151 of 760 7.1.3 Regi ster Configurati on Table 7.1 Register Configuration Name Abbr. R/W Initial Value * 1 A ddress Access Size Location Break address regi ster A BARA R/W H&a.
Rev. 5.00, 09/0 3, page 152 of 760 7.2 Register Descriptions 7.2.1 Break Address Register A (BARA) BARA is a 32-bit read/ write register. B ARA specifies the address used as a break condition in channel A. A power-on reset initializes BARA t o H'00000000.
Rev. 5.00, 09/03, pa ge 153 of 760 7.2.2 Break Address Ma sk Register A (BAMRA) BAMRA is a 32-bit read/w rite register. BAMRA s pecifies bits m as ked in the break address specifi ed by BARA.
Rev. 5.00, 09/0 3, page 154 of 760 7.2.3 Break Bus Cycle Register A (BBRA) Break bus cy cle registe r A (BBRA ) is a 16- bit read/w rite reg ister, w hich specifi es (1) CPU cy cle or DMAC cyc l e , (2) instruc tio n fetc h or data acces s, ( 3 ) read or writ e, an d (4 ) op e rand size in the break conditions of channel A.
Rev. 5.00, 09/03, pa ge 155 of 760 Bits 3 and 2—Read/Write Select A (RWA1, RWA0): Selects the read cycle or w rite cycle as the bus cy cle of the channel A break condition.
Rev. 5.00, 09/0 3, page 156 of 760 7.2.4 Break Address Register B (BA RB) BARB is a 32-bit read /write register . BARB speci fies the address used as a break condition in channel B.
Rev. 5.00, 09/03, pa ge 157 of 760 7.2.5 Brea k Address M a sk Register B ( B AM RB) BAMRB is a 32- bit read/write register. BAMRB specifies bits masked in the break addres s specified by BARB.
Rev. 5.00, 09/0 3, page 158 of 760 7.2.6 Break Data Register B ( B DRB) BDRB is a 32- bit read/w rite regist er. A power- on reset i nitializes BDRB to H'00000000.
Rev. 5.00, 09/03, pa ge 159 of 760 7.2.7 Break Data Mask Register B (BD MRB) BDMRB is a 32-bit read/w rite register. BDMRB specifies bits masked in the break data specif ied by BDRB.
Rev. 5.00, 09/0 3, page 160 of 760 7.2.8 Break Bus Cycle Register B (BBRB) Break bus cycle register B (BBRB) is a 16-bit read/w rite register, wh ich specifies, (1) CPU cycle or DMAC cycl e , (2) instructio n fetc h or data acces s, ( 3 ) read/wri t e , and ( 4 ) op e rand size in the break con ditions of c hannel B.
Rev. 5.00, 09/03, pa ge 161 of 760 Bits 3 and 2— Read/Write Select B (RWB1, RWB0): Select the read cycle or write cycle as the bus cycle of the channel B break condition.
Rev. 5.00, 09/0 3, page 162 of 760 7.2.9 Break Control Register (BRCR) BRCR sets the following condition s: 1. Chan nels A and B are used in two independent channels conditio n or under the sequential condition. 2. A break is set before or after instruction execution.
Rev. 5.00, 09/03, pa ge 163 of 760 Bit 21—Break ASID Ma sk A (BASM A): Specifies wheth er the bits of t he channel A break ASID7-A SID0 (BASA 7 to BASA 0) set in BAS RA are mask ed or no t.
Rev. 5.00, 09/0 3, page 164 of 760 Bit 13—DMAC Condition Match Flag A (SCMFDA): When the on- chip DM AC bus cy cl e conditio n in the brea k conditio ns s et for channel A is sa tisfi ed, this flag is set to 1 (not clear ed to 0). In order to clear this flag, w rite 0 into t his bit.
Rev. 5.00, 09/03, pa ge 165 of 760 Bit 6—PC Break S elect B (PCBB): Selects th e break tim i ng of the instruction fetch cycle for channel B as before or after ins tructio n execution.
Rev. 5.00, 09/0 3, page 166 of 760 7.2.10 Execution Times Break Register (BETR) When the exec ution-times br eak condition of channel B is enabled, this register sp ecifies the number of execution times to make the break. The m aximum number is 2 12 – 1 t imes .
Rev. 5.00, 09/03, pa ge 167 of 760 7.2.11 Branch Source Register (BRSR) BRSR is a 32-bit read register. BR SR s tores the l ast fetched addres s before bran ch an d the pointer (3 bits) which indicates the n umber of cycles from fet ch to execution for the last executed instruction.
Rev. 5.00, 09/0 3, page 168 of 760 Bits 30 to 28—Instruction Decode Pointer (PID2 t o PID 0 ): PID is a 3-bi t binary pointer (0–7). These bits indicate the inst ruction buff er number wh ich stores the last executed ins truction before branch. Bits 30 to 28 : PID Description Even PID indicat es the instr uction buff er number.
Rev. 5.00, 09/03, pa ge 169 of 760 Bit 31—BRDR Valid Flag (DVF): Indicates w h ether a branch destination address is stored. When a branch destinat ion address is fetched, this fla g is set to 1.
Rev. 5.00, 09/0 3, page 170 of 760 7.3 Operation Descri p ti on 7.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break exception proc essing is described below: 1.
Rev. 5.00, 09/03, pa ge 171 of 760 3. When the condition is specified to be occurred after execu t ion, the instructi o n se t with the break condition is executed and the n the break is generated prior to the execution of th e next instruction. As with pre-execution br eaks, this cannot b e used with overrun fetch instr uctions.
Rev. 5.00, 09/0 3, page 172 of 760 7.3.4 Sequential Brea k 1. By specifying SEQ in BRCR is set to 1, the seque ntia l break is issued whe n channel B break condition matches after channel A break condition matches. A user break is ignored even if channel B break condition matches before c hannel A br eak condition matches.
Rev. 5.00, 09/03, pa ge 173 of 760 7.3.6 PC Trace 1. Setting PCT E in BRCR to 1 enables PC traces. W hen branch (branch instruction, repeat, and interrupt) is generated, the a ddress fr om which the branch sourc e address can be calculated and the branch destination addres s are st ored in BRSR and BRDR, respectively.
Rev. 5.00, 09/0 3, page 174 of 760 reaches the botto m of the queues. After s witchin g the P CTE b it (in BRCR) off and on, the values in the queues are inv alid. T he read pointer stay at the p ositi on before PCTE is switched, but the trace pointer restart at the bo tt om of t he queues.
Rev. 5.00, 09/03, pa ge 175 of 760 2. Register specifications BARA = H'00037226, BAMRA = H'0000000 0, BBRA = H'0056, BA RB = H'0003722E , BAMR B = H'00000000, B BRB = H' .
Rev. 5.00, 09/0 3, page 176 of 760 4. Register specifications BARA = H'00037226, BAMRA = H'0000000 0, BBRA = H'005A , BARB = H' 0003722E, BAMR B = H'00000000, B BRB = H' .
Rev. 5.00, 09/03, pa ge 177 of 760 6. Register specifications BARA = H' 00008404, BA MRA = H'00000FFF, BBRA = H'0054, BA RB = H'0000801 0, BAMR B = H'00000006, B BRB = H'.
Rev. 5.00, 09/0 3, page 178 of 760 Break Condition Specified to a DMAC Data Access Cycle 1. Register specifications : BARA = H'00314156, BAMR A = H'0000000 0, BBRA = H'0094, BAR B = H&a.
Rev. 5.00, 09/03, pa ge 179 of 760 7.3.8 Notes 1. Only CPU can read/write UBC registers. 2. UBC cannot monitor CPU and DM AC access in the sa me channel.
Rev. 5.00, 09/0 3, page 180 of 760.
Rev. 5.00, 09/03, pa ge 181 of 760 Section 8 Power-Down Modes 8.1 Overview In the pow er -down modes, all CPU and som e on-chip peripheral module funct i ons are halted. This lowers power consum ption. 8.1.1 Power -Down Modes The SH7709S h as th e followi ng power- down modes and fun ction: 1.
Rev. 5.00, 09/0 3, page 182 of 760 Table 8.1 Power-Down Modes State Mode Tran si ti on Conditions CPG CPU CPU Reg- ister On-Chip Me mory On-Chip Peripheral Modules Pins External Me mory Ca nceling Procedure Sleep mod e E xecute SLEEP instru ction w ith STBY bi t cleare d to 0 in STBC R Runs Hal ts Held Held Run Held Refres h 1.
Rev. 5.00, 09/03, pa ge 183 of 760 8.1.2 Pi n Configur ation Table 8.2 lists the pi ns used f or the power- down modes. Table 8.2 Pin Configura tion Pin Name Abbrev iation I/O Description Processing state 1 STATUS1 O Operating st ate of th e processor.
Rev. 5.00, 09/0 3, page 184 of 760 Bit 7— St a ndby (STBY) : Sp ecifies transitio n to standb y mode. Bit 7: STBY Description 0 Executing SLEEP instr uct ion put s chip into sleep mo de (Initial value) 1 Executing SLEEP instr uct ion puts chip into standby mode Bits 6, 5, and 3—Res erved: T hese bits are always read as 0.
Rev. 5.00, 09/03, pa ge 185 of 760 Bit 0—M odule Sta ndby 0 (MST P 0): Specifies halting of the cl ock supply to the serial communication interface SCI (an on -chip periphera l module). W hen the MSTP0 bit is set to 1, the supply of the clock to the SC I is halted.
Rev. 5.00, 09/0 3, page 186 of 760 Bit 4—M odule Sto p 7 (M STP7): Sp eci fies ha l ti ng of the clo ck supp ly to the D MAC ( an on- chip peripheral m odule).
Rev. 5.00, 09/03, pa ge 187 of 760 8.3 Sleep Mo de 8.3.1 Transition t o Sleep M ode Execut ing the S LEEP instruc tion when the ST BY bit in S TBCR is 0 causes a trans iti on fr om the program execution state to sleep mode.
Rev. 5.00, 09/0 3, page 188 of 760 8.4 Standby Mode 8.4.1 Transition t o Sta ndby M ode To e nter standb y mode, set t he STB Y b it to 1 in S TBCR , then exec ute the S LEE P i nstru ct ion. The chip sw itches from the program execution state to standby mode.
Rev. 5.00, 09/03, pa ge 189 of 760 8.4.2 Canceling St a ndby M ode Standby mode is can celed by an interrupt (NMI, IRQ, IR L, PINT, or on-chip peripheral module) or a reset.
Rev. 5.00, 09/0 3, page 190 of 760 Canceling with a Reset: Stan dby mode is canceled by a reset (pow er-on or m anual). Keep the RESET p in low until the clock os cillation se ttles . The in ter nal c lock w ill continue to be output to the C KIO and CKIO2 pin s.
Rev. 5.00, 09/03, pa ge 191 of 760 8.5 Module St andby F unction 8.5.1 Transition to M odule St a ndby Functio n Setting the standb y control register MST P8–MSTP 0 bits to 1 halts the supply of clo cks to the correspo nding on-chip peripheral modules.
Rev. 5.00, 09/0 3, page 192 of 760 8.6 Timing of STATUS P in Changes The timi ng of STATUS1 and STATUS0 pi n cha nges is s hown in f igures 8.1 to 8.8. 8.6.1 T iming for Rese ts Power-On Reset CKIO, CKIO2 * 4 RESETP STATUS Normal * 2 Normal * 2 Reset * 1 PLL settling time 0 to 5 Bcyc * 3 0 to 30 Bcyc * 3 RESETOUT Notes: 1.
Rev. 5.00, 09/03, pa ge 193 of 760 Manual Reset CKIO, CKIO2 * 5 RESETM STATUS Normal * 3 Normal * 3 Reset * 2 0 Bcyc or more * 4 0 to 30 Bcyc * 4 RESETOUT Notes: 1. In a manual reset, ST A TUS becomes HH (reset) and the internal reset begins after waiting for the executing bus cycle to end.
Rev. 5.00, 09/0 3, page 194 of 760 8.6.2 Timing fo r Ca nceling St andby Standby to Interrupt CKIO, CKIO2 * 3 STATUS Normal * 2 Normal * 2 WDT count Oscillation stops Standby * 1 Interrupt request WDT overflow WAKEUP Notes: 1. Standby: LH (STATUS1 low, STATUS0 high) 2.
Rev. 5.00, 09/03, pa ge 195 of 760 Standby to P ow er- O n Reset CKIO, CKIO2 * 7 STATUS Normal * 5 Normal * 5 Oscillation stops Standby * 4 0 to 10 Bcyc * 6 0 to 30 Bcyc * 6 Reset Reset * 3 RESETP * 1 * 2 Notes: 1. When standby mode is cleared with a power-on reset, the WDT does not count.
Rev. 5.00, 09/0 3, page 196 of 760 Standby t o M a nua l Reset CKIO, CKIO2 * 6 STATUS Normal * 4 Normal * 4 Oscillation stops Standby * 3 Reset * 2 0 to 20 Bcyc * 5 Reset RESETM * 1 Notes: 1. When standby mode is cleared with a manual reset, the WDT does not count.
Rev. 5.00, 09/03, pa ge 197 of 760 Sleep to Po wer-On Reset CKIO, CKIO2 * 7 STATUS Normal * 5 Normal * 5 Sleep * 4 0 to 10 Bcyc * 6 0 to 30 Bcyc * 6 Reset Reset * 3 * 2 RESETP * 1 Notes: 1. When the PLL1 ’ s multiplication ratio is changed by a power-on reset, keep RESETP low during the PLL ’ s oscillation settling time.
Rev. 5.00, 09/0 3, page 198 of 760 Sleep to M anual Reset CKIO, CKIO2 * 6 0 to 80 Bcyc * 5 0 to 30 Bcyc * 5 Reset STATUS Normal * 4 Normal * 4 Sleep * 3 Reset * 2 RESETM * 1 Notes: 1. Keep RESETM low until ST A TUS becomes reset. 2. Reset: HH (ST A TUS1 high, ST A TUS0 high) 3.
Rev. 5.00, 09/03, pa ge 199 of 760 8.7 Hardware St andby Mode 8.7.1 Transition to H a rdw are Standby M ode Driving the CA pin low causes a transition to hard ware standb y mode.
Rev. 5.00, 09/0 3, page 200 of 760 8.7.3 Hardw are Standby M ode Timing Figures 8.10 and 8.1 1 s how e xamples of pi n timin g i n hardware standb y mode. The CA pin is sampled usin g EXTAL2 (32. 768 kHz) , and a h ar dware stand by requ est i s only rec o gn ized w hen th e pin is l o w for tw o conse c uti ve clock c y cles.
Rev. 5.00, 09/03, pa ge 201 of 760 Normal * 3 STATUS CA CKIO, CKIO2 * 6 Standby * 2 Reset * 1 R ESETP Undefined 2 Rcyc or more * 5 0 − 10 Bcyc * 4 Standby WDT operation Notes: 1. Reset: HH (STATUS1 high, STATUS0 high) 2. Standby: LH (STATUS1 low, STATUS0 high) 3.
Rev. 5.00, 09/0 3, page 202 of 760.
Rev. 5.00, 09/03, pa ge 203 of 760 Section 9 On-Chip Oscillation Circuits 9.1 Overview The on-chip oscillation circuits consist of a clock pulse generator (CP G) block an d a watchdog timer (WD T) bl ock.
Rev. 5.00, 09/0 3, page 204 of 760 9.2 Overview of CPG 9.2.1 C PG Bl ock Diagram A block di ag ram of the on-chi p clock pu lse generator is shown i n fi gure 9.
Rev. 5.00, 09/03, pa ge 205 of 760 The clock p u l se generator blocks function as follows: 1. PLL Circuit 1: PLL circuit 1 doubles, triples, quadruples, s extupl es, o r leaves uncha nge d the input cloc k freque nc y fro m the CKIO pin. T he mu ltiplic atio n rate is set by the fre quency control regis ter.
Rev. 5.00, 09/0 3, page 206 of 760 9.2.2 CPG Pin Conf iguration Table 9.1 lists the CPG pi ns an d their fun ctions. Table 9.1 CPG Pins and Functio ns Pin Name S y mbol I/O Description MD0 I Set the c.
Rev. 5.00, 09/03, pa ge 207 of 760 9.3 Clock Operating Modes Ta b le 9 .3 sho ws the r e latio nshi p be tween the mode c ontrol p in (MD2–MD0) combinatio ns and the clock operatin g modes. Table 9.4 sh ows the us able frequency ranges in the clock operating modes.
Rev. 5.00, 09/0 3, page 208 of 760 Mode 7: In this mode, the CKIO pin is an input, an external clock is i nput to this p in, and undergoes waveform shaping, and also freque ncy multiplication according to the setting, b y PLL circ uit 1 bef ore b eing supp lie d to the ch ip.
Rev. 5.00, 09/03, pa ge 209 of 760 Clock Mode FRQCR PLL1 PLL2 Clock Rate * (I :B:P ) Input Frequency Range CKIO Frequency Range 1, 2 H'0100 ON ( × 1) ON ( × 4) 4:4:4 6.25 M Hz to 8.34 MHz 25 MH z to 33.3 4 MH z H'0101 ON ( × 1) ON ( × 4) 4:4:2 6.
Rev. 5.00, 09/0 3, page 210 of 760 Cautions: 1. The frequency of th e internal clock (I φ ) beco mes: • The product of the frequency of the CKIO pin, the frequency multiplicatio n ratio of PLL circuit 1, and th e division ratio of div ider 1. • Do not se t the int ern al cl ock fre quency l ower than the CK IO pin f req uency.
Rev. 5.00, 09/03, pa ge 211 of 760 9.4 Register Descriptions 9.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR) i s a 16-bit readable/w r itable register used to specify the frequency multiplicatio n ratio of PLL circuit 1 and the freq uency di vision ratio of the internal clock and the peripheral clock.
Rev. 5.00, 09/0 3, page 212 of 760 Bits 14, 3, an d 2—Intern al Clock Frequency Di vision R atio (IFC): These bits specify the frequency divisio n ratio of the internal clo ck with respect to the output frequency of PLL circuit 1.
Rev. 5.00, 09/03, pa ge 213 of 760 9.5 Changing the Frequency The frequen cy of th e internal clock and per ipheral clock ca n be changed either b y changing the multiplication ratio of PLL cir cuit 1 o r by changing the division ratios of dividers 1 a n d 2.
Rev. 5.00, 09/0 3, page 214 of 760 9.6 Overview of WDT 9.6.1 Block Diagra m of WDT Figure 9.2 s hows a bl ock diag ra m of t he WDT. WTCSR Standby control Bus interface WTCNT Divider Clock selector Cl.
Rev. 5.00, 09/03, pa ge 215 of 760 9.7 WDT Registers 9.7.1 W atchdog Timer C ounter (WTCNT) The watchdog timer counter (WTCNT) is an 8-bit readable/w r itable counter t hat increments on t he selected clock. WT CNT differs from other registers in that it is mor e diff icult to write to.
Rev. 5.00, 09/0 3, page 216 of 760 Bit 6—Timer Mode Select (WT/ I I I IT T T T ): Selects whether to use the WDT as a w atc hdog time r or an interval timer.
Rev. 5.00, 09/03, pa ge 217 of 760 Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Division Ratio Overflow Period (when P φ φ φ φ = 15 MH z) 0001 ( I n i t i a l v a l u e ) 1 7 µ s 1 1/4 68 µ s 1 0 1/16 273 µ s 1 1/32 546 µ s 1001 / 6 4 1 . 0 9 m s 1 1/256 4.
Rev. 5.00, 09/0 3, page 218 of 760 9.8 Using the WDT 9.8.1 Canceling St a ndby The WDT can be u sed to cancel s tandby m ode with an NMI or oth er interru pt. The procedu re is desc r ibe d bel ow. ( Th e WDT does not run when a res e t is u s ed f o r canc el ing, so kee p the RESE T pin low until the cl ock stabilizes.
Rev. 5.00, 09/03, pa ge 219 of 760 When the f ol low ing t h ree cond ition s ar e a ll m et, FRQC R sho ul d no t b e cha n g ed w hile a DMAC transfer is in progress . • Bits IFC2 to IFC0 are chan ged. • STC2 to STC0 are not chan ged. • The clock ratio of I φ (on-chip clock ) to B φ (bus clo ck) a fte r the ch ang e is oth e r than 1 : 1.
Rev. 5.00, 09/0 3, page 220 of 760 9.9 Notes on Board Design When Usin g an External Crysta l Resonator: Place the cr ystal resonator, capaci tors CL1 and CL2 cl o se t o th e EXT AL and XT AL pins.
Rev. 5.00, 09/03, pa ge 221 of 760 CAP2 V CC (PLL2) V CC (PLL1) V CC C1 = 470 pF C2 = 470 pF V SS CAP1 V SS (PLL2) V SS (PLL1) Avoid crossing signal lines Power supply Reference values C2 C1 Figure 9.
Rev. 5.00, 09/0 3, page 222 of 760.
Rev. 5.00, 09/03, pa ge 223 of 760 Section 10 Bus State Controller (BSC) 10.1 Overview The bus state controller (BSC) divi des physical address sp ace an d output control signals for various t ypes of memor y and bus interface s pec ificati ons.
Rev. 5.00, 09/0 3, page 224 of 760 • Short refresh cy cle control The overflow interrupt function of the refresh coun ter enables the ref resh function immediately after a self-refres h operatio.
Rev. 5.00, 09/03, pa ge 225 of 760 10.1.2 Block D iagram Figure 10.1 shows a block diagram of the bus state controll er. WCR1 WCR2 BCR1 Module bus MCR BSC RFCR RTCNT Comparator Refresh controller Peri.
Rev. 5.00, 09/0 3, page 226 of 760 10.1.3 Pin Configurati on Table 10.1 sh ows t he BSC pi n conf igurati on. Table 10. 1 BSC Pins Pin Name Signal I/O Description Address bus A25–A0 O Address output Data bus D15–D0 I/O Data I/O D31–D16 I/O Data I/O when u sing 32-bit bus width Bus cycle start BS O Shows start of bus cycle.
Rev. 5.00, 09/03, pa ge 227 of 760 Pin Name Signal I/O Description Data enable 3 WE3 /DQMUU/ ICIOWR O W hen me mory other than synchronou s DRAM and PCMCIA is us ed, D31–D24 w rite strobe signal. When sy nchronou s DRAM is used, selects D 31– D24.
Rev. 5.00, 09/0 3, page 228 of 760 10.1.4 Register C onfiguration The BSC has 21 registers (t able 10.2). Sync h ronous DRAM als o has a buil t- i n synchronous DRAM mode register. These reg isters control direct conn ection interfaces to memory, w ait states, and refreshes devices.
Rev. 5.00, 09/03, pa ge 229 of 760 10.1.5 Area Overvie w Space Allocation: In the architecture of the SH7709S, both logical spaces and physical spaces have 32-bit ad dress spaces . The logical sp ace is divided into five are a s b y the value o f the upper bits of the address.
Rev. 5.00, 09/0 3, page 230 of 760 Table 10.3 Physical Address Space M ap Area Connectable Memory Ph y sical Address Capacity Access Size 0 H'00000000 to H'03FFFFFF 64 Mbytes 8, 16, 32 * 2 O.
Rev. 5.00, 09/03, pa ge 231 of 760 Area 0: H'00000000 Area 1: H'04000000 Area 2: H'08000000 A rea 3: H'0C000000 Area 4: H'10000000 Area 5: H'14000000 The PCMCIA interface.
Rev. 5.00, 09/0 3, page 232 of 760 Shadow Space: Areas 0 and 2–6 are decoded by physical address es A28– A26, whic h co rre sp on d to areas 000 to 110.
Rev. 5.00, 09/03, pa ge 233 of 760 Table 10.6 PCMCIA Support Int erface IC Memory Card Interface I/O Card Interface Pin Signal I/O Function Signal I/O Function SH7709S Pin 1 GND — Ground GND — Gro.
Rev. 5.00, 09/0 3, page 234 of 760 IC Memory Card Interface I/O Card Interface Pin Signal I/O Function Signal I/O Function SH7709S Pin 31 D1 I/O Data D1 I/O Data D1 32 D2 I/O Data D2 I/O Data D2 33 W .
Rev. 5.00, 09/03, pa ge 235 of 760 IC Memory Card Interface I/O Card Interface Pin Signal I/O Function Signal I/O Function SH7709S Pin 61 REG I Attribute memory space sele ct REG I Attribut e memory s.
Rev. 5.00, 09/0 3, page 236 of 760 Bit 15—Pin A25 to A0 Pull-Up (PULA): Specifies w hether or n ot pins A25 to A 0 are pulled u p for 4 cy cles immediately after BACK is asse rted.
Rev. 5.00, 09/03, pa ge 237 of 760 Bits 10 and 9 —Area 0 Bur st ROM Contro l (A0BST1, A0BST0 ): Specify whether to use b urst ROM in physical space are a 0.
Rev. 5.00, 09/0 3, page 238 of 760 Bit 6: A6BS T1 Bit 5: A6BST0 Description 0 0 Access area 6 accessed as ordin ary me mory (initial val ue) 1 Burst acc ess of area 6 ( 4 conse cutive a ccesses). Can be used w hen bus width is 8, 16, or 32. 1 0 Burst access of area 6 (8 consecut ive accesses).
Rev. 5.00, 09/03, pa ge 239 of 760 Bit 0—Area 6 Bu s Typ e (A6PCM): Designates whether to access physical space area 6 as PCMCIA space. Bit 0: A6PCM Description 0 Physical spac e area 6 ac ces s ed as ord inary m emory (Initial value) 1 Physica l space area 6 ac ces sed as PCMCIA space 10.
Rev. 5.00, 09/0 3, page 240 of 760 Bit 2n + 1: A n SZ1 Bit 2n: AnSZ0 Port A / B Description 0 0 Not used Reserved (Setting pr ohibited) 1 Byte (8-bit) size 1 0 W ord (16-bit) size 1 Longword (32-bit) siz e 0 0 Used Res e rved (Setting prohibited) 1 Byte (8-bit) size 1 0 W ord (16-bit) size 1 Reserved (Settin g prohibited) 10.
Rev. 5.00, 09/03, pa ge 241 of 760 Bit 15—WAIT Sampling Ti ming Select (WAIT SEL): Specifies the WAIT signal s ampling timing. Bit 15: WA ITSEL Description 0 Setting to 1 w hen using the WA IT signal * (Initi al value) 1 Sampled WAIT signal at fall of CKIO Note: * Operation is not guar anteed if WAIT is asserte d while W E ITSEL = 0.
Rev. 5.00, 09/0 3, page 242 of 760 Bits 15 t o 13—Area 6 Wait Con trol (A6W2, A 6W1, A6W0): Specify t he num ber of wait stat es inserted in ph ysical space area 6 .
Rev. 5.00, 09/03, pa ge 243 of 760 Bits 9 to 7—Area 4 Wait Contro l (A4W2, A4W1, A4W0) : Specify the n umber of w ait states inserted in physical space area 4.
Rev. 5.00, 09/0 3, page 244 of 760 Bits 4 and 3 —Area 2 Wai t Control (A 2W1, A2W 0): Specify the number of wait states inserted in physi cal space area 2.
Rev. 5.00, 09/03, pa ge 245 of 760 10.2.5 Ind ividual Me m ory Control Regis ter (MCR) The individual memory con trol register (MCR) is a 16-bit readable/ writable register that specifi es RAS and CAS timing for s ynchronous DRAM ( areas 2 and 3), specifies address multipl exing, and controls ref resh.
Rev. 5.00, 09/0 3, page 246 of 760 Bits 13 and 12—RAS–CAS Delay (RCD1, RCD0): When syn c hronous DRAM interface is selected as con nected mem ory, these bits set the bank active read/write command delay time.
Rev. 5.00, 09/03, pa ge 247 of 760 Bits 6 to 3—Addres s Multip l ex (AMX3, AMX2, AMX1, AMX0): Specify address multiplexi ng for s ynchr o no us DR AM.
Rev. 5.00, 09/0 3, page 248 of 760 Bit 1—Refresh Mod e (RMODE): Selects w hether t o perform an ordinar y refresh or a self- refr e sh whe n the RFS H b i t is 1 . When the RFSH bit is 1 and this bit is 0, an auto-refr esh i s per fo rmed on synchronous D RAM at the peri od set by ref resh- rela t ed r eg iste r s RTCN T, RTCOR, and RTCSR.
Rev. 5.00, 09/03, pa ge 249 of 760 Bit 15—Area 6 Wait Co ntrol (A6W3): Specif ies the number of inserted w ait states for area 6 combin ed with bits A6W2–A 6W0 in WCR2. A lso specifies t he number of transfer states in burs t transfer. Clear this bit to 0 when area 6 is not set to PCMCIA.
Rev. 5.00, 09/0 3, page 250 of 760 Bits 11 , 7, and 6 —Area 5 Ad d ress O O O OE E E E / W W W WE E E E Assert Delay (A5TED2, A5TED1, A5TED0 ): Specify the delay tim e from address output to OE / WE assertion for the P CMCI A interface connected to area 5.
Rev. 5.00, 09/03, pa ge 251 of 760 Bits 9, 3, and 2—Area 5 O O O OE E E E / W W W WE E E E Negate Addres s Delay (A5T EH2, A5TE H1, A5TEH0): Specify the address hold dela y time from OE / WE negation for th e PCMCIA interface connected to area 5. Bit 9: A5T EH 2 Bit 3: A5T EH 1 Bit 2: A5TEH0 Descr iption 0000 .
Rev. 5.00, 09/0 3, page 252 of 760 10.2.7 Synchron ous DRAM Mode Re gister (SDMR) The s ynchrono u s DRAM mode regist e r (SDMR) is an 8-bit wri te-only registe r that is written to via th e syn chron ous DRAM address bus. It s e t s synchronou s DRAM mode for areas 2 and 3.
Rev. 5.00, 09/03, pa ge 253 of 760 10.2.8 Refresh Timer Control/Status Register (RT CSR) The r efresh ti me r co ntr ol/stat us registe r (RTCSR) is a 16-bit readable/ writable register that spec i fie s the re fr e sh cyc l e, wh e ther to ge ner ate an int errup t, an d the cycl e of th a t in terru pt.
Rev. 5.00, 09/0 3, page 254 of 760 Bits 5 to 3—Clock Select Bits (CKS2 to CKS0): Select the c lock inp ut t o RT CN T. The so urce clock is the external bus clock ( CKIO). The R TCNT count clock is CKIO divided by the specified ratio. RT COR must be set b efore setti n g CKS2-CKS0 .
Rev. 5.00, 09/03, pa ge 255 of 760 Bit 0—Refresh Count Overflow Limit Select (LMTS): Indicates the count limit value to be compa r ed t o the n umb e r o f re fr es he s i ndic ated in the r efre sh co u nt regi ste r (RFCR ) . When the value in RFCR ov erflows the value specified by LMTS, the OVF flag is set.
Rev. 5.00, 09/0 3, page 256 of 760 10.2.10 Refres h Time Cons tant Register (R TCOR) The refresh time constant r egister (RTCOR) sp ecifies the upper-limit valu e of RTC NT .
Rev. 5.00, 09/03, pa ge 257 of 760 Bit: 15 14 13 12 11 10 9 8 I n i t i a l v a l u e : 00000000 R / W : —————— R / W R / W B i t : 76543210 I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W 10.
Rev. 5.00, 09/0 3, page 258 of 760 10.2.13 MCS0 Contr ol Register (MCSCR 0) The MCS0 control regi ster (MCSCR0) is a 16-bit readable/ w ritable register that specifies the MCS[0] pin output conditions. MCSCR0 is initialized to H'0000 b y a p ower-on reset, but is not initialized by a manual reset or in standby mode.
Rev. 5.00, 09/03, pa ge 259 of 760 10.2.14 MCS1 Contr ol Register (MCSCR 1) The MCS1 contro l register (MCS CR1) specifies the MCS [1] pin output conditions.
Rev. 5.00, 09/0 3, page 260 of 760 10.3 BSC Operation 10.3.1 Endian/Access Size and Data Alignment The SH7709S su pport s both bi g endian, in which the 0 address is the most signif i cant byte in the byte data, and little endian, in which the 0 address is the least sig ni fica nt byte.
Rev. 5.00, 09/03, pa ge 261 of 760 Table 10.8 16-Bit Extern al Device/Big-En d ian Access an d Data Alignm ent Data Bus St robe Signals Operation D31– D24 D23– D16 D15–D8 D7–D0 W W W WE E E E3.
Rev. 5.00, 09/0 3, page 262 of 760 Table 10.9 8-Bit Extern al Device/Bi g-Endi an Access and D ata Alignm ent Data Bus Strobe Si gnals Operation D31– D24 D23– D16 D15– D8 D7–D0 W W W WE E E E3.
Rev. 5.00, 09/03, pa ge 263 of 760 Table 10.10 32-Bit Extern al Device/L ittle-Endian Access and Data Alignm ent Data Bus Strobe Signals Operation D31–D24 D23–D16 D15–D8 D7–D0 W W W WE E E E3 .
Rev. 5.00, 09/0 3, page 264 of 760 Table 10.12 8-Bit External De vice/Littl e-Endian Access and Data A lignm e nt Data Bus Strobe Signals Operation D31– D24 D23– D16 D15–D8 D7–D0 W W W WE E E .
Rev. 5.00, 09/03, pa ge 265 of 760 10.3.2 Description of Areas Area 0: Area 0 p hysical address b its A28–A26 are 000. Addre ss bits A31–A29 are i gnored and the address ran ge is H'00000000 + H ' 20000000 × n – H'03FFFFFF + H' 20000000 × n (n = 0–6 and n = 1–6 are the shadow spaces).
Rev. 5.00, 09/0 3, page 266 of 760 Area 3: Area 3 p hysical address b its A28–A26 are 011. Addre ss bits A31–A29 are i gnored and the address ran ge is H'0C000000 + H'20000000 × n – H'0FFFFFFF + H'2000000 0 × n (n = 0–6 and n = 1–6 are the shadow spaces).
Rev. 5.00, 09/03, pa ge 267 of 760 When the area 5 space is accessed and ordinary memory is connect ed, the CS5 signal is asserted. The RD signal that can be used as OE and the WE0 – WE3 signals for w rite control are also asserted.
Rev. 5.00, 09/0 3, page 268 of 760 10.3.3 Basic I nterface Basic T i mi ng: The basic interface of the SH7709S us es strobe sig nal output in consideration of th e f act t hat mainl y stati c RAM w i ll b e di re ctly c o nnected. F igure 10.6 show s the basic timing of normal space acc esses.
Rev. 5.00, 09/03, pa ge 269 of 760 T 1 CKIO A25 to A0 CSn RD/WR RD D31 to D0 WEn D31 to D0 BS T 2 Read Write Figu re 10.6 Bas ic Timing of Bas ic In terf ace.
Rev. 5.00, 09/0 3, page 270 of 760 Figures 10.7, 10.8, an d 10.9 sh ow exampl es of con nection to 32, 16 , and 8-bit data -w idth static RAM, respectively.
Rev. 5.00, 09/03, pa ge 271 of 760 A16 A0 CS OE I/O7 I/O0 WE •••• •••• •••• •••• A17 A1 CSn RD D15 D8 WE1 D7 D0 WE0 SH7709S 128k × 8-bit SRAM •••• A16 A0 CS OE I/O7 I/O0 WE •••• •••• •••• •••• •••• •••• •••• •••• Figure 10.
Rev. 5.00, 09/0 3, page 272 of 760 A16 A0 CSn RD D7 D0 WE0 SH7709S 128k × 8-bit SRAM •••• A16 A0 CS OE I/O7 I/O0 WE •••• •••• •••• •••• •••• •••• •••• Figure 10.
Rev. 5.00, 09/03, pa ge 273 of 760 Wait Stat e Co ntrol: Wait state insertion on the basic interface c an be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software w ait is inserted in accordance with that specification.
Rev. 5.00, 09/0 3, page 274 of 760 When so ftware wait i nsertio n is sp ec ified by WCR 2, the ext ernal wait input WA IT signa l is also sampled. WAIT pin sam pling i s sh own in figure 10.
Rev. 5.00, 09/03, pa ge 275 of 760 T 1 CKIO A25 to A0 CSn RD/ WR RD D31 to D0 WEn D31 to D0 WAIT Tw Tw Tw T 2 Read Write BS Wait states inserted by WAIT signal Figure 10.
Rev. 5.00, 09/0 3, page 276 of 760 10.3.4 Synchron ou s DRAM Interface Synchronous DRAM Direct Connection: Since synchronous DRAM can be selected by th e CS signal, phy sical space areas 2 and 3 can be connected us ing RAS and other control sig nals in common.
Rev. 5.00, 09/03, pa ge 277 of 760 A15 A2 CKI0 CKE CSn RAS3x CASx RD/ WR D31 D16 DQMUU DQMUL D15 D0 DQMLU DQMLL SH7709S 64M synchronous DRAM (1M × 16-bit × 4-bank ) •••• A13 A0 CLK CKE CS RA.
Rev. 5.00, 09/0 3, page 278 of 760 SH7709S 64M synchronous DRAM (1M × 16 bit × 4 bank) A14 A13 A12 A1 CKIO CKE CSn RAS3x CASx RD/ WR D15 D0 DQMLU DQMLL A13 A12 A1 1 A0 CLK CKE CS RAS CAS WE DQ15 DQ0 DQMU DQML ••• ••• ••• ••• ••• ••• ••• ••• Figure 10.
Rev. 5.00, 09/03, pa ge 279 of 760 Table 10.13 Relationship bet ween Bus Width, AMX Bits, and Address Multiplex Output Setting External A ddress Pins Bus Widt h Memo ry Ty pe AM X 3 AM X 2 AM X 1 AM X.
Rev. 5.00, 09/0 3, page 280 of 760 Setting External A ddress Pins Bus Widt h Memo ry Ty pe AM X 3 AM X 2 AM X 1 AM X 0 Output Tim in g A1 t o A8 A9 A1 0 A1 1 A1 2 A1 3 A1 4 A1 5 A1 6 2M × 16bits × 4.
Rev. 5.00, 09/03, pa ge 281 of 760 Table 10.1 4 Exa mple of Correspo ndence between SH7709S an d Synchronous DRAM Address Pi n s (AMX [3:0] = 0100 (32-Bi t Bus Width )) SH7709S Addr ess Pin Synchronou.
Rev. 5.00, 09/0 3, page 282 of 760 indepen dently for areas 2 and 3 b y m eans of bits A2W1 and A2W0 or A3W 1 and A3W 0 in WCR2. This num ber of cycles correspon ds to the number of sy nchronous DRAM CAS l a t e n c y cycles.
Rev. 5.00, 09/03, pa ge 283 of 760 Figure 10.15 s hows the burs t read timi ng when RCD is set to 1, A3W 1 and A3W0 are set to 10, and TPC is set to 1. The B S cycle, whic h i s asserte d for o ne c ycle at the s tart of a bus cycle fo r n ormal acces s space, is asserted in each of cycles Td1–Td4 in a sy n chron ous DRAM cycle.
Rev. 5.00, 09/0 3, page 284 of 760 Single Read: Figure 10.16 show s the timing when a single addre ss read is perfor med. As the b urst length is set to 1 in synchro nous DRA M burst rea d/sing le wr ite mode, only the re quired data is output. Co nseque ntly, no unneces sar y bus cycles are gener ated e ven whe n a cache-thr ough area is accessed.
Rev. 5.00, 09/03, pa ge 285 of 760 Burst Write: The tim i n g chart for a burst write is shown in figure 10.17. In the SH7709S , a burst write o cc ur s o nly i n t he event of c a che wri t e-b ack o r 16- byte D MAC t ran sf er.
Rev. 5.00, 09/0 3, page 286 of 760 CKIO CSn RD/ WR RAS3x CASx DQMxx D31 to D0 (read) BS Tr Tc1 Tc2 Tc3 Tc4 (Trwl) (Tpc) A ddress upper bits A 12, A11, A 10 or A9 A ddress lower bits Figure 10.
Rev. 5.00, 09/03, pa ge 287 of 760 Single Write: T he basic tim ing chart for w rite acce ss is shown in figure 10.18. In a single w rite operation, f ollowing the Tr cycle in which ACTV com mand outp ut is performed, a W RITA command that perf orms auto-precharge is issued in t he Tc1 cycle.
Rev. 5.00, 09/0 3, page 288 of 760 CKIO CSn RD/ WR RAS3x CASx DQMxx D31 to D0 BS A ddress upper bits A 12 or A10 A ddress lower bits CKE Tr Tc1 (Trwl) (Tpc) Figure 10.
Rev. 5.00, 09/03, pa ge 289 of 760 Bank Active: The sy nchronous DRAM bank function is us ed to support h igh-s peed accesses to the same row addres s. When the RASD bit in MCR is 1, read/write command accesses are perform ed using comm ands without auto-precharge (READ, WRIT).
Rev. 5.00, 09/0 3, page 290 of 760 A Tnop cycle, in which no opera tion is performed, is inserted before the T c cycle in which the READ command is i ss u ed in figure 10.20, bu t when syn chron ous DRAM is read, there is a tw o- cycle latency for the DQMxx signal that perf orms the byte specification.
Rev. 5.00, 09/03, pa ge 291 of 760 CKIO A 25 to A16, A 13 (A25 to A 16, A11) A 12 (A10) A 15, A14, A 11 to A0 (A15 to A12, A 9 to A0) CS2 or CS3 RAS3x CASx RD/ WR DQMxx D31 to D0 BS Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 Figure 10.
Rev. 5.00, 09/0 3, page 292 of 760 CKIO A 25 to A16, A 13 (A25 to A 16, A11) A 12 (A10) A 15, A14, A 11 to A0 (A15 to A12, A 9 to A0) CS2 or CS3 RAS3x CASx RD/ WR DQMxx D31 to D0 BS Tnop Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 Figure 10.
Rev. 5.00, 09/03, pa ge 293 of 760 CKIO A 25 to A16, A 13 (A25 to A 16, A11) A 12 (A10) A 15, A14, A 11 to A0 (A15 to A12, A 9 to A0) CS2 or CS3 RAS3x CASx RD/ WR DQMxx D31 to D0 BS Tp Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 Figure 10.
Rev. 5.00, 09/0 3, page 294 of 760 CKIO A 25 to A16, A 13 (A25 to A 16, A11) A 12 (A10) A 15, A14, A 11 to A0 (A15 to A12, A 9 to A0) CS2 or CS3 RAS3x CASx RD/ WR DQMxx D31 to D0 BS Tr Tc1 Tc2 Tc3 Tc4 Figure 10.
Rev. 5.00, 09/03, pa ge 295 of 760 CKIO A 25 to A16, A 13 (A25 to A 16, A11) A 12 (A10) A 15, A14, A 11 to A0 (A15 to A12, A 9 to A0) CS2 or CS3 RAS3x CASx RD/ WR DQMxx D31 to D0 BS Tc1 Tc2 Tc3 Tc4 Figure 10.
Rev. 5.00, 09/0 3, page 296 of 760 CKIO A 25 to A16, A 13 (A25 to A 16, A11) A 12 (A10) A 15, A14, A 11 to A0 (A15 to A12, A 9 to A0) CS2 or CS3 RAS3x CASx RD/ WR DQMxx D31 to D0 BS Tp Tr Tc1 Tc2 Tc3 Td4 Figure 10.
Rev. 5.00, 09/03, pa ge 297 of 760 Refreshing: T he bus state controller is provided with a function for contro lling synchronous DRAM ref reshing. Auto-ref reshing can be perform ed by clearing the RMODE bi t to 0 and setting the RFSH bit to 1 in MCR.
Rev. 5.00, 09/0 3, page 298 of 760 RTCOR value RTCNT H'00000000 RTCSR.CKS(2 to 0) CMF External bus CMF flag cleared by start of refresh cycle = 000 ≠ 000 RTCNT cleared to 0 when RTCNT = RTCOR Auto-refresh cycle Time Figure 10.
Rev. 5.00, 09/03, pa ge 299 of 760 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U , RAS3L CASU , CASL RD/ WR Figure 10.26 Synchronous DRAM Auto-Refresh Timing.
Rev. 5.00, 09/0 3, page 300 of 760 • Self-Ref re shing Sel f-ref resh mod e is a k ind o f sta ndby mode in wh ich t he ref res h timin g an d re fres h addr esses are generated within the synchron ous DRAM. Self-refreshing is activated by setting both th e RMODE bit and the R FSH bit to 1.
Rev. 5.00, 09/03, pa ge 301 of 760 TRs1 CKIO RD/WR CSn RAS3U, RAS3L CASU, CASL CKE (TRs2) (TRs2) TRs3 (Tpc) (Tpc) Tp Figure 10.27 S ynchronous DRAM Self-Refres h Timing • Relation ship be tween Ref .
Rev. 5.00, 09/0 3, page 302 of 760 Power-On Sequence: In order to use sy nchron ous DRAM, m ode setting must first be perf ormed after po wering on. To perform synchr onous DRAM initializ ati on correctly, the bus s tate con tr oller regist ers must first be set, f ollo wed by a w rite t o the sy nchronous DRAM m ode register.
Rev. 5.00, 09/03, pa ge 303 of 760 Before m ode register se tting, a 100 µ s idle time (depending on the m emory manufacturer) must be guarant eed aft e r powe ring on requested by the synchronous DRAM . If th e reset s ignal pu l s e width is greater than this idle time, there is no problem in performing mode register setting immediately.
Rev. 5.00, 09/0 3, page 304 of 760 10.3.5 Burst R OM Interface Setting bits A0BST1–0, A5BST1–0, and A 6BST1–0 in BCR1 to a n on-zero va lue all ows burst ROM to be connected to areas 0, 5, and 6. Th e burst ROM interface provide s high-speed access to ROM that ha s a nibb le access funct i on.
Rev. 5.00, 09/03, pa ge 305 of 760 T 1 T W T W T B2 T B1 T W T B2 CKIO A 25 to A4 A 3 to A0 CSn RD/ WR RD D31 to D0 BS WAIT T 2 Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Rev. 5.00, 09/0 3, page 306 of 760 T 1 T B2 T B1 T B2 T B1 T B2 T B1 T 2 CKIO A25 to A4 A3 to A0 CSn RD/ WR RD D31 to D0 BS WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Rev. 5.00, 09/03, pa ge 307 of 760 10.3.6 PCMCIA Interface In th e SH7709S , se t t in g th e A5PC M bit i n BCR1 to 1 makes the b u s int erface for p hysic a l space area 5 an IC mem ory card and I/O card interface as stipulated i n JEIDA version 4 .
Rev. 5.00, 09/0 3, page 308 of 760 A24 to A0 D15 to D0 RD/WR CE1B/(CS6) CE1A/(CS5) RD WE1 ICIORD ICIOWR WAIT IOIS16 SH7709S A25 to A0 D15 to D0 CE2 OE WE/PGM (IORD) (IOWR) WAIT (IOIS16) CD1, CD2 CE1 P.
Rev. 5.00, 09/03, pa ge 309 of 760 Memory Card In terface Basic Timing: Fig ure 10.32 show s the basic timing for t he PCMC IA IC memory card interface. When phy sical sp ace areas 5 and 6 are designated as PCMCIA interface areas, bus accesses are automatically pe rformed as IC memory card interface accesses.
Rev. 5.00, 09/0 3, page 310 of 760 CKIO Tpcm1 Tpcm2 A 25 to A0 CExx RD/ WR D15 to D0 (read) D15 to D0 (write) RD (read) WE (write) BS Figure 10.32 Basi c Timing for PCMCIA Memory Card Interface.
Rev. 5.00, 09/03, pa ge 311 of 760 CKIO Tpcm0 A 25 to A0 RD/ WR CExx RD (read) D15 to D0 (read) D15 to D0 (write) WE (write) BS WAIT Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w Figure 10.
Rev. 5.00, 09/0 3, page 312 of 760 Memory Card In terface Burst Timing: In th e SH7709S, w he n the IC memor y card interface is selected, page m ode burst access m ode can be used, for read access only , by setting bit s A5B ST1 and A 5BST0 in BCR1 f o r physical space area 5, or bit s A6BST1 a nd A6BS T0 in BCR1 for area 6.
Rev. 5.00, 09/03, pa ge 313 of 760 CKIO Tpcm0 A25 to A4 CExx A3 to A0 RD/WR RD (read) D15 to D0 (read) BS WAIT Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w Figure 10.
Rev. 5.00, 09/0 3, page 314 of 760 When the entire 32 -Mbyte mem ory s pace is used as IC memory card inte rface space, the common memory/attribute memor y switching signal REG is generate d using a port, etc.
Rev. 5.00, 09/03, pa ge 315 of 760 I/O Card In terface Timing: Figu res 1 0.37 a nd 10 .38 s how the timing for t he PCMC IA I/O car d interface. Switching between the I/O card interface and the IC memory card inte rface is perfo rmed according to the a c ce sse d ad d r es s.
Rev. 5.00, 09/0 3, page 316 of 760 CKIO Tpci1 Tpci2 A 25 to A0 RD/ WR CExx ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS Figure 10.
Rev. 5.00, 09/03, pa ge 317 of 760 CKIO A 25 to A0 RD/ WR CExx ICIORD (read) ICIOWR (write) D15 to D0 (read) D15 to D0 (write) BS WAIT IOIS16 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w Figure 10.
Rev. 5.00, 09/0 3, page 318 of 760 CKIO Tpci0 A 25 to A1 CExx A 0 RD/ WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS WAIT IOIS16 Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w Figure 10.
Rev. 5.00, 09/03, pa ge 319 of 760 10.3.7 Waits between Access Cycles A problem as sociated with higher ex ternal memory bus operating f r eque ncie s is that data buffer turn-off on completion of a read from a low-speed device may be t oo slow, c ausing a collision with data in the next access.
Rev. 5.00, 09/0 3, page 320 of 760 T 1 CKIO CSm CSn A 25 to A0 BS RD/ WR RD D31 to D0 T 2 Twait T 1 T 2 Twait T 1 T 2 Area m read Area m inter-access wait specification Area n inter-access wait specification Area n space read Area n space write Figure 10.
Rev. 5.00, 09/03, pa ge 321 of 760 I I I IR R R RQ Q Q QO O O OU U U UT T T T Pin Assertio n Condition s: • When a me mor y re fre sh r eque st has be en gener ated bu t the refr esh cy cl e has n o.
Rev. 5.00, 09/0 3, page 322 of 760 Pull-up CKIO D31 to D0 RD CSn Pull-up Figure 10.42 Pu ll-Up T iming for Pi ns D31 to D0 (Read Cycle) Pull-up CKIO D31 to D0 WEn CSn Pull-up Figure 10.
Rev. 5.00, 09/03, pa ge 323 of 760 10.3.10 M M M MC C C CS S S S[ [ [ [0 0 0 0] ] ] ] to M M M MC C C CS S S S[ [ [ [7 7 7 7] ] ] ] Pin Control The SH7709S i s prov ided wi th pin s MCS[ 0] – MCS[7] as dedicated CS pins for the R OM connected to area 0 or 2.
Rev. 5.00, 09/0 3, page 324 of 760 Table 10. 15 MCSCRx Setting s and M M M MC C C CS S S S[ [ [ [x x x x] ] ] ] Assertion Con ditions (x: 0–7) MCSCRx Settin gs M M M MC C C CS S S S[ [[ [x x x x] ]].
Rev. 5.00, 09/03, pa ge 325 of 760 MCSCRx Settin gs M M M MC C C CS S S S[ [[ [x x x x] ]] ] A ssertion Conditions CS 2/ 0 C AP 1 C AP 0 A2 5 A2 4 A2 3 A2 2 C C C CS S S S0 0 0 0C C C CS S S S2 2 2 2 .
Rev. 5.00, 09/0 3, page 326 of 760.
Rev. 5.00, 09/03, pa ge 327 of 760 Section 11 Direct Memory Access Controller (DMAC) 11.1 Overview The SH7709S includes a four-channel direct memory access controller (DMAC).
Rev. 5.00, 09/0 3, page 328 of 760 Channel 3: In th is ch a nnel, direct address mode or indirect address trans fer m ode can be specified. • Reload function: The value th at was specified in the source address register can be automatically reloaded ev ery four DMA transfers.
Rev. 5.00, 09/03, pa ge 329 of 760 11.1.2 Block D iagram Figure 11.1 s hows a block diagram of the DMAC . Peripheral bus Internal bus DREQ0 , DREQ1 Iteration control SARn DMAC module Register control .
Rev. 5.00, 09/0 3, page 330 of 760 11.1.3 Pin C onfigurati on Table 11.1 sh ows th e DM AC pins. Table 11.1 DMAC Pins Channel Name Sy mbol I/O Function 0 DMA transfer requ est DREQ0 I DMA transfer req.
Rev. 5.00, 09/03, pa ge 331 of 760 11.1.4 Register C onfiguration Table 11.2 summarizes the DMAC registers. The DMAC has a total of 17 reg isters: each channel has four reg isters, and one overall DMAC c ontrol register.
Rev. 5.00, 09/0 3, page 332 of 760 Channel Name Ab br e v i - ation R /W Initial Va lue Addre ss Register Size A c cess Size 3 DMA sourc e address register 3 SAR3 R/W Undefined H'04000050 (H&apos.
Rev. 5.00, 09/03, pa ge 333 of 760 11.2 Register Descriptions 11.2.1 DMA Source Address Regis ters 0–3 (SAR0–SAR3) DMA source address re gisters 0–3 (SAR0–SAR3) are 32-bit readable/ writable registers that specify the source address of a D MA transfer.
Rev. 5.00, 09/0 3, page 334 of 760 11.2.2 DMA Destination Address Regi sters 0–3 (DAR0–DAR3) DMA destin a tion address registers 0–3 (DA R0–DAR3) are 32-bit reada ble/ writabl e reg is t ers that specify the destination address of a DMA transfer.
Rev. 5.00, 09/03, pa ge 335 of 760 11.2.3 DMA Trans fer Count Regis ters 0–3 (DMATCR0–D M ATCR3) DMA t ransfer count registers 0–3 (DMATCR0–D MATCR3) are 24-bit readable/w ritable reg isters that specify the DMA transfer count (bytes, w o rds, or longwords).
Rev. 5.00, 09/0 3, page 336 of 760 11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) DMA chann el control regi sters 0–3 (CHCR 0–CHCR3) are 32-bit readable/writable reg isters that specify the operation mode, transfer m ethod, etc., for each channel.
Rev. 5.00, 09/03, pa ge 337 of 760 Bits 31 t o 21—Reserved: T hese bits are a lways read as 0. The write va lue shoul d always b e 0. Bit 20—Direct/Indirect Selection (DI): Sel ect s direct address mode or indirect addres s m ode in channel 3. This bit is onl y valid in C HCR3.
Rev. 5.00, 09/0 3, page 338 of 760 Bit 17—Ackn owledge Mode Bit (A M): Specifies wheth er DACK is output in the data read cycle or in t he data wri te cycle in du al address mode. DACK is always output i n single addre ss mode, regardless of this bit specificati on.
Rev. 5.00, 09/03, pa ge 339 of 760 Bits 13 and 12—Source Address Mode Bits 1 and 0 (SM1, SM0): Select w hether the DMA sou rce a ddr es s i s i ncreme nted , d ecr em ente d, or le ft f ixed.
Rev. 5.00, 09/0 3, page 340 of 760 Bits 11 t o 8—Resource Select Bits 3 to 0 (RS3 to RS0 ): Specify which tra nsfer r e quests w ill be sent to th e D MAC.
Rev. 5.00, 09/03, pa ge 341 of 760 Bit 6— D D D DR R R RE E E EQ Q Q Q Select Bit (DS): Selects low-level or falling -edge detection a s the samplin g method for t h e DREQ pin used in extern al requ est mode. This bit is only val i d in CHCR0 and CHCR 1.
Rev. 5.00, 09/0 3, page 342 of 760 Bit 1—Trans fer End Bit (TE): Set to 1 on completion of the number of data transfers specified in DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated.
Rev. 5.00, 09/03, pa ge 343 of 760 11.2.5 DMA Operation Register (DMA OR) The DMA operation register (DMAOR) is a 16-bit readable/ w ritable register that controls the DMAC transfer mode. These r egister va l ues are i nitialize d to 0 in a r eset. Th e pr evi ous value is r etain ed in stan d by mode.
Rev. 5.00, 09/0 3, page 344 of 760 Bit 2—Address E rror Flag Bit (AE): Indicates th at an address error occurred b y the DMAC. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to this bit. This bit can only be cleared by writing 0 after reading 1.
Rev. 5.00, 09/03, pa ge 345 of 760 11.3 Operation When there is a DMA transfer request, the DMA C starts the transfer according to the predetermined channel p riority order ; when the transfer e nd conditio ns are satisfied, it ends the transfer.
Rev. 5.00, 09/0 3, page 346 of 760 Normal end AE = 1 or NMIF = 1 or DE = 0 or DME = 0? Bus mode, transfer request mode, DREQ detection selection system Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR).
Rev. 5.00, 09/03, pa ge 347 of 760 11.3.2 DMA Transfer R equests DMA transfer requests are basical ly generated in ei the r the data transfer sourc e or destin ati on, but they can also be generated by devices and on-chip periphera l modules that are neither the source nor the destination .
Rev. 5.00, 09/0 3, page 348 of 760 request sign al. T he source of the transfer req uest does not have to be the data transfe r source or destination. W hen RXI is s et as the transfer request, however, the t ransfer source mus t be the S CI's receive data register (RDR).
Rev. 5.00, 09/03, pa ge 349 of 760 11.3.3 Channe l Priority When the DMAC receives simultaneo us transfer requests on two or m ore channels, it se lects a channel according to a predeterm ined priority order. Two m odes (fixed m ode and round-robi n mode) are s elected by pri ority bit s PR1 an d PR0 in the DMA operati on reg ister (DMAOR).
Rev. 5.00, 09/0 3, page 350 of 760 CH1 > CH2 > CH3 > CH0 CH0 > CH1 > CH2 > CH3 CH2 > CH3 > CH0 > CH1 CH0 > CH1 > CH2 > CH3 CH2 > CH3 > CH0 > CH1 CH0 > C.
Rev. 5.00, 09/03, pa ge 351 of 760 Figure 11.4 show s ho w the priority order chang es when ch annel 0 and channel 3 transfers are requested simultan eously and a channel 1 transfer i s requested during the channel 0 tran sfer . The DMAC opera tes as follows: 1.
Rev. 5.00, 09/0 3, page 352 of 760 11.3.4 DMA Transfer T ypes The DMAC supports th e transfers sh own in ta ble 11.5. Dual address mode has a direct address mode and i ndirect address mode.
Rev. 5.00, 09/03, pa ge 353 of 760 (1) In direct address transfer m ode, DMA transfer requires two bu s cycles b ecause data is read from the transfer s ource in a data read cy cle and written to the trans fer destination in a data write cycle. At this time, transfer data is temporaril y stored in the DMAC.
Rev. 5.00, 09/0 3, page 354 of 760 (1st cycle) (2nd cycle) Data read cycle Data write cycle Transfer source address Transfer destination address CKIO A25 to A0 CSn D31 to D0 RD WEn DACKn Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn .
Rev. 5.00, 09/03, pa ge 355 of 760 Memory Transfer source module Transfer destination module SAR3 DAR3 Data buffer Temporary buffer D M A C When the value in SAR3 is an address, the memory data is read and the value is stored in the temporary buffer. The value to be read must be 32 bits since it is used for the address.
Rev. 5.00, 09/0 3, page 356 of 760 T ransfer source address (H) T ransfer source address (L) Indirect address NOP T ransfer destination address Indirect address (H) Indirect address (L) T ransfer data.
Rev. 5.00, 09/03, pa ge 357 of 760 • Sing le Addres s Mode In sing le addres s mode, eit her the transfer source or tran sfer destination peripheral device is accessed (selected) by means of the DACK s ignal, and the other dev ice is accessed by address.
Rev. 5.00, 09/0 3, page 358 of 760 Address output to external memory space Data output from external device with DACK DACK signal (active-low) to external device with DACK Write strobe signal to exter.
Rev. 5.00, 09/03, pa ge 359 of 760 CKIO A25 to A0 D31 to D0 RD WEn DACKn CSn Transfer source address +4 +8 +12 Figure 11 .11 E xample of DMA Transfe r Timing in Single A ddre ss Mode (16-byte Trans fer, External Memory Space (Ordinary Memory) → → → → External Device with DACK) Bus M odes: There are two bus modes: cycle-steal and burst.
Rev. 5.00, 09/0 3, page 360 of 760 CPU CPU CPU DMAC DMAC CPU DMAC DMAC CPU CPU DREQ Bus cycle Bus returned to CPU Read Write Write Read Figure 11.12 Example of DMA Transfer in Cycle-Steal Mode • Burst Mode Once the bus is obtain ed, the transf er is performed con tinuously until the transfer e nd condition is satisfied.
Rev. 5.00, 09/03, pa ge 361 of 760 Relationship between Reque st Modes and Bus M odes by DMA Transfer Category: Tabl e 11. 6 sho ws the rela t i o nship be twe en r eques t modes and bus m ode s by DMA t ransf e r cate g ory.
Rev. 5.00, 09/0 3, page 362 of 760 Bus M ode and Channel P riority Order: When, for example, channel 1 is transferring in burst mode and there is a transfer request to channel 0, which has higher priority, the channel 0 transfer will b egi n imme dia tel y.
Rev. 5.00, 09/03, pa ge 363 of 760 11.3.5 Num ber of Bus C ycle States an d D D D DR R R RE E E EQ Q Q Q Pin S ampling Timing Number of Bus Cycle States : When the DMAC is the bus master, the num ber of bus cycle st ates is controlled by the bus state control ler (BSC) in the same way as when the CPU is the bus master.
Rev. 5.00, 09/0 3, page 364 of 760 • Burst Mode, Level Detection In the case of burst mode with level detection, the DREQ samplin g timing is the same as in cycle-steal mode. For example, in figure 11.20 , DMAC transfer begins, at the earliest, three cycles after the first sampl ing is performe d.
Rev. 5.00, 09/03, pa ge 365 of 760 CKIO DRAK DREQ DACK Bus cycle DMAC(R) CPU DMAC(W) DMAC(R) CPU DMAC(W) 1st sampling 2nd sampling 3rd sampling Figure 11.
Rev. 5.00, 09/0 3, page 366 of 760 CPU CPU CKIO DRAK DREQ DACK DMAC(R) DMAC(W) DMAC(R) 1st sampling 2nd sampling 3rd sampling Bus cycle Figure 11.16 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles.
Rev. 5.00, 09/03, pa ge 367 of 760 CKIO DRAK (High output) Bus cycle DREQ DACK (RD output) DMAC(W) CPU DMAC(W) DMAC(R) CPU 1st sampling 2nd sampling 3rd sampling Figure 11.
Rev. 5.00, 09/0 3, page 368 of 760 CKIO DRAK Bus cycle DREQ DACK (RD output) CPU CPU DMAC(W) DMAC(R) DMAC(W) DMAC(R) CPU 3rd sampling is performed, but since DREQ is high, per-cycle sampling starts 2nd sampling is performed, but since DREQ is high, per-cycle sampling starts 1st sampling 2nd sampling 3rd sampling Figure 11.
Rev. 5.00, 09/03, pa ge 369 of 760 CKIO DRAK Bus cycle DREQ DACK (RD output) CPU CPU DMAC(W) DMAC(R) DMAC(W) DMAC(R) CPU High High High High 3rd sampling is performed, but since there is no DREQ falli.
Rev. 5.00, 09/0 3, page 370 of 760 CKIO DRAK DREQ DACK Bus cycle DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) CPU 1st sampling 2nd sampling 3rd sampling Figure 11.
Rev. 5.00, 09/03, pa ge 371 of 760 CKIO DRAK DREQ DACK Bus cycle CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) 1st sampling Figure 11.21 Burst Mode , Edge Inp u t.
Rev. 5.00, 09/0 3, page 372 of 760 11.3.6 Source Address Reload Function Channel 2 includes a reload function, i n which the value is returned to the value set in the source add ress re gister (SAR 2 ) ev e ry f our t ran sf ers by set t ing the RO bi t in CH CR2 t o 1 .
Rev. 5.00, 09/03, pa ge 373 of 760 CK Internal address bus Internal data bus SAR2 DAR2 DAR2 DAR2 DAR2 SAR2+2 SAR2+4 SAR2+6 SAR2 SAR2 data SAR2+2 data SAR2+4 data SAR2+6 data First transfer on channel .
Rev. 5.00, 09/0 3, page 374 of 760 11.3.7 DMA Trans fer Endi ng Conditi ons The DMA transfer ending conditio ns are different for ending on an individual c hannel and ending on all cha nnel s toget her.
Rev. 5.00, 09/03, pa ge 375 of 760 Conditions fo r Ending on All Channels S imultaneo usly: Transfers on all ch annels end (1) when the AE or NMIF (NMI flag) bit is set to 1 in DMAOR, or (2) when the DME b it in DMAOR is cleared to 0.
Rev. 5.00, 09/0 3, page 376 of 760 11.4 Co mpare Match Timer (CMT) 11.4.1 Overvie w The DMAC has an on-chip compare match timer (CMT) to generate DMA tr ansfer requests.
Rev. 5.00, 09/03, pa ge 377 of 760 Register Configuratio n Table 11.7 summ arizes the CMT regis ter configuration. Table 11.7 Register Configuration Name Abbreviation R/W Initial Value Address Access .
Rev. 5.00, 09/0 3, page 378 of 760 Bit 0—Count Start 0 (STR0): Selects whether to operate or halt CMCNT 0. Bit 0: STR0 Description 0 CMCNT0 count opera tion halted (Initial valu e) 1 CMCNT 0 count o.
Rev. 5.00, 09/03, pa ge 379 of 760 Bit 6—Reserved: Thi s bi t ca n be rea d or writte n. The wit e valu e shou ld alw ays be 0 . Bits 1 and 0 —Clock Select 1 and 0 (CKS1, CKS0): Select th e cloc k inpu t to CM CNT from among t h e four internal clocks obt ai n ed by dividing the sys tem clock (P φ ).
Rev. 5.00, 09/0 3, page 380 of 760 Compare Match Cons tant Register 0 (C MCOR0) Compare match constant regis ter 0 (CMCOR0) is a 16- bit register that s ets the CMCNT0 compare match peri od. CMCOR0 is initial ized to H'FFFF b y a reset, but retains its previo us value in standb y mode.
Rev. 5.00, 09/03, pa ge 381 of 760 CMCNT0 Co unt Ti ming One of fou r clocks (P φ /4, P φ /8, P φ /16, P φ /64) obt ained by divi ding the P φ clock can be selected with the CKS1 and CKS0 bits in CMCSR0. Figure 11.26 shows th e timing . N+1 CK Internal clock CMCNT0 input clock CMCNT0 N-1 N Figure 11.
Rev. 5.00, 09/0 3, page 382 of 760 CK CMCOR0 CMCNT0 input clock Compare match signal CMF CMI CMCNT0 N N 0 Figure 11.27 CMF Setting Ti ming Compare Match Flag Clearing Timi ng The CMF bit in the CMCSR 0 register is cleare d by wri t ing 0 to it after reading 1 .
Rev. 5.00, 09/03, pa ge 383 of 760 11.5 Examples of Use 11.5.1 Exam ple of DMA Transfer between On-C hip IrDA and External Mem ory In th is example, receive data of the on- chip IrDA is transferred to extern al memory using DMAC channel 3. Tab le 11.8 shows the transfer conditions and register sett in gs.
Rev. 5.00, 09/0 3, page 384 of 760 11.5.2 Example of DMA Transfer be tween A/D Converter and E xternal Memory In t his exam ple, DMA transf er is perf ormed bet ween the on -chip A/D converter (tran sfer source) and the exter nal memory (trans fer destination) with the address reload function on.
Rev. 5.00, 09/03, pa ge 385 of 760 As a result, t he va lues in the DMAC ar e as sh own in tabl e 11 . 10 when the fou rth t ran sfer en ds, depending on whether the addre ss reload function is on or o ff.
Rev. 5.00, 09/0 3, page 386 of 760 Table 11.11 Transfer Conditions and Register Settings for Transfer between External Memory and SCIF Transmitter Transfer Conditions Register Setting Transfer sourc e.
Rev. 5.00, 09/03, pa ge 387 of 760 11.6 Usage Notes 1. The DMA channel control reg isters (CHCR0–CHCR 3) can be accessed with any data size. The DMA operation register (DMAOR) must be accessed b y byte (8 bits) or word (16 bits); other registers must be accessed by word (16 bits) or longw ord (32 bits).
Rev. 5.00, 09/0 3, page 388 of 760.
Rev. 5.00, 09/03, pa ge 389 of 760 Section 12 Timer (TMU) 12.1 Overview The SH7709S h as a th ree-channe l (channels 0 to 2) 32-bi t timer unit (TMU). 12.1.1 Features The TMU has the follo wing features: • Each chan n el is prov ided with a n auto-reload 32-bit do w n c ounter.
Rev. 5.00, 09/0 3, page 390 of 760 12.1.2 Block D iagram Figure 12.1 s hows a block diagram of the TMU. TOCR Prescaler TSTR TCR0 TCNT0 Module bus Internal bus TCOR0 TCR1 TCNT1 TCOR1 Counter controller TCLK P φ RTCCLK TUNI0 Bus interface Ch.
Rev. 5.00, 09/03, pa ge 391 of 760 12.1.3 Pin C onfigurati on Table 12.1 sh ows th e pin confi guration o f th e TMU. Table 12.1 TMU Pin Channel Pin I/O Description Clock in put/ clo ck outp ut TCLK I/O External clock inpu t pin/in put capture control inp ut pin/realtime cl oc k (RTC ) output pin 12.
Rev. 5.00, 09/0 3, page 392 of 760 12.2 TMU Regist ers 12.2.1 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects whether to use the external TCLK pin as an external clock or an input capture co ntrol usage input pi n, or an o utput pi n for the on-chip R TC output clock.
Rev. 5.00, 09/03, pa ge 393 of 760 Bits 7 to 3—Reserved: These bits are always read as 0. The write value should a lways be 0 . Bit 2—Coun ter Start 2 (ST R2): Selects whether to ru n or h alt timer coun ter 2 (TCNT2).
Rev. 5.00, 09/0 3, page 394 of 760 Chann els 0 and 1 TCR B it Config uration: Bit: 15 14 13 12 11 10 9 8 ——————— U N F I n i t i a l v a l u e : 00000000 R / W : RRRRRRR R / W B i t : 76.
Rev. 5.00, 09/03, pa ge 395 of 760 Bit 8—Underflow Flag (UNF): Status flag that indicates occurrence of a TCNT underflow. Bit 8: UN F Descr iption 0 TCNT has not underflow ed Clearing cond ition: W .
Rev. 5.00, 09/0 3, page 396 of 760 Bits 4 and 3 —Cloc k Edge 1 and 0 (CKEG1, C KEG0): Select t he external clock edge when the extern al clock is selected, or when the in put ca pt ure function is used.
Rev. 5.00, 09/03, pa ge 397 of 760 12.2.4 Timer Constant Registers (TCOR) The TM U has three TCOR registers, one for each channel. T COR specifies the value for settin g in TCN T whe n a T CNT c ount-d o wn res ults i n an u nde r fl o w. TCOR is a 32-bit readab le/ writable register.
Rev. 5.00, 09/0 3, page 398 of 760 Because the internal bus for the SH7709S on -chip peripheral modules is 16 bits wide, a time lag can occu r between the time wh en the upper 16 bits a nd lower 16 bits are read. S ince TCNT counts sequentially, this time lag can create discrepancies betwee n the data in the upper and lo wer halves.
Rev. 5.00, 09/03, pa ge 399 of 760 12.2.6 Input Ca pture Regist er (TCPR2) Input capture reg ister 2 (TCPR2) is a read- only 32- bit register provided o n ly in t imer 2. Control o f TCPR2 setting conditions due to the T CLK pin is affected by the input capture function bits (ICPE1/I CPE0 and CKEG1/CKEG0) in TCR2.
Rev. 5.00, 09/0 3, page 400 of 760 12.3 TMU Operation Each of three channels has a 32-bit ti mer counter (TC NT) and a 32-bi t timer con stant register (TCOR). TCNT counts down . The auto-reload fu nction enables cycle count i ng and c ounting by external events.
Rev. 5.00, 09/03, pa ge 401 of 760 Select operation Select counter clock Set underflow interrupt generation Set timer constant register Initialize timer counter Start counting (1) (2) (4) (5) (6) Set .
Rev. 5.00, 09/0 3, page 402 of 760 Auto-Reload Coun t Operation: Figure 12.3 sh ows the TCNT auto-reload operation. TCNT value TCOR H'00000000 STR0 − STR2 UNF TCOR value set to TCNT during underflow Time Figure 12.
Rev. 5.00, 09/03, pa ge 403 of 760 • External Clock Operation: Set the T PSC 2–TPSC0 bits in TCR to select t he external clock (TCLK) as the timer clock. Use t he CKEG1 and CKEG0 bits in TCR to select the detecti on edge. Ris ing, falling, or both edg es may be s elected.
Rev. 5.00, 09/0 3, page 404 of 760 TCNT value TCOR H'00000000 TCLK TCPR2 Set TCNT value ICPI TCOR value set to TCNT during underflow Time Figure 12.
Rev. 5.00, 09/03, pa ge 405 of 760 12.4.2 Status Flag Cleari ng Timi ng The status flag can be cleared by writing 0 from the CPU. Figure 12.9 shows the timing. P φ Peripheral address bus UNF, ICPF TCR address T 1 T 2 TCR write cycle T 3 Figure 12.9 Stat us Flag Clearing Ti ming 12.
Rev. 5.00, 09/0 3, page 406 of 760 12.5 Usage Notes 12.5.1 Writin g to Registers Synch ronization processing is not perform ed for timer counting during register writes. When writing t o regis ters, always clear the appropriate star t b i ts for the chann el ( STR2 – STR0) in t he timer start register (TS TR) to hal t timer counting.
Rev. 5.00, 09/03, pa ge 407 of 760 Section 13 Realtime Clock (RTC) 13.1 Overview The SH7709S has a realtime clock (RTC) with its own 32 . 768-kHz crysta l oscillato r.
Rev. 5.00, 09/0 3, page 408 of 760 13.1.2 Block D iagram Figure 13.1 s hows a block diagram of the RTC. Module bus RTC Internal bus Interrupt control circuit Prescaler ( ÷ 2) RTCCLK Bus interface Car.
Rev. 5.00, 09/03, pa ge 409 of 760 13.1.3 Pin C onfigurati on Table 13.1 sh ows th e RTC pin configurat ion. Table 13 .1 RTC Pi n s Pin Signal Name I/O Description RTC oscillator crysta l pin EXT AL2 .
Rev. 5.00, 09/0 3, page 410 of 760 13.1.4 RTC Reg ister Conf iguration Table 13.2 sh ows th e RTC regist er configurat ion. Table 13 .2 RTC Re gisters Name Abbr eviation R/W Initial Value Address A cc.
Rev. 5.00, 09/03, pa ge 411 of 760 13.2 RTC Regist ers 13.2.1 64-Hz Counter (R 64CNT) The 64-Hz counter (R 64CNT) is an 8- bit rea d-only register that indi cat es the states of th e RTC divider circu it, RTC prescal er, and R64CNT betw ee n 64 Hz and 1 Hz.
Rev. 5.00, 09/0 3, page 412 of 760 13.2.3 M inute Counter (RMINCNT) The minute counter (RMINCNT) is an 8-bit readable/ wr itab le register used for setting/countin g in the BCD-coded minute section of the RTC. The count operation is perfo rmed by a c a rr y for each minute of the second counter.
Rev. 5.00, 09/03, pa ge 413 of 760 13.2.5 Day of We ek Counter (RWKCN T) The day of week counter (RWKCNT) is an 8-bit readable/ writable register us ed for setting/counting in the BCD-coded day of week section of the RTC. The count operation is per for med b y a car ry f or each d ay of th e da te co unt er.
Rev. 5.00, 09/0 3, page 414 of 760 13.2.6 Date Co unter (RDAYCNT) The date counter (RDAYCNT) is an 8-bit readable/ writab le register used for setting/counting in the BCD-coded date section of the RT C. The count operation is perfo rmed by a car ry for each d ay of th e hour counter.
Rev. 5.00, 09/03, pa ge 415 of 760 13.2.8 Year Co unter (RYRCNT) The year coun ter (RYRCNT) is an 8-bit readable/ writable register used f or setting/counting in the BCD-coded y ear section of the RTC. The least significant 2 di gits of the western calendar year are displayed.
Rev. 5.00, 09/0 3, page 416 of 760 13.2.10 M inute Alarm Register (RMINAR) The minute alarm r egister (RMINAR) is an 8-bit readable/writable re gister, and an alarm register correspondin g to the BCD-coded minu te section coun ter RMINCNT of the RTC. When t h e ENB bit is s et to 1, a compar ison with the RMINCNT value is performed.
Rev. 5.00, 09/03, pa ge 417 of 760 13.2.12 Day of Wee k Ala r m Register (R WKAR) The day of week alarm register ( RWKAR) is an 8-bit readable/w r itable register, and an alarm regist er corresponding to the BCD-coded da y of week section counter RWKCNT of the RTC.
Rev. 5.00, 09/0 3, page 418 of 760 13.2.13 Date Alar m Register (RDAYAR) The date alarm register (RDAYAR) is an 8-bit readable/w ritable regis ter, and an alarm register corres pondin g to th e BCD- coded date se ction coun ter RDAYCNT o f the R TC. When the EN B bit is set to 1, a comp arison w ith the RDAYCNT value is performed.
Rev. 5.00, 09/03, pa ge 419 of 760 13.2.15 RTC Control Register 1 (RCR1) The RT C contr o l register 1 (RCR1) is an 8-bit rea d able/ writable regi ster tha t a ffec ts ca r ry fla gs and alarm flags. It also selects whether to gen erate interrupts for each flag.
Rev. 5.00, 09/0 3, page 420 of 760 Bit 3 — Alarm Interrupt Enable Flag (AIE): When the alarm flag (AF ) is set to 1, the AIE bit allows interrupts. Bit 3: AIE Description 0 An alarm interr upt is no.
Rev. 5.00, 09/03, pa ge 421 of 760 Bits 6 to 4—Period i c I n terru pt Flags (PES 2-PE S0): Specify the periodic interru pt. Bit 6: PES2 Bit 5: PES1 Bit 4: PES0 Description 0 0 0 No periodic i nterr.
Rev. 5.00, 09/0 3, page 422 of 760 Bit 0 — Start B it (START): Halts and restart s the counter (clock). Bit 0: STAR T Description 0 Second/minut e/hour/day/week/ month/year coun ter halts 1 Second/minut e/hour/day/week/ month/year coun ter runs norm a lly (Initial valu e) Note: The 64-H z counter always runs unless stopped with the RTCEN bit.
Rev. 5.00, 09/03, pa ge 423 of 760 13.3.3 Readin g the Time Figure 13 . 3 sho ws ho w to re ad t he t ime. I f a ca rry oc curs wh ile r ead ing the tim e , the c o rre ct time will n ot be obtained, s o it must be read ag ain. Part (a) in figu re 13.
Rev. 5.00, 09/0 3, page 424 of 760 13.3.4 Alarm F unction Figure 13.4 s hows how to use the alar m function. Alar ms ca n be ge nera t ed usi ng se cond s, min ute s, hour s, d a y of the week, dat e , mont h, or a ny combination of these.
Rev. 5.00, 09/03, pa ge 425 of 760 13.3.5 C rystal Oscillat or Circuit Crystal oscillator cir cuit co nstants (reco mmended values) are shown in table 13 .5, and the RTC crystal oscillator circuit i n figure 13.5. Table 13.5 Reco mmended Oscillato r Circuit Consta nts (Reco mme nded Values) fosc Cin Cout 32.
Rev. 5.00, 09/0 3, page 426 of 760 13.4 Usage Notes 13.4.1 Register W riting d uring RTC Count The following RTC reg isters cannot be w ritte n to during an RTC co unt (while bit 0 = 1 in RC R2). RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT , RYRCNT The RTC count mus t be halted before writing to any of the above registers.
Rev. 5.00, 09/03, pa ge 427 of 760 Section 14 Serial Communicati on Interface (SCI) 14.1 Overview The SH7709S has an on -chip serial communication interface (SCI) that supports both asynchronou s and clock sy n chronous serial communication.
Rev. 5.00, 09/0 3, page 428 of 760 • Internal or external transmit /receive clock source: From either ba ud rate generator (internal) or SCK pin (e xte rnal) • Four types of interru pts: Transmit-data-empty, transmit-en d, receive-data-full, and receive- error interru pts are requ ested in dependently.
Rev. 5.00, 09/03, pa ge 429 of 760 Figures 14.2, 14.3, an d 14.4 show bl ock diag ra ms of the SCI I/O port pin s. SCIF pin I/O and data c ontrol is perf ormed by bits 11 to 8 of S CPCR and bit s 5 and 4 o f SCP DR. For det ails , see sect ion 14.2.8, SC Port C ontrol Reg ist er (S CPCR)/SC Port Data R e gister (SCPDR).
Rev. 5.00, 09/0 3, page 430 of 760 Internal data bus Output enable SCI Serial transmission output R SCP0MD0 PCRW Reset C Q Q D R SCP0MD1 PCRW Reset C QD R SCP0DT1 PDRW Reset SCPT[0]/TxD0 C D PCRW: PDRW: SCPCR write SCPDR write Legend Figure 14.
Rev. 5.00, 09/03, pa ge 431 of 760 SCI Serial receive data Internal data bus PDRR * SCPT[0]/RxD0 PDRR: PDR read Note: * When reading the RxD0 pin, set the RE bit in SCSCR to 1. Legend Figure 14.4 SCP T[0]/RxD0 Pin 14.1.3 Pin C onfigurati on The SCI has th e serial pins summ arized in table 14.
Rev. 5.00, 09/0 3, page 432 of 760 14.1.4 Register C onfiguration Table 1 4.2 summarizes the SCI internal regi sters. These register s select the communication mode (asynch ronous or sy nchronou s), specify the data format an d bit rate, and control the trans mitter and receiver s ections.
Rev. 5.00, 09/03, pa ge 433 of 760 14.2.2 Receive Data Register (SCRDR) The receive data register (SCRDR) stores serial receiv e data . The SCI completes the reception of one byte of serial data b y moving the received data from the receive s hift register (SCRSR ) int o SCRDR for storage.
Rev. 5.00, 09/0 3, page 434 of 760 14.2.4 Transm it Data Register (SCTDR) The transmit data r egister (SCTDR ) is an 8-bi t register th at stores data for serial tra nsmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in SCTDR into SCT SR a nd star ts serial t ransmis s ion.
Rev. 5.00, 09/03, pa ge 435 of 760 Bit 6—Character Length (CHR): Selects 7- bit or 8-bit data in asy nchronous mode. In th e synchronous mode, the d ata lengt h is always eight bits, regardless o f the CH R setting.
Rev. 5.00, 09/0 3, page 436 of 760 Bit 3—Stop Bit Length (STOP): Selects one or t wo bits as the stop bit l ength in a synchr onous mode. This setting is used only in asyn chronous mode. It is ignore d in synchrono us mode because no stop bi ts are added.
Rev. 5.00, 09/03, pa ge 437 of 760 14.2.6 Serial Con trol Register (S CSCR) The serial con trol regis ter (SCSCR) operates the S CI transmitter/receiver, s elects the serial clock output in asynchronous mode, enables/disab les interrupt requests, and selects the tra nsmit/receive clock source.
Rev. 5.00, 09/0 3, page 438 of 760 Bit 5—Tran smit E nable (TE ): Enables or disables the SCI serial transmitter. Bit 5: TE Description 0 Transmitter d isabled * 1 (Initial valu e) 1 Transmitter en abled * 2 Notes: 1 . The transmi t d ata register empty bit (TDRE) in the serial status register (SCSSR) is fixed at 1.
Rev. 5.00, 09/03, pa ge 439 of 760 Bit 2—Transmit-End I nterrupt Enable (TEIE): Enables or dis ables the tran smit-e nd inte rru pt (TEI) requested if SCTDR does not contain new tr ansmi t data when the MSB is tran smitted.
Rev. 5.00, 09/0 3, page 440 of 760 14.2.7 Serial Status Register (S C SSR) The se rial stat us regis ter (SCSSR) is an 8- bit regist er conta ining multiprocessor bit va lues, a nd status flags th at indicate the SCI operating state.
Rev. 5.00, 09/03, pa ge 441 of 760 Bit 6—Receive Data Register Full (RDRF): Indicates that SCR DR contains received data. Bit 6: RDRF Description 0 SCRDR does not conta in valid receiv e data (Initial v alue) [Clearing c onditions] (1) RDRF is cleared to 0 w hen the chip is rese t or enters stand by mode.
Rev. 5.00, 09/0 3, page 442 of 760 Bit 4—Fram i ng Error (FER): Indicates that data reception aborted due to a framing error i n async hro no us mo de . Bit 4: FER Description 0 Receiving i s in progr ess or has end ed normally * 1 (Initial val ue) [Clearing c onditions] (1) FER is cleared t o 0 when the chip is reset or enters stand by mode.
Rev. 5.00, 09/03, pa ge 443 of 760 Bit 2—Tran smit E nd (TEND): In dicates that when the last bit of a serial character w as transmitted, SCTDR did not contain valid data, so transmission has ended.
Rev. 5.00, 09/0 3, page 444 of 760 14.2.8 SC Port Control Reg ister (SCPCR)/SC Port Data Register (SCPDR) The SC port control regis ter (SCPCR) a nd SC port data register (SCPDR) control I/O and data for the port pins multiplexed with the serial communication interface (SCI) pins.
Rev. 5.00, 09/03, pa ge 445 of 760 SCPDR Bit 1—Serial Clock Port Data (SCP1DT): Specifies the serial port SCK pin I/O data. Input or o utput is specified by the SC P1MD1 and SCP1MD0 bits. In output mode, the valu e of the SCP1DT bit is output to the SCK pin.
Rev. 5.00, 09/0 3, page 446 of 760 14.2.9 Bit Ra te Reg ister (SCB RR) The bit rate re gister (SCBRR) is an 8- bit register that, t ogether w ith the ba ud rate generator clock source selected b y the CKS1 and CKS0 bits in the serial mode register (SCSMR) , determines the serial transmit/receive bit rate.
Rev. 5.00, 09/03, pa ge 447 of 760 Table 14.4 lists ex a mples of SCBRR setting s in asynchron ous mode, and table 14.5 lis t s examples of SC BRR se tti ng s in synchron o us mode. Table 14.4 Bit Rates and S C BRR Setti ngs in A synchronous Mode P φ φ φ φ (MHz) 2 2.
Rev. 5.00, 09/0 3, page 448 of 760 P φ φ φ φ (MHz) 4.9152 5 6 Bit Rate (bits/s) n N Error ( % % % % ) n N Error ( % % % % ) n N Error ( % % % % ) 110 2 86 0.31 2 88 –0.25 2 106 –0.44 150 1 255 0.00 2 64 0.16 2 77 0.16 300 1 127 0.00 1 129 0.16 1 155 0.
Rev. 5.00, 09/03, pa ge 449 of 760 P φ φ φ φ (MHz) 14.7456 16 19.6608 20 Bit Rate (bits/s) n N Error ( % % % % )n N Error ( % % % % )n N Error ( % % % % )n N Error ( % % % % ) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 –0.25 150 2 191 0.00 2 207 0.16 2 255 0.
Rev. 5.00, 09/0 3, page 450 of 760 Table 14.5 B it Rates a nd SCBRR Settings in Synchron ous Mode P φ φ φ φ (MHz) 4 8 16 28.7 30 Bit Rate (bits/s) n N n N n N n N n N 1 1 0 ————— — — — — — 250 2 249 3 124 3 249 — — — — 500 2 124 2 249 3 124 3 223 3 233 1k 1 249 2 124 2 249 3 111 3 116 2.
Rev. 5.00, 09/03, pa ge 451 of 760 Table 14.6 indicates t h e maximum bit rate s in asynchron ous mode when the baud rate gene rat or is used. Tables 1 4.
Rev. 5.00, 09/0 3, page 452 of 760 Table 14. 7 M a ximum Bit Rate s w ith External Clo ck Input (As ynchronous M ode) P φ φ φ φ (MHz) External I nput Clock ( MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.
Rev. 5.00, 09/03, pa ge 453 of 760 14.3 Operation 14.3.1 Overvie w For serial comm unication, the SCI has an asynchronous mode in which characters are synch ro nized indi vidually, an d a synchron ous mode in whi ch communicat ion is synchron ized wi th clock pu lses.
Rev. 5.00, 09/0 3, page 454 of 760 Table 14.9 Serial M ode Register Sett ings and SCI C ommunication Fo rmats SCSMR Settings SCI Communication Format Bit 7 C/ A A A A Bit 6 CHR Bit 5 PE Bit 2 MP Bit 3.
Rev. 5.00, 09/03, pa ge 455 of 760 14.3.2 Operation i n Asynch ronous Mode In asynchronous m ode, each transmitted or received character beg i n s with a start bit and ends with a stop bit. Ser ial communication i s synchronized one character at a time.
Rev. 5.00, 09/0 3, page 456 of 760 Transmit/Receive Formats: Table 14.11 lists the 12 commun ication for mats that can be selected in asynchronous mode.
Rev. 5.00, 09/03, pa ge 457 of 760 When the SCI o perates on an inter nal clock, it can o utput a clock signal at the SCK pin. The frequen cy of this outpu t cloc k is equal to the bit rate. The phase is aligned as in figure 14.6 so that the rising edge of the clock occ urs at the center of each transmit data bit.
Rev. 5.00, 09/0 3, page 458 of 760 Initialization Clear TE and RE bits in SCSCR to 0 Select communication format in SCSMR Set value in SCBRR Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) Wait.
Rev. 5.00, 09/03, pa ge 459 of 760 TDRE = 1? Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 All data transmitted? Yes TEND = 1? Read TEND bit in SCSSR Break output? Yes Clear TE bit in .
Rev. 5.00, 09/0 3, page 460 of 760 In transmitting serial d ata, the SCI operates as follo ws: 1. T he SCI monitors the T DRE bit in SCS SR. When TDR E is cleared t o 0, the SCI recognizes that t he tra nsmi t dat a regi ster (SC TDR ) con t ains new d ata, and loads this data from SCTDR into the transmit shi ft register ( SC TSR).
Rev. 5.00, 09/03, pa ge 461 of 760 Figure 14.9 s hows an ex ample of SCI transm it operation in asynch ronous mode. 01 1 1 0/1 0 1 TDRE TEND Parity bit Parity bit Serial data Start bit Data Stop bit S.
Rev. 5.00, 09/0 3, page 462 of 760 Start of reception Read ORER, PER, and FER bits in SCSSR All data received? End of reception No Yes PER ∨ FER ∨ ORER = 1? RDRF = 1? Yes Yes Clear RE bit in SCSCR.
Rev. 5.00, 09/03, pa ge 463 of 760 Error handling ORER = 1? Overrun error handling FER = 1? Yes Break? No Framing error handling PER = 1? Yes Parity error handling Clear ORER, PER, and FER bits in SCSSR to 0 End No No No Yes Yes Clear RE bit in SCSCR to 0 Figure 14.
Rev. 5.00, 09/0 3, page 464 of 760 In receiving, the SCI operates as follows: 1. T he SCI monitors the c omm unication l ine. When it detects a start bit (0) , the SCI synchr oniz es internally and st arts receiving. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB.
Rev. 5.00, 09/03, pa ge 465 of 760 Figure 14 .11 sho ws an example of SCI receive operat ion in asynch r onous m ode. RDRF FER ERI interrupt request generated by framing error 1 frame RXI interrupt ha.
Rev. 5.00, 09/0 3, page 466 of 760 Receiving station A (ID = 01) (ID = 02) (ID = 03) (ID = 04) Receiving station B Receiving station C Serial communication line H'01 H'AA (MPB = 0) (MPB = 1).
Rev. 5.00, 09/03, pa ge 467 of 760 TDRE = 1? Write transmit data to SCTDR and set MPBT bit in SCSSR Transmission ended? Yes TEND = 1? Read TEND bit in SCSSR Clear TDRE bit to 0 Break output? Yes Clear.
Rev. 5.00, 09/0 3, page 468 of 760 In transmitting serial d ata, the SCI operates as follo ws: 1. T he SCI monitors t he TDRE b it in SCSSR. When TDRE is cleare d to 0 the SCI recognizes that t he tr a nsmi t da ta re gister (SC T DR) c onta ins n ew dat a, an d tra nsfe rs th is d ata fr om SC TDR into the transmit shi ft register ( SC TSR).
Rev. 5.00, 09/03, pa ge 469 of 760 Receiving Multiprocessor Serial Data: Fig ure 14.15 shows a sam ple flowchart for receiving multiprocessor serial data. The pr ocedure for receiv ing multiprocessor serial data is: 1. ID receive cycle: Set the MPIE bit in the serial control register (SCSCR) to 1.
Rev. 5.00, 09/0 3, page 470 of 760 RDRF = 1? FER = 1 or ORER = 1? RDRF = 1? All data received? No End of reception Yes Set MPIE bit in SCSCR to 1 Read RDRF bit in SCSSR Clear RE bit in SCSCR to 0 No N.
Rev. 5.00, 09/03, pa ge 471 of 760 ORER = 1? Break? Yes Framing error handling Yes Error handling Overrun error handling Yes FER = 1? Clear ORER and FER bits in SCSSR to 0 End No No No Clear RE bit in SCSCR to 0 Figure 14.
Rev. 5.00, 09/0 3, page 472 of 760 Figure 14.16 show s an example of SCI receive operation using a multiprocessor format. RDRF MPIE RDR value ID1 RXI interrupt request (multiprocessor interrupt) gener.
Rev. 5.00, 09/03, pa ge 473 of 760 RDRF MPIE RDR value Example: Own ID matches data ID1 ID2 Data2 01 1 1 10 1 MPB MPB Serial data Start bit Data (ID2) Data (Data 2) Stop bit Start bit Stop bit Idle (m.
Rev. 5.00, 09/0 3, page 474 of 760 14.3.4 Synch ron ou s Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for hi g h-speed serial communicatio n. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock.
Rev. 5.00, 09/03, pa ge 475 of 760 Clock: An in ter nal cl ock ge nera ted by the on-ch ip b au d ra te gene rat or or an ext ern a l cl ock i nput from the SCK pin can be selected as the SCI transmit/receive clock.
Rev. 5.00, 09/0 3, page 476 of 760 Initialization Clear TE and RE bits in SCSCR to 0 (1) Has a 1-bit period elapsed? Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits Set transmit.
Rev. 5.00, 09/03, pa ge 477 of 760 Start of transmission Read TDRE bit in SCSSR All data transmitted? Yes No End of transmission (1) (2) TDRE = 1? Write transmit data to SCTDR and clear TDRE bit in SC.
Rev. 5.00, 09/0 3, page 478 of 760 In transmitting serial d ata, the SCI operates as follo ws: 1. T he SCI monitors t he TDRE b it in SCSSR. When TDRE is cleare d to 0 the SCI recognizes that t he tra nsmi t dat a regi ster (SC TDR ) con t ains new da ta and l oad s thi s data f rom S CTDR into the transmit shi ft register ( SC TSR).
Rev. 5.00, 09/03, pa ge 479 of 760 Receiving Serial Data (Synchronous Mode): Fig ure 14.21 sh ows a s ample flowchart for receiving s e rial data. When sw itching from asynchronous mode to synch ronou s mode, ma k e sure that ORER, PER, and FER are cleared to 0.
Rev. 5.00, 09/0 3, page 480 of 760 Read ORER bit in SCSSR All data received? End of reception No Yes ORER = 1? RDRF = 1? Yes Clear RE bit in SCSCR to 0 No No Read RDRF bit in SCSSR (3) (2) Yes Error h.
Rev. 5.00, 09/03, pa ge 481 of 760 Error handling End ORER = 1? No Clear ORER bit in SCSSR to 0 Yes Overrun error handling Figure 14.21 Sample Flowcha r t for Receiving Serial Da ta (cont ) In receiving, the SCI operates as follows: 1. T he SCI s ynchronizes with serial cloc k input or output and in itializes i nternally.
Rev. 5.00, 09/0 3, page 482 of 760 Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Serial clock Serial data Transfer direction Bit 7 RXI interrupt handler reads data and clears RDRF bit to 0 1 frame RXI interrupt request generated RXI interrupt request generated ERI interrupt request generated by overrun error RDRF ORER Figure 14.
Rev. 5.00, 09/03, pa ge 483 of 760 Start of transmission/reception Read TDRE bit in SCSSR All data transmitted/received? End of transmission/reception (1) No Yes TDRE = 1? Write transmit data to SCTDR.
Rev. 5.00, 09/0 3, page 484 of 760 14.4 SCI Interrupts The SCI has four interru pt sources transmit-end (TEI), receive-error (ERI), receive -data-full (RXI), and transmit-data-empty (TXI). Table 14.13 lists the interrupt sources an d indicates their priority .
Rev. 5.00, 09/03, pa ge 485 of 760 14.5 Usage Notes Note the following points when using the SCI. SCTDR Writin g and TDR E Flag: T he TDRE b it in the serial status register ( SCSSR) is a status flag indicating load ing of transmit data from SCT DR into S CTSR.
Rev. 5.00, 09/0 3, page 486 of 760 TEND F l a g and TE Bit P rocessing : The T E ND flag is set to 1 during transmissio n of the stop bit of the last data.
Rev. 5.00, 09/03, pa ge 487 of 760 The r eceive margin in a sync hrono us mode can therefor e be expres sed as in equa tion 1. Equa tio n 1: M = 0.5 − 1 2N D − 0.5 N − (L − 0.5)F − (1 + F) × 100% Where: M = Receive margin ( % ) N = Ratio of c lock fr equency t o bit rat e (N = 16) D = Clock duty cy cl e (D = 0 to 1.
Rev. 5.00, 09/0 3, page 488 of 760.
Rev. 5.00, 09/03, pa ge 489 of 760 Section 15 Smart Card Interface 15.1 Overview As an added serial communications interf ace function, the SCI supports an IC card (sma rt card) interface that conf orms to the data transf er protocol (asynchron ous half-duplex character transm ission protocol) of the ISO/IEC7816- 3 (Identif ication C ard) standard.
Rev. 5.00, 09/0 3, page 490 of 760 15.1.2 Block D iagram Figure 15.1 show s a block diagram of the smart card interface. RxD TxD SCK SCI SCBRR SCSCR SCSMR SCTDR SCTSR SCRDR SCRSR SCSCMR SCSSR Parity g.
Rev. 5.00, 09/03, pa ge 491 of 760 15.1.3 Pin C onfigurati on Table 15.1 summarizes the smart card interf ace pins. Table 15.1 Smart Card Interface Pins Pin Name Abbreviation I/O Function Serial clock pin SCK0 O utput Clock output Receive d ata pin Rx D0 Input Receive data inp ut Transmit data pin TxD 0 Output Transmit data out put 15.
Rev. 5.00, 09/0 3, page 492 of 760 15.2 Register Descriptions This section describes the registers added for t he smart card interf ace and th e bits w ho se f unc tions are changed.
Rev. 5.00, 09/03, pa ge 493 of 760 Bit 0—Sm art Card Interface Mod e Select ( SMIF): Enables the smart card interface function. Bit 0 : SMIF Descr iption 0 Smart card interface funct ion dis abl ed (Initial value) 1 Smart card interface funct ion enab led 15.
Rev. 5.00, 09/0 3, page 494 of 760 Bits 3 to 0: These bits h ave the same function as in the ordin ary SCI. See section 14, Serial Communication Interface (SCI), for more information. The setting conditions for bit 2, the transmit end bit (TEND), are changed as follows.
Rev. 5.00, 09/03, pa ge 495 of 760 15.3.2 Pin Con n ections Figure 15.2 shows the pin connection diag ram for the smart card interface. During communi cation with an IC card, transmission and reception are bo th carried out over the same data transfer line, so connect the TxD and Rx D pins on the chip.
Rev. 5.00, 09/0 3, page 496 of 760 15.3.3 Data Form at Figure 15.3 show s the data form at for the smart card interface. In this mode, parity is checked every f ra me whi le receiv ing and error sign als se nt to the transmitti ng side whenever an error is detected so th at data can be re -transm itted.
Rev. 5.00, 09/03, pa ge 497 of 760 5. The transmitting side transmits the next frame of data un less it receives an error signal. If it does receive an error signal, it returns to step 2 to re-tr an s mit the erroneous data. 15.3.4 Register S ettings Tab le 15 .
Rev. 5.00, 09/0 3, page 498 of 760 In the inver se c onventi on type, the l ogical 1 level is sta te A, the logical 0 l evel is state Z, and communication is MSB first. The start character data is H'3F. Parity is even (from the smart card standard), an d so the pari ty bi t is 0, which corresponds to state Z.
Rev. 5.00, 09/03, pa ge 499 of 760 Table 15.4 Rela tionship of n to CK S1 and CKS 0 n CKS1 CKS0 000 101 210 311 Table 15.5 Examples of Bit Rate B (Bits/s) f or SCBRR Settings (n = = = = 0) P φ φ φ φ (MHz) N 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.
Rev. 5.00, 09/0 3, page 500 of 760 Table 15.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) P φ φ φ φ (MHz) Maximum Bit R ate (Bits/s) N n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.
Rev. 5.00, 09/03, pa ge 501 of 760 15.3.6 Data Transmission and Reception Initializatio n: Initialize the SCI usin g the follo wing procedure before sending or receiving data. Initialization is also required for switching f rom transmit mode to receive mode or fro m receive mode to transmit mode.
Rev. 5.00, 09/0 3, page 502 of 760 Initialization Clear TE and RE bits in SCSCR to 0 Set value in SCBRR Clear FER/ERS, PER and ORER flags in SCSSR to 0 Wait Set TIE, RIE, TE, and RE bits in SCSCR Has .
Rev. 5.00, 09/03, pa ge 503 of 760 Serial Data T r ansmi ssion: The processi ng procedu res in the smart card m ode differ f rom ordinary SCI pro cessing because data is retransmitted when an error signal is sampled during a data transmiss ion. This resu lts in the tr ansmissio n processing flo wchart shown in figure 15 .
Rev. 5.00, 09/0 3, page 504 of 760 Start End of transmission Start of transmission Initialize Write transmit data in SCTDR and clear TDRE flag in SCSSR to 0 (1) Clear TE bit in SCSCR to 0 (6) Error ha.
Rev. 5.00, 09/03, pa ge 505 of 760 Serial Data Reception: The processing procedu res in smart card m ode are the same as in ordinary SCI processing. The reception processi n g flowchart is shown i n figure 15.7. 1. Initialize the smart card interf ace mode as described above i n I nitialization and in f igure 15.
Rev. 5.00, 09/0 3, page 506 of 760 Start End of reception Start of reception Initialize Write receive data from SCRDR and clear RDRF flag in SCSSR to 0 (1) Clear RE bit in SCSCR to 0 (6) Error handlin.
Rev. 5.00, 09/03, pa ge 507 of 760 Switching Mo des: W hen sw itching from receive mode to transmit mode, check that the receive operation is completed before starting initializati on, clearing RE to 0, and setting TE to 1. The RDRF, PER, and ORER flags can be used to chec k if reception is completed.
Rev. 5.00, 09/0 3, page 508 of 760 0 185 371 0 185 371 0 Base clock Receive data (RxD) Synchro- nization sampling timing Data sampling timing 186 clock cycles 372 clock cycles Start bit D0 D1 Figure 15.8 Receive Data Sampling Timing i n Sm art C ard Mode The receive m argin is f ound from the following equation: For smart card m ode: M = (0.
Rev. 5.00, 09/03, pa ge 509 of 760 15.4.2 Retransmission (Receive and Transmit Modes) Retransmission w hen SCI is in Receive Mode: Figure 15.9 s hows t he retransmi ssion operation in the SCI receive m ode. 1. When the received parity bit is checked and an error is found, the PER bit in SCSSR is automatical ly set to 1.
Rev. 5.00, 09/0 3, page 510 of 760 Retrans mission whe n SCI is in Tr ansmit Mode: Figure 15 . 10 shows the retrans mission operatio n in the SCI transmit mode. 1. After transmis sion of o ne frame is completed, the FER/ERS bit in SCSSR is set to 1 when a error sig nal is retu rned fr o m the r ecei ving side.
Rev. 5.00, 09/03, pa ge 511 of 760 Section 16 Serial Communicati on Interface with FIFO (SCIF) 16.1 Overview The SH7709S has a two-chann el serial co mmuni cation interface with FIFO (SCIF ) that supports asynchronous serial co mmuni cation.
Rev. 5.00, 09/0 3, page 512 of 760 16.1.2 Block D iagram Figure 16.1 s hows a block diagram of the SCIF . RxD TxD SCK SCIF SCBRR SCSSR2 SCSCR2 SCFTDR2 SCTSR SCFRDR2 (16 (16 stages) stages) SCRSR SCSMR.
Rev. 5.00, 09/03, pa ge 513 of 760 Figures 16.2 to 1 6.4 s how the SCIF I/ O port pi ns. SCIF pin I/O and data c ontrol is perf ormed by bits 11 to 8 of S CPCR and bit s 5 and 4 o f SCP DR. For det ails , see sect ion 14.2.8, SC Port C ontrol Reg ist er (S CPCR)/SC Port Data R e gister (SCPDR).
Rev. 5.00, 09/0 3, page 514 of 760 Internal data bus Output enable SCIF Serial transmission output R SCP4MD0 PCRW Reset C Q Q D R SCP4MD1 PCRW Reset C Q D R SCP4DT1 PDRW Reset SCPT[4]/TxD2 C D PCRW: PDRW: SCPCR write SCPDR write Legend Figure 16.
Rev. 5.00, 09/03, pa ge 515 of 760 SCIF Internal data bus PDRR * Serial receive data SCPT[4]/RxD2 PDRR: SCPDR read Legend Note: * When reading the RxD2 pin, set the RE bit in SCSCR to 1. Figure 16.4 SCP T[4]/RxD2 Pin 16.1.3 Pin C onfigurati on The SCIF has the serial pins summarized in table 16.
Rev. 5.00, 09/0 3, page 516 of 760 16.1.4 Register C onfiguration Table 16.2 summarizes the SCIF internal registers. These reg isters specify the data fo rmat and bit rate, and control the transmitter and receiver sect ions.
Rev. 5.00, 09/03, pa ge 517 of 760 16.2 Register Descriptions 16.2.1 Receive Shift Register (SCRSR) The receive shift register (SCRSR) receives serial data. Data input at the Rx D pin is loaded into SCRSR in the ord er received, LSB (bit 0) first, convertin g t he data to parallel form.
Rev. 5.00, 09/0 3, page 518 of 760 16.2.4 Transm it F IFO Data Register (SCFT DR) The trans mit FIFO d ata regis ter (SCFTDR) is a FIFO register c omprising sixteen 8 -bit stag es that stores d ata fo r se rial t ransm issi on.
Rev. 5.00, 09/03, pa ge 519 of 760 Bit 5—Parit y Enable (PE): Selects wh e ther t o ad d a p a r ity bit to t ransm i t d a ta an d to check the parity of receiv e data.
Rev. 5.00, 09/0 3, page 520 of 760 Bits 1 and 0 —Clock Select 1 and 0 (CKS1, CKS0): Select the internal clock source of the on- chip baud rate generator. According to the setting of the CKS1 and CKS0 bi ts four clock sources are available. P φ , P φ /4, P φ /16 and P φ /64 .
Rev. 5.00, 09/03, pa ge 521 of 760 Bit 6—Receive Interrupt Enable (RIE): En ables or disables the receive-data-f ull (RXI) and receive-error ( ERI) interrupts reque sted when serial receive data is .
Rev. 5.00, 09/0 3, page 522 of 760 Bits 1 and 0—Cloc k Enable 1 and 0 (CKE1, CKE0): Select the SCIF clock source and enable or disable clock outp ut from the SCK pin. Depending on t he combination of CKE1 and CKE0, the SCK pin can be u s ed for serial clock ou tput or serial clock input.
Rev. 5.00, 09/03, pa ge 523 of 760 Bit 7—Receive Error (ER): Indicates the occurren ce of a f raming error, or of a parity error w hen receiving data that includes parity .
Rev. 5.00, 09/0 3, page 524 of 760 Bit 5—Tr ansmi t FIFO Data Em pty (TD FE): In dicates that data has been transf erred f rom the transmit FIFO data register (SCFTDR) to the transmit s hift registe.
Rev. 5.00, 09/03, pa ge 525 of 760 Bit 3—Fram ing Error (FER): Indicates a framing error in the data read from the receive FIFO data r e gister (SCFRDR) .
Rev. 5.00, 09/0 3, page 526 of 760 Bit 1—Receive FIFO Data Full (RDF): In dicates that receive data h as been transf erred to the receive FIFO data r egis ter (SCFRDR) , an d the quant ity o f data in SCFRDR has be c ome greater than the receive trigger number specified by the RTRG1 and RT RG0 bits in the FIFO control regist er (SCFCR).
Rev. 5.00, 09/03, pa ge 527 of 760 Upper 8 bit s: 15 14 13 12 11 10 9 8 PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 I n i t i a l v a l u e : 00000000 R / W : RRRRRRRR Bits 15 t o 12—Number of Parity Er.
Rev. 5.00, 09/0 3, page 528 of 760 Table 16.3 SCSM R Setting s SCSMR Settings n Clock Source CKS1 CKS0 0P φ 00 1P φ /4 0 1 2P φ /16 1 0 3P φ /64 1 1 Note: The bit rate error is given by the foll owing formu la: Error (%) = P φ × 10 6 − 1 × 100 (N+1) × 64 × 2 2n − 1 × B Table 16.
Rev. 5.00, 09/03, pa ge 529 of 760 P φ φ φ φ (MHz) 3 3.6864 4 Bit Rate (bits/s) n N Error ( % % % % ) n N Error ( % % % % ) n N Error ( % % % % ) 110 1 212 0.03 2 64 0.70 2 70 0.03 150 1 155 0.16 1 191 0.00 1 207 0.16 300 1 77 0.16 1 95 0.00 1 103 0.
Rev. 5.00, 09/0 3, page 530 of 760 P φ φ φ φ (MHz) 6.144 7.3728 8 Bit Rate (bits/s) n N Error ( % % % % ) n N Error ( % % % % ) n N Error ( % % % % ) 110 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 79 0.00 2 95 0.00 2 103 0.16 300 1 159 0.00 1 191 0.
Rev. 5.00, 09/03, pa ge 531 of 760 P φ φ φ φ (MHz) 14.7456 16 19.6608 20 Bit Rate (bits/s) n N Error ( % % % % )n N Error ( % % % % )n N Error ( % % % % )n N Error ( % % % % ) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 –0.25 150 2 191 0.00 2 207 0.16 2 255 0.
Rev. 5.00, 09/0 3, page 532 of 760 Table 16.5 indicates t h e maximum bit rate s in asynchron ous mode when the baud rate gene rat or is used. Ta ble 16.
Rev. 5.00, 09/03, pa ge 533 of 760 Table 16. 6 M a ximum Bit Rate s w ith External Clo ck Input (As ynchronous M ode) P φ φ φ φ (MHz) External I nput Clock ( MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.
Rev. 5.00, 09/0 3, page 534 of 760 16.2.9 FIFO Contro l Register (SCFCR) B i t : 76543210 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ .
Rev. 5.00, 09/03, pa ge 535 of 760 Bit 3—Modem Control Enable (MCE): Enables m ode m cont rol signals C TS and R TS. Bit 3: MCE Description 0 Modem signal disabled * (Initial valu e) 1 Modem signal enabled Note: * CTS is fi xed at active 0 re gardless of the inp ut value, and RTS is also fixed at 0.
Rev. 5.00, 09/0 3, page 536 of 760 16.2.10 FIFO Data Count Reg ister (SCFDR) SCFDR is a 16-bit reg ister which indicates the quantity of data stored in the trans mit FIFO data register (SCF TDR) and the receive FIFO data register (SCFRDR) .
Rev. 5.00, 09/03, pa ge 537 of 760 16.3 Operation 16.3.1 Overvie w For serial communication , the SCIF has an asynch ronous mode in which characters are synch ronized indivi dually.
Rev. 5.00, 09/0 3, page 538 of 760 Table 16.8 SCSCR Setting s and SCIF Clock Source Selection SCSCR Settings SCIF Trans mit/R eceive C loc k Mode Bit 1 CKE1 Bit 0 CKE0 Clock Source SCK Pin Function 0 .
Rev. 5.00, 09/03, pa ge 539 of 760 Clock: An in ter nal cl ock ge nera ted by the on-ch ip b au d ra te gene rat or or an ext ern a l cl ock i nput from the SCK pin can be selected as the SCIF transmit/receive clock. T he clock source is selected by bi ts CKE1 an d CKE0 in the serial control register (S CSCR) (table 16.
Rev. 5.00, 09/0 3, page 540 of 760 Initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 1-bit interval elapsed? Set RTRG1-0, TTRG1-0, and MCE in SCFCR Clear TFRST a.
Rev. 5.00, 09/03, pa ge 541 of 760 • Serial data tr ansmission Figure 16. 6 shows a sample flo wchart fo r seri al tra nsmis si on. Use the following procedure for ser ial data transmission after enabli ng the SCIF for transmission.
Rev. 5.00, 09/0 3, page 542 of 760 Start of transmission Read TDFE bit in SCSSR TEND= 1? Read TEND bit in SCSSR Clear TE bit in SCSCR to 0 Set SCPDR and SCPCR Yes No TDFE= 1? No All data transmitted? .
Rev. 5.00, 09/03, pa ge 543 of 760 In serial transmi ssion, the SCIF operates as described below. 1. W hen data is writte n into the trans mit FIFO da ta register (SCF TDR), the SC IF tran sfe rs the data fro m SCFT DR to the transmit s hi ft register (SC TSR) and starts tr ansmitting.
Rev. 5.00, 09/0 3, page 544 of 760 Figure 16.7 s hows an ex ample of th e operation f or transmission. 01 1 1 0/1 0 1 TDFE TEND Parity bit Parity bit Serial data Start bit Data Stop bit Start bit Data.
Rev. 5.00, 09/03, pa ge 545 of 760 • Serial data recep tion Figures 16.9 and 16.10 s ho w a sample flowch art for serial reception. Use the following procedu re for serial data reception after enabling the SCIF for reception.
Rev. 5.00, 09/0 3, page 546 of 760 Start of reception Read ORER, PER, FER flags in SCSSR All data received? End of reception No Yes PER v FER v ORER = 1? RDF = 1? Yes Yes Clear RE bit in SCSCR to 0 No.
Rev. 5.00, 09/03, pa ge 547 of 760 1. Whether a framing error or parity error has occu rred in the receive data read f rom SCFRDR can be ascertained from the F ER and PER bits in SCS SR. 2. When a break signal is received, receive data is n ot tr ansferred to SCFRD R while the BRK flag is set.
Rev. 5.00, 09/0 3, page 548 of 760 In serial reception, th e SCIF operates as des cribed below. 1. The SCIF m onitors th e tra nsmiss ion lin e, and if a 0 start bit is detected, per forms interna l synchronization and starts reception. 2. T he received data is stor ed in SCRSR in L SB-to-MSB o rder.
Rev. 5.00, 09/03, pa ge 549 of 760 Figure 16.11 s hows an ex ample of the operation for reception. RDF FER ERI interrupt request generated by receive error One frame Data read and RDF flag read as 1 t.
Rev. 5.00, 09/0 3, page 550 of 760 16.4 SCIF Interrupts The SCIF has four interrupt sou rces: transmit-FIFO-data-empty ( TXI), receive-error (ERI), receive-data-full (R XI), and break (BRI). Table 16.10 sh ows th e interrupt s ources and th eir order of priority .
Rev. 5.00, 09/03, pa ge 551 of 760 16.5 Usage Notes Note the following when using the SCIF. 1. SCFTDR Writing an d TDFE Flag: The T DFE flag in the serial status register (SCSSR) is set when the numbe.
Rev. 5.00, 09/0 3, page 552 of 760 5. TEND Fl ag and TE Bit Proces sing: The TEND fl ag is set t o 1 during trans mission of the stop bit of the las t data.
Rev. 5.00, 09/03, pa ge 553 of 760 Equa tio n 2: When D = 0.5 and F = 0: M = (0.5 – 1/(2 × 16)) × 100 % = 46.875 % This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev. 5.00, 09/0 3, page 554 of 760.
Rev. 5.00, 09/03, pa ge 555 of 760 Section 17 IrDA 17.1 Overview The SH7709S has an on -chip Infrared Data Association (IrDA) interface which is based on the IrDA 1.0 sy stem and can perform infrared communication. It also can be us ed as the SCIF by making register set t ings .
Rev. 5.00, 09/0 3, page 556 of 760 17.1.2 Block D iagram Figure 17.1 s hows a block diagram of the IrDA. SCIF Clock input TxD Transfer clock RxD Switching IrDA/SCIF IrDA SCK TxD1 RxD1 Modulation unit Demodulation unit Legend SCIF: Serial communication interface with FIFO Figure 17.
Rev. 5.00, 09/03, pa ge 557 of 760 Figures 17.2 to 17 .4 sho w the IrDA I/ O port pin s. SCIF pin I/O a nd data control is performed by bits 7 to 4 of SCPCR and bit s 3 and 2 of SCPDR. For det ails , see sect ion 14.2.8, SC Port C ontrol Reg ist er (S CPCR)/SC Port Data R e gister (SCPDR).
Rev. 5.00, 09/0 3, page 558 of 760 Internal data bus Output enable IrDA Serial transfer output Q R SCP2DT1 PDRW Reset SCPT[2]/TxD1 C D PCRW: PDRW: Legend SCPCR write SCPDR write R SCP2MD0 PCRW Reset C Q D R SCP2MD1 PCRW Reset C QD Figure 17.
Rev. 5.00, 09/03, pa ge 559 of 760 IrDA Serial receive data Internal data bus PDRR * SCPT[2]/RxD1 Legend PDRR: SCPDR read Note: * When reading the RxD1 pin, set the RE bit in SCSCR to 1. Figure 17.4 SCP T[2]/RxD1 Pin 17.1.3 Pin C onfigurati on The IrDA has the s erial pins summarized in table 17.
Rev. 5.00, 09/0 3, page 560 of 760 17.1.4 Register C onfiguration The IrDA has the internal registers shown in table 17.2. These registers select IrDA or SCIF mode, s pecify the data format and a bit rate, and con trol the transmit and receive units. Table 17.
Rev. 5.00, 09/03, pa ge 561 of 760 17.2 Register Desc ription Specifications of the registers in the I rDA are the same as th ose in the SCIF except fo r the serial mode regis ter described below. Therefore, refer to section 16, Serial Communicatio n I nterface with FIFO ( SCIF), for details o f these regis ters.
Rev. 5.00, 09/0 3, page 562 of 760 Bits 6 to 3—Ir Clock Sel ect Bits (I CK3 to ICK0) Bit 2—Output Pul se Width Select (PSEL): PSEL selects an IrD A outpu t pulse width that is 3/ 16 of the bi t l ength for 115 kbps or 3/1 6 of t he bit len gth for th e selected baud rat e.
Rev. 5.00, 09/03, pa ge 563 of 760 17.3 Operation Description The IrDA modu le can perform infrared communication conforming to IrDA 1.0 b y connecting infrared transmit/receive units.
Rev. 5.00, 09/0 3, page 564 of 760 17.3.3 Receiving Received 3/16 I R fra me bit-width pulses are demo dulated and co nverted to a UA RT fra me, as shown in fi gur e 17 .5 . Demodulation to 0 is perfor med for pulse o utput, and demodulation to 1 is per form ed for no pulse outpu t.
Rev. 5.00, 09/03, pa ge 565 of 760 Section 18 Pin Function Controller 18.1 Overview The pin func tion co nt r oll er ( PFC) is c omposed of regist ers for sele c ting the fu nc tion of multiplexe d p ins and th e input/out put dir ection.
Rev. 5.00, 09/0 3, page 566 of 760 Port Port Function (Related Module) Other Function (Related Module) C PTC0 input/output (port)/PIN T0 input (INTC) MCS0 output (BSC) D PTD7 input/output (port) DACK1.
Rev. 5.00, 09/03, pa ge 567 of 760 Port Port Function (Related Module) Other Function (Related Module) G PTG1 input (por t) AUDATA1 output (AUD) G PTG0 input (por t) AUDATA0 output (AUD) H PTH7 input/.
Rev. 5.00, 09/0 3, page 568 of 760 Port Port Function (Related Module) Other Function (Related Module) L PTL4 input ( port) AN4 input (ADC ) L PTL3 input ( port) AN3 input (ADC ) L PTL2 input ( port) .
Rev. 5.00, 09/03, pa ge 569 of 760 18.2 Register Conf iguration Table 18.2 sum marizes the registers of the pi n function control ler. Table 18.2 Pin Function Controller Registers Name Abbreviation R/.
Rev. 5.00, 09/0 3, page 570 of 760 18.3 Register Descriptions 18.3.1 Port A Contr ol Re gister (PACR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA7 MD1 PA7 MD0 PA6 MD1 PA6 MD0 PA5 MD1 PA5 MD0 PA4 MD1.
Rev. 5.00, 09/03, pa ge 571 of 760 18.3.2 Port B Con trol Regis ter (PBCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PB7 MD1 PB7 MD0 PB6 MD1 PB6 MD0 PB5 MD1 PB5 MD0 PB4 MD1 PB4 MD0 PB3 MD1 PB3 MD0 PB.
Rev. 5.00, 09/0 3, page 572 of 760 18.3.3 Port C Control Regi ster (PCCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PC7 MD1 PC7 MD0 PC6 MD1 PC6 MD0 PC5 MD1 PC5 MD0 PC4 MD1 PC4 MD0 PC3 MD1 PC3 MD0 PC2.
Rev. 5.00, 09/03, pa ge 573 of 760 18.3.4 Port D Control Regi ster (PDCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD7 MD1 PD7 MD0 PD6 MD1 PD6 MD0 PD5 MD1 PD5 MD0 PD4 MD1 PD4 MD0 PD3 MD1 PD3 MD0 PD2.
Rev. 5.00, 09/0 3, page 574 of 760 18.3.5 Port E C ontrol Regis ter (PECR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PE7 MD1 PE7 MD0 PE6 MD1 PE6 MD0 PE5 MD1 PE5 MD0 PE4 MD1 PE4 MD0 PE3 MD1 PE3 MD0 PE.
Rev. 5.00, 09/03, pa ge 575 of 760 18.3.6 Port F Control R egister (PFCR ) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PF7 MD1 PF7 MD0 PF6 MD1 PF6 MD0 PF5 MD1 PF5 MD0 PF4 MD1 PF4 MD0 PF3 MD1 PF3 MD0 PF.
Rev. 5.00, 09/0 3, page 576 of 760 18.3.7 Port G Control Regis ter (PGCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PG7 MD1 PG7 MD0 PG6 MD1 PG6 MD0 PG5 MD1 PG5 MD0 PG4 MD1 PG4 MD0 PG3 MD1 PG3 MD0 PG2.
Rev. 5.00, 09/03, pa ge 577 of 760 Bit (2n + 1) Bit 2n PGnMD1 PGnMD0 Pin Function 0 0 Other function (n = 1–3, 5) (see table 18.1) (Initial valu e) ( ASEMD0 = 0) 0 1 Reserved 1 0 Port input (Pu ll-u.
Rev. 5.00, 09/0 3, page 578 of 760 Bits 15 a nd 14—PH7 Mode 1, 0 (PH7MD1, PH 7MD0): These b its select the pin functions and perform i nput pu ll-up MOS con trol.
Rev. 5.00, 09/03, pa ge 579 of 760 18.3.9 Port J Contr ol Regis ter (PJCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PJ7 MD1 PJ7 MD0 PJ6 MD1 PJ6 MD0 PJ5 MD1 PJ5 MD0 PJ4 MD1 PJ4 MD0 PJ3 MD1 PJ3 MD0 PJ.
Rev. 5.00, 09/0 3, page 580 of 760 18.3.10 Port K Control R egister (PKCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PK7 MD1 PK7 MD0 PK6 MD1 PK6 MD0 PK5 MD1 PK5 MD0 PK4 MD1 PK4 MD0 PK3 MD1 PK3 MD0 PK.
Rev. 5.00, 09/03, pa ge 581 of 760 18.3.11 Port L Control R egister (PLCR ) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PL7 MD1 PL7 MD0 PL6 MD1 PL6 MD0 PL5 MD1 PL5 MD0 PL4 MD1 PL4 MD0 PL3 MD1 PL3 MD0 P.
Rev. 5.00, 09/0 3, page 582 of 760 18.3.12 SC Port Control Regi ster (SCPCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCP7 MD1 SCP7 MD0 SCP6 MD1 SCP6 MD0 SCP5 MD1 SCP5 MD0 SCP4 MD1 SCP4 MD0 SCP3 MD1.
Rev. 5.00, 09/03, pa ge 583 of 760 Bits 11 a nd 10—SCP5 Mode 1 and 0 (SCP5MD1, SCP5MD0): These bits select the pin functi o ns a nd p e rf o rm inpu t pu l l-up M OS co ntro l. Bit 11 Bit 10 SCP5MD1 SCP5MD0 Pin Function 0 0 Other function (see t able 18.
Rev. 5.00, 09/0 3, page 584 of 760 Bits 5 and 4 —SCP2 Mode 1 and 0 (SCP 2 MD1, SC P2MD0): These bits select the pin function and p e rfo rm input pul l -up MOS co ntro l.
Rev. 5.00, 09/03, pa ge 585 of 760 Bits 1 and 0 —SCP0 Mode 1 and 0 (SCP 0 MD1, SC P0MD0): These bits select th e pin function and p e rfo rm input pul l -up MOS co ntro l.
Rev. 5.00, 09/0 3, page 586 of 760.
Rev. 5.00, 09/03, pa ge 587 of 760 Section 19 I/O Ports 19.1 Overview The SH7709S has twelve 8- bit ports (ports A to L and SC). All port pins are multiplexed with other pin functio ns (the pin function controller (PFC) handles the select ion of pin funct ions and pull-u p MOS control).
Rev. 5.00, 09/0 3, page 588 of 760 19.2.2 Port A Data Register (PADR) B i t : 76543210 PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W The port A data reg ister (PADR) is an 8-bit readable/w ritable register that stores data for pins PTA7 t o PT A0 .
Rev. 5.00, 09/03, pa ge 589 of 760 19.3 Port B Por t B is an 8-bit input /out put p ort wi th the pin configu rati on sh own in fi gure 19.2. Each pin has an input pull-up MOS, which is controlled b y the port B control r egister (PBC R) in the PFC.
Rev. 5.00, 09/0 3, page 590 of 760 19.3.2 Port B Data Register (PBDR) B i t : 76543210 PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W The port B data register (PBDR) is an 8-bit readable/ writable register that stores data for pins PTB 7 to PTB 0.
Rev. 5.00, 09/03, pa ge 591 of 760 19.4 Port C Port C is an 8-bit in p ut/output port with the pin configuration shown i n figure 19.3. Each pin has an in put pull-up MOS, w hich is controlled by th e port C cont rol register (PCCR) in t he PFC.
Rev. 5.00, 09/0 3, page 592 of 760 19.4.2 Port C Data Register (PCDR) B i t : 76543210 PC7DT PC6DT PC5DT PC4DT PC3 DT PC2DT PC1DT PC0DT I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W The p ort C data r egister ( PCDR) is an 8-bi t r eadable/writable register that stores data for pins PTC7 to PT C0 .
Rev. 5.00, 09/03, pa ge 593 of 760 19.5 Port D Port D c ompris es a 6-bit inp ut/output port a nd 2-bit input p ort with the pin configurat ion shown in figure 19.4. Each pin has a n input pull- up MOS, which is controlled by the port D control register (PD CR) in the P FC.
Rev. 5.00, 09/0 3, page 594 of 760 19.5.2 Port D Data Register (PDDR) B i t : 76543210 PD7DT PD6DT PD5DT PD4DT PD3 DT PD2DT PD1DT PD0DT Initial valu e: 0 * 0 * 0000 R/W: R/W R R/W R R/W R/W R/ W R/W N.
Rev. 5.00, 09/03, pa ge 595 of 760 19.6 Port E Po rt E i s an 8-b it inpu t/output port with th e pin con f iguration show n in figure 19.5. Ea ch pin h as an input pull-up MOS, which is contro lled b y the port E control register (PEC R) in the PFC.
Rev. 5.00, 09/0 3, page 596 of 760 19.6.2 Port E D ata Register (PE DR) B i t : 76543210 PE7DT PE6DT PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W The port E data register (PEDR) i s an 8-bit readable/w r itable register that st ores data for pins PTE 7 to PTE0 .
Rev. 5.00, 09/03, pa ge 597 of 760 19.7 Port F Por t F is an 8-bit input port wi th the pin c onfi gur at ion shown in f igure 19.6. Each pin has a n i nput pull-up MOS, which is controlled b y the port F contro l register (PFCR ) in the PFC.
Rev. 5.00, 09/0 3, page 598 of 760 19.7.2 Port F Data Regi ster (PFDR) B i t : 76543210 PF7DT PF6DT PF5DT PF4DT PF3DT PF2DT PF1DT PF0DT Initial valu e: ******** R / W : RRRRRRRR Note: * Undefined The port F data regist er (PFDR) is an 8-bit read-only register that stores data for pins PTF7 to PTF0 .
Rev. 5.00, 09/03, pa ge 599 of 760 19.8 Port G Port G c ompris es a 5-bit inp ut/output port a nd 3-bit input p ort with the pin configurat ion shown in figur e 1 9.7 . E ach p in has an input pul l-up MO S, whi ch i s cont rol led b y the p or t G c ontr ol regist er (PG CR) in the P FC.
Rev. 5.00, 09/0 3, page 600 of 760 19.8.2 Port G Data Register (PG DR) B i t : 76543210 PG7DT PG6DT PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT Initial valu e: ******** R / W : RRRRRRRR Note: * Undefined The port G dat a regist er (PGDR) i s an 8-bit read-on ly register that stores data for pins PTG7 to PTG0.
Rev. 5.00, 09/03, pa ge 601 of 760 19.9 Port H Port H c ompris es a 1-bit inp ut/output port a nd 7-bit input p ort with the pin configurat ion shown in figur e 1 9.8 . E ach p in has an input pul l-up MO S, whi ch i s cont rol led b y the p or t H c ontr ol regist er (PH CR) in the P FC.
Rev. 5.00, 09/0 3, page 602 of 760 19.9.2 Port H Data R egister (PHD R) B i t : 76543210 PH7DT PH6DT PH5DT PH4DT PH3 DT PH2DT PH1DT PH0DT Initial valu e: 0 ******* R / W : R / W RRRRRRR Note: * Undefined The port H data register (PHD R) is a 1-bit readable/w ri table and 7-bit rea d-only register that stores data for pins PTH7 t o P TH0.
Rev. 5.00, 09/03, pa ge 603 of 760 19.10 Port J Port J is an 8- bit input/o utput port with the pin co nfig uration shown in figure 19.9. Eac h pin has an input pull-up MOS, which is controlled b y the port J control r egister (PJC R) in the PFC.
Rev. 5.00, 09/0 3, page 604 of 760 19.10.2 Port J Data Register ( PJDR) B i t : 76543210 PJ7DT PJ6DT PJ5DT PJ 4DT PJ3DT PJ2DT PJ 1DT PJ0DT I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W The port J data regis ter (PJDR) is an 8-bit readable/w r itable register that stores data f o r pins PTJ7 to PTJ 0.
Rev. 5.00, 09/03, pa ge 605 of 760 19.11 Port K Por t K is an 8-bit input /output po rt with the pin c onfigurat ion shown in figu re 19.10. Each pin has an input pull-up MOS, which is co ntro lled b y the port K control register (PKC R) in the PFC.
Rev. 5.00, 09/0 3, page 606 of 760 19.11.2 Port K Data Register (P KDR) B i t : 76543210 PK7DT PK6DT PK5DT PK4DT PK3DT PK2DT PK1DT PK0DT I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W The port K data register (PK DR) is an 8-bit readable/w r itable register that stores data for pins PTK 7 to PT K 0 .
Rev. 5.00, 09/03, pa ge 607 of 760 19.12 Port L Port L is an 8-bit in put port with the pin configuratio n s hown in figure 19.11. PTL7 (input) / AN7 (input) / DA0 (input) PTL6 (input) / AN6 (input) /.
Rev. 5.00, 09/0 3, page 608 of 760 19.12.2 Port L Data Regis ter (PLDR) B i t : 76543210 PL7DT PL6DT PL5DT P L4DT PL3DT PL2DT PL1D T PL0DT I n i t i a l v a l u e : 00000000 R / W : RRRRRRRR The port L data register (PLDR) is an 8-bit read -only register that stores data for pin s PTL7 to PTL0.
Rev. 5.00, 09/03, pa ge 609 of 760 19.13 SC Port The SC port com prises a 4- bit input/ou tput port, 3-bit ou tput port , and 4-bit input p or t with the p in configuration shown in figure 19.12. Each pin has an i nput pull-up MOS, which is controlled by the SC port con trol regi s ter (SCP CR) in the PFC.
Rev. 5.00, 09/0 3, page 610 of 760 19.13.2 SC Port Data Register (SCPDR) B i t : 76543210 SCP7DT SCP6DT SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT Initial valu e: * 0000000 R/W: R R/W R/W R/ W R/W R/W .
Rev. 5.00, 09/03, pa ge 611 of 760 Table 19.24 Read/Write Operation of the SC Port Data Register (SCPDR) SCPnMD1 SCPnMD0 Pin State Read Write 0 0 Other fun ction (see table 18.
Rev. 5.00, 09/0 3, page 612 of 760.
Rev. 5.00, 09/03, pa ge 613 of 760 Section 20 A/ D Converter 20.1 Overview The SH7709S in cludes a 10-bit successiv e-approxim ation A/D convert er allowing selection of up to e ight a nalo g inp ut c hanne ls . 20.1.1 Features A/D converter f eatures are listed below.
Rev. 5.00, 09/0 3, page 614 of 760 20.1.2 Block D iagram Figure 20.1 s hows a block diagram of the A/D converter. 10-bit D/A ADDRA ADDRB ADDRD Bus interface Peripheral data bus Analog multi- plexer Co.
Rev. 5.00, 09/03, pa ge 615 of 760 20.1.3 In put Pins Table 20.1 sum marizes the A/D convert er’s inpu t pins. The ei ght analog i npu t pins are divided into t wo gro ups: gro up 0 (AN 0 t o A N 3) , and g roup 1 (AN4 to AN7) . AV CC and AV SS are the power su pply inputs for the analog circuits in the A/D converter.
Rev. 5.00, 09/0 3, page 616 of 760 20.1.4 Regi ster Configuration Table 20.2 summarizes the A/D conv erter’s registers. Table 20.2 A/D Converter Registers Name Abbreviation R/W Initial Value Address.
Rev. 5.00, 09/03, pa ge 617 of 760 20.2 Register Descriptions 20.2.1 A/D Data Regi sters A to D (ADDRA to ADDRD) Upper register: H B i t : 76543210 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 I n i t i a l v a l .
Rev. 5.00, 09/0 3, page 618 of 760 20.2.2 A/D Control/Status Register (ADCSR) B i t : 76543210 ADF ADIE ADST MULTI CKS CH2 CH1 CH0 I n i t i a l v a l u e : 00000000 R/W: R/(W ) * R/W R/ W R/W R/ W R/W R/W R/ W Note: * W rite 0 to clear the flag. ADCSR is an 8-bit readable/ writable register that selects th e mode and controls the A/D converter.
Rev. 5.00, 09/03, pa ge 619 of 760 Bit 5—A/D Start (ADS T): Starts or stop s A/D conversion. The ADST bit remains set to 1 during A/D c onve rsi on. It c an al so be set to 1 by exter na l trigger input at the ADTRG pin.
Rev. 5.00, 09/0 3, page 620 of 760 Bits 2 to 0—Channel Select 2 to 0 (C H2 to CH0): T hese bits and th e MULTI bit select the analog input chann els.
Rev. 5.00, 09/03, pa ge 621 of 760 20.2.3 A/D Contro l Register (ADCR) B i t : 76543210 TRGE1 TRGE0 SCN RESVD1 RESVD2 — — — I n i t i a l v a l u e : 00000111 R/W: R/W R/ W R/W R/ W R/W R R R ADCR is an 8-bit readable/ writable reg ister that enables or disables ex ternal triggering of A/D conversion.
Rev. 5.00, 09/0 3, page 622 of 760 20.3 Bus Master Interf ace ADDRA to ADDRD are 1 6-bit regis ters, but the y are connected to the bus master by the upper 8 bits of the 16-bit periph eral data bus.
Rev. 5.00, 09/03, pa ge 623 of 760 20.4 Operation The A/D conv erter operates by successive appro ximations with 10-bit resolutio n. It has t hree operating modes: single mode, multi m o de, and scan mode. 20.4.1 Sin gle Mode (MULTI = 0) Single mod e s hould be se lect ed when only one A /D c onve rsi on on one cha nne l is requ ire d.
Rev. 5.00, 09/0 3, page 624 of 760 Channel 0 (AN0) operating ADIE ADST ADF Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA ADDRB ADDRC ADDRD Waiting Waiting Waiting.
Rev. 5.00, 09/03, pa ge 625 of 760 20.4.2 Multi Mode ( M ULTI = 1, SCN = 0) Multi mod e sho uld be selecte d when perfo rming A/D conver sions on one or more channels . When the ADST bit is set to 1 by software or external trigger input, A/D conv ersion starts on the first channel in th e group (AN0 w hen C H2 = 0, AN4 w h en CH2 = 1).
Rev. 5.00, 09/0 3, page 626 of 760 Channel 0 (AN0) operating ADST ADF Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA ADDRB ADDRC ADDRD Waiting Waiting Waiting Wait.
Rev. 5.00, 09/03, pa ge 627 of 760 20.4.3 Scan Mode (MULTI = 1, SCN = 1) Scan m ode is u seful for m onitoring analog inpu ts in a g roup of o ne or more channels.
Rev. 5.00, 09/0 3, page 628 of 760 ADST ADF Channel 0 (AN 0 ) operating Channel 1 (AN 1 ) operating Channel 2 (AN 2 ) operating Channel 3 (AN 3 ) operating ADDRA ADDRB ADDRC ADDRD Waiting Waiting Wait.
Rev. 5.00, 09/03, pa ge 629 of 760 20.4.4 Input Sa mpling and A/D Co nvers io n Time The A/D converter h as a built-in sam ple-and-hold circuit. The A/D converter samples the analog input at a time t D after the ADST bit is set t o 1, then s tarts conv er sion.
Rev. 5.00, 09/0 3, page 630 of 760 Table 20.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Sy mbol Min T y p Max Min Ty p Max A/D conversion start delay t D 17 — 28 10 — 17 Input sampling t ime t SPL — 129 —— 65 — A/D conversion time t CONV 514 — 525 259 — 266 Note: Value s in the tab le are numbe r s of states ( t cyc ).
Rev. 5.00, 09/03, pa ge 631 of 760 20.5 Interrupts The A/D converter g enerates an interrupt (ADI) at the end of A/D conversion. Th e ADI interrupt request can be enabled or disabled b y the ADIE bit in ADCSR.
Rev. 5.00, 09/0 3, page 632 of 760 111 110 101 100 011 010 001 000 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage FS: Full-scale voltage (3) Quantization error Ideal A/D conversion characterist.
Rev. 5.00, 09/03, pa ge 633 of 760 20.7.3 Access S ize and Read D ata Table 2 0 .6 shows the relationship between acce ss si ze and read data. Note the read data obtained with dif f erent access size s, bus widths, and endian modes. The case is shown here in which H'3FF is obtaine d whe n AV CC is input as an analog inp ut.
Rev. 5.00, 09/0 3, page 634 of 760 Table 20. 5 Ana lo g Input Pin Ra tings Item Min Max Unit Analog input capa cit an c e — 20 pF Allowable sig nal- source impedance — 5k Ω Table 20.
Rev. 5.00, 09/03, pa ge 635 of 760 Section 21 D/ A Converter 21.1 Overview The SH7709S in cludes a D /A converter w ith two channe ls. 21.1.1 Features D/A converter f eatures are listed below.
Rev. 5.00, 09/0 3, page 636 of 760 21.1.3 I/O Pi ns Table 21.1 sum marizes the D/A conv erter ’s input and outp ut pins. Table 21.1 D/A Converter Pins Pin Name Abbrev iation I/O Function Analog pow .
Rev. 5.00, 09/03, pa ge 637 of 760 21.2 Register Descriptions 21.2.1 D/A Data Registe rs 0 and 1 (DADR0/1) B i t : 76543210 I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/W R/ W R/W R/W R/ W The D/A data registers (DADR0 and DADR1) are 8-bit readable/w r itable registers that st ore the dat a to b e conve rte d.
Rev. 5.00, 09/0 3, page 638 of 760 Bit 5—D/A Enable (DAE): Control s D/A conv ersion, together wi th bi ts DAOE0 an d DAOE1. When the DAE bit is cleared t o 0, D/A conv ers io n is controlled in d ependentl y in c hannel s 0 an d 1.
Rev. 5.00, 09/03, pa ge 639 of 760 21.3 Operation The D/A conv ert er has two b uilt-i n D/A con ver sio n circ uits t hat can perfo rm conversion independen tly. D/A conversion is performed constantly while enable d in DA CR. If the DA DR0 or DADR1 value is modified, conv ersio n of the new data begins immediately.
Rev. 5.00, 09/0 3, page 640 of 760.
Rev. 5.00, 09/03, pa ge 641 of 760 Section 22 User Debugging Interface (UDI) 22.1 Overview This LSI incorp orates a User deb ugging inter face (UDI) and ad vanced user d ebugger (AUD) for program debugging. 22.2 User D ebugging Interface (UDI) The UDI (User debugging inter face) perfo rms on-chip de bugging which is supporte d by t his LSI.
Rev. 5.00, 09/0 3, page 642 of 760 mode, boun dar y scan and emulator func tions ca n be used. The input lev el a t the ASEMD0 pin should be held fo r at leas t one cycle after R ESETP nega tio n. A A A AS S S SE E E EB B B BR R R R KAK KAK KAK KAK : Dedicated emulator pin 22.
Rev. 5.00, 09/03, pa ge 643 of 760 Table 22.1 show s the U DI register con f iguration. Table 22.1 UDI Registers CPU Side UDI Side Initial Name Abbrev iation R/W Size Address R/W Size Value * Bypass r.
Rev. 5.00, 09/0 3, page 644 of 760 Table 22. 2 UDI Co mmands Bit 15 to 12 TI3 TI2 TI1 TI0 Description 0000E X T E S T 0100S A M P L E / P R E L O A D 0101R e s e r v e d 0110U D I r e s e t n e g a t .
Rev. 5.00, 09/03, pa ge 645 of 760 Table 22.3 Pins of t his LSI and Boundary Scan Register Bit s Bit Pin Name I/O Bit Pin Name I/O from TDI 308 D1 IN 338 D31/PTB7 IN 307 D0 IN 337 D30/PTB6 IN 306 MD1 .
Rev. 5.00, 09/0 3, page 646 of 760 Bit Pin Name I/O Bit Pin Name I/O 277 D10 OUT 247 D12 Control 276 D9 OUT 246 D11 Control 275 D8 OUT 245 D10 Control 274 D7 OUT 244 D9 Control 273 D6 OUT 243 D8 Contr.
Rev. 5.00, 09/03, pa ge 647 of 760 Bit Pin Name I/O Bit Pin Name I/O 217 A7 OU T 187 CS4 /PTK2 OUT 216 A8 OU T 186 CS5 / CE1A /PTK3 OUT 215 A9 OU T 185 CS6 / CE1B OUT 214 A10 OUT 184 CE2A /PTE4 OUT 21.
Rev. 5.00, 09/0 3, page 648 of 760 Bit Pin Name I/O Bit Pin Name I/O 157 A25 Control 127 BREQ IN 156 BS/PTK4 Control 126 WAIT IN 155 RD Control 125 AUDCK/PTH6 IN 154 WE0 /DQM LL Control 124 IOIS16 /PT.
Rev. 5.00, 09/03, pa ge 649 of 760 Bit Pin Name I/O Bit Pin Name I/O 97 ASEBRKAK /PTG5 OUT 65 RxD2/SCPT4 IN 96 AUDATA 3/PTG3 OUT 64 WAKEUP /PTD3 IN 95 AUDATA 2/PTG2 OUT 63 RESETOUT /PTD2 IN 94 AUDATA1.
Rev. 5.00, 09/0 3, page 650 of 760 Bit Pin Name I/O Bit Pin Name I/O 33 MCS6 /PTC6/PINT6 OUT 15 SCK1/SCPT3 Control 32 MCS5 /PTC5/PINT5 OUT 14 TxD2/SCPT4 Con trol 31 MCS4 /PTC4/PINT4 OUT 13 SCK2/SCPT5 .
Rev. 5.00, 09/03, pa ge 651 of 760 22.4 UDI Operation 22.4.1 TAP C ontroller Figure 22.2 s hows the intern al states of the TAP con troller. Stat e transitions basically conform wi th the JTA G stan dard.
Rev. 5.00, 09/0 3, page 652 of 760 22.4.2 Reset Confi guration Table 22.4 Reset Configuration ASE ASE ASE ASEM M M MD D D D0 0 0 0 * 1 R R R RESE ESE ESE ESET T T TP P P PT T T TR R R RS S S ST T T T .
Rev. 5.00, 09/03, pa ge 653 of 760 22.4.3 UDI R e s et An UDI res et is execu te d by se tt ing an UDI r ese t asser t comma nd in SDIR. An UDI res et is of the same ki nd as a po wer-on reset. An UDI reset is release d by inputt ing an UDI reset negate comma nd .
Rev. 5.00, 09/0 3, page 654 of 760 22.5 Boundary Scan A command can be set in SDIR by the UDI to place the UDI pins in the boundar y scan mode stipulated by JTAG. 22.5.1 Supported Inst ructions This LSI supports the three essential instructions defined in the JTAG standard ( BYPAS S, SAM P LE/ PRE LO AD, a nd E XT EST ) .
Rev. 5.00, 09/03, pa ge 655 of 760 Data loaded in to the ou tput pin boundary scan regi ster in the Capture- DR state is not used for extern al circuit testin g (it is repl aced by a shi f t ope r a t i on) . The inst ruction code is 0000. 22.5.2 Points for Atten t i on 1.
Rev. 5.00, 09/0 3, page 656 of 760.
Rev. 5.00, 09/03, pa ge 657 of 760 Section 23 Electrical Characteristics 23.1 Absolute Maximu m Ratings Table 23.1 sh ows th e absolute maximum ratings. Table 23. 1 Abso lute M aximum Rating s Item S y mbol Rating Unit Power supply voltage ( I/O) VccQ –0.
Rev. 5.00, 09/0 3, page 658 of 760 Pin states undefined (Max. 1 ms) 3.3 V 1.7 V/1.8 V/1.9 V/2.0 V 3.3 V power 1.7 V/1.8 V/1.9 V/2.0 V power RESETP A ll other pins * Pin states undefined Power-on reset state Note: * Except power/GND, clock related, and analog pins Power-On Sequence • Pow e r-off order 1.
Rev. 5.00, 09/03, pa ge 659 of 760 23.2 DC Characteristics Tables 23.2 and 23.3 list DC characteristics. Table 23.2 DC Characteristics Ta = –20 to 75° C Item S y mbol Min T y p Max Unit Measurement Conditi ons Power supply voltage VccQ 3.0 3.3 3.6 V Vcc, 1.
Rev. 5.00, 09/0 3, page 660 of 760 Item S y mbol Min T y p Max Unit Measurement Conditi ons Input high voltage RESETP , RESETM , NMI, IRQ5 to IRQ0, MD5 to MD 0, IRL3 to IRL0 , IRLS3 to IRLS0 , PINT15 to PINT0, ASEMD0 , ADTRG , TRST , EXTAL, CKIO, RxD1, CA V IH VccQ × 0.
Rev. 5.00, 09/03, pa ge 661 of 760 Item S y mbol Min Ty p Max Unit Meas urement Conditi ons Input low voltage RESETP , RESETM , NM I, IRQ5–IRQ0, MD5–MD 0, IRL3 to IRL0 , IRLS3 to IRLS0 , PINT15– PINT0, ASEMD0 , ADTRG , TRST , EXTAL, CKIO, RxD1, CA V IL –0.
Rev. 5.00, 09/0 3, page 662 of 760 Item Sy mbol Min T y p Max Unit Measurement Conditions Analog power- supply voltage AVcc 3.0 3.3 3.6 V Analog power- supply During A/D conversion AIcc — 0.
Rev. 5.00, 09/03, pa ge 663 of 760 23.3 AC Ch aracteristics In g eneral, in putting for this LSI should be cloc k synch ronous. Keep the setup a nd hold t imes for each input signal un less otherwise specified. Table 23.4 Opera t ing F requency Ra nge VccQ = 3.
Rev. 5.00, 09/0 3, page 664 of 760 23.3.1 Clock Timing Table 23.5 Clock Timing VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.1 5 V, AV cc = 3.3 ± 0.3 V, Ta = –20 to 75° C Item Sy mbol Min Max Unit Figure EXTAL clock input frequenc y (clock mode 0) f EX 25 66.
Rev. 5.00, 09/03, pa ge 665 of 760 t EXH t EXF t EXR t EXL t EXcyc V IH V IH V IH 1/2 V CC Q 1/2 V CC Q V IL V IL EXTAL * (input) Note: * The clock input from the EXTAL pin. Figure 23 .1 EXTAL Cl ock Inpu t T iming t CKIH t CKIF t CKIR t CKIL t CKIcyc V IH 1/2 V CC Q 1/2 V CC Q V IH V IL V IH V IL CKIO (input) Figure 23.
Rev. 5.00, 09/0 3, page 666 of 760 V CC min t RESPW t RESPS t OSC1 V CC RESETP CKIO, internal clock Stable oscillation Note: Oscillation settling time when built-in oscillator is used Figure 23.
Rev. 5.00, 09/03, pa ge 667 of 760 CKIO, internal clock Stable oscillation Standby t OSC3 NMI Note: Oscillation settling time when built-in oscillator is used in the oscillation off mode WAKEUP Figure 23.
Rev. 5.00, 09/0 3, page 668 of 760 EXTAL input or CKIO input Stable input clock Reset or NMI interrupt request Stable input clock Normal Normal Standby PLL output, CKIO output Internal clock STATUS 0 .
Rev. 5.00, 09/03, pa ge 669 of 760 EXTAL input * 1 (CKIO input) CKIO output * 2 (PLL output) Internal clock Multiplication rate modified t PLL2 Notes: 1.
Rev. 5.00, 09/0 3, page 670 of 760 23.3.2 Control Signal T imin g Table 23.6 Control S ignal T iming Vcc = 3.3 ± 0.3 V, Vcc = 1. 55 to 2.15 V, AV cc = 3.3 ± 0.3 V , Ta = –2 0 to 7 5 °C Item S y mbol Min M ax Unit Figure RESETP pulse w idth t RESPW 20 * 2 — tcyc 23.
Rev. 5.00, 09/03, pa ge 671 of 760 CKIO t RESPS/MS t RESPS/MS RESETP RESETM t RESPW/MW Figure 23. 11 Reset I nput Ti ming CKIO RESETP RESETM t RESPH/MH t RESPS/MS V IH V IL NMI t NMIH t NMIS V IH V IL IRQ5 to IRQ0 t IRQH t IRQS V IH V IL Figure 23. 12 Interrupt Signal Input Timing CKIO t IRQOD t IRQOD IRQOUT Figure 23.
Rev. 5.00, 09/0 3, page 672 of 760 CKIO BREQ BACK RD , RD/ WR , RAS , CAS , CSn , WEn , BS , A25 to A0, D31 to D0 t BACKD t BOFF2 t BOFF1 t BON1 t BACKD t BON2 t BREQH t BREQH t BREQS t BREQS MCSn Figure 23.
Rev. 5.00, 09/03, pa ge 673 of 760 23.3.3 AC Bu s Timi n g Table 23. 7 B us Timing Clock Modes 0/1/2/7, VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75° C Item S y mbol Min Max Unit Figure Address delay time t AD 1.5 12 ns 23.
Rev. 5.00, 09/0 3, page 674 of 760 Item S y mbol Min Max Unit Figure ICIORD delay ti me t ICRSD — 10 ns 23.44–23.46 ICIOWR delay time t ICWSD — 10 ns 23.44–23.46 IOIS16 setup time t IO16S 6 — ns 23.45, 23. 46 IOIS16 hold t ime t IO16H 4 — ns 23.
Rev. 5.00, 09/03, pa ge 675 of 760 23.3.4 Basic T imin g T 1 CKIO A25 to A0 CSn RD/ WR RD D31 to D0 (read) WEn D31 to D0 (write) BS T 2 t AD t AH t AD t CSD1 t RWD t RSD t CSD2 t WED t WDD1 t RDS1 t BSD t BSD t DAKD1 t DAKD1 t RDH1 t RDH1 t WED t RSD t AH t RWH t RWD t WDH1 t RWH t RWH t AH t WDH3 DACKn (read) (write) t AS Figure 23.
Rev. 5.00, 09/0 3, page 676 of 760 T 1 T w T 2 CKIO A25 to A0 CSn RD/ WR RD D31 to D0 (read) WEn D31 to D0 (write) BS WAIT t AD t AD t RWD t RWH t AH t AH t RSD t CSD1 t WED t WDD1 t BSD t WTS t WTH t BSD t RDS1 t CSD2 t WED t RSD t RDH1 t RDH1 t RWD t AH t RWH t WDH3 t WDH1 t RWH t DAKD1 t DAKD1 DACKn (read) (write) t AS Figure 23.
Rev. 5.00, 09/03, pa ge 677 of 760 t RDH1 t AH t RSD t WED t AH t WDD1 T 1 T w T w T 2 CKIO A25 to A0 CSn RD/ WR RD (read) D31 to D0 (read) WEn (write) D31 to D0 (write) BS WAIT t AD t AD t RWD t RSD t WED t WTS t WTH t BSD t BSD t RDS1 t WTS t WTH t CSD1 t CSD2 t RDH1 t RWH t AH t RWH t RWD t RWH t WDH3 t WDH1 t DAKD1 t DAKD2 DACKn t AS Figure 23.
Rev. 5.00, 09/0 3, page 678 of 760 23.3.5 Burs t ROM Tim ing CKIO A25 to A4 A3 to A0 CSn RD/ WR RD D31 to D0 BS DACKn WAIT t AD t AD t AD t AD t CSD1 t RWD t BSD t BSD t AH t BSD t DAKD1 t DAKD2 t CSD.
Rev. 5.00, 09/03, pa ge 679 of 760 t RSD t AH t RSD t AH t AH t RDH1 CKIO A25 to A4 A3 to A0 CSn RD/ WE RD D31 to D0 Note: In the write cycle, the basic bus cycle is performed.
Rev. 5.00, 09/0 3, page 680 of 760 CKIO A25 to A4 A3 to A0 CSn RD/ WR RD D31 to D0 BS DACKn WAIT T 1 T w T w T B2 T B1 T 2 T Bw t AD t AD t CSD1 t CSD2 t RWD t RWH t RDH1 t AH t AH t RWD t RSD t RSD1 .
Rev. 5.00, 09/03, pa ge 681 of 760 23.3.6 Synchron ous DRAM Timing CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tr tAD Row address Row address Read A command Row address Column.
Rev. 5.00, 09/0 3, page 682 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE (High) A25 to A16 A15 to A0 Tr Trw Trw Tc1 Tcw Td1 (Tpc) (Tpc) D31 to D0 Row address Row address Read A command Row a.
Rev. 5.00, 09/03, pa ge 683 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE (High) A25 to A16 A15 to A0 Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 (Tpc) (Tpc) D31 to D0 Row address Row address Read A c.
Rev. 5.00, 09/0 3, page 684 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 (Tpc) D31 to D0 (read) tAD tAD tAD tAD tAD tAD tAD tAD tA.
Rev. 5.00, 09/03, pa ge 685 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tr Tc1 (Trwl) (Tpc) (High) D31 to D0 tAD Row address Row address Write A command Row address Col.
Rev. 5.00, 09/0 3, page 686 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tr Trw Trw Tc1 (Trwl) (Trwl) (Tpc) (Tpc) (High) D31 to D0 tAD Row address Row address Write A co.
Rev. 5.00, 09/03, pa ge 687 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tr Tc1 Tc2 Tc3 Tc4 (Trwl) (Tpc) (Tpc) (High) D31 to D0 tAD Row address Row address Write A comma.
Rev. 5.00, 09/0 3, page 688 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE (High) A25 to A16 A15 to A0 Tr Trw Tc1 Tc2 Tc3 Td4 (Trwl) (Tpc) D31 to D0 Row address Row address Write A command Wri.
Rev. 5.00, 09/03, pa ge 689 of 760 CKIO A 12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A 25 to A16 A 15 to A0 Tnop Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 D31 to D0 t AD t AD t CSD3 t CSD3 t RWD t RWD t RASD2 t .
Rev. 5.00, 09/0 3, page 690 of 760 A25 to A16 (High) t AD t AD t AD t CASD2 t CSD3 t RWD t DQMD t BSD t RDH2 t RDS2 t RDH2 t RDS2 t BSD t RASD2 t CASD2 t DQMD t RWD t CSD3 t AD t AD t AD Tc1 Tc2 Tc3/T.
Rev. 5.00, 09/03, pa ge 691 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tp Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 D31 to D0 t AD t AD t CSD3 t CSD3 t RWD t RWD t RWD t RASD.
Rev. 5.00, 09/0 3, page 692 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tp Tpw Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 D31 to D0 t AD t AD t CSD3 t CSD3 t RWD t RWD t RWD t RASD.
Rev. 5.00, 09/03, pa ge 693 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tc1 Tc2 Tc3 Tc4 D31 to D0 t AD t AD t CSD3 t CSD3 t RWD t RWD t RASD2 t RASD2 t DQMD t DQMD t WDD2 t WDD2 t BSD t BSD (High) t AD t AD t AD t CASD2 t CASD2 t AD Row address Write command Column address t DAKD1 t DAKD1 DACKn Figure 23.
Rev. 5.00, 09/0 3, page 694 of 760 t WDD2 t WDD2 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tp Tr Tc1 Tc2 Tc3 Tc4 D31 to D0 t AD t AD t CSD3 t CSD3 t RWD t RWD t RWD t RWD t .
Rev. 5.00, 09/03, pa ge 695 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tp Tpw Tr Trw Tc1 Tc2 Tc3 D31 to D0 t AD t AD t CSD3 t CSD3 t RWD t RWD t RWD t RWD t RASD2 t RA.
Rev. 5.00, 09/0 3, page 696 of 760 CKIO CSn RD/ WR CASxx CKE RAS3x Tp Tpc TRr TRrw TRrw (Tpc) (Tpc) t CSD3 t CSD3 t CSD3 t CSD3 t RASD2 t RASD2 t RASD2 t RASD2 t CASD2 t CASD2 t RWD t RWD (High) Figure 23.
Rev. 5.00, 09/03, pa ge 697 of 760 Tpc TRa1 (TRs2) (TRs2) TRs3 CKIO CKE CSn RAS CAS RD/ WR t RWD t RWD t CASD2 t RASD2 t CSD3 t CASD2 t CSD3 t RASD2 Tp t CSD3 t CSD3 t RASD2 t RASD2 (Tpc) (Tpc) t CKED t CKED t RWD Figure 23.
Rev. 5.00, 09/0 3, page 698 of 760 CKIO A12 or A10 RD/ WR CSn RAS CASxx D31 to D0 A13 or A11 A11 to A2 or A9 to A2 TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 (High) CKE tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tCSD3 tRWD tRWD tRWD tRASD2 tRASD2 tRASD2 tRASD2 tCASD2 tCASD2 t DAKD1 t DAKD1 DACKn Figure 23.
Rev. 5.00, 09/03, pa ge 699 of 760 23.3.7 PCMCIA Ti ming T pcm1 T pcm2 CKIO A25 to A0 CExx RD/ WR RD D15 to D0 WE1 D15 to D0 BS DACKn t AD t AD t CSD1 t CSD1 t RWD t RSD t RSD t RWD t DAKD1 t DAKD1 t WED t WDD1 t WED t RDS1 t RDH1 t BSD t BSD t WDH4 t WDH1 (read) (read) (write) (write) Figure 23.
Rev. 5.00, 09/0 3, page 700 of 760 CKIO T pcm0 T pcm0w T pcm1 T pcm1w T pcm1w T pcm2 T pcm2w A25 to A0 CExx RD/ WR RD (read) D15 to D0 (read) WE1 (write) D15 to D0 (write) BS DACKn WAIT t AD t CSD1 t RWD t AD t CSD1 t RWD t WDH4 t RSD t RSD t DAKD1 t DAKD1 t WED t WDD1 t WED t WDH1 t RDH1 t BSD t WTS t WTH t WTS t WTH t RDS1 t BSD Figure 23.
Rev. 5.00, 09/03, pa ge 701 of 760 CKIO T pcm1 T pcm2 T pcm1 T pcm2 T pcm1 T pcm2 T pcm1 T pcm2 A25 to A4 A3 to A0 CExx RD/ WR RD D15 to D0 BS DACKn t AD t AD t CSD1 t RWD t CSD1 t RWD t AD t AD t AD .
Rev. 5.00, 09/0 3, page 702 of 760 t RDS1 t RSD CKIO T pcm0 T pcm1 T pcm1w T pcm1w T pcm1w T pcm2 T pcm1 T pcm1w T pcm2 T pcm2w A25 to A4 A3 to A0 CExx RD/ WR RD (read) D15 to D0 (read) Note: Even though burst mode is set, the write cycle operation is the same as in normal mode.
Rev. 5.00, 09/03, pa ge 703 of 760 T pci1 T pci2 CKIO A25 to A0 CExx RD/ WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS DACKn t AD t AD t CSD1 t CSD1 t RWD t ICRSD t ICRSD t RWD t DAKD1 t DAKD1 t ICWSD t WDD1 t ICWSD t RDH1 t RDS1 t BSD t BSD t WDH1 t WDH4 Figure 23.
Rev. 5.00, 09/0 3, page 704 of 760 CKIO T pci0 T pci0w T pci1 T pci1w T pci1w T pci2 T pci2w A25 to A0 CExx RD/ WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS DACKn WAIT IOIS16 .
Rev. 5.00, 09/03, pa ge 705 of 760 CKIO T pci0 T pci1 T pci1w T pci2 T pci1 T pci1w T pci2 T pci2w A25 to A4 A0 CExx RD/ WR ICIORD D15 to D0 ICIOWR D15 to D0 BS WAIT IOIS16 DACKn t AD t AD t CSD1 t CS.
Rev. 5.00, 09/0 3, page 706 of 760 23.3.8 Peripheral Module Signal T iming Table 23.8 Periphera l Mo dule Signal Timing VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.1 5 V, AV cc = 3.3 ± 0.3 V, Ta = –20 to 75° C Module Item Sy mbol Min Max Unit Figure Timer input setu p time t TCLKS 15 — ns 23.
Rev. 5.00, 09/03, pa ge 707 of 760 t TCLKS CKIO TCLK (input) Figure 23.47 TCLK Input Timing t TCKS t TCKS t TCKWH t TCKWL CKIO TCLK (input) Figure 23.48 TCLK Clo ck Input Timing RTC crystal oscillator Stable oscillation V CC V CCmin t ROSC Figure 23.
Rev. 5.00, 09/0 3, page 708 of 760 t SCYC t TXD SCK TxD (data trans- missiion) RxD (data reception) t RXH t RXS t RTSD RTS CTS t CTSH t CTSS Figure 23.
Rev. 5.00, 09/03, pa ge 709 of 760 DRAK0/1 CKIO t DRAKD t DRAKD Figure 23.54 D RAK Output Timi ng 23.3.9 UDI-Rel ated Pin Timin g Table 23. 9 UDI-R elated Pin Ti ming VccQ = 3.3 ± 0.3V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3V, Ta = –20 to 75 ° C Item S y mbol Min M ax Unit Figure TCK cycle time t T CKCYC 50 — ns 23.
Rev. 5.00, 09/0 3, page 710 of 760 RESETP t TRSTS t TRSTH TRST Figure 23.56 T T T TR R R RS S S ST T T T Input Tim ing (Reset Hold) TCK TDI TMS t TDIS t TMSS t TDIH t TCKCYC t TMSH t TDOD TDO Figure 23.57 UDI Data Transfer Timing t ASEMD0S t ASEMD0H RESETP ASEMD0 Figure 23.
Rev. 5.00, 09/03, pa ge 711 of 760 23.3.10 AC Characteristics Measurement Co nditions • I/O sign al reference level: VccQ/ 2 (VccQ = 3.3 ± 0.3 V, V cc = 1.
Rev. 5.00, 09/0 3, page 712 of 760 23.3.11 Delay Time Variati on Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipul a t e d (3 0 or 50 p F) i s co nnecte d to this L SI 's pi ns is sho w n bel ow.
Rev. 5.00, 09/03, pa ge 713 of 760 23.4 A/D Converter Ch aracteristics Table 23.10 lists the A /D converter characteristics. Table 23.10 A/D Converter Characteristics VccQ = 3.
Rev. 5.00, 09/0 3, page 714 of 760.
Rev. 5.00, 09/03, pa ge 715 of 760 Appendix A Pin Functions A.1 Pin States Table A.1 show s pin states during resets, pow er-down states, an d the bus-released st ate.
Rev. 5.00, 09/0 3, page 716 of 760 Reset Power-Do wn Category Pin Power-On Reset Manual Reset Standby Sleep Bus Released Address bus A[25:0] Z O ZL * 9 OZ D[15:0] Z I Z IO Z D[23:16]/PTA [7:0] Z IP * .
Rev. 5.00, 09/03, pa ge 717 of 760 Reset Power-Do wn Category Pin Power-On Reset Manual Reset Standby Sleep Bus Released RxD0/SCPT[0] Z ZI * 6 ZI Z * 5 IZ * 5 TxD0/SCPT[0] Z ZO * 6 ZK * 2 OZ * 5 OZ * .
Rev. 5.00, 09/0 3, page 718 of 760 Reset Power-Do wn Category Pin Power-On Reset Manual Reset Standby Sleep Bus Released AN[5:0]/PTL[5:0] Z ZI * 6 ZI I Analog AN[6:7]/DA[1:0]/PTL[6:7 ] Z ZI * 6 OZ * 1.
Rev. 5.00, 09/03, pa ge 719 of 760 A.2 Pin Sp ecifications Table A.2 shows the pin specifications. Table A.2 Pin Specifications Pin Pin No. (FP-208C, FP-208E) Pin No.
Rev. 5.00, 09/0 3, page 720 of 760 Pin Pin No. (FP-208C, FP-208E) Pin No. (BP-240A) I/O Function A25 to A0 86, 84, 82 , 80, 78 to 72, 70, 68 to 60, 58, 56 to 53 V12, T12, V11, W 10, V10, U9, T9, V9, W.
Rev. 5.00, 09/03, pa ge 721 of 760 Pin Pin No. (FP-208C, FP-208E) Pin No. (BP-240A) I/O Function CS2 /PTK[0] 98 T16 I/O Chip select 2 / I/O p ort CS0 / MCS0 96 T15 O Chip select 0 / Mask ROM chip sele.
Rev. 5.00, 09/0 3, page 722 of 760 Pin Pin No. (FP-208C, FP-208E) Pin No. (BP-240A) I/O Function CKIO2/PT G [4] 129 L16 I/O System clock output / input port AUDATA[3]/ PTG[3] 130 L17 I AUD data / inpu.
Rev. 5.00, 09/03, pa ge 723 of 760 Pin Pin No. (FP-208C, FP-208E) Pin No. (BP-240A) I/O Function CKIO 162 A15 I/O System clo ck I/O XTAL2 4 D1 O Crystal oscilla tor pin (for on-chip RTC) EXTAL2 5 D3 I.
Rev. 5.00, 09/0 3, page 724 of 760 A.3 Treatment of Unu sed Pin s • When RT C is no t use d EXTAL2: Pull up (2.0/1.9/1.8/1.7 V) XTAL2: Leave un connected V CC –RTC: Pow er supply (2.0/1.9/1.8/ 1.7 V) V SS –RTC: Power su pply (0 V) • When PLL2 is not used CAP2: Leave unconnected V CC –PLL 2: Power supply (2.
Rev. 5.00, 09/03, pa ge 725 of 760 A.4 Pin States in Access to Each Add ress Space Table A.3 Pin States (Ordinary Memory/Little E ndian) 8-Bit Bus W idth 16-Bi t Bus Width Pin Byte/ Word/Long- word A .
Rev. 5.00, 09/0 3, page 726 of 760 32-Bit Bus Width Pin By te Ac c e s s (A ddres s 4n) By te A cces s (Address 4n + 1) By te A cces s (Address 4n + 2) By te Ac c e s s (A ddres s 4n + 3) Wor d Ac c e.
Rev. 5.00, 09/03, pa ge 727 of 760 Table A.4 Pin States (Ordinary Memory/Big Endian) 8-Bit Bus W idth 16-Bi t Bus Width Pin Byte/ Word/Long- word A ccess B yte A ccess (Address 2n) Byte A ccess (Addre.
Rev. 5.00, 09/0 3, page 728 of 760 32-Bit Bus Width Pin By te Ac c e s s (A ddres s 4n) By te A cces s (Address 4n + 1) By te A cces s (Address 4n + 2) By te Ac c e s s (A ddres s 4n + 3) Wor d Ac c e.
Rev. 5.00, 09/03, pa ge 729 of 760 Table A.5 Pin States ( Burst RO M/Little Endian) 8-Bit Bus W idth 16-Bi t Bus Width Pin Byte/ Word/Long- word A ccess B yte A ccess (Address 2n) Byte A ccess (Addres.
Rev. 5.00, 09/0 3, page 730 of 760 32-Bit Bus Width Pin By te Ac c e s s (A ddres s 4n) By te A cces s (Address 4n + 1) By te A cces s (Address 4n + 2) By te Ac c e s s (A ddres s 4n + 3) Wor d Ac c e.
Rev. 5.00, 09/03, pa ge 731 of 760 Table A.6 Pin States (Burst ROM/Big En dian) 8-Bit Bus W idth 16-Bi t Bus Width Pin Byte/ Word/Long- word A ccess B yte A ccess (Address 2n) Byte A ccess (Address 2n.
Rev. 5.00, 09/0 3, page 732 of 760 32-Bit Bus Width Pin By te Ac c e s s (A ddres s 4n) By te A cces s (Address 4n + 1) By te A cces s (Address 4n + 2) By te Ac c e s s (A ddres s 4n + 3) Wor d Ac c e.
Rev. 5.00, 09/03, pa ge 733 of 760 Table A.7 Pin States (Synchronous DRAM /Little Endian) 32-Bit Bus Width Pin By te A cces s (Address 4n) By te A cces s (Address 4n + 1) By te A cces s (Address 4n + .
Rev. 5.00, 09/0 3, page 734 of 760 Table A.8 Pin States (Synchronous DRAM/ Big En di an ) 32-Bit Bus Width Pin By te A cces s (Address 4n) By te Ac c e s s (Address 4n + 1) By te A cces s (Address 4n .
Rev. 5.00, 09/03, pa ge 735 of 760 Table A.9 Pin States (PCMCIA/Little Endian) PCMCI A Memor y Interface ( Area 5) P CMCIA/IO Interface (Area 5) 8-Bit Bus Widt h 16-Bi t Bus Width 8-Bi t Bus Widt h 16.
Rev. 5.00, 09/0 3, page 736 of 760 PCMCI A Memor y Interface ( Area 6) P CMCIA/IO Interface (Area 6) 8-Bit Bus Widt h 16-Bi t Bus Width 8-Bit Bus Widt h 16-Bi t Bus Width Pin By te/ Wor d/ Long- wor d.
Rev. 5.00, 09/03, pa ge 737 of 760 Table A.10 Pin States (PCMCIA/Big Endian) PCMCI A Memory Interface (A rea 5) PCMCIA I/O Interface (A rea 5) 8-Bit Bus Widt h 16-Bi t Bus Width 8-Bi t Bus Widt h 16-B.
Rev. 5.00, 09/0 3, page 738 of 760 PCMCI A Memor y Interface ( Area 6) P CMCIA/IO Interface (Area 6) 8-Bit Bus Widt h 16-Bi t Bus Width 8-Bit Bus Widt h 16-Bi t Bus Width Pin By te/ Wor d/ Long- wor d.
Rev. 5.00, 09/03, pa ge 739 of 760 Appendix B Memory-Mapped Control Registers B.1 Register Ad d ress Map Table B.1 M emory-Mapped Co ntrol Regist ers Control Register Module * 1 Bus * 2 Address * 4 Size (Bits) A ccess Size (Bits) 3.
Rev. 5.00, 09/0 3, page 740 of 760 Control Register Module * 1 Bus * 2 Address * 4 Size (Bits) A ccess Size (Bits) * 3 W TCSR CPG I FFFFFF86 8 16 BCR1 BSC I FFFFFF60 16 16 BCR2 BSC I FFFFFF62 16 16 W .
Rev. 5.00, 09/03, pa ge 741 of 760 Control Register Module * 1 Bus * 2 Address * 4 Size (Bits) A ccess Size (Bits) * 3 R W KAR RTC P FFFFFED6 8 8 RDAYAR RTC P FFFFFED8 8 8 RMONAR RTC P FFFFFEDA 8 8 RC.
Rev. 5.00, 09/0 3, page 742 of 760 Control Register Module * 1 Bus * 2 Address * 4 Size (Bits) A ccess Size (Bits) * 3 ICR1 INTC I 4000010 16 16 ICR2 INTC I 4000012 16 16 PINTER INTC I 4000014 16 16 I.
Rev. 5.00, 09/03, pa ge 743 of 760 Control Register Module * 1 Bus * 2 Address * 4 Size (Bits) A ccess Size (Bits) * 3 ADDRCL A/D P 400008A 8 8,16 * 5 ADDRDH A/D P 400008C 8 8,16,32 * 5 * 6 ADDRDL A/D.
Rev. 5.00, 09/0 3, page 744 of 760 Control Register Module * 1 Bus * 2 Address * 4 Size (Bits) A ccess Size (Bits) * 3 SCSMR1 IrDA P 4000140 8 8 SCBRR1 IrDA P 4000142 8 8 SCSCR1 IrDA P 4000144 8 8 SCF.
Rev. 5.00, 09/03, pa ge 745 of 760 B.2 Regi ster Bits Table B.2 Register Bits Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ———— SDMR BSC SCSMR C/A CHR PE O/E STOP M P CKS1 .
Rev. 5.00, 09/0 3, page 746 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ——————— U N F TCR1 — — UNIE CKEG1 CKEG 0 TPSC2 TPSC1 TPSC0 TMU TCOR2 TMU TCNT2 TMU.
Rev. 5.00, 09/03, pa ge 747 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RCR1 CF — — CI E AIE — — A F RT C RCR2 P EF PES2 PES1 PES0 RTCEN ADJ RESET ST ART RTC N M L .
Rev. 5.00, 09/0 3, page 748 of 760 Regist er Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ——— — — — — — RFCR BSC STC2 IF C2 PFC2 — — — SLPFRQ CKOEN FRQCR PLLEN PSTBY S.
Rev. 5.00, 09/03, pa ge 749 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BAMRA UBC ——————— — BBRA CDA1 CDA0 IDA1 IDA0 RWA1 RW A0 SZA 1 S ZA0 UBC ————.
Rev. 5.00, 09/0 3, page 750 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BASRA UBC BASRB UBC —————— — — —————— — — —————— — —.
Rev. 5.00, 09/03, pa ge 751 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IRR0 PINT0R P INT1R IRQ5R IRQ4R IRQ3R I RQ2R IRQ1R I RQ0R INTC IRR1 TXI1R BRI1R R XI1R ERI 1R DEI 3R.
Rev. 5.00, 09/0 3, page 752 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ——————— — ————— R L A M A L DM1 DM0 S M1 SM0 RS3 RS2 RS1 RS 0 CHCR0 —D S.
Rev. 5.00, 09/03, pa ge 753 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ——————— — ———— R O ——— DM1 DM0 S M1 SM0 RS3 RS2 RS1 RS 0 CHCR2 — —.
Rev. 5.00, 09/0 3, page 754 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A /DC ADDRBL AD1 AD0 — — — — — — A/DC ADDRCH A D9.
Rev. 5.00, 09/03, pa ge 755 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PG7M D1 PG7M D0 PG6M D1 PG6M D0 PG5M D1 PG5M D0 PG4M D1 PG4M D0 PGCR PG3M D1 PG3M D0 PG2M D1 PG2M D0.
Rev. 5.00, 09/0 3, page 756 of 760 Register BIT7 BI T6 BIT5 BIT4 BIT3 BIT2 BI T1 BIT0 Mod ule TI3 TI2 TI1 TI0 — — — — SDIR ——————— — UDI SCSMR1 IRM0D ICK3 ICK2 I CK1 ICK0 PSEL .
Rev. 5.00, 09/03, pa ge 757 of 760 Appendix C Product Lineup Table C .1 SH7709S Models Power Sup ply Voltage Ab b r . I/O Internal Operating Frequency Model Marking P ackage 2.0±0.15 V 200 MHz HD6417709SHF200B 208-pin plas tic HQFP (FP-208E) HD6417709SF167B 208-pin pla stic LQFP (FP-208C) 1.
Rev. 5.00, 09/0 3, page 758 of 760 Appendix D Package Dimensions Figures D.1 to D.3 s how th e SH7709S pack age dimensi ons. Package Code JEDEC JEITA Mass (reference value) FP-208C − Conforms 2.7 g * Dimension including the plating thickness Base material dimension 30.
Rev. 5.00, 09/03, pa ge 759 of 760 Package Code JEDEC JEITA Mass (reference value) FP-208E − Conforms 5.3 g * Dimension including the plating thickness Base material dimension 30.6 ± 0.2 30.6 ± 0.2 0.5 3.56 Max 0 ° − 8 ° * 0.17 ± 0.05 156 105 104 52 1 157 208 53 * 0.
Rev. 5.00, 09/0 3, page 760 of 760 0.65 0.65 13.00 13.00 0.15 4 × 0.2 C C 0.10 C 0.65 0.33 ± 0.05 1.40Max B A D C F E H G K J M L P N T R V U W 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0.20 C A 0.20 C B B C φ 0.08 AB 240 × φ 0.40 ± 0.05 M 0.
SH7709S Group Hardware Manual Publicat ion Da te: 1st Editi on, Septem ber 2001 Rev.5.00 , Septem ber 18, 2003 Publish ed by: Sales Stra tegic P lanni ng D iv . Renesas T echno logy Cor p. Edited by: T ec hnical Docum entat ion & Inf orm ation Dep artm ent Renesas Kod aira Sem iconduct or Co.
Colophon 1.0 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited.
SH7709S Grou p Hardware M anual REJ09B0081-0500O (ADE-602-250C).
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