Benutzeranleitung / Produktwartung R61509V des Produzenten Renesas
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Rev. 0.11 April 25, 2008, page 1 o f 181 Target Spec R61509V 260k-color, 240RGB x 432-dot graphics liquid crystal controller driver for Amor phous-Silicon TFT Panel REJxx xxxxx- xxxx Rev.0.11 April 25, 2008 Description ........... .......... .........
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 2 o f 181 Outline ..................................... ...................................................... ............................. .............. .................................... 40 Instruction Data Format .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 3 o f 181 NVM Control ................................................ ...................................................... .............. ............................................ 90 NVM Access Cont rol 1 (R6F0h), NVM Acce ss Control 2 (R6F1h ), NVM Access Co ntrol 3 (R6F2h) .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 4 o f 181 Partial Display Function ....... ............. ........... ............. ............. ........... ............. .... 139 Liquid Crystal Pa nel Interf ace Timing ........... .............. .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 5 o f 181 Clock Charact eristics ........................................ ....................................................... ........... ................................... 172 80-system 18-/1 6-/9-/8-bit Bus interface Timing Characteristic s .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 6 o f 181 Description The R61509V is a single-chip liquid crystal controll er driver LSI for a-Si TFT panel, incorporating RAM for a maximum 240 RGB x 432 dot graphics display, gate driver, source driver and power supply circuits.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 7 o f 181 Feature s • A single-chip controller driver incorporating a gate circuit and a power supply circuit for a m aximum 240RGB x 432dots grap.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 8 o f 181 Power Supply Specifications Table 1 No. Item R61509V 1 TFT data lines 720 output 2 TFT gate lines 432 output 3 TFT display storage capacit.
Difference Between R61509 and R61509V 2008.04.18 Index Command Code Function R61509 R61509V (Pin) System Interface IM2-0=011, TRI=1, DFM=0 8bit 3 transfer (2bit-8bit-8bit) Supported Deleted R000h Device Code Read 1509H B509H R002h LCD Drive Waveform Control NW[1-0] --> NW bit is deleted.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 10 of 181 Block Diagram 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 VCC VDD 㩷 㩷 㩷 㩷 C13P.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 11 of 181 Block Function 1. System Interface The R61509V supports 80-system high-speed interface v ia 8-, 9-, 16-, 18-bit parallel ports and a clo ck synchronous serial interface. The interface is selected by setting the IM2-0 pins.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 12 of 181 Table 4 IM2 IM1 IM0 System interface DB pins RAM write data Instruction write transfer 0 0 0 80-system 1 8-bit interface DB17-0 Single tra.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 13 of 181 4. Graphics RAM (GRAM) GRAM sta nds fo r grap hics RAM, which ca n stor e bit- patte rn data of 233, 280 (240 RGB x 43 2 (dots ) x 18(bits)) bytes at maximum, using 18 bits per pix el.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 14 of 181 Pin Function Table 5 External Power Supply Signal I/O Conne ct to Function When no t used VCC I Power supply Power supp ly for Interna l VDD regulator . VCC ≧ IOVCC ― IOVCC I Power supply Power supply for int erface pins.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 15 of 181 DB[17:0] I/O Host processor 18-bit parallel bi-dir ectional data bus for 80-system interface operation (Amplitude: IOVCC-GND). 8-bit I/F: DB17-DB10 are used. 9-bit I/F: DB17-DB9 are used. 16-bit I/F: DB17-DB10 and DB8-1 are used.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 16 of 181 PROTECT I Host processor Reset protect pin. The R61509V enters a reset protect status by fixing PROTECT to GND level disabling hardware reset. With this, erroneous operations caused by nois e are prevented.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 17 of 181 Table 8 LCD drive Signal I/O Connect to Function When not in use VREG1OUT O Stabilizing capacitor Output voltage generated from the refere nce voltage VCIR. The factor is determined by instruction (VRH bits).
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 18 of 181 Table 9 Others (test, dummy pins) Signal I/O Connect to Function When not in use VTEST O Open Test pin. Leave open. Open VREFC I GND Test pin. Make su re to fix to the GND level . - VREFD O Open Test pin.
R61509V Pad Arrangement Rev 0.6 (1-a) No No □ DUMMYR4 1434 □ DUMMYR3 1433 □ TESTO15 1432 1 DUMMYR1 □ □ VGLDMY4 1431 2 DUMMYR2 □ □ G1 1430 3 AGNDDUM1 □ □ G3 1429 4 VPP3B □ □ G5 14.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 20 of 181 ● Chip size: 19.03mm x 0 .76mm ● Chip thickness: 280 μ m (ty p) ● Pad coordinates: Pad center ● Coordinate origin: Chip center ● Au bump size 1. 50 μ m x 90 μ m (I/O side: No.1-262) 2.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 1 DUMMYR1 -9135.0 -269.0 51 TS5 -5635.0 -269.0 2 DUMMYR2 -9065.0 -269.0 52 TS4 -5565.0 -269.0 3 AGNDDUM1 -8995.0 -269.0 53 TS3 -5495.0 -269.0 4 VPP3B -8925.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 101 GNDDUM8 -2135.0 -269.0 151 GND 1365.0 -269.0 102 DB3 -2065.0 -269.0 152 GND 1435.0 -269.0 103 DB2 -1995.0 -269.0 153 GND 1505.0 -269.0 104 DB1 -1925.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 201 VCI 4865.0 -269.0 251 C21M 8365.0 -269.0 202 VCI 4935.0 -269.0 252 C21M 8435.0 -269.0 203 VCI 5005.0 -269.0 253 C21P 8505.0 -269.0 204 VCI 5075.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 301 G70 8827.5 157.0 351 G170 8077.5 157.0 302 G72 8812.5 276.0 352 G172 8062.5 276.0 303 G74 8797.5 157.0 353 G174 8047.5 157.0 304 G76 8782.5 276.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 401 G270 7327.5 157.0 451 G370 6577.5 157.0 402 G272 7312.5 276.0 452 G372 6562.5 276.0 403 G274 7297.5 157.0 453 G374 6547.5 157.0 404 G276 7282.5 276.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 501 S704 5632.5 276.0 551 S654 4882.5 276.0 502 S703 5617.5 157.0 552 S653 4867.5 157.0 503 S702 5602.5 276.0 553 S652 4852.5 276.0 504 S701 5587.5 157.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 601 S604 4132.5 276.0 651 S554 3382.5 276.0 602 S603 4117.5 157.0 652 S553 3367.5 157.0 603 S602 4102.5 276.0 653 S552 3352.5 276.0 604 S601 4087.5 157.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 701 S504 2632.5 276.0 751 S454 1882.5 276.0 702 S503 2617.5 157.0 752 S453 1867.5 157.0 703 S502 2602.5 276.0 753 S452 1852.5 276.0 704 S501 2587.5 157.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 801 S404 1132.5 276.0 851 TESTO12 -457.5 276.0 802 S403 1117.5 157.0 852 TESTO13 -472.5 157.0 803 S402 1102.5 276.0 853 S360 -487.5 276.0 804 S401 1087.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 901 S312 -1207.5 276.0 951 S262 -1957.5 276.0 902 S311 -1222.5 157.0 952 S261 -1972.5 157.0 903 S310 -1237.5 276.0 953 S260 -1987.5 276.0 904 S309 -1252.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 1001 S212 -2707.5 276.0 1051 S162 -3457.5 276.0 1002 S211 -2722.5 157.0 1052 S161 -3472.5 157.0 1003 S210 -2737.5 276.0 1053 S160 -3487.5 276.0 1004 S209 -2752.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 1101 S112 -4207.5 276.0 1151 S62 -4957.5 276.0 1102 S111 -4222.5 157.0 1152 S61 -4972.5 157.0 1103 S110 -4237.5 276.0 1153 S60 -4987.5 276.0 1104 S109 -4252.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 1201 S12 -5707.5 276.0 1251 G359 -6652.5 157.0 1202 S11 -5722.5 157.0 1252 G357 -6667.5 276.0 1203 S10 -5737.5 276.0 1253 G355 -6682.5 157.0 1204 S9 -5752.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y pad No pad name X Y 1301 G259 -7402.5 157.0 1351 G159 -8152.5 157.0 1302 G257 -7417.5 276.0 1352 G157 -8167.5 276.0 1303 G255 -7432.5 157.0 1353 G155 -8182.5 157.0 1304 G253 -7447.
R61509V Pad Coordinate （ Unit ： μ m ） 2008.04.21 rev0.1 pad No pad name X Y X Y 1401 G59 -8902.5 157.0 -9381.0 -251.0 1402 G57 -8917.5 276.0 9381.0 -251.0 1403 G55 -8932.5 157.0 1404 G53 -8947.5 276.0 1405 G51 -8962.5 157.0 1406 G49 -8977.5 276.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 36 of 181 Bump Arrangement 㪪 㪪 㪈䌾㪪㪎㪉㪇䋬 㩷 㪞㪈䌾㪞㪋㪊㪉䋬 㩷 㪛㪬㪤㪤㪰㪩㪎㪄㪈㪇㪃㩷 㪫㪜㪪㪫㪦㪈㪈.
R61509V Wiring Example & Recommended Wiring Resistance (Pad Arrangement Rev0.6) 2008.04.21 Rev0. 5 VCOM R61509V Pad name □ DUMMYR4 1 DUMMYR1 □ DUMMYR3 2 DUMMYR2 □ TESTO15 3 AGNDDUM1 □ VG.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 38 of 181 GRAM Address Map Table 1 1 GRA M addre ss and di splay positi on on th e pa nel (SS = 0, BGR = 0) S/G pin S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 39 of 181 Table 1 2 GRA M addre ss and di splay positi on on th e pa nel (SS = 1, BGR = 1) S/G pin S720 S719 S718 S717 S716 S715 S714 S713 S712 S711.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 40 of 181 Instruction Outline The R61509V adopts 18-bit bus architecture in order to in terface to high-performance microcomputer in high speed.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 41 of 181 Index (IR) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 0 0 0 0 0 0 ID [10] ID [9] ID [8] ID [7] ID [6] ID [5] ID [4] ID [3] ID [2] ID [1] ID [0] The index register specifies the index es of control register or RAM control to be accessed.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 42 of 181 LCD Drive Wave Control (R002h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R/W 1 0 0 0 0 0 0 0 BC 0 0 0 0 0 0 0 0 Defaul t value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BC: Selects the liquid crystal drive waveform VCOM.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 43 of 181 BGR: Reverses the order from RGB to BGR in writing 18-bit pixel data in the GRAM. BGR = 0: Write data in the order of RGB to the GRAM. BGR = 1: Reverse the order from RGB to BGR in writing data to the GRAM.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 44 of 181 ORG = 0 AM = 0 Horizontal AM = 1 V ertical ID1-0 = 00 Horizontal: Decrement V ertical: Decrement ID1-0 = 01 Horizontal: Increment V ertica.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 45 of 181 Display Control 1 (R007h) BASEE: Base image display enable bit. BASEE = 0: No base image is displayed. The R61509V drives the LCD at non-lit d isplay level or displays partial images. BASEE = 1: A base im age is displayed.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 46 of 181 Display Control 2 (R008h) FP[7:0]: Sets the number of lines for f ront porch period (a blank period made af ter the end of display). BP[7 :0]: Sets the numb er of lines for back porch period (a blank period made before the beginning of disp lay).
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 47 of 181 VSYNCX NL BP FP Back porch Front porch Display Area Note: The output timing to the panel is delayed by 2 line period from the synchronous signal (VSYNCX) input.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 48 of 181 Display Control 3 (R009h) PTS: Sets the source output level to drive non-display area. PTS also sele cts operation of grayscale amplifier and step-up clock frequency.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 49 of 181 8 Color Control (R00Bh) R/W RS IB15 IB14 IB13 IB12 IB11 IB1 0 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W/R 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COL Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COL: When COL = 1, the R61509V enters the eig ht-color display mode.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 50 of 181 External Display Interface Control 1 (R00Ch) RIM: Sets the interface form at when RGB interface is selected by RM and DM bits. Set R IM bit before starting display operation via the ex ternal display interface.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 51 of 181 ENC[2:0]: Sets the RAM write cycle via RGB i nterface. Table 21 ENC[2:0] RAM Write Cycle (frame periods) 3’h0 1 frame 3’h1 2 frames 3.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 52 of 181 External Display Interface Control 2 (R00Fh) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R/W 1 0 0 0 0 0 0 0 0 0 0 0 VSPL HSPL 0 EPL DPL Default v alue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPL: Sets th e si gnal polari ty of DOTCL K pin .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 53 of 181 Panel Interface Control 1 (R010h) RTNI[4:0]: Sets 1H (line) period. This setting is val id when the R61509V’s display operation i s synchronized with internal clock sig nal.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 54 of 181 Frame Frequency Calculation fosc Frame frequency = Clocks per line x division ratio x (line + BP + FP) [H z] fosc : RC oscillation frequen.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 55 of 181 Panel Interface Control 2 (R011h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R/W 1 0 0 0 0 0 NOW I[2] NO.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 56 of 181 Panel Interface Control 3 (R012h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R/W 1 0 0 0 0 0 VEQ WI[2] VEQ WI[1] VEQ WI[0 ] 0 0 0 0 0 SEQ WI[2 ] SEQ WI[1 ] SEQ WI[0] Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VEQWI[2:0]: Sets VCOM equalize period.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 57 of 181 SEQWI[2:0]: Sets source equalize period. SEQWI setting is enabled only when the R615 09V executes display operation in synchronization with internal clock.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 58 of 181 Panel Interface Control 4 (R013h) MCPI : Defines VCOM alternating timing. This bit i s enabled when displaying in synchronization with internal clock. MCP cannot be used in RGB interface operation.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 59 of 181 Panel Interface Control 5 (R014h) PCDIVH[2:0], PCDIVL[2:0] : When DM=1 and RGB I/F is selected, d isplay operation is executed using DOTCLKD. PCDIVH and PCDIVL define divi sion ratio of DOTCLK to generate DO TCLKD.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 60 of 181 Panel Interface Control 6 (R020h) DIVE[1:0]: Sets the division ratio of DOTCLK. The R615 09V’s internal operation is synchronized with the frequency-divided DOTCLK, the f requency of which is divided by the division ratio set by DIVE[1:0].
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 61 of 181 RTN E[5:0 ]: Sets RTNE in combination with PCDIVH and PCDIVL to decide the num ber of DOTCLK in 1H (1 line) period according to th e following formula. RTNE is enabled when RGB interface is selected.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 62 of 181 Panel Interface Control 7 (R021h) NOWE[2:0]: Sets the non-overlap period of adjacent gate outputs.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 63 of 181 Panel Interface Control 8 (R022h) VEQWE[2:0]: Sets low power VCOM drive period. The setting is enabled when RGB interface is selected.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 64 of 181 SEQWE [2:0 ]: Sets source e qualize period. SEQWE setting is enabl ed when the R61509V execu tes display operation via RGB interface.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 65 of 181 Panel Interface Control 9 (R023h) MCP E [2:0] : Specifies VCOM alt ernating point. MCPE is enabled when RGB interface is selected.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 66 of 181 Frame Marker Control (R090h) FMI[2:0]: Sets FMARK output interval by FMI register se tting according to the up date period of display data and transfer rate. Set FMKM = 1 if FMARK signal is output from FMARK pin.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 67 of 181 Power Control Power Control 1 (R100h) DSTB: When DSTB = 1, the R615 09V enters the shut down mode. In shu t down mode, the internal logic power supply is turned off to reduce pow er consumption.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 68 of 181 BT[2: 0]: Sets the f actor used in the step-up circuits. Sel ect the optimal step-up factor for the operating voltage.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 69 of 181 Power Control 2 (R101h) DC1 [2:0] : Sets step-up clock frequency for Step-up Circuit 2. The step-up clock is in synchronizat ion with internal clock.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 70 of 181 DC0 [2:0] : Sets step-up clock frequency for Step-up Circuit 1. The step-up clock is in synchronizat ion with internal clock. Table 43 Step-up Frequency (Step-up Circuit 2) Note 1: Make sure that fDC DC1 ≥ fDCDC2.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 71 of 181 VC[2:0] : Sets VCI voltage level. VC[2:0] VCI1 voltage (Reference voltage for step-up operation) 3’h0 Setting inhibited 3’h1 0.94 x VCILVL 3’h2 0.89 x VCILVL 3’h3 Setting inhibited 3’h4 Setting inhibited 3’h5 0.
■DC0ｘ Value and DCD C1 Step -up Clock S igna l W avef or m Exa mp le DCDC1 performs charge operation and boost operation with the step-up clock generated from the timing generator. The DCDC1 step-up clock frequency is adjusted by setting the division ratio of the reference clock frequency with DC0x registe r.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 73 of 181 Power Control3 (R102h) Note: True values of PSON and PON are not read when instruction read is executed. PON, PSON : Turn power supply ON. PON and PSON must be written to power supply ON and start the internal power supply operation.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 74 of 181 Power Control 4 (R103h) VDV[4:0]: Selects the factor of VREG1OUT to set the amplitud e of VCOM alternating vol tage from 0.70 to 1.32. Table 46 VDV[4:0] VCOM amplitude VDV[4:0] VCOM amplitude 5’h0 VREG1OUT x 0.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 75 of 181 RAM Access RAM Address Set (Horizontal Address) (R200h) RAM Address Set (Vertical A ddress) (R201h) AD[16:0]: Sets a GRAM address in the A.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 76 of 181 GRAM Data Write (R202h) R / W R S W 1 RAM write data WD[17:0] is tran sferred via differe nt data b us in different interface operation. RGB interface RAM write data WD[17:0] is transferred via di ffere nt data bus in different interface operatio n.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 77 of 181 GRAM Data Read (R202h) R / W R S R 1 RAM read data RD[17:0] is transferred via differ ent data bus in different interface operation. RD[17:0]: 18-bit data read from the GRAM. RAM read data RD [17:0] is transferred via different data bus in different interface operation.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 78 of 181 NVM Data Read / NVM Data Write (R280 h) UID[3:0] : Used to temporarily store NVM data such as used identification code. The write data is loaded t o NVM data write register (NVDAT [7:0]) and th en is written to NVM.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 79 of 181 Table 48 VCM [6:0] VCOMH voltage VCM [6 :0] VCOMH voltage 7’h00 VREG1OUT x 0.4 92 7’h40 VREG1OUT x 0.748 7’h01 VREG1OUT x 0.4 96 7’h41 VREG1OUT x 0.752 7’h02 VREG1OUT x 0.5 00 7’h42 VREG1OUT x 0.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 80 of 181 7’h38 VREG1OUT x 0.716 7’h78 VREG1OUT x 0.972 7’h39 VREG1OUT x 0.720 7’h79 VREG1OUT x 0.976 7’h3A VREG1OUT x 0.724 7’h7A VREG1O UT x 0.980 7’h3B VREG1OUT x 0.728 7’h7B VREG1O UT x 0.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 81 of 181 Window Address Control Window Horizontal RAM Address Start (R210h), Window Horizontal RAM Addr ess End (R211h) Window Vertical RAM Address.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 82 of 181 γ Control γ Control 1 ~ 14 (R30 0h to R309h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB 6 IB5 IB4 IB3 IB 2 IB1 IB0 R 300 W 1 0 .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 83 of 181 PR0P00[4:0] PR0N00[4:0 ] Adjusts refere nce level fo r positive po larity outp ut R0 Adjusts refere nce level fo r negative pol arity outp.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 84 of 181 Base Image Display Control Base Image Number of Li ne (R400h) Base Image Display Control (R401h) Base Image Vertical Scroll Control (R404h) GS: Sets the direction of scan by the gate driver in the range d etermined by SCN and NL bit s.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 85 of 181 Table 50 VLE Base image 0 Fixed 1 Scrolling enabled REV: Grayscale level of a image is inv erted when REV = 1. This enables the R61509V to display the same image from th e same set of data both on norm ally black and white panels.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 86 of 181 Table 53 NL [5:0] Number of drive li ne NL [5:0] Number of drive li ne 6’h00 Setting inhibited 6’h1C 232 lines 6’h01 16 lines 6’ h.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 87 of 181 Table 54 Gate scan start position SM=0 SM=1 SCN[5:0] GS=0 GS=1 GS=0 GS=1 6’h00 G1 G(N ) G 1 G(2N-432) 6’h01 G9 G(N+8) G17 G(2N-416) 6.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 88 of 181 Partial Display Control Partial Image 1: Display Position (R50 0h), RAM Address 1 (Start Line Address) (R501h), RAM Address 1 (End Line Address) (R502h) PTDP[8:0]: Sets the display position of partial im age 1.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 89 of 181 Pin Control Test Register (Software Reset) (R600h) TRSR: When TRSR = 1, test registers are initialized. When TRSR = 0, in itialization of test registers halts. Instruction Write R600h TRSR="1" R600h TRSR="0" 㩷 Instruction Write T est registers are initialized (0.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 90 of 181 NVM Control NVM Access Control 1 (R6F0h), NVM A ccess Control 2 (R6F1h), NVM Access Control 3 (R6F2h) EOP [1 :0]: Writes data on R280h to NVM or halts the write operation .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 91 of 181 R6F1h Write data to NVM (NVM) Read data from NVM R280h Write “1” to NVDAT[15]. 㪥㪭㩷 㪛㪘㪫㩷 㪲㪈㪌㪴 㩷 㪥㪭㩷 㪛.
●R61509V Instruction List Rev 0.50 2008. 04. 22 Middle category Upper Index Index Command IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 - Index － Index 00000 ID10 ID9 ID8.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 93 of 181 Reset Function The R61509V is initialized by the RESETX input. Durin g reset period, the R61509V is in a busy state and instruction from the microcomputer and GRAM access are no t accepted.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 94 of 181 5 When a RESETX inpu t is entered into the R61509V while it is in shutdown mode, the R61509V starts up the inside logic regulator and makes a transit ion to the initial state. During this period, the state of the interface pins may become unstable.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 95 of 181 Basic Mode O peration of the R615 09V The basic operation modes of the R61509V are show n in the following diagram. Wh en making a transition from one mode to another, refer to instruction setting sequence.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 96 of 181 Interface and Data Format The R61509V supports system interface for making instruction and ot her settings, and external display interface for displaying a moving p icture.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 97 of 181 CSX RS WRX R61509V System interface 18/16/9/8 RGB interface 18/16 DB17-0 (RDX) ENABLE VSYNCX HSYNCX DOTCLK System interface RGB interface .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 98 of 181 RGB interface operation (2) This mode enables the R61509V to rewrite RA M data via system interface while using RGB interface for display operation. To rewrite RAM d ata via system interface, make sure that display data is not transferred via RGB interface (ENABLE = high).
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 99 of 181 System Inte rface The following are the kinds of system interfaces available w ith the R61509V. The interf ace operation is selected by setting the IM2/1/0 pins. The sy stem interface is used for instruction setting and RAM access.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 100 of 181 80-S ystem 1 8- bit Bu s In terf ace A1 HWR RS WRX 18 R61509V HOST PROCESSOR IM[2:0] = 000 CSn (RDX) (RDX) D31-0 CSX DB17-0 Figure 14.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 101 of 181 80-S ystem 1 6- bit Bu s In terf ace A1 HWR RS WR : 16 R61509V HOST PROCESSOR IM[2:0] = 010 CSn (RD : )( R D : ) D15-0 CS : DB17-10, .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 102 of 181 1 DB 17 DB 6 DB 5 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 RAM data write (1-transfer mode: TRI = 0) 1 7 Note: 65,536 colors are available.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 103 of 181 Data Transfer Synchronization i n 16-bit Bus Interface O peration The R61509V supports data transfer synchronization function to reset the counters for upper 16-/2-bit and lower 2-/16-bit transfers in 16-bit 2-transf er mode.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 104 of 181 80-System 9-bit Bus Interface When transferring 16-bit instruction, it is divided into upper and lo wer 8 bits, and the upper 8 bits are transferred first (the LSB is not used). The RAM write data is also divided int o upper and lower 9 bits, and the upper 9 bits are transf erred first.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 105 of 181 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 6 DB 5 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 106 of 181 80-System 8-bit Bus Interface When transferring 16-bit instruction, it is divided into upper and lo wer 8 bits, and the upper 8 bits are transferred first. The RAM write data is also div ided into upper and lower 8 bits, and th e upper 8 bits are transferred first.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 107 of 181 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 RAM data write (2-transfer mode: TRI = 0) Input First transfer Second transfer Note: Normal display in 65,536 colors.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 108 of 181 Data Transfer Synchronization in 8 -bit Bus Interface operation The R61509V supports data transfer synchronization function to reset the counters for upper and lower 8- bit transfers in 8-bit bus transfer m ode.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 109 of 181 Serial Interface The serial interface is selected by setting the IM2/1 pins to the IOVCC/GND lev els, respectively. The data is transferred via chip select line (CS), serial transf er clock line (SCL), serial data input line (SD I), and serial data output line (SDO).
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 110 of 181 Fi rst t ransfer (upper) S ec on d t ransfer (lower) D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IB 15 IB 14 IB 13 IB 12 .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 111 of 181 D0 LSB 1 “0” “1” “1” “1” “0” ID RS RW D15 D1 4 D13 D1 2 D11 D1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 2 3 4 5 6 7 8 9 1 01 1 1 .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 112 of 181 VSYNC Interface The R61509V supports VSYNC interface, wh ich enables displaying a moving picture via system interface by synchronizing the display operation with the VSYNCX signal.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 113 of 181 The VSYNC interface has the m inimum for RAM data write speed and internal clo ck frequency, which must be more than the values calcu lated from the following formulas, resp ectively.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 114 of 181 RAM write Display operation 0 16.67 (60 Hz) Back porch (14 lines) Main panel Moving picture display (432 lines) Front porch (2 lines) Blank period RC oscillation ±7% Display operation VSYNCX [line] 432 VSYNCX BP = 14H RAM write 7.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 115 of 181 3. The front porch perio d continues from the end of one f rame period to the next VSYNCX input. 4. The instructions to swit ch from internal clock operation (DM1-0 = 00) to VSYNC interface operatio n modes and vice versa are enabled f rom the next frame period.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 116 of 181 FMARK Interface In the FMARK interface o peration, data is written to internal RAM via system interface synchronizing with the frame mark signal (FM ARK), realizing tearing less video imag e while using conventional system interface.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 117 of 181 When transferring data in synchronization wit h FMARK signal, minimum RAM data write speed and internal clock frequency must be taken i nto consideration. They must be more than the values cal culated from the fo llowing equations.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 118 of 181 starts the display operation of the data writt en in that line and can write moving pic ture data without causing flicker on the display.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 119 of 181 Table 60 Table 61 FMP[ 8:0] F MARK output position 9’h000 0 9’h001 1 st line 9’h002 2 nd line : 9’h1BD 445 th line 9’h1BE 446 t.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 120 of 181 FMP Setting Example NL=6'h35 Front porch Display area FMP=9’h008 NL=6’h35 (432 lines) FP=4’h8 BP=4’h8 VL=8’h00 Line addres.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 121 of 181 RGB Interface The R61509V supports the RGB interface. The in terface format is set by RM[1:0] bits.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 122 of 181 Polarities of VSYNCX, HSYNCX, ENABLE, and DOTCLK Signals The polarities of VSYNCX, HSYNCX , ENABLE, and DOTCLK signals can be changed by settin g the DPL, EPL, HSPL, and VSPL bits, respectively for convenience of system configuration.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 123 of 181 Setting Example of Display Control Clock in RGB Interface Operat ion Register The display operation via DPI is performed in synchronization wi th the internal clock (PCLKD) that is generated by dividing PCLK frequency.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 124 of 181 RGB Interface Timing The timing relationship of signals in RGB interface operation is as follows.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 125 of 181 Moving Picture Display via RGB Interface The R61509V supports RGB interface for moving picture display and i ncorporates RAM for storing display data, which provides the fol lowing advantages in displaying a moving picture.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 126 of 181 16-Bit RGB Interface The 16-bit RGB interface is selected b y setting RIM = 1. The display operation is synchronized with VSYNCX, HSYNCX, and DO TCLK signals.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 127 of 181 18-bit RGB Interface The 18-bit RGB interface is selected b y setting RIM = 0. The display operation is synchronized with VSYNCX, HSYNCX, and DO TCLK signals.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 128 of 181 Notes to RGB Interface Operation 1. The following functions are not available in RGB interface operation.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 129 of 181 RAM Address and Display Position on the Panel The R61509V has memory to store display data of 240RGB x 432 lines. The R6 1509V incorporates a circuit to control partial display, which allows switch ing driving method between full-screen display mod e and partial display mode.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 130 of 181 (VSA,VEA) 9’h000 9’h1AF NL (HSA,HEA) Window Address PTDP 1 PTSA0 PTEA0 䇼 LCD 䇽 Panel display position Display data output positio.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 131 of 181 The following figure shows the relationship among the RAM address, displ ay position, and the lines driven for the display.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 132 of 181 Instruction Setting Example The followings are examples of settings for 24 0(RGB) x 432(lines) panel. 1. Full screen display (no partial display) The following is an example of settin gs for full screen display.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 133 of 181 2. Partial only The following is an example of settings fo r displaying partial image 1 only and turning off th e base image. The partial image 1 is displayed at t he position specified by PTDP0 bit.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 134 of 181 Window Address Function The window address function enables writing disp lay data consecutively in a rectangular area (a window address area) made in the internal RAM.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 135 of 181 Scan Mode Setting The R61509V can set the gate pin assignm ent and the scan direction in the f ollowing 4 different ways by setting SM and GS bits to realize various connections between the R61509V and the LCD panel.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 136 of 181 8-Color Display Mode The R61509V has a function to display in eight co lors. In this display mode, only V0 and V63 are used and power supplies to other grayscales (V1 to V62) are turned off to reduce pow er consumption.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 137 of 181 Frame-Frequency Adjustment Function The R61509V supports a function to adjust f rame frequency. The frame frequency for driving liquid crystal can be adjusted by setting the DIVI, RTNI bits w ithout changing the oscillation frequency.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 138 of 181 Under the above conditions, the f rame frequency can be changed according to the table show n below.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 139 of 181 Partial Display Function The partial display function allows the R61 509V to drive lines selectively to display partial im ages by setting partial display control registers.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 140 of 181 Liquid Crystal Panel Interface Timing The relationships between RGB interface signals and liquid crystal panel control signals in internal operation and RGB interface operations are as f ollows.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 141 of 181 RGB Interface Operation 1 2 3 4 5 6 432 431 430 1 2 3 BP 1H 5DOTCLK FP One frame VSYNCX HSYNCX DOTCL K S ( 3n+1 ) ENABLE DB FMAR K G1 G2 .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 142 of 181 γ Correctio n Function γ Correction Function The R61509V supports γ -correction function to make t he optimal colors according to the characteristics of the panel. The R61509V h as registers for positive and negative polarities.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 143 of 181 γ Correction Registers The γ -correction registers include 42 bits for each of R, G, and B dots and 8-bit interpolation adjustm ent registers.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 144 of 181 Table 71 Reference Level Adjustment Registers and Resistors Register Register Resistor Name Valu e Resistance Resistor Name Valie Resista.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 145 of 181 Interpolation Registers Table 72 Interpolation Registers Gamma Control Interpolation adjustment Positive polarity Negati ve polarity PI0P.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 146 of 181 Table 74 Interpolation Factor for V56 to V61 PI0*3[1:0] PI0*2[1: 0] IPV56 IPV57 IPV58 IPV59 IPV60 IPV61 2'h0 87% 74% 61 % 48% 33 % 1.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 147 of 181 Table 75 Grayscale Voltage Calculation Formula Grayscale voltage Formula Grayscale voltage Formula V0 ΔV ｘ Σ（R1～R8)/SUMR V32 V43 .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 148 of 181 Frame Memory Data and the Grayscale Vo ltage Table 76 Grayscale Voltage G rayscale Voltage REV = 1 REV = 0 REV = 1 REV = 0 Frame memory d.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 149 of 181 Power Supply Generating Circui t The following figures show the configurations of liquid crystal driv e voltage generating circuit of the R61509V. Power Supply Circuit Connection Ex ample 1 (VCI1 = VCIOU T) In the following example, the VC I1 level can be adjusted.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 150 of 181 Power Supply Circuit Connection Example 2 (VCI1 = V CI Direct Input) In the following example, the electrical p otential VCI is directly applied to VCI1. In this case, the VCIOUT level cannot be adjusted int ernally but step-up operation becomes more effective.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 151 of 181 Specifications of Power-supply Circuit External Elements The specifications of external elements connected to the power-supply circuit of the R61509V are as follows.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 152 of 181 Voltage Setting Pat tern Diagram The following are the diagram s of voltage generation in the R61509V and the TFT display application voltage waveforms and electrical potential relati onship.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 153 of 181 Liquid Crystal Application Voltage Wav eform and Electrical Potential VCOM Gn (panel interface output) Sn (source driver output) VG H VRE.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 154 of 181 VCOMH and VREG1OU T Voltage Adjust ment Sequence When adjusting the VCOMH voltage by setting VCM[6:0] (R28 0h, internal VCOMH level adjustment circuit), follow the sequence below . The R61509V can retain permanently the VREG1OUT and VCOMH level adjustment setting v alues in NVM.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 155 of 181 NVM Control The R61509V incorporates 16-bit NVM for user’s use. • 7 bits are for VCOM adjustm ent (VCM register value is stored). • 8 bits are for UID. • 1 bit is for a dummy bit. To write, read and erase data f rom/to the NVM, follow the sequence s below.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 156 of 181 NVM Load (Register Resetting) Sequence Data on the NVM is loaded either automatically or by setting a comm and. During the following sequence, the data written to the NVM is autom atically loaded to the internal register.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 157 of 181 NVM Write Sequence Defined 16 bit data is written to the selected address. When “0” is w ritten to these bits, the bits are set to “0”. If the data is erased from the bit, the bit is returned to ”1”.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 158 of 181 NVM Erase Sequence The data written to the selected 16 b its is erased all together. The bit s from which data is erased are set to “1”. To erase data from NV M, make sure VGL < VPP3A, and follow the sequence below after power supply ON sequence.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 159 of 181 Power Supply Setting Sequence The following are the sequences for setting power supp ly ON/OFF instructions. Set power supply ON/OFF instructions according to the foll owing sequences in Display ON/OFF, Sleep set/ex it sequences.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 160 of 181 ޣᶧ᥏㔚Ḯ ࠝࡈࡈࡠ ޤ R102h: PON=0 PSON=0 㪞 㪥㪛 Power Supply OFF Sequence 5 frames or more (A) Liquid crystal p.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 161 of 181 Notes to Power Supply ON Sequence When voltages do not rise in the order of VCC, IOVCC and then V CI and have to change the order, please follow the following note. Note Internal operation of the R61509V is unstable until VCC rises.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 162 of 181 Instruction Setting Sequence and Refresh Sequence Display ON/OFF Sequences and Refresh Sequence In setting instruction in the R61509V, follow the sequences below. To reduce malfunction caused b y noise, execute refresh sequence 1 regularly.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 163 of 181 Shutdown Mode Sequences CSX=”Low” ( 1 ) CSX=”Low” ( 2 ) CSX=”Low” ( 3 ) CSX=”Low” ( 4 ) CSX=”Low” ( 5 ) CSX=”Low” ( 6 ) 㩷 㩷 㩷 㩷 Waveforms in Exiting Shutdown Mode (Input CSX="Low") Notes: 1.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 164 of 181 Index Write ( Data=16’h0000 ) Index Write ( Data=16’h0000 ) Index Write ( Data=16’h0000 ) Index Write ( Data=16’h0000 ) Index Write ( Data=16’h0000 ) Index Write ( Data=16’h0000 ) 㩷 Automatic NVM data load Set shutdown mode Notes: 1.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 165 of 181 Index Write ( Data=8’h00 ) Index Write ( Data=8’h00 ) Index Write ( Data=8’h00 ) Index Write ( Data=8’h00 ) Index Write ( Data=8.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 166 of 181 8-Color Mo de Setting R00Bh: COL=1 262,144-color mode display 8-color mode display 8 color to 262,144 color mode R00Bh: COL=0 262,144-col.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 167 of 181 Absolute Maximum Ratings Table 82 Notes: 1. If used beyond the absolute maximum ratings, the LSI may be per manently damaged. It is strongly recommended to use the LSI un der the condit ion within the electrical characteristics in normal operation.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 168 of 181 Electrical Characteristics DC Characteristics (VCC= 2.50V~3.30V, VCI=2.50 V~3.30 V, IOVCC=1.65V~3.30V, Ta= -40 ° C~+85 ° C * See note 1 ) Table 83 Items Symbol Unit T est condition Min. Typ.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 169 of 181 LCD power supply current (VCI-GND) 8-color, 64-line partial display Ici2 mA IOVCC=1.8V, VCC=VCI=2.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 170 of 181 Step-up Circuit Characteristics Table 84 Item Unit Test condi tion Min. Typ. Max. Note DDVDH V IOVCC=VCC=VCI=2.80[V], fosc=678[kHz], Ta =25 ℃ , VC=3’h1, AP=3’h3, BT=3’h2, DC0=3’h4 (div.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 171 of 181 Power Supply Voltag e Range (Ta= -40 ° C~+85 ° C, GND=AGND=0V) Table 86 Item S ymbol Unit Min. Typ. Max. Condition Power Supply Voltage IOVCC V 1.65 1.80/2.80 3.30 - Power Supply Voltage VCC V 2.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 172 of 181 AC Characteristics (VCC= 2.50V~3.30V, IOVCC=1.65V~3.30V, Ta= -40 ° C~+85 ° C * See note 1 ) Clock Characteristics Table 88 Item Symbol Unit Test condition Min. Typ. Max. Not e Oscillation cloc k f osc kHz VCC=IOVCC=3.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 173 of 181 Clock Synchronous Serial Interface Timi ng Char acteristics (IOVCC=1.65V~3.30V) TBD Table 90 Item Symbol Unit Test condition Min.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 174 of 181 LCD Driver Output Characteristics Table 92 Item Symbol Unit Test condition Min. Typ. Max.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 175 of 181 Notes to Electrical Characteristics Note 1. The DC/AC electrical characteristics of bare die and wafer products are guaranteed at 85 ℃ . Note 2. The following figures illustrate the conf igurations of input, I/O, and output pins.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 176 of 181 Note 3: Test 1, 2 and 3 pins must be grounded. The VDDTEST and VREFC m ust be fixed to AGND. The IM0_I D pin must be fixed t o IOVC C or be ground ed. Note 4: This excludes the current in th e output drive MOS.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 177 of 181 Timing Characteristics 80-system Bus Interface tDDR tDHR VIL VOL tWRf VIH VIL VIH VIL VIL VIH VIL VIH VIH VIL VIH RS CSX WRX RDX tAS tAH .
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 178 of 181 Clock Synchronous Serial Interface VIL VIL VIL VIL VIL tsc r VIL VIH CSX tSCYC VIH SCL VIH tCSU SDI VIH VIH VIL VIH tCH tSCH tSCL tscf VI.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 179 of 181 RGB Interface tPDH VIL VIH VIL VIH VIL VIL VSYNCX HSYNCX VIH VIH VIL ENABLE VIH tENS tENH VIL VIL VIH VIL DOTCLK VIH PWDL PWDH VIH VIL DB.
Keep safety rst in your circuit designs! 1. Renesas T echnology Corp. puts the maximum eort into making semiconductor products better and more reliable, but there is al way s the possibility that trouble may occur with them. T rouble with semic onductors may lead to personal injury, re or property damage.
R61509V Tar get Spec Rev. 0.11 April 25, 2008, page 181 of 181 Revision Reco rd Rev. Date Page No. Contents of Modifica tion Drawn by Approv ed by 0.11 2008/04/25 First issue.
Ein wichtiger Punkt beim Kauf des Geräts Renesas R61509V (oder sogar vor seinem Kauf) ist das durchlesen seiner Bedienungsanleitung. Dies sollten wir wegen ein paar einfacher Gründe machen:
Wenn Sie Renesas R61509V noch nicht gekauft haben, ist jetzt ein guter Moment, um sich mit den grundliegenden Daten des Produkts bekannt zu machen. Schauen Sie zuerst die ersten Seiten der Anleitung durch, die Sie oben finden. Dort finden Sie die wichtigsten technischen Daten für Renesas R61509V - auf diese Weise prüfen Sie, ob das Gerät Ihren Wünschen entspricht. Wenn Sie tiefer in die Benutzeranleitung von Renesas R61509V reinschauen, lernen Sie alle zugänglichen Produktfunktionen kennen, sowie erhalten Informationen über die Nutzung. Die Informationen, die Sie über Renesas R61509V erhalten, werden Ihnen bestimmt bei der Kaufentscheidung helfen.
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Jedoch ist die eine der wichtigsten Rollen, die eine Bedienungsanleitung für den Nutzer spielt, die Hilfe bei der Lösung von Problemen mit Renesas R61509V. Sie finden dort fast immer Troubleshooting, also die am häufigsten auftauchenden Störungen und Mängel bei Renesas R61509V gemeinsam mit Hinweisen bezüglich der Arten ihrer Lösung. Sogar wenn es Ihnen nicht gelingen sollte das Problem alleine zu bewältigen, die Anleitung zeigt Ihnen die weitere Vorgehensweise – den Kontakt zur Kundenberatung oder dem naheliegenden Service.
