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Compaq Computer Corporation Al pha A rc h it ec tu re Ha ndb oo k Order Number: EC–QD2KC–T E Revision/Upd ate Information : This is V ersion 4 of the Alpha Architectur e Ha ndbook.
Oc tober 1 998 The inform atio n in this publ ic atio n is subj ect to chang e with o ut notic e. COMP AQ COMP UTER C ORPORA TION SHALL NOT BE LIABLE FOR TECHNICA L OR EDITORIAL ERRORS OR OMISSIONS CONT AINED HEREIN, NOR FOR INCIDENT AL OR CONSEQUENTIAL DAM- AGES RESUL TING FROM TH E FURNISHING, PERFORMANC E, OR USE OF THIS MA TE RIAL.
iii T able of Contents 1 In tr oduction 1.1 The A lph a Ap pro ach to R IS C A rch it ect ure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1.2 Da ta F orm at O ve rvi ew . . . . . . . . . . . . . . . . . . . . . . .
iv 2.3 Big- Endi an Addr essi ng Suppo rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 3 In str uction Fo rmats 3.1 Alpha Regi ster s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v 4.4. 5 Integer Signed Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29 4.4. 6 Integer Unsigned Com pare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi 4.7. 10.4 Propaga ting NaN Valu es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–89 4.8 Me mo ry F or ma t F loa ti ng -Po int In str u ctio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi i 5 Syst em Arch itect ure an d P rog ramm ing Implicat ions 5.1 Intr o duc tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 5.2 Ph ysic al A ddr ess Sp ac e Ch ara cte ri stic s .
viii 6.5 PALcode Eff ects on Syst em Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3 6.6 PALcode Repl acemen t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix A.4 .4. 6 NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–13 A.4. 4.7 Booleans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x E.2. 2.2 Windows NT Alph a Functio ns and Argume nt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E–10 E.2. 2.3 OpenVMS Alpha and DI GITAL UNIX Functi ons and Argument s . . . . . . . . . . . . . . E–12 E.2. 3 21264 Perf or mance M oni to ri ng .
xi Fi gu res 1–1 In s truc t ion Fo rma t Ov erv iew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 2–1 B yte F orm at . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xii Ta b l e s 2–1 F_fl oat in g Load Expon ent Mapping ( MAP_F) ..... .... ... .... . .... . .. .. ... .... . .... ... ... .... .. ... ... .... . ... 2–4 2–2 S_fl oat in g Load Expone nt Mappi ng (MAP_S) . ... . .... ... .... . .... ... ... ...
xiii C–15 PALcode O pcod es in Numeric al Order .. ... .. ... .. ... ...... ... .. ... ... .. ... .. .... . .... . .... . .... .. . .... . .... . C–18 C–16 Req uir ed PALco de O pcodes ..... .... . .... ... .... . .... ... ... .... .. ... ... ..
xiv.
xv Pref ac e Chapters 1 through 8 a nd appendixes A through E of this book are directly derived fr om the Alpha Sys- te m Ref erence Ma nual, Ve r si on 7 and pa ssed engineering change orders (ECOs) that have been appli ed. It is an accurate repr esen tat ion of the desc ri bed par ts of the Alpha archi te ctur e.
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Int roduct ion 1–1 Chapter 1 In troduct ion Alpha is a 64-bit load/sto re RIS C archite cture that is designe d with particu lar emph asis on the three elements that m ost affect performance: c lock spe ed, multiple instruction i ssue , and multi- ple process or s.
1–2 Alpha Architecture Handbook Alpha makes it easy to mainta in binar y compat ibil ity a cross mul tipl e imple mentations and easy to mainta in full s peed on multiple -issue im plementat ions. F or exampl e, th ere are no im plemen- tati on-spe ci fic pipeli ne timing hazar ds, no load-de lay slots, and no branch-de la y slots.
Int roduct ion 1–3 PALcode is writte n i n standard machine code with som e implementa tion-specific exte nsions to provi de access to low- le vel hardware . PALcode le ts Alpha im pleme ntations run the full Ope nVM S Alpha , DI GITA L UN IX, a nd Windows NT Alpha o pe rating system s.
1–4 Alpha Architecture Handbook 1.3 In s t ruc t ion Form at Ov erv iew As shown in Figure 1–1 , Alpha instruction s are all 32 bits in length. There are four major instruction format classes that contain 0, 1, 2, or 3 register fields. All formats have a 6-bit opcode.
Int roduct ion 1–5 Branch In st ru ct i o ns Conditio nal bran ch i nstruc tions can tes t a regist er for p ositiv e/negat ive or fo r zero /nonze ro, and they c an test inte ge r re gister s fo r even/od d. Unc on dition al branch ins tru ctions c a n write a retur n addr ess into a r egist er.
1–6 Alpha Architecture Handbook Floating-P oint Op erate Inst ructi ons The floa ting-poin t oper ate instr uctions include four complete se ts of VAX and I EEE arith- metic inst ructio ns, plus in struc tions f or pe rforming convers ions between floa ti ng-po int and inte ger quantiti es.
Int roduct ion 1–7 1.6 .1 Numbe ring All num bers a re de cimal unle ss oth erwis e ind icated. Wher e ther e is am bigu ity, num be rs othe r than deci mal are indic at ed with the name of the base in subscript form , for example, 10 16.
1–8 Alpha Architecture Handbook Operat ions that pr oduc e UNPREDICTABLE results may also produce ex cepti ons. • An occur rence specified a s UNPREDICT AB LE may happen or no t based on an arbi- trary c h oice fu nc tion.
Int roduct ion 1–9 1.6.6 Must Be Zero (MBZ) Fields spec ified as Must be Zero (M BZ) must neve r be filled by sof tware with a non-zer o value. These field s may b e us ed at som e fu ture tim e. If the pro cess or enco unters a no n- zero value in a fie ld specifie d as M BZ, an Illegal Ope rand e xcepti on occur s.
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Bas i c Arch i te ct ure 2–1 Chapter 2 Basic Ar chitectur e 2.1 Addr essing The ba sic a ddr essa ble un it in the Al pha arc hitec tur e is the 8- bit by te . Vir tua l addr es ses are 64 bits lon g. An im pl em en ta tio n m ay su ppo r t a sm a lle r vir tua l add r ess sp ace .
2–2 Alpha Architecture Handb ook Figure 2–2: Wor d Format A wor d is sp ecified by its address, the addr ess of the byte containi ng bit 0. A word is a 16 -bit val ue. Th e w ord is only suppo rted in Alpha by th e lo ad , store, sign- e xte nd, extra ct, mask, and inser t instruc tio ns.
Bas i c Arch i te ct ure 2–3 A quadword is spe cified by its address A, the address of the byte c ontaining bit 0. A quadword is a 64-bit value. Wh en int erpreted arithm etically, a quadw ord is ei.
2–4 Alpha Architecture Handb ook The F _floa ting stor e ins truction reord ers regis ter b its on the w ay to m emo ry an d does no checking of the low-ord er fraction bits. Reg ister bits <61:59> and <28:0> are ignored by the stor e instru cti on.
Bas i c Arch i te ct ure 2–5 A G_floating ope rand occu pie s 64 bits in a floating r egi ster , a rra nged as shown in Figure 2–8. Figure 2–8: G_f loating Register Format A G_floa ting datum is spe cified by its ad dress A, the add ress of the byte conta ining bit 0.
2–6 Alpha Architecture Handb ook The r eord erin g of bits r equir e d for a D_ floa ting lo ad or store is ide ntica l to th at r equir e d for a G_floating load or store. Th e G_fl oating l oad and sto re instr uctions are therefor e use d for l oa d- ing or storing D_floa ti ng data.
Bas i c Arch i te ct ure 2–7 NaNs. Signaling NaN s are used to provide values for uninitialized variables and for arithmetic enh anc emen ts . Quie t NaNs prov ide r etr ospe ct iv e dia gnost ic infor ma tion r ega rdi ng pr evio us inval id or un av aila ble data an d r esults .
2–8 Alpha Architecture Handb ook This mapping pr eser ves bo th normal valu es and ex ceptional va lues. Note that the map ping for all 1’ s di ffe rs from th a t of F_f loa tin g loa d, s inc e fo r S_f lo at ing all 1’s is an e xc eptio na l valu e and for F_fl oating al l 1’s is a normal value.
Bas i c Arch i te ct ure 2–9 A T_floating ope rand occupie s 64 bits in a floating r eg ister , a rra nged as shown in Figure 2–14. Figure 2–14: T_floating Regis ter Format The T_floa ting l oad instr uction perfor ms no bit reordering on input, nor does i t pe rform check- ing of the i nput data.
2–10 Alpha Architecture Handbo ok Figure 2–15: X _floating Datu m An X_floa ting datum occupies two co nsecutive even/od d floa ting-point registers (suc h as F4/F5) , as sho wn in Figure 2–16 . Figure 2–16: X _floating Register Format An X_floatin g datum is specified by its address A, the a ddress of t he byte c ontaining bit 0.
Basic Archit ecture 2– 1 1 Figure 2–17: X _floating Big-Endi an Dat um Figure 2–18: X _floating Big-Endi an Regis ter Format 2.2.7 Lo ngword Inte ger Forma t in Fl oatin g-P oin t Uni t A longword intege r opera nd occupie s 32 bits in memory, arra ng ed a s s h own i n Figur e 2–1 9.
2–12 Alpha Architecture Handbo ok Note: Alpha imple mentatio ns will im pose a signif ican t performanc e penalty whe n accessing longwor ds t hat a re not nat urally a li gned. (A natur ally aligne d lo ngword datum has zero a s the low-or der two bits of its addr ess.
Basic Archit ecture 2–13 • T railing Numeric S tr ing • Leading Sepa rate Numer ic Stri ng • Pack ed D eci ma l String 2.3 Big -Endi an A ddr essing Suppo rt Alpha imple mentation s may include opti onal big- endi an addr essing suppor t.
2–14 Alpha Architecture Handbo ok used unchanged for b oth conve nti ons. Bi g-endian ch arac te r str i ngs have t hei r most sig- nifi cant charact er on the left, while litt le-endia n strings have their most signif icant cha r- acte r on the right.
Instruc tion For mats 3–1 Chapter 3 Instruction Formats 3.1 Al pha R egi ste rs Each Alpha p rocesso r has a set of reg isters that h old the cu rrent proc essor state. If an A lpha system c onta ins mu ltiple Alpha proce ssors, th ere are m ultiple per-proc essor se ts of thes e regist e rs.
3–2 Alpha Architecture Handb ook There are some inte res ting c ases invol ving R31 as a destinati on: • STx_C R31,di sp( Rb) Although this might se em like a goo d way to zero out a sh a red loc atio n and r eset the lock_ flag, thi s instruction c ause s th e lock_fl ag and vir tual l ocati on {Rbv + SEXT(disp) } to become UNPREDICTABLE.
Instruc tion For mats 3–3 3.1.5 Pr ocess or Cycle Counter ( PCC) Register The PCC re giste r consists of two 32-bit fields. The low-order 32 bits (PCC< 31:0>) are an unsigned wrapping counter, P CC _CNT. The high-order 32 bits (PCC<63:32>), PCC_OFF, are opera ting syst em depende nt in their implementa ti on.
3–4 Alpha Architecture Handb ook 3.2.1 Operan d Notat ion Tab le s 3– 1, 3 –2 , an d 3 –3 l ist the no ta ti on f o r t he op e ran ds, t he op e ran d va l ue s, a nd th e o the r expre ssion oper and s.
Instruc tion For mats 3–5 3.2.2 In str ucti on Operan d Nota tion The notation used to describe instruction operands follows from the operand specifier notation used in the VAX Arc hit ecture Standa rd . Instruc tio n op erands are descr ibed a s fo llows: <nam e> .
3–6 Alpha Architecture Handb ook 3.2.2.3 Operand Data T ype Notation A le tter th at denote s the d ata type o f the o perand: 3.2.3 Operators Table 3–7 descr ibes the opera tor s: r The operand is rea d only. m The operand is both r ead and writt en.
Instruc tion For mats 3–7 || Bi t con cate na tion {} Indicat es explicit op erato r p rec ed ence (x) Contents of memory loca tion whose addre ss is x x <m:n> Contents of bit field of x defined by bits n through m x <m> M’th bit of x ACCESS(x, y) Accessibi lit y of the location whos e addr ess is x using the access mode y.
3–8 Alpha Architecture Handb ook CASE The CASE const r uct sele cts on e of several acti ons b ased on the value o f its ar gument. Th e form of a cas e is: CASE argument OF argvalue1: a ction_1 argvalue2: a ction_2 .
Instruc tion For mats 3–9 NOT Logical ( ones) complement OR Logical s um PHYSICAL_ADDRESS Translat ion of a vir tual a ddress PRIORITY_ENCODE Returns the bit posi tion of most signific ant set bit, inter- preting it s argument as a posi tive inte ger ( =in t(lg(x))).
3–10 Alpha Architecture Handbo ok 3.2.4 N otation Convent ions The following conventio ns are used : • Only ope ra nds that appe ar on the l eft side of a re placement op erato r are mo difie d. • No operat or precede nc e is assume d othe r than tha t rep la cement ( ← ) has the lowe st pre- cedence .
Instruc tion Format s 3–11 3.3.1 Memory In struct ion F ormat The Memory form at is used to transfer data between registers and memory, to load an effec- tive addr ess, and f or subrouti ne jumps.
3–12 Alpha Architecture Handbo ok 3.3.1.2 Memory Format Jump Instructions For computed branch inst ructions (CALL, RET, JMP, JSR _COROUTIN E) the displacement field is used to p rovide bra nch-predic ti on hints a s desc ribe d in S ecti on 4.3. 3.3.
Instruc tion Format s 3–13 An Operat e format inst ructi on contains a 6-bit opco de field and a 7-bit func tion code field. Unuse d functi on codes for opc odes defi ned as reserve d in th e Version 5 Alpha arc hitect ur e specification (May 1992) produce an illegal instruction trap.
3–14 Alpha Architecture Handbo ok A Fl oa ti ng - poi nt Op e rat e fo rm a t in st ru c tio n c o nta i ns a 6 - bi t op c od e fie ld a n d a n 11 -b it fu nc - tion field. Unused f unction codes f or those o pcodes defined as reserved in the Ve rsion 5 A lpha architecture specification (May 1992) pro duce an i llegal instruction trap.
Instruc tion Format s 3–15 Figure 3–6: PALcode Instruction Form at The 26-bit PALcod e function field s pecifies the operation. T he sourc e an d destination o per- ands for PALcode instr uctions are supplie d in fixed regist ers tha t are speci fi ed in the individual instr uction de sc ription s.
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Inst ructi on Desc ripti ons 4–1 Chapter 4 Instruction Descrip tions 4.1 Instruction Set Overview This chapter describes the instructions implemented by the Alpha architecture.
4–2 Alpha Architecture Handbook • Quali fiers spe ci fic to the instr uc tio ns in the group • A descrip tion of the inst ru ction opera tio n • Optiona l programming e xample s and optiona l note s on the instructi on 4.
Inst ructi on Desc ripti ons 4–3 4.1.3 Sof tware Emulation R ules General-purpose layere d and appli cation software that executes in User m ode may assume that certain lo ads (L DL, L DQ, LD F, LD G , LDS , and LD T) an d ce rtain s tores (ST L , ST Q , STF , STG, STL, and S TT) of unaligned data are emulate d by syst em sof tware.
4–4 Alpha Architecture Handbook 4.2 M emory Integer Lo ad/S to r e Instructions The instruc ti ons in this se ction move dat a betwe en the intege r regi ste rs and memory. They use the Memory inst ructi on format. The instr uctions are summariz e d in Table 4–2.
Inst ructi on Desc ripti ons 4–5 4. 2.1 L oa d Ad dr ess Format: Operat ion: Ra ← Rbv + SEXT(disp) !LDA Ra ← Rbv + SEXT(disp*65536) !LDAH Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des.
4–6 Alpha Architecture Handbook 4.2.2 Load Memory Dat a into Int eger Register Format: Operat ion: va ← {Rbv + SEXT(disp)} CASE big_endian_data: va’ ← va XOR 000 2 !LDQ big_endian_data: va’ .
Inst ructi on Desc ripti ons 4–7 In the case of LD Q an d LD L, the so ur ce operand is fetch ed from m emo ry, sign -exte nded, and writt en to registe r Ra. In the case of LDW U and LDB U, the sour ce ope rand is fetche d from m emo ry, zero- extend ed, and writte n to regist er Ra.
4–8 Alpha Architecture Handbook 4.2.3 Load Unal igned Memory Data in to Integer Regis ter Format: Operat ion: va ← {{R bv + SEXT(disp)} AND NOT 7} Ra ← (va )<63:0> Excepti ons: Inst ruct i.
Inst ructi on Desc ripti ons 4–9 4.2.4 Load Memory Data i nto I nteger Regis ter Locked Format: Operat ion: va ← {Rb v + SEXT(disp) } CASE big_endian_data: va’ ← va XOR 000 2 ! LDQ_L big_endia.
4–10 Alpha Architecture Handbo ok When a LDx_L instr uction is executed without faulting, the processor records the target physi- cal address in a pe r-processor loc ked_ physical_address register and se ts the per-proce ssor loc k _f la g .
Instruc tio n Desc riptio ns 4–11 If two LDx_L in structions exe cute with no i nter veni ng STx_C, the second one overwr ites the st ate of the f irst one . If two STx_C inst ructi ons execut e with no inte rvenin g LDx_L, the second one a lways fail s bec ause the first c lea rs lo ck_flag.
4–12 Alpha Architecture Handbo ok 4.2.5 S tor e In teger Regist er Data i nto Memory Conditional Format: Operat ion: va ← {Rbv + SEXT(disp)} CASE big_endian_data: va’ ← va XOR 000 2 ! STQ_C bi.
Instruc ti on Desc riptio ns 4 –13 • The comput ed virt ual address m ust spec ify a loc ation withi n the natural ly aligne d 16-byt e block in virtua l memory acc essed by the preced ing LDx_L instr uction .
4–14 Alpha Architecture Handbo ok Software Note: If the addr ess specifi e d by a STx_C inst r uct ion do es not match the one given i n the precedi ng LDx_L ins truction, an M B is re quired to gua rantee orde ring betwe en th e two instr uctions .
Instruc ti on Desc riptio ns 4 –15 4.2.6 S tore Inte ger Regist er Data i nto Memory Format: Operat ion: va ← {Rbv + SEXT(disp)} CASE big_endian_data: va’ ← va XOR 000 2 !STQ big_endian_data: .
4–16 Alpha Architecture Handbo ok The Ra oper and is writt e n to memory at this a ddress. If the da ta is not natur all y aligne d, an alig nment exceptio n i s gene rated. Notes: • The word o r byte that t he STB or STW instr ucti on sto res to memo ry comes from the low ( rightm ost) byte o r word of Ra.
Instruc ti on Desc riptio ns 4 –17 4.2.7 S tor e Unalig ned Integer Register Data in to Memory Format: Operat ion: va ← {{Rb v + SEXT(disp)} AND NOT 7} (va)<63:0> ← Rav<63:0> Excepti.
4–18 Alpha Architecture Handbo ok 4. 3 Cont r ol In str uc tion s Alpha provi des int e ger cond iti onal br anch, uncond itional bra nch, branc h to sub routi ne, and jump instructions. The PC use d in these instru ctions is the updated PC, a s d escribed in S ection 3.
Instruc ti on Desc riptio ns 4 –19 BNE Branc h if Register Not Equal to Zero BR Uncondi tional Bra nc h BSR Branch to Subrout ine JMP Ju mp JSR Jump to Subrout ine RET Return fr om Subrout ine JSR_C.
4–20 Alpha Architecture Handbo ok 4.3.1 Cond itio nal Branch Format: Operat ion: {update PC} va ← PC + {4*SEXT(disp)} IF TEST(Rav, Condition_ba sed_on_Opcode) THEN PC ← va Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Regis te r Ra i s te ste d .
Instruc ti on Desc riptio ns 4 –21 4.3.2 Uncond itional Bran ch Format: Operat ion: {update PC} Ra ← PC PC ← PC + {4*SEXT(disp)} Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The PC of the fol lowin g instr uc tion (the upda ted PC) is wr itten to registe r Ra an d then the PC is loaded with the target a ddr ess.
4–22 Alpha Architecture Handbo ok 4.3 .3 Jumps Format: Operat ion: {update PC} va ← Rbv AND {NOT 3} Ra ← PC PC ← va Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The PC of.
Instruc ti on Desc riptio ns 4 –23 The design in Table 4–4 a llo w s speci fication of the low 16 bits of a likel y lon gw o rd ta rget address (enoug h bits to start a useful I-c ach e ac cess ea rly), and al so allows d istingu ishin g call from retu rn (and from the othe r two less fre que nt operati ons).
4–24 Alpha Architecture Handbo ok 4.4 I nteg er Arith metic Instr uctio ns The inte ger arithm etic instr uctions perf orm add, su btr act, m ultiply , signed a nd uns igne d c om- pare, and bit count operat ions.
Instruc ti on Desc riptio ns 4 –25 4.4.1 Longword Add Format: Operat ion: Rc ← SEX T( (Rav + Rbv) <31:0>) Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Register Ra is added to register Rb or a literal and the sign-extended 32-bit su m is written to Rc.
4–26 Alpha Architecture Handbo ok 4.4.2 Scaled Longword Add Format: Operat ion: CASE S4ADDL: Rc ← SEXT (((LEFT_SHIFT(Rav, 2)) + Rbv)<31: 0>) S8ADDL: Rc ← SEXT (((LEFT_SHIFT(Rav, 3)) + Rbv).
Instruc ti on Desc riptio ns 4 –27 4.4.3 Quad word Ad d Format: Operat ion: Rc ← Rav + Rbv Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Registe r R a is added to registe r R b or a li te ral a nd t he 64-bit sum is wr itte n t o Rc.
4–28 Alpha Architecture Handbo ok 4.4.4 Scaled Qu adw ord Add Format: Operat ion: CASE S4ADDQ: Rc ← LEFT_SHIFT(Rav,2) + Rbv S8ADDQ: Rc ← LEFT_SHIFT(Rav,3) + Rbv ENDCASE Excepti ons: Inst ruct io.
Instruc ti on Desc riptio ns 4 –29 4.4.5 Integer Signed C ompare Format: Operat ion: IF Rav SIGNED_RELATION Rb v THEN Rc ← 1 ELSE Rc ← 0 Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Registe r Ra is compared to Register Rb or a literal.
4–30 Alpha Architecture Handbo ok 4.4.6 Integer Unsigned Compar e Format: Operat ion: IF Rav UNSIGNED_RELATION Rbv THEN Rc ← 1 ELSE Rc ← 0 Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Registe r Ra is compared to Register Rb or a literal.
Instruc ti on Desc riptio ns 4 –31 4.4.7 Coun t Leading Zero Format: Operat ion: temp = 0 FOR i FROM 63 DOWN TO 0 IF { Rbv<i> EQ 1 } THEN BREAK temp = temp + 1 END Rc<6:0> ← temp<6:.
4–32 Alpha Architecture Handbo ok 4.4.8 Count Pop ula tion Format: Operat ion: temp = 0 FOR i FROM 0 TO 63 IF { Rbv<i> EQ 1 } THEN temp = temp + 1 END Rc<6:0> ← temp<6:0> Rc<63:7> ← 0 Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The number of ones i n Rb i s wr itte n t o Rc.
Instruc ti on Desc riptio ns 4 –33 4.4.9 Coun t T rail ing Zero Format: Operat ion: temp = 0 FOR i FROM 0 TO 63 IF { Rbv<i> EQ 1 } THEN BREAK temp = temp + 1 END Rc<6:0> ← temp<6:0&.
4–34 Alpha Architecture Handbo ok 4.4.10 Longwo rd Mu ltiply Format: Operat ion: Rc ← SE XT ((Rav * Rbv)<31:0>) Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Registe r Ra is multiplie d by register Rb or a literal and the sign-extende d 32-bit product is writt en to R c.
Instruc ti on Desc riptio ns 4 –35 4.4.1 1 Q uadword Mul tiply Format: Operat ion: Rc ← Rav * Rbv Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Register Ra is multiplied by register Rb or a literal and the 64-bit produc t is written to registe r Rc.
4–36 Alpha Architecture Handbo ok 4.4.12 Uns ign ed Quad wor d Mul tip ly High Format: Operat ion: Rc ← {Rav * U Rbv}<127: 64> Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Register Ra and Rb or a literal are multiplied as unsigned numbe rs to produc e a 128-bit result.
Instruc ti on Desc riptio ns 4 –37 4.4.13 Longwo rd Sub tract Format: Operat ion: Rc ← SEX T ((Rav - Rbv) <31:0>) Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Register Rb or a literal is subtracted from register Ra and the sign-exte nded 32-bit differenc e is writt en to R c.
4–38 Alpha Architecture Handbo ok 4.4.14 Scaled Lon gword Subtract Format: Operat ion: CASE S4SUBL: Rc ← SEXT (((LEFT_SHIFT(Rav, 2)) - Rbv)<31: 0>) S8SUBL: Rc ← SEXT (((LEFT_SHIFT(Rav, 3)).
Instruc ti on Desc riptio ns 4 –39 4.4.15 Quadword S ubtract Format: Operat ion: Rc ← Rav - Rbv Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Registe r Rb or a lite ral is sub tracted from regi ster Ra and the 6 4-bit difference i s writt en to r eg- ister Rc.
4–40 Alpha Architecture Handbo ok 4.4.16 Scaled Quad word Subtract Format: Operat ion: CASE S4SUBQ: Rc ← LEFT_SHIFT(Rav,2) - Rbv S8SUBQ: Rc ← LEFT_SHIFT(Rav,3) - Rbv ENDCASE Excepti ons: Inst ru.
Instruc ti on Desc riptio ns 4 –41 4.5 Logical and Shift In st ructions The log ical in str uc tions perf or m qua dwo rd Boole an opera tio ns. Th e c ond ition al mo ve inte ger instr uctions perf orm condit ionals wi thout a br anch. The shi ft ins tructi ons perf orm lef t and right logic al shi f t and right ari thmeti c shif t.
4–42 Alpha Architecture Handbo ok 4.5.1 Logical Fu nct ions Format: Operat ion: Rc ← Rav AND Rbv !AND Rc ← Rav OR Rbv !BIS Rc ← Rav XOR Rbv !XOR Rc ← Rav AND {NOT Rbv} !BIC Rc ← Rav OR {NO.
Instruc ti on Desc riptio ns 4 –43 4.5.2 Cond itio nal Move Integer Format: Operat ion: IF TEST(Rav, Condition_ba sed_on_Opcode) THEN Rc ← Rbv Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Regi ster R a is t est ed. If the spec if ied re lat io ns hip is true, t he va l ue Rbv is writ ten to reg is ter Rc.
4–44 Alpha Architecture Handbo ok Notes: Except tha t it is likely in many impl emen tations to be s ubsta nti al ly faster , the instr uctio n: CMOVEQ Ra,Rb,Rc is e xact ly equivale nt t o: BNE Ra,label OR Rb,Rb,Rc label: .
Instruc ti on Desc riptio ns 4 –45 4.5.3 Shi ft Logical Format: Operat ion: Rc ← LEFT_SHIFT(Rav, R bv<5:0>) !SLL Rc ← RIG HT_SHIFT(Rav, Rbv<5:0>) !SRL Excepti ons: Inst ruct ion mne .
4–46 Alpha Architecture Handbo ok 4.5 .4 Shi ft Ar it hm et ic Format: Operat ion: Rc ← ARITH_RIGHT_SHIFT( Rav, Rbv<5:0>) Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Register Ra is right shifted arithmetically 0 to 63 bits by the cou nt in register Rb or a literal.
Instruc ti on Desc riptio ns 4 –47 4.6 By te Mani pul ation I nstr u ctions Alpha impleme ntations that suppor t the BWX extension pr ovide the following instructions fo r loadi ng, sign-ext e nding.
4–48 Alpha Architecture Handbo ok INSWH Inser t Word High INSLH Inser t Longwor d High INSQH Inser t Quadword High MSKBL Mask B yte Low MSKWL Mask Wor d Lo w MSKLL Mask Longword Low MSKQL Ma sk Quad.
Instruc ti on Desc riptio ns 4 –49 4.6.1 Comp are Byte Format: Operat ion: FOR i FROM 0 TO 7 temp<8:0> ← 0 || Rav<i*8+7:i*8>} + { 0 || NOT Rbv<i *8+7:i*8>} + 1 Rc<i> ← te.
4–50 Alpha Architecture Handbo ok To compare two chara cter str ings f or greater/e qua l/ les s: <initialize R1 to aligned QW address of string1> <initialize R2 to aligned QW address of st.
Instruc ti on Desc riptio ns 4 –51 4. 6. 2 Ext rac t B yt e Form at: Operat ion: CASE big_endian_data: Rbv’ ← Rbv XOR 111 2 little_endian_data: Rbv’ ← Rbv ENDCASE CASE EXTBL: byte_mask ← 0.
4–52 Alpha Architecture Handbo ok Des cription: EXTxL shifts regis ter Ra ri ght by 0 to 7 bytes, inserts z eros into vacat ed bit positions, and the n extr a cts 1 , 2, 4, or 8 byte s into regi ster Rc .
Instruc ti on Desc riptio ns 4 –53 For software that i s not designed to use the BWX e xtension, the intended sequence for loading and zero- extend ing a word from unalign ed addr ess X is: LDQ _U R.
4–54 Alpha Architecture Handbo ok For software that i s not designed to use the BWX e xtension, the intended sequence for loading and zero- extend ing an aligne d word from 10(R3) is: LDL R1, 8(R3 ).
Instruc ti on Desc riptio ns 4 –55 4.6.3 Byte Insert Format: Operat ion: CASE big_endian_data: Rbv’ ← Rbv XOR 111 2 little_endian_data: Rbv’ ← Rbv ENDCASE CASE INSBL: byte_mask ← 0000 0000.
4–56 Alpha Architecture Handbo ok Qualifie rs: Des cription: INSxL and INSxH shift bytes from register R a and insert the m into a field of zeros, st oring the res ult in regi ster R c. Regis ter Rb v ’ <2:0> s elects the shift am ount, a nd the functio n cod e selects the ma ximum field width: 1, 2, 4, or 8 bytes.
Instruc ti on Desc riptio ns 4 –57 4. 6. 4 B yt e Mas k Format: Operat ion: CASE big_endian_data: Rbv’ ← Rbv XOR 111 2 little_endian_data: Rbv’ ← Rbv ENDCASE CASE MSKBL: byte_mask ← 0000 0.
4–58 Alpha Architecture Handbo ok Des cription: MSKxL a nd M SKxH set selecte d byte s of register Ra to zer o, storing the resu lt in register Rc. Regist er Rbv ’ <2:0> sele cts th e start ing posit ion of the field of zero byt es, and the functi on co de se l e c t s t h e m ax i m u m w i dt h : 1 , 2 , 4, or 8 by te s.
Instruc ti on Desc riptio ns 4 –59 For softwa re that is not des igne d to use the BWX extensio n, the inte nded seq ue nce for stor ing an unaligne d word R5 at X is: LDA R6, X(R1 1) ; R6<2: 0&g.
4–60 Alpha Architecture Handbo ok 4.6.5 Sign Exte nd Format: Operat ion: CASE SEXTB: Rc ← SEXT(Rbv<07:0>) SEXTW: Rc ← SEXT(Rbv<15:0>) ENDCASE Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The byte or word in reg ister R b is sign-ext end ed to 64 bits and written to r egister Rc.
Instruc ti on Desc riptio ns 4 –61 4.6.6 Zer o Bytes Format: Operat ion: CASE ZAP: Rc ← BYTE_ZAP(Rav, Rbv<7:0>) ZAPNOT: Rc ← BYTE_ZAP(Rav, NOT Rbv<7:0>) ENDCASE Excepti ons: Inst ruc.
4–62 Alpha Architecture Handbo ok 4.7 Floati ng-Poin t Instr uctions Alpha prov ides i nstruct ions fo r oper ating on float ing-p oint op erands in each of fo ur da ta form ats : • F_floa ting (V.
Instruc ti on Desc riptio ns 4 –63 All floating-point loads and stores may take mem ory managem ent faults (access control viola- tion, tr anslati on not vali d, f ault on r e ad/wr ite , data alig nment).
4–64 Alpha Architecture Handbo ok For VAX f loati ng-p oint, fi nites do not includ e rese rved op erands or d irty zero s (th is di ffers from the usual VA X inte rpr etation of dirty z eros a s finite ). F or IEE E flo ating- point, f inite s do not i nc lude inf in ites, NaNs, or d enormal s, but do include m inus zero.
Instruc ti on Desc riptio ns 4 –65 true zer o The value +0, repr esent ed as exac tly 64 zer os in a floating-poin t regist er. 4.7.4 Encodin gs Floating- point numbers are r eprese nted with thre e fiel ds: sign, e xponent, and f raction. The sign is 1 bit; the expon ent is 8, 11 , or 15 bits; a nd the fr action is 2 3, 52, 55 , o r 11 2 bits.
4–66 Alpha Architecture Handbo ok 4.7.5 Roun ding Mo des All roundi ng modes map a true result tha t is exac tly r eprese nta ble to that repr esent a ble value . VAX Rounding Modes For VAX floa ting- point operations , two rounding modes are provided and are specifie d in each instr uction: nor mal ( biase d) roundi ng and c hopped round ing.
Instruc ti on Desc riptio ns 4 –67 The following tables summari ze the floati ng- point roundin g modes: 4.7.6 C omp ut atio nal Model s The Alpha archi tect ur e provides a choic e of flo ati ng-point computationa l models .
4–68 Alpha Architecture Handbo ok 4.7.6.2 High-Performance V AX-Format Arithmetic This model provides arithmetic operations on VAX fini te numbe rs. An i mp recise ari thmetic trap is generate d by any operatio n t hat in volves non- finite numbers, floa ti ng overf low, a nd divide -by- zero e xceptions.
Instruc ti on Desc riptio ns 4 –69 4.7.6.5 High-Performance I EEE-Format Arithmetic This model provides arithme tic operations on IEEE finite numbers and notifies applications of all exc eptional floating-poi nt operations.
4–70 Alpha Architecture Handbo ok When /U or /V mode is specified : • Arith metic i s p erfor med on V AX f in ite nu mbers. • Operat ions give impre c ise traps when ever the follo w ing occur:.
Instruc ti on Desc riptio ns 4 –71 A summary of the VAX trappin g modes, instructio n notation, and thei r meaning foll ows in Table 4–8: 4.7.7.2 IEEE T rapping Modes This sectio n de scribes th e cha rac terist ics of the four IEE E trap ping mo de s, whic h are sum m a- rize d i n Table 4–9.
4–72 Alpha Architecture Handbo ok • T raps are impreci se, and it is not always pos sible to d etermi ne which i nstruction trig- gered a t rap or th e operands of t hat instr uction . • An underfl ow trap produces a zero. • A conver sion t o inte ger trap with a n in te ger ove rfl ow pr oduces the low- order bi ts of the inte ger .
Instruc ti on Desc riptio ns 4 –73 4.7.7.3 Arith metic T rap Comp letion Becaus e floa ting-po int ins tructi ons may be pip elined , the t rap PC can be an arbi trary nu mber of instructions past the one triggering the trap.
4–74 Alpha Architecture Handbo ok Cond ition 3 al low s an OS com ple tio n ha ndl er to e mula te the tr igg er ins truct ion w ith its ori gi- nal input op erand valu e s. Condition 4 allows the handler to re-execute instructions in the trap shadow with their original opera nd valu es.
Instruc ti on Desc riptio ns 4 –75 T able 4–10: T r ap Shadow Length Rul es Floatin g-Point Inst ruct ion Group T r ap Shadow E xtends Until Any of t he Following Occurs: Floating - point ope rate (except DIVx and SQRTx) • Encount ering a CALL_P AL, EXCB, or TR APB instr uction.
4–76 Alpha Architecture Handbo ok 4.7.7.4 Invalid Operation (INV ) Arithmetic T rap An invalid o peration ari thme tic trap is signaled if an op erand is a non-fi nite numb er or i f an operand is invalid for the operation to be performed. (Note that CMPTxy does not trap on plus or minus i nfi nity.
Instruc ti on Desc riptio ns 4 –77 An i mplementa ti on may choo se n ot to take an INV trap for a valid I EEE op e ra tion tha t involve s denormal opera nds if : • The instruc tio n is mo difie d by a ny vali d qua lifi er combinatio n th at include s the / S (excepti on c ompletion ) qualif ie r .
4–78 Alpha Architecture Handbo ok 4.7.7.7 Underflow ( UNF) Arit hmetic T rap An underflow occurs if the rounded result is smalle r in ma gni tude than the smallest finite num- ber of the de stina tion for mat. If a n und erflow oc curs, a tr ue zer o (64 bits of z ero) i s alwa ys stor ed in the result r egister.
Instruc ti on Desc riptio ns 4 –79 4.7.7.1 1 IEE E Denormal Con tr ol Bits In the c ase of IEEE e xception comple tion mo des, the ha ndling of denorma l operan ds and results is contr olled by the DNZ and UNDZ bits in the FPCR.
4–80 Alpha Architecture Handbo ok VAX and IEEE subsets, appropri ately set the FPCR exception bits. It is UNPREDICTABLE wheth er floating- point op erates that be long only to th e VAX flo a tin g-point subs et set th e FPCR excepti on bits. Alpha floatin g-p oint hardw are only transition s thes e exception bits from zero to one.
Instruc ti on Desc riptio ns 4 –81 FPCR is read from and writte n to the floating-point r egisters by the MT_FPC R and MF_FPCR instr uctions respe cti ve ly, which are descr ibed in Sect ion 4.7. 8.1. 57 Integer Overflow ( IOV). An inte ger ari thmetic oper ation or a conversion f rom floati ng to i nteger overflo wed the d estination precision.
4–82 Alpha Architecture Handbo ok FPCR and the i nstru ctions to ac cess it are r equired for an implement ation that support s float- ing- point ( see S ectio n 4.7 .8). On impl ementa tions that d o not su pp ort floa ting-p oin t, the instr uctions that access FPCR (MF_FPCR and MT_FPCR) take an Illegal I nstr uctio n Trap.
Instruc ti on Desc riptio ns 4 –83 4.7.8.2 Default V alues of t he FPC R Processor init ia liza tion le aves the val ue of FPCR UNPREDICTABLE. Software Note: Com paq soft ware should initi aliz e FPCR<DYN> = 10 during program ac tivati on.
4–84 Alpha Architecture Handbo ok Compaq s oftware may choos e to in itia lize t he software st at us bits a nd t he trap disable bits t o all 1’s to avoi d any in itial trapping when an e xce ption conditi on fir st occurs.
Instruc ti on Desc riptio ns 4 –85 T able 4–12: I EEE Floating-Point Fu nction Field Bit Summary Bit s Fi eld Meaning † 15–13 TRP Trapping modes: 12–11 RND Rounding m odes: 10–9 SRC Sour c.
4–86 Alpha Architecture Handbo ok 8–5 FNC I nstructi on class: † Enco dings fo r th e inst ruct ion s CVT ST an d CVTST/ S ar e ex c epti o n s to this ta ble ; us e th e enco ding s in Sec tion C.
Instruc ti on Desc riptio ns 4 –87 T able 4–13: V AX Floating-Point Function F ield Bit Summary Bits F ield Mean ing 15–13 TRP Trapping modes: 12–11 RND Rounding m odes: 10–9 SRC S our ce da.
4–88 Alpha Architecture Handbo ok 4.7.10 IEEE S tandard The IE EE S ta ndar d f or Bin a ry Floa ti ng -Po int A r ith m etic ( AN S I/IE EE S ta nd ard 754 - 198 5) is includ e d by refere n ce. This stan dard leav es cert ain op erat ions a s impl ement ation dep ende nt.
Instruc ti on Desc riptio ns 4 –89 4.7.10.2 Copying NaN V alues Copyi ng a NaN value wit hout chan ging its p recisio n does not cau se an in valid op eration except ion.
4–90 Alpha Architecture Handbo ok 4. 8 Mem ory For mat F loa ti ng- Po int I n str uc tio ns The inst ruct ions in t his se cti on move data be t ween the flo atin g-point reg iste rs a nd memory . They use the Memory instruc tion format . They do not interpr et the bits moved in any way; spe- cific ally, they do not trap on non-fini te values.
Instruc ti on Desc riptio ns 4 –91 4. 8.1 L oa d F _ fl oa ti ng Format: Operat ion: va ← {Rb v + SEXT(disp) } CASE big_endian_data: va’ ← va XOR 100 2 little_endian_data: va’ ← va ENDCASE.
4–92 Alpha Architecture Handbo ok 4.8.2 Lo ad G_f loating Format: Operat ion: va ← {Rbv + SEXT(disp)} Fa ← (va) <15:0> || (va)<31:16> || (va )<47:32> || (v a)<63:48> Exce.
Instruc ti on Desc riptio ns 4 –93 4.8.3 Load S_f loat ing Format: Operat ion: va ← {Rbv + SEXT(disp)} CASE big_endian_data: va’ ← va XOR 100 2 little_endian_data: va’ ← va ENDCASE Fa ← .
4–94 Alpha Architecture Handbo ok 4. 8.4 L oa d T_f loa t ing Format: Operat ion: va ← {Rbv + SEXT(disp)} Fa ← (va) <63:0> Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: LDT fetches a quadwo rd (integer or T_floating) from mem ory and writes it to register Fa.
Instruc ti on Desc riptio ns 4 –95 4. 8.5 S to re F_f l oa t ing Format: Operat ion: va ← {Rbv + SEXT(disp)} CASE big_endian_data: va’ ← va XOR 100 2 little_endian_data: va’ ← va ENDCASE (.
4–96 Alpha Architecture Handbo ok 4.8.6 S tore G_float ing Format: Operat ion: va ← {Rbv + SEXT(disp)} (va)<63:0> ← Fav<15:0> || Fav<31:16> || Fav<47:32> || Fav<63:48> Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: STG stores a G _floating (or D_floa ting) datum from Fa to mem ory.
Instruc ti on Desc riptio ns 4 –97 4.8.7 S tore S_floa tin g Format: Operat ion: va ← {Rbv + SEXT(disp)} CASE big_endian_data: va’ ← va XOR 100 2 little_endian_data: va’ ← va ENDCASE (va.
4–98 Alpha Architecture Handbo ok 4.8.8 S t ore T_floati ng Form at: Operat ion: va ← {Rbv + SEXT(disp)} (va)<63:0> ← Fav<63:0> Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: STT stores a quadword (intege r or T_floati ng) datum from Fa to m emory.
Instruc ti on Desc riptio ns 4 –99 4.9 Branch Format Flo atin g-Po int Instruct ion s Alpha pr ovi de s six flo ating co ndit iona l b ranc h instr ucti ons. T he se br a nc h-fo rma t in str uctio ns test the value of a floating- poi nt regis ter and condi tiona ll y change the PC.
4–100 Alpha Architecture Handboo k 4.9.1 Cond itio nal Branch Format: Operat ion: {update PC} va ← PC + {4*SEXT(disp)} IF TEST(Fav, Condition_ba sed_on_Opcode) THEN PC ← va Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Regi ste r F a is te ste d .
Instruc tion Desc ription s 4– 101 Notes: • T o bran ch properly on non-finite o perands, compar e to F 31, then branch on the resul t of the co m pare . • The lar gest negative intege r (8000 0000 000 0 000 0 16 ) is t he s ame bi t pa tter n as float ing minus zero, so i t i s t reated as equal to zero by the bran ch instr uctio ns.
4–102 Alpha Architecture Handboo k 4.1 0 Floating -Po int Op erat e Format Instructio ns The floating-point bit- operate instructions perform copy and integer c onvert operations on 64-bit r egiste r value s. Th e bit -op erate in stru ctions do not inte rpret the bits mo ve d in any wa y; specif ica lly, they do not trap on non-fini te values.
Instruc tion Desc ription s 4– 103 Arith metic Ope rations ADDF Add F_floating VAX ADDG Add G_floating VAX ADDS Add S_floating IEEE ADDT Add T_f loatin g IEEE CMPGxx Compare G_floating VAX CMPTxx Co.
4–104 Alpha Architecture Handboo k Arith metic Ope rations MULF M ultip ly F_f loati ng VAX MULG Multiply G_ float ing VAX MULS M ultip ly S_f loati ng IEEE MULT Multiply T _float ing IEEE SQRTF Squ.
Instruc tion Desc ription s 4– 105 4.1 0.1 Co py Si gn Format: Operat ion: CASE CPYS: Fc ← Fav<63> || Fbv<62:0> CPYSN: Fc ← NOT(Fav<63>) || Fbv<62: 0> CPYSE: Fc ← Fav&l.
4–106 Alpha Architecture Handboo k 4.10.2 Convert Integer to Integer Format: Operat ion: CASE CVTQL: Fc ← Fbv<31:30> || 0<2:0> | | Fbv<29:0> || 0<28:0> CVTLQ: Fc ← SEXT(F.
Instruc tion Desc ription s 4– 107 4.10.3 Floatin g-Poin t Cond itional Mov e Format: Operat ion: IF TEST(Fav, Condition_ba sed_on_Opcode) THEN Fc ← Fbv Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Regi st er F a i s t e ste d .
4–108 Alpha Architecture Handboo k Notes: Except tha t it is likely in many impl emen tations to be s ubsta nti al ly faster , the instr uctio n: FCM OVxx Fa, Fb,Fc is e xact ly equivale nt t o: FByy Fa, labe l ! yy = NOT xx CPYS Fb, Fb,F c label: .
Instruc tion Desc ription s 4– 109 4.10.4 Move f rom/to Fl oating- Point Control Regis ter Format: Operat ion: CASE MF_FPCR: Fa ← FPCR MT_FPCR: FPCR ← Fav ENDCASE Excepti ons: Inst ruct ion mne .
4–1 10 Alpha Architecture Handboo k 4.10.5 V AX Floating Add Format: Operat ion: Fc ← Fav + Fbv Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Registe r F a is adde d t o registe r F b, a nd the su m is w ritte n t o regist e r Fc.
Instruc tion Descri ptions 4 – 111 4.10.6 IEEE Fl oating Add Format: Operat ion: Fc ← Fav + Fbv Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Registe r F a is adde d t o registe r F b, a nd the su m is w ritte n t o regist e r Fc.
4–1 12 Alpha Architecture Handboo k 4.10.7 V AX Floating Com pare Format: Operat ion: IF Fav SIGNED_RELATION Fb v THEN Fc ← 4000 0000 0000 0 000 16 ELSE Fc ← 0000 0000 0000 0 000 16 Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The two operands in Fa and Fb are compared.
Instruc tion Desc riptions 4– 1 13 4.10.8 IEEE Floating Compar e Format: Operat ion: IF Fav SIGNED_RELATION Fb v THEN Fc ← 4000 0000 0000 0 000 16 ELSE Fc ← 0000 0000 0000 0 000 16 Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The two operands in Fa and Fb are compared.
4–1 14 Alpha Architecture Handboo k 4.1 0 .9 Conve r t V AX Flo atin g to In te ge r Format: Operat ion: Fc ← {con version of Fbv } Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The f loating operand in register Fb is c onverted to a tw o’s-comple ment qua dword n umber a nd writte n t o regi ste r Fc .
Instruc tion Desc riptions 4– 1 15 4.10.10 Conv ert In teger to V AX Floati ng Format: Operat ion: Fc ← {con version of Fbv<63:0>} Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cr.
4–1 16 Alpha Architecture Handboo k 4.10.1 1 Convert V AX Floatin g to V AX F loating Format: Operat ion: Fc ← {con version of Fbv} Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The f loating operand in regist er Fb is co nverted to the spe cified al terna te float ing for mat and writt en to registe r Fc.
Instruc tion Desc riptions 4– 1 17 4.10.12 Conv ert IEEE Floating to Integer Format: Operat ion: Fc ← {con version of Fbv } Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The floating ope rand in regis ter Fb is conve rted to a two’s- complem e nt numbe r and written to register Fc.
4–1 18 Alpha Architecture Handboo k 4.10.13 Convert Integer to IEEE Floating Format: Operat ion: Fc ← {con version of Fbv<63:0>} Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des crip.
Instruc tion Desc riptions 4– 1 19 4.10.14 Convert IEEE S _Floating to IEE E T_Float ing Format: Operat ion: Fc ← {con version of Fbv} Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The S_floa ting op eran d in register Fb is con verte d to T_floatin g form at and writte n to registe r Fc.
4–120 Alpha Architecture Handboo k 4.10.15 Convert IEEE T_Floating to IEEE S_Floating Format: Operat ion: Fc ← {con version of Fbv} Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The T_f loating ope rand in r egister Fb is conve rted to S _floatin g form at and wr itten to registe r Fc.
Instruc tion Desc ription s 4– 121 4.10.1 6 V AX Float ing Div ide Format: Operat ion: Fc ← Fav / Fbv Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The di vidend operand i n regi ster Fa is di vided by the divis or operand i n regi ster Fb and the quotie nt is writte n to regis ter F c.
4–122 Alpha Architecture Handboo k 4.10.17 IEEE Floati ng Divide Format: Operat ion: Fc ← Fav / Fbv Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The di vidend operand i n regi ster Fa is di vided by the divis or operand i n regi ster Fb and the quotie nt is writte n to regis ter F c.
Instruc tion Desc ription s 4– 123 4.10.18 Floati ng- Point Regis ter to Integer Register Move Format: Operat ion: CASE: FTOIS: Rc<63:32> ← SEXT(Fav<63>) Rc<31:0> ← Fav<63:6.
4–124 Alpha Architecture Handboo k 4.10.19 I nteger Regist er to F loating-Point Register Move Format: Operat ion: CASE: ITOFF: Fc ← Rav<31> || MAP _F(Rav<30:23> || Rav<22:0> || .
Instruc tion Desc ription s 4– 125 ITOFS is exactly e quivale nt to the sequence : STL LDS ITOFT is exactly e quival ent t o t he se quence: STQ LDT Software Note: ITOFF , ITOFS, and ITOF T are no slower than th e corr esponding s tore/ load se quence and can be signi ficantl y fa ster.
4–126 Alpha Architecture Handboo k 4.10.2 0 V AX Float ing M ultip ly Format: Operat ion: Fc ← Fav * Fbv Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The m ult ipl ic a nd op era n d in reg ist e r Fb is m ult ipl ie d b y th e m ul tip lie r op e ran d in r eg is te r F a and the product is wr itt en to regi ster Fc.
Instruc tion Desc ription s 4– 127 4.10.21 I EEE Floati ng Mult ipl y Format: Operat ion: Fc ← Fav * Fbv Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The m ult ipl ic a nd op era n d in reg ist e r Fb is m ult ipl ie d b y th e m ul tip lie r op e ran d in r eg is te r F a and the product is wr itt en to regi ster Fc.
4–128 Alpha Architecture Handboo k 4.10.2 2 V AX Float ing Sq uare Root Format: Operat ion: Fc ← Fb * * (1/2) Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The square root of the floating-point operand in register Fb is written to register Fc.
Instruc tion Desc ription s 4– 129 4.10.23 I EEE Floati ng Squ are Root Format: Operat ion: Fc ← Fb * * (1/2) Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The square root of the floating-point operand in register Fb is written to register Fc.
4–130 Alpha Architecture Handboo k 4.10.2 4 V AX Float ing Su bt ract Format: Operat ion: Fc ← Fav - Fbv Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The subtrahend operand in regist er Fb is subtracted from the minuend operand in register Fa and the d if fere n ce is wri tten to re gister Fc .
Instruc tion Desc ription s 4– 131 4.10.25 I EEE Floati ng Sub tract Format: Operat ion: Fc ← Fav - Fbv Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The subtrahend operand in regist er Fb is subtracted from the minuend operand in register Fa and the d if fere n ce is wri tten to re gister Fc .
4–132 Alpha Architecture Handboo k 4.1 1 Misce llaneou s In structions Alpha provide s the misce lla neous instr uc ti ons shown in Tabl e 4–17. T able 4–17: Miscellaneous Instructions Summary M.
Instruc tion Desc ription s 4– 133 4.1 1 .1 A r ch itectur e Mask Format: Operat ion: Rc ← Rbv AND {NOT CPU_feature_mask} Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Rbv rep resen t s a m as k of the req u ested a rch itectu ral exte nsions .
4–134 Alpha Architecture Handboo k • On 21 164A (EV56), 21 164PC (PCA56), and 21264 ( EV6), AM ASK cor rectly indi cates suppor t for architec ture extensio ns by copyin g Rbv t o Rc and cl ear ing app ropriat e bits. Bits are a ssign ed and pla ced in Appe ndix D for archit ecture extension s as ECOs for those extensi ons are passed.
Instruc tion Desc ription s 4– 135 4.1 1 .2 C all Priv ilege d Archit ec ture Libr ary Format: Operat ion: {Stall instruction issuin g until all prior instructions are gu aranteed to complete without incurrin g exceptions.
4–136 Alpha Architecture Handboo k 4.1 1 .3 E v ic t Da ta C ac h e Block Format: Operat ion: va ← Rbv IF { va maps to memory sp ace } THEN Prepare to reuse cache r esources that are occupied b y the the addressed byte.
Instruc tion Desc ription s 4– 137 • ECB is not inte nded for fl ushing caches pr ior to powe r failure or low powe r operat ion — CFLUSH is int en ded for that purpose .
4–138 Alpha Architecture Handboo k 4. 1 1 . 4 E xc epti o n Bar rie r Format: Operat ion: {EXCB does not appear to issue until co mpletion of al l exceptions and dependenc ies on the Flo ating-point Co ntrol Register (FPCR) from pri or instruction s.
Instruc tion Desc ription s 4– 139 4.1 1.5 P ref etc h Data Format: Operat ion: va ← {Rbv } {Optionally prefetch alig ned 512-byte b lock surroundi ng va.} Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The virtual address is gi ven by Rbv.
4–140 Alpha Architecture Handboo k No exceptions are generated by FE TCH x. If a Load (or Store in the case of F ETCH_ M) that uses the same a ddress w ould fault, the pr efetch request is igno red. It is UNP RED ICT ABL E whether a TB-mis s fault is ever take n by FETCHx.
Instruc tion Desc ription s 4– 141 4.1 1 .6 Implementation V ersion Format: Operat ion: Rc ← valu e, which is defined in Appen dix D Excepti ons: Inst ruct ion mne moni cs: Des cription: A small inte ger is pla ced in R c tha t sp ec ifie s the ma jor impl eme nt at ion v ersio n of the proc e s- sor on wh ic h it is ex ec ut e d.
4–142 Alpha Architecture Handboo k 4.1 1.7 M emory Barrier Format: Operat ion: {Guarantee that all subse quent loads or stores will not access memory un til after all previous loads and stores have acc essed memory, as observed by other process ors.
Instruc tion Desc ription s 4– 143 4.1 1.8 R ead Pr ocess or Cycle Counter Format: Operat ion: Ra ← {cyc le counter} Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: Register Ra is w ritte n w ith the pro ces sor cycl e cou nter ( PCC) .
4–144 Alpha Architecture Handboo k 4.1 1.9 T rap Barrier Format: Operat ion: {TRAPB does not appear to issue until a ll prior instr uctions are guaranteed to comple te without cau sing any arith metic traps}.
Instruc tion Desc ription s 4– 145 4.1 1 .10 Write Hin t Format: Operat ion: va ← Rbv IF { va maps to memory sp ace } THEN Write UNPREDICTABLE data to the aligne d 64-byte regi on containing the addressed byte.
4–146 Alpha Architecture Handboo k Implementation No te: If the 6 4-byte region c ontain ing t he add ressed byte is not in t he data cache , implementa ti ons are encoura ged to al locate th e region in the data cach e without f irst readi ng i t from memory .
Instruc tion Desc ription s 4– 147 4.1 1.1 1 Write Memory Barri er Format: Operat ion: { Guarantee that { All preceding stores t hat access mem ory-like { regions are ordered before any sub sequent .
4–148 Alpha Architecture Handboo k The WMB instruction is t he preferred method for providing high- bandwidth write streams where orde r mus t be pres erved betwe en wr ites in that stre am.
Instruc tion Desc ription s 4– 149 4.12 V AX Comp atib ility Instr uctio ns Alph a provid es the in structi ons s hown in Tabl e 4–1 8 for us e in trans lated VAX c ode. Th ese instruc tions are not a perm a n e nt par t of the arch itecture and w ill not be availa ble in some futur e imp lemen tations .
4–150 Alpha Architecture Handboo k 4.12.1 V AX Compat ibility I nstru ctions Format: Operat ion: Ra ← intr _flag intr_flag ← 0 !RC intr_flag ← 1 !RS Excepti ons: Inst ruct ion mne moni cs: Qualifie rs: Des cription: The intr_f lag is retur ne d in Ra and then cleared to zero (RC) or set to one (RS).
Instruc tion Desc ription s 4– 151 4.1 3 Multimedia (G raph ics and V ideo) Sup port Alpha provide s the f ollowing instr uctions t hat enhance suppor t for gra phics and vide o algorit hm s: The M .
4–152 Alpha Architecture Handboo k 4.13.1 Byte and W ord Mi nimum an d Maximum Format: Operat ion: CASE MINUB8: FOR i FROM 0 TO 7 Rcv<i*8+7:i*8> = MINU (Rav<i*8+7:i*8 >,Rbv<i*8+7:i* 8.
Instruc tion Desc ription s 4– 153 Inst ruct ion mne moni cs: Qualifie rs: Des cription: For MINxB8, each b yte of Rc is wr itten wi th the s m a ller of t he co rresponding byte s of Ra or Rb. The bytes may be interpre te d as signed or unsigne d val ues .
4–154 Alpha Architecture Handboo k 4.13.2 Pixel Error Format: Operat ion: temp = 0 FOR i FROM 0 TO 7 IF { Rav<i*8+7:i*8> GEU Rbv<i*8+7:i*8> } THEN temp ← temp + (Rav<i* 8+7:i*8> .
Instruc tion Desc ription s 4– 155 4.1 3 .3 Pac k By te s Format: Operat ion: CASE PKLB: BEGIN Rc<07:00> ← Rbv<07:00> Rc<15:08> ← Rbv<39:32> Rc<63:16> ← 0 END PKW.
4–156 Alpha Architecture Handboo k 4.13.4 Unp ack Bytes Format: Operat ion: temp = 0 CASE UNPKBL: BEGIN temp<07:00> = Rbv<07:00 > temp<39:32> = Rbv<15:08 > END UNPKBW: BEGIN .
System Archi tect ur e and Programming Implicati ons 5–1 Chapter 5 System Ar chitectur e an d Pr ogramming Implic ati ons 5.1 I ntr oduc tio n Portions of the Alpha archi tecture have implication s for programming, and the system struc- ture, of both uniprocessor and m ultiprocessor implem entations.
5–2 Alpha Architecture Handb ook Memory coherency may be provided i n different ways for eac h of the four physical address regions. Possi ble pe r-re gion pol ic ies in clude, but a re not re stric.
System Archi tect ur e and Programming Implicati ons 5–3 For a byt e a ccess re gion, a ccesse s to physical memor y must be im plemente d such that i ndepen- dent acc esses to adjac ent bytes or adja cent aligne d wo rds prod uce the same re sult s, regardle ss of t he or der of e xecuti on.
5–4 Alpha Architecture Handb ook • Address r anges may overlap , such that a write to one lo catio n changes the bits r ead from a dif fere nt loc ation.
System Archi tect ur e and Programming Implicati ons 5–5 The follo wing requirements must be met by all cache/write-b uffer imp lementations. All pro- cessor s must provid e a coherent vie w of memory. • W rite buffer s m ay b e used to de lay a nd agg re gate w r ites.
5–6 Alpha Architecture Handb ook 5.5 Da t a Sh a ri ng In a multiprocessor environme nt, writes to shared data must b e synchronized by the prog ram mer. 5.5.1 Atom ic C hange of a Si ngle Datum The ordina ry STL an d STQ instru cti ons can be used to perfo rm an ato mic cha nge of a s hared alig ned long word or q uadword.
System Archi tect ur e and Programming Implicati ons 5–7 This load-locked/stor e-conditional paradigm may be used whe n e ver an atomic upda te of a share d ali gned qua dword is desired, inc luding getti ng t he e ffect o f atomi c byte wri tes. 5.
5–8 Alpha Architecture Handb ook • Both conditi onal branc hes are for ward branches, so they are prope rly predicte d not to be taken (to matc h the common case of no contention for the lock).
System Archi tect ur e and Programming Implicati ons 5–9 5.5.4 Ordering Considerations for Shared Data S tructures A crit ical sec tion se quenc e, s uch as s hown in Se ction 5.5.3, is conc eptually only three steps: 1. Acquire s oftware l oc k 2. Cr iti cal se ct ion — read/wri te sha red da ta 3.
5–10 Alpha Architecture Handbo ok an ADDL2 to updat e a va ri able that is shared between a "MAIN" routine and an AST routi ne, i f runn ing on a single pr oces sor. In t he Alpha archit ecture , a progr ammer m ust deal with AST shared da ta by using multi pro cessor shared da ta sequences.
System Archi tectu re and Progra mming Impli catio ns 5– 11 In most systems, DMA I/O devices or other agents can read or write shared memory locations.
5–12 Alpha Architecture Handbo ok there is at least one byte that is acc essed by both, tha t is, if max(x,y) < min( x+m,y+n) . 5.6.1.1 Architectural Definition of Proces sor Issue Sequence The i.
System Archi tectu re and Prog ramming I mplicatio ns 5–13 Wher e "over l a p" den otes the condit ion m ax( x,y) < min(x+m ,y+n). For t wo ac cesses u and v issued by pr oc esso r Pi, if u precedes v by pr oc essor issue c onstra int, then u pre cedes v i n BE FORE or der.
5–14 Alpha Architecture Handbo ok 5.6.1.4 Definition of Location Access Constraint s Location acc ess constraints a re imposed on ove rlapping read/write ac cesses.
System Archi tectu re and Prog ramming I mplicatio ns 5–15 and acce sses byt e z; th en the valu e of byt e z read by v is e xactly t he value writt en by u .
5–16 Alpha Architecture Handbo ok Repre senting those cod e sequenc es in the style of the litmus tests in Sectio n 5.6.2, it is impos- sible for t he foll owing sequence t o result: Analysis: Given.
System Archi tectu re and Prog ramming I mplicatio ns 5–17 5.6.1.9 Tim eliness Even in the absence of a ba rrier after the write, no write by a processor may be delayed indefi- nite ly in t he BEFORE or der ing.
5–18 Alpha Architecture Handbo ok 5.6.2.2 Litmus T est 2 ( Impossible Sequence) Init ially, l ocati on x contains 1: Analysis: Thus, once pr ocessor Pj reads a new value writ ten by U1, any other writes that must p recede the read must also precede U1.
System Archi tectu re and Prog ramming I mplicatio ns 5–19 5.6.2.4 Litmus T est 4 ( Sequence Okay) Init ially, l ocati ons x and y c ont ai n 1: Analysis: There are no c onfli cts i n t he se quence. Ther e are no violatio ns o f the defini tion of B EFORE.
5–20 Alpha Architecture Handbo ok There is V2 ⇐ U1 ⇐ U2 ⇐ U3 ⇐ V 1. There are no conflicts in this sequence. There are no viola tions of the de finit ion of B EFORE.
System Archi tectu re and Prog ramming I mplicatio ns 5–21 5.6.2.9 Litmus T est 9 ( Impossible Sequence) Init ially, l ocati on x contains 1: Analysis: Both <1> and <2> cannot be true . Tim e cannot go backwards. If V3 reads 2, then U3 must r ead 2.
5–22 Alpha Architecture Handbo ok 5.6 .3 Im p li ed B a rr i er s Ther e are no impl ied barriers in Alp ha . If an implie d bar rier is neede d for func tion all y co rrect access to s hared data, it must b e wri tten as an explicit instru ction. ( Software m ust explicitly incl ude a ny n eeded MB, WMB, or CALL_PAL I MB ins tructions.
System Archi tectu re and Prog ramming I mplicatio ns 5–23 is c ommunica ted t hrough j ust one l ocati on in m emory, memory barrie rs are not ne cessary. Software Note: Note t hat thi s se ction does not describ e how to re liabl y communic ate d ata from a pro cessor to a DMA de vice .
5–24 Alpha Architecture Handbo ok This impli es that after a DMA I/O d evice ha s writ ten so me I-st ream to memory (su ch as pag- ing in a page from disk), the DMA device m ust logica lly execute .
System Archi tectu re and Prog ramming I mplicatio ns 5–25 MB [1] e nsure s that t he wri tes done to sa ve the state of t he curre nt proc ess happe n bef ore the owners hip is passe d.
5–26 Alpha Architecture Handbo ok 5.6.4.6 Mu lt i processor Se nd/Rece ive Interr upt If one p rocessor w rites some shared dat a, th en send s an interrupt to a se cond p rocesso r, and that pr ocess or re ceives the inte r rupt, then acc es ses the share d data , the seque nc e from S ectio n 5.
System Archi tectu re and Prog ramming I mplicatio ns 5–27 Leav ing out th e MB at the begi nning of th e interru pt-r eceipt ro utine causes t he code to fail if an old value of th e context remai ns in the second pro cessor’s cache, and inval idates f rom the writes done on the first pr ocessor are not delive red soon enough.
5–28 Alpha Architecture Handbo ok will detect the w rite s of the shared data be fore detecting the flag write, i nterr upt, or device reg- iste r write.
System Archi tectu re and Prog ramming I mplicatio ns 5–29 The MB on the first processor guarantees tha t t he write to CSR_A precede s the wr ite to flag in memory, as p erceived o n other proc essors. (T he MB does not guaran tee t hat the write t o CSR_ A ha s com pl eted.
5–30 Alpha Architecture Handbo ok 5.7 Arithmetic T raps Alpha impleme ntations are allowed to execute multiple instructions concurrently and to for- ward results from one instruc tion to another.
Common PALco de Ar chitect ure 6–1 Chapter 6 Common P ALcode Ar chitectur e 6.1 P ALc ode In a fam ily of m ach ines, both users an d operat ing s ystem d evelope rs re quire function s to b e implem en ted con siste ntly.
6–2 Alpha Architecture Handb ook The Alpha architecture lets t hese functions be implemented in standard machine code t hat is resident in main m emory. PALco de is written in standa rd machine cod e with some impleme n- tation-specific extensions to provide access to low-level hardware.
Common PALco de Ar chitect ure 6–3 • P A Lco de nee d s a hardw are m echa nism to tr ansi tion the mac hine f rom t he P ALcode environm ent to the non-P ALcode envir onment. This mech anism loads the PC, enable s inte rrupt s, e nabl es mapping, and disa ble s P ALcode pri vile ges.
6–4 Alpha Architecture Handb ook PAL c ode s hou ld b e writt en mod ula rly to f ac ilit at e the e a sy re pl ac em e nt or cond iti ona l b uil d- ing of each component. Such a prac tice simplifies the int egration of CPU hardware, system plat form hardware , c onsole fi rmware, oper ating syste m softwa re, and compi lers.
Common PALco de Ar chitect ure 6–5 The PALc od e ins tru ctions liste d in Ta bl e 6– 2 and des cribe d in the follow ing se ctions m us t be suppor ted by all Alpha impl ement ations: T able 6–.
6–6 Alpha Architecture Handb ook 6. 7.1 Dr ai n A b or ts Format: Operat ion: IF PS<literal>(<)CM> NE 0 THEN {privileged instructio n exception} {Stall instruction issuin g until all pr ior instructions are guarant eed to complet e without incurring aborts .
Common PALco de Ar chitect ure 6–7 6.7.2 Halt Format: Operat ion: IF PS<literal>(<)CM> NE 0 THEN {privileged instruct ion exception} CASE {halt_action} OF ! Operating System or Platform .
6–8 Alpha Architecture Handb ook 6.7.3 Instructi on Memory Barrier Format: Operat ion: {Make instruction stream coherent with data stream} Excepti ons: Inst ruct ion mne moni cs: Des cription: An IM.
Console S ubsys tem Overview 7–1 Chapter 7 Cons ole S ubs ys tem Ov erview On an Alpha sys te m, underlying contr ol of the sys tem platform hardware is provided by a con- sole subs ystem . The console subsyst em: • Init ializ es, test s, and pr epares the system plat form hardwar e for Alpha system soft ware.
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Chapter 8 Inpu t/Ou tp ut Ov erv iew Concept ually, Alpha s ystems can consis t of processo rs, memory, a pro cessor-memory int er- connec t (PMI), I/O buses, bri dge s, and I/O devices .
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9–1 Chapter 9 Open VMS Alph a The fo llowin g sec tions s pe cify th e Pr ivileged A rchitect ure L ibrar y (PAL code) instruct ions, that ar e requir ed t o su pport a n OpenVMS Alpha system.
9–2 Al pha Architecture Handbook CHME Change mode to e xec utiv e The CHME instruct ion allows a proc ess to change its mode in a contr olled manner. A cha nge in mode a lso r esults in a ch ange of stac k pointe rs: th e old pointe r is sa ved, the new poi nter i s loaded .
9–3 IMB I-S tream m em ory b arri er IMB ensur es tha t t he conte nts of a n instr uction cache are c oherent after the instr uction str e am has b een modif ied b y softwa re or I/O d evices.
9–4 Al pha Architecture Handbook INSQTILR Inse r t into longwo r d queue at tail, interl ocked reside nt The entry speci fied in R17 is inserte d in to the self-rela tive queu e preceding the hea der s pecified i n R 16. The inserti on is a nonint er ruptibl e operation .
9–5 RD_PS Read processo r status RD_PS writes the Processor Status ( PS) to registe r R0. READ_UNQ Read unique con text READ_UNQ reads the hardwar e process (thr ead) unique cont ext value, if previous ly writte n by WRITE_UNQ, and places tha t va lue in R 0.
9–6 Al pha Architecture Handbook REMQHIQR Remove f rom quadwor d queue a t header, int erlo cked resident The queue entr y f oll owing t he h eade r, poi nted to by R1 6, i s remove d f rom the self-re la tive qu eue a nd the a ddr ess of th e remo ved e ntry is ret urned in R 1 .
9–7 REMQUEL Remove from longword que ue The queue entr y addr essed by R16 for REMQUEL or the entr y addressed by the longword add ressed by R16 for REMQUEL/D is r emoved from the long- word absol ute queue, and t he address of the removed e ntry is retu rned i n R1.
9–8 Al pha Architecture Handbook 9.2 Priv ile ge d Op en VMS Alpha Pal c ode The privile ged PALcode instr uctions can be ca lle d in kernel mode only.
9–9 STQP Store quadword physical The quadword conte nt s of R17 are writt en to the memory loca tion who se phys- ical a ddres s is in R 16. If the ope rand a ddres s in R 16 i s not quadword- aligne d, the re sult is UNPREDICTABLE.
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10–1 Chap ter 10 Digital UNIX The foll owing s ection s speci fiy the P rivileg ed A rchitect ure L ibrary (P ALcod e) i nstruc tions t hat ar e requir ed t o su pport a Digital UNIX sys te m. 10.1 U npriv ileg ed Digital UNIX P ALcode Table 10–1 des cribes the unpri vilege d Digita l UNIX PALcode instructi ons.
10–2 A lpha A rchitectu re Handbook 10.2 Privileged Digital UNIX P ALcode The p ri vilege d PA Lc od e inst ru ctions can be call ed onl y fro m kern e l mode . Th e y prov ide an in te r face to control the privile ge d state of the machine. Table 10–2 des cribes the pri vilege d Digita l UNIX PALcode instruc tio ns.
10–3 retsys Return fr om system c all The r etsys inst ructi on p ops t he r etur n a ddres s, the u se r stack point er, and the user global point er from the ker nel stack. It then saves the kerne l st ack poi nter, s ets mod e to use r, enables inter rupts, and ju mps to the addre ss p opped of f t he st ack.
10–4 A lpha A rchitectu re Handbook wrval Write system value The wrval instr ucti on writes a 64-bi t p er-proc e ssor value. wrvptp tr Wr ite vir tual page t able pointe r The wrvptptr ins tr uction writ e s a pointe r to the virt ual pa ge t able poin ter ( vptptr) .
1 1–1 Chap ter 1 1 W indows NT Alpha The followi ng sec tions spe cify the Privi leged Archite cture Library (PALcode ) inst ructi ons that are requir ed t o su pport a Windows NT Alp ha syst em.
11 – 2 A lpha Ar chitecture Han dbook 1 1.2 Privileged W indows NT Alpha P ALco de The privi leged PALcode instuc tion s pro vide suppo rt for syst em operat ions and may be called fr om only kerne l mode.
1 1–3 draina Dra in all aborts includ ing machine che cks The dra ina inst r uction dra ins all abort s, inc ludin g machine c hecks, f rom the curr ent pr ocessor. Draina guar antees t hat no a bort is s ignale d for a n ins truct ion issue d befo re th e draina whil e any instruction issu e d subse quent t o the dr aina is execut ing.
11 – 4 A lpha Ar chitecture Han dbook rdirq l Re ad the cu rre n t IR QL from the PS R The rdir ql inst ruction retur ns the c ontents of the interrupt reque st level (IRQL) field of the PSR internal pr ocesso r regi ste r .
1 1–5 retsys Return fr om syste m ser vice call e xce ption The re tsys inst ruction r etur ns from a sy stem service c all e xception by unwind- ing the t rap fr ame and ret urning t o the c ode st ream that wa s e xecut ing w hen t he origi nal exce pti on was initi ated.
tbia Tra nslatio n bu ffer invali dat e all The tbia inst r u ction inva lidates a ll tra nslatio ns and virt ual cache blocks wit hin the process or . tbim Translatio n bu ffer invali dat e multipl e The tb im instr uction invalid a tes multiple vir tu al tr anslations f or the cu rrent ASN.
A–1 Ap pe ndi x A Soft war e Considerat ions A.1 Ha r dwar e-So ft war e C ompa ct The Alpha architectur e, like all RISC architec tures, depends on careful atten tion to data align- ment a nd inst ruction s c heduling to achieve hi gh perf ormance.
A–2 Alpha Architecture Handboo k In s ome cases, ther e are performanc e advanta ges to aligning instr uctions or da ta to cache-bloc k boundaries, or putting data whose use is correlated into the s.
Software Conside rat ions A–3 branch - taken s. If the infreq uen t ca se is rare (5%), put it far e nough away th at it never com es i nto the I-cach e . If t he in freq uen t ca se i s ext remel y r are (er ror m ess age code), put i t on a pa ge of r arely execute d code an d expe ct t hat pa ge neve r to be paged in.
A–4 Alpha Architecture Handboo k quickly as possible, second priority to predicting conditional branc hes based on the sign of th e displacement field (backw ard taken, forward not-taken), and third priority to predicting sub- routine return a ddresses by run ning a sma ll prediction stac k.
Software Conside rat ions A–5 aligne d octaword bound aries whe never langua ge rules allow . In some im plement ations, a seri es of wri tes th at complet ely f ill a cach e bl ock may be a factor of 10 fas ter t han a seri es of writes that partiall y fill a cache blo ck, when that cache blo ck would give a read miss.
A–6 Alpha Architecture Handboo k data in the same cache block as the lock. For the high-sharing case, compilers should assume that almost all accesses to shared data result in ca che mi sses al l the w ay b ack t o ma in m emo ry, for ea ch distinc t cach e block us ed.
Software Conside rat ions A–7 In a fr eque nt ly e xe cute d l oop , co m piler s c oul d a lloca te the data ite ms acc esse d f r om m e mor y so that, on each loop iteratio n, all of the memory addresses accessed are either in exactly t he same aligned 64-byte block or di ffer in bits VA<1 0:6>.
A–8 Alpha Architecture Handboo k ti on addres ses di ffer , and if t hey do not, inser ting up to 8K by tes of p addin g betw ee n the arrays . This rul e will avoi d thrashi ng in di rect-mapped TBs and in some large di rect-mapped data c aches wit h t otal s izes of 32 page s (256 KB) or m ore.
Software Conside rat ions A–9 A.4 Cod e Se quen ces The following se ction desc ribes c ode s equence s. A.4.1 A lign e d Byte/W ord (Within Register) Mem ory A ccesses The i nstruct ion sequences give n in Secti on 4.6 f or b yte-wit hin-regist er acces ses are w orst-ca se code.
A–10 Al pha Architecture Handbook Note: The shi fts of ten c an be combine d with s hifts t hat migh t surround sub se quent arithmetic opera tions (for example , to produce word overflow from the high end of a regist er). In the common case, the inte nded sequ ence for load ing and zero-exte nding a byte is: LDL R1, D.
Softwa re Conside rati ons A–1 1 16-bit quoti ent digit pl us a 48-bit new partia l divi dend. Three more such steps can ge nerate the full quot ient.
A–12 Al pha Architecture Handbook The standa rd NOP forms are: NOP == BIS R31 ,R31 ,R31 FNOP == CPY S F31 ,F31 ,F31 These ge nerate no exceptions. In most im plementations, t hey shoul d enc ounter no ope rand issue delays and no destina tion issue delay.
Softwa re Conside rati ons A–13 The ge n eral se q uen ce i s: LDA Rd st, low( R31) LDAH Rdst, extr a(Rd st) ! O mit if extra =0 LDAH Rd st, high (Rds t) ! Omit if h igh= 0 A.
A–14 Al pha Architecture Handbook A.4.5 Ex c eptions and T rap Barriers The EXCB ins truction allows sof tware t o guarante e that in a pipelined i mplementation, all pr e- vious inst r uctions ha ve comple ted any be havior that i s rel ated to e xcepti ons or rounding m odes befo re any instr uctions af ter the EXCB are iss ued.
Softwa re Conside rati ons A–15 FNEG Fx, Fy No-except ion ge neric fl oatin g nega tio n CPYS N Fx, Fx, Fy FNOP Flo at ing-point no-op CPYS F31, F3 1, F31 MOV Lit , Rx Move 16-bit s ign-ext ende d l.
A–16 Al pha Architecture Handbook A.5 T iming Considera tion s: Atomic Seque nces A suff iciently lo ng instr uction se que nce b etween LD x_L and S Tx_C will n ever comple te, becaus e periodic timer inter r upts will always occur before the sequence complete s.
B–1 Ap pendix B IEEE Fl oating-Point Conformance A subse t of I EEE Sta ndar d for B inar y Floa ting- Poi nt Arithm etic ( ANSI/ IEEE S tandar d 754-1985) is pr ovided in the Alpha floating-point instr uctions. This appendix describes how to const ruct a complet e IEEE implementa ti on.
B–2 A lpha A rchitecture Handbook Overf low and un de r flow, N aN s, a nd in fi nities en count er ed du ring so ft war e b inar y to d ec ima l conver sion ret urn strings tha t specif y the condition s. Alpha hardware support s comparisons of same-format numbers.
IEEE Floa ti ng-Poi nt Confor mance B–3 In the Alph a archi tec tu re, use r si gnal ha ndle rs are supp or ted by c ompile r s and a n OS com ple - tion handler (interposed between th e hardware a nd the IEEE user), as described in the next section .
B–4 A lpha A rchitecture Handbook these bits ma y choose to com plete comp utatio ns involving non-finite values witho ut the assis- tance of software completion.
IEEE Floa ti ng-Poi nt Confor mance B–5 • Intege r overfl ow (IOV) exceptions are control led by the INVE enable mask bit (FP_C<1>) , as allowe d by the IEEE st andard.
B–6 A lpha A rchitecture Handbook B.3 Mapping to IEEE S tandard There are five IEEE exce ptions, each of which can be "I EEE soft ware tr ap-en abled" or dis- able d (the de f ault c o ndi tio n) . Im ple me nt ing the IEE E s of tw are tr ap- e nabl e d mod e is o ptio na l in th e IEEE st a ndard.
IEEE Floa ti ng-Poi nt Confor mance B–7 Figure B–2: IEEE Trap Handling Behavior The IE EE - spec if ie d tr ap be ha v ior o ccu rs on ly wi th r esp ect t o th e use r si gna l h a nd le r (th e last laye r in F ig ur e B–2) ; a ny tr ap- a nd-f ixu p be h av ior in the f irst th ree laye r s is out sid e t he sc op e of the IEEE standa rd.
B–8 A lpha A rchitecture Handbook T able B–2: IEEE Floating-Point T rap Handling Alp ha In st ru ct io n s Hardware 1 PA L - Code OS Comp letio n Handle r User Signal Handler FBEQ FBNE FBLT FBLE F.
IEEE Floa ti ng-Poi nt Confor mance B–9 MULx OUTP UT Exc e pt io ns: Expone nt ov e rflow Trap Trap Supply +/– Inf +/– MA X [Overflow 3 ] Scale by bias adj us t Expone nt underflow and di sabl e.
B–10 Alpha Architecture Hand book CMP T L T CMP TLE INPUT Excepti ons: Denormal op erand Trap T rap Supp ly ≤ or < [Denormal Op 2 ] QNaN operand Trap T rap Supply Fal se [Inva li d Op] SNa N op.
IEEE Floa ting -Point Confor mance B–1 1 Other IEEE operati ons (softw are subroutines or seq uences of ins tructions) are l isted here for co m pl e te ne s s: Rema ind er Round float t o inte ger .
B–12 Alpha Architecture Hand book Table B–3 show s the I EEE stan dard charts. I n the cha rts, the se cond colum n is the result when the use r signa l handle r is di sabled ; the third col um n is the resul t whe n that ha ndle r is enabled. The OS completi on handler sup plies the IEEE defau lt that i s specifi ed in t he second column.
C–1 Ap pe ndi x C Instruction Summary This appendix summarizes all instructions and o pcodes in the Alpha architecture. All values are in hexad ecimal rad ix. C.1 C om mo n Archit ecture Instructi on Sum mary This se c tio n sum m ariz es a ll c om mo n A lph a in str uc tio ns.
C–2 Alpha Architecture Handboo k T able C–2: Common Architectu r e Inst ructi ons Mnemonic Format Opcode Descri ption ADDF F-P 15.080 Add F_float ing ADDG F-P 15.0A0 Add G_floating ADDL Opr 10. 00 Add longword ADDL/V 10.40 ADDQ Opr 10. 20 Add quadword ADDQ/V 10.
Instruc ti on Summary C–3 CVTGQ F -P 15.0AF C onvert G_f loati ng t o q uadword CVTLQ F -P 17.010 Conve rt l ongword t o qu adword CVTQF F -P 15. 0 BC Convert quadword to F_floa ti ng CVTQG F -P 15. 0 BE Convert quadword to G_floa ting CVTQL F-P 17.
C–4 Alpha Architecture Handboo k LDA Mem 08 Load add ress LDAH Mem 09 Load add ress high LDBU Mem 0A Load zero- extend ed byte LDWU M em 0C Loa d zero- ext ended word LDF Mem 20 Load F_floati ng LDG.
Instruc ti on Summary C–5 S8SUBQ Opr 10. 3B Scaled subtra ct quadword by 8 SEXTB Opr 1C.00 Sign extend byte SEXTW Opr 1C .01 Sign exte nd word SLL Opr 12. 39 Shift left logic al SQRTF F-P 14.08A Square roo t F_floa tin g SQRTG F -P 14.0AA Square roo t G_fl oating SQRTS F-P 14.
C–6 Alpha Architecture Handboo k C.2 IEEE Floating -Point Inst ructions Table C–3 l ists the he xadecimal value of t he 11-bit function code f ield for t he IEEE float - ing-point instructions, with and without qualifiers. The opcode for t he following instructions is 16 16 , except for SQRTS and SQRTT, which are opcode 14 16 .
Instruc ti on Summary C–7 Programming Note: To use CMPTxx with software comple tion trap handling, specify the /SU IEEE trap mode, even though an under flow trap is not possi ble. To use CVTQS or CVTQT with software complet ion trap handling, specif y t he /SUI IEEE tr ap mode, eve n though a n und erflow t rap is not possibl e.
C–8 Alpha Architecture Handboo k C.4 In depe ndent Flo atin g-Po int Instru ctions Tab le C –5 lis ts th e hex a dec i m a l v a lu e of t he 1 1- b it f un c tio n c od e fie ld f or t he fl oa ti ng - po in t instructions that are not directly tied to IEEE or VAX floating point.
Instruc ti on Summary C–9 The ins truct ion format is liste d un der the i nstr ucti on symbol . Th e sym bols i n Table C–6 ar e explaine d in Table C–7.
C–10 Al pha Architecture Handbook C.6 C om mo n Archit ecture Opco de s in Nu mer ic al Ord er T able C–8: Common Architecture Opcodes in Numer ica l Order Opcod e Opcode Opcode 00 CALL_PAL 11.26 C MOVNE 14.014 IT OFF 01 OPC01 11.28 ORNOT 14.024 ITOFT 02 OPC02 11.
Instruc tion Summary C–1 1 14.78 B SQRT S/SUI 15.12F CVTGQ/VC 15.521 SUBG/SUC 14.7AB SQRTT/S UI 15.180 ADDF/U 15. 522 MULG/SUC 14.7C B SQRTS/SUID 15.181 SUBF/U 15.523 DIVG/SUC 14.7E B SQRTT/ SUID 15.182 MUL F/U 15.52C CVTGF/SUC 15.00 0 ADDF/C 15.183 DIVF/U 15.
C–12 Al pha Architecture Handbook 16.0A0 ADDT 16.182 MUL S/U 16.5A3 DIVT/SU 16.0A1 SU BT 16.183 DIVS/U 16.5A4 CMPTUN/SU 16.0A2 MUL T 16.1A0 ADDT/U 16.5A5 CMPTEQ/SU 16.0A3 DIVT 16.1A1 SUBT/U 16.5A6 CMPTLT/ SU 16.0A4 CMPT UN 16.1A2 MULT/U 16. 5A7 CMPTLE/ SU 16.
Instruc tion Summary C–13 16.7A0 ADDT/SUI 18. 4000 MB 1F PAL1F 16.7A1 SUBT/SUI 18.4400 WMB 20 LDF 16.7A2 MULT/SUI 18.8000 FETCH 21 L DG 16.7A3 DIVT/SUI 18.A000 FE TCH_M 22 LDS 16.7AC CVTTS/S UI 18.C000 RPCC 23 LDT 16.7AF CVTTQ/S VI 18.E000 RC 24 STF 16.
C–14 Al pha Architecture Handbook C.7 OpenVMS Alpha P ALcode Instru ction Su mma ry T able C–9: O penVMS Al pha Unprivilege d P ALcode In st ruct i on s Mnemonic Opc ode Description AMOVRM 00.00A1 Atomic m ove fr om r egister to memory AMOVRR 00.00A0 Atomic m ove f rom r egiste r to reg ister BPT 00.
Instruc tion Summary C–15 T able C–10: O p enVMS Alpha Privileged P ALcode Instructions Mnemonic Opcode Descrip tion CFLUSH 00. 0001 Cache flush CSERVE 00. 0009 Console servi ce DRAINA 00.0002 Dra in a borts HALT 00.0000 Ha lt processor LDQP 00.0003 Load quadword physic al MFPR_ASN 00.
C–16 Al pha Architecture Handbook C.8 DIGIT AL UNIX P ALcod e Instru ction Summar y T able C–1 1: DIGIT AL UNI X Unprivileged P AL code Inst ructions Mnemonic Opcode Descrip tion bpt 00.0080 Breakpoint t rap bugchk 00.0081 Bugc heck callsys 00.0083 Syste m cal l clrf en 00.
Instruc tion Summary C–17 C.9 W indows NT Alpha Instruction Summary T able C–13: Wi ndows NT Alpha Unprivileged P ALcode Instructions Mnemonic Opcode Descrip tion bpt 00.0080 Breakpoint t rap callkd 00. 00AD Call k ernel debugge r callsys 00.0083 Cal l syste m se rvic e gentra p 00.
C–18 Al pha Architecture Handbook C.10 P ALcod e Op code s in Numer ical Order Opcod es 00.003 816 throug h 00.0 03F16 are rese rved fo r processor imple mentat ion-sp ecific PALcode inst ructions. Al l o ther opcodes are reserv ed fo r use by Com p aq.
Instruc tion Summary C–19 00.0032 00.0 050 — r d val wrperfmon 00.0033 00.0 051 — tbi — 00.0034 00.0 052 — wr ent — 00.0035 00.0 053 — swpipl — 00.0036 00.0 054 — r d ps — 00.0037 00.0 055 — wr k gp initpc r 00.0038 00.0 056 — wr u sp — 00.
C–20 Al pha Architecture Handbook C.1 1 Requ i r e d P ALcod e Opco des The opcode s li sted in Table C–16 are requir ed fo r all Alpha imple menta tion s. The notati on used is o o.ffff, where oo is the hexad ecimal 6-bit op code and ffff is the hexa decimal 26-bit functio n code.
Instruc tion Summary C–21 C.13 Opco des Rese rve d to Co mpaq The opcodes li sted i n Tabl e C–18 ar e reser ved t o C ompaq. Programming Note: The code point s 18.4800 a nd 1 8.4C00 ar e reserved f or a dding weake r memory ba rrier instr uctions .
C–22 Al pha Architecture Handbook C.15 ASCII Ch aracte r Set Table C–19 show s the 7-bit AS C II cha rac te r set and the c orre spo nding he xa decima l va lue f or each cha rac ter.
D–1 Ap pe ndi x D Registered S ystem and Pr oce ssor Identifiers This appe ndi x con tain s a ta bl e of the proce ss or ty pe a ssignm ent s, PALc ode impl e menta ti on informa tion, and the architec ture mask (AMA SK) and im plemen tation value (IMP LVER ) assi gnments.
D–2 Alpha Architecture Handboo k For OpenVMS Alpha and DIGITAL UNIX, the processor types are stor ed in the P er-CPU Slot Table (SLOT[ 176]), pointe d to by HWRPB[160]. D.2 P ALcode V ariation Assign ments The PALcode va ria tion a ssig nments are as follows: 5 = EV5 (2116 4) 0 = Reserve d (Pass 1) 1 = Pass 2, 2.
Registe red System and Proce ssor Identi fi ers D–3 D.3 A rchitectu re M ask and Im plem en tatio n V alues The following bi ts are de fined f or the AMASK instr uctio n.
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E–1 Ap pendix E W aivers and Im p leme ntat ion- Dep ende nt Functionality This a ppe nd ix d es crib es wa iver s to t he Alp ha arc hit ectu re a nd fun ction al ity th at is spec if ic to partic ular har dware implemen tations. E.1 W a ivers The following wa ivers ha ve b een passed for t he Alpha a rchitec ture.
E–2 Alpha Architecture Handboo k The DECch ip 21064, DEC chip 21066, and D ECchip 21 068 implem entations differ from the abo ve sp eci fic at ion in han dli ng the Ine xact condi ti on for t he IEEE DI VS and DIVT in struc- tions in two ways: 1.
Waivers and I mple mentation-De penden t Functio na lity E–3 The DEC c hip 2126 4 varies from that description, with regard to the WH64 instruc tion, as foll ows: If any oth er memory acces s (ECB, .
E–4 Alpha Architecture Handboo k The perfo rmance monitor functi ons, descr ibed in Section E.2 .1.2, can provide the fol lowing, depending on imple mentation: • Enable the performance counters to interrupt and trap into the perfor mance monitoring vector i n t he oper ating system.
Waivers and I mple mentation-De penden t Functio na lity E–5 E.2.1.2 Functions and Arguments for the DECchip 21064/21066/21068 The functions execute on a single (the current running) processor only and are described in Table E–1.
E–6 Alpha Architecture Handboo k Windows NT Alpha Input : a0 = 0 Select c ounter 0 a0 = 1 Select counte r 1 a1 = 0 Dis abl e select ed counte r Select desired eve nts ( mux_ctl) DIGITAL UNI X Input .
Waivers and I mple mentation-De penden t Functio na lity E–7 OpenVMS Al pha Input : R16 = 3 Function code R17 = opt F un cti on argument opt is: <0> = log a l l pro cesse s if set <1> = .
E–8 Alpha Architecture Handboo k 11:8 PCMUX0 Event select ion, counter 0: 3 PC0 Frequenc y setting, counte r 0: 0 PC1 Frequenc y setting, counte r 1: T able E–2: DE Cchip 210 64/21066/21068 MUX Co.
Waivers and I mple mentation-De penden t Functio na lity E–9 E.2.2 DECch ip 21 164/ 21 164PC Performance Moni torin g Unless othe rwise state d, the term "21164 " in this section m eans im plem entations of the 21164 at all fre quenci es .
E–10 Al pha Architecture Handbook For the Windows NT Alpha Opera ting System When a cou nter ove rflows and inter rup t enabling cond itions are corre ct, the counter cau ses an interru pt to PALco de. The PALcode builds a frame on the kernel stack and dispatches to the kerne l at the inter rup t entry point .
Waivers and I mplementat ion-De pendent F unctiona lity E–1 1 T able E–3: Bit Summary of PMCTR R egister for W ind ows NT Alpha Bits N am e Meaning 63–48 CTR0 Counter 0 value 47–32 CTR1 Counte.
E–12 Al pha Architecture Handbook E.2.2.3 OpenVMS Alpha and DIGIT AL UNIX Functions and Argument s The func tio ns execute only on a single (the cur rent runn ing) proc essor and ar e describe d in Table E–4.
Waivers and I mplementat ion-De pendent F unctiona lity E–13 Enable perform an ce monitor ing; start the counter s from zer o DIGITAL UNIX Input : a0 = 7 Function code value a1 = arg Argument from T.
E–14 Al pha Architecture Handbook Select Processor Mode options DIGITAL UNIX Input : a0 = 3 Function code value a1 = arg Argument from Table E–9 Output: v0 = 1 Success v0 = 0 Failur e (not generat.
Waivers and I mplementat ion-De pendent F unctiona lity E–15 Write the c ount ers DIGITAL UNIX Input : a0 = 6 Function code value a1 = arg Argument from Table E–12 Output: v0 = 1 Success v0 = 0 Fa.
E–16 Al pha Architecture Handbook T able E–7: 21 164 Select Desired E vents for OpenVMS Alp ha and DI GIT AL UNIX Bits N ame Meaning 63:32 M BZ 31 P CSEL0 Counter 0 se lect ion: 30:25 M BZ 24:22 CBOX2 CBOX2 event se lec tion (onl y has mean ing when event sele ction fie ld PCSEL2 is value <15>; otherwise MBZ).
Waivers and I mplementat ion-De pendent F unctiona lity E–17 Setting an y of the "NOT" bits causes the counters to not count when the process or is running in the specified m ode.
E–18 Al pha Architecture Handbook T able E–10: 21 164/21 164PC Select Des ir ed Frequencies for OpenVMS Alp ha and DIGIT AL UNIX Table E–10 c ontains the selecti on definitions f or e ach of the t hree count ers.
Waivers and I mplementat ion-De pendent F unctiona lity E–19 T able E–1 1: 21 164/21 164PC Read Counters for OpenVMS Al pha and DIGIT AL UNIX Bits Meani ng When Re turned 63:48 C ounter 0 retur ne.
E–20 Al pha Architecture Handbook 9 Integer ope rate instr uc tio ns 10 Floating point operate inst r uctions 11 Load in struc tions 12 Store instruc ti ons 13 Instruc tion cache access 14 D a ta ca che acc ess 15 For the 21164, use CBOX1 event selection in Tab le E–15.
Waivers and I mplementat ion-De pendent F unctiona lity E–21 T able E–15: 21 164 CBOX1 Event Selection The following values choose the CBOX1 event selecti on.
E–22 Al pha Architecture Handbook T able E–17: 21 164PC PM0_MUX Event Se lection The following val ues choose the PM0_M UX event selection a nd perform the chosen ope ration in C ounter 0.
Waivers and I mplementat ion-De pendent F unctiona lity E–23 E.2.3 21 264 Performan ce Monitorin g PALcode instru ctions con trol the 21264 on-chip pe r form ance cou nters. For Ope nV M S Alp ha, the in st ruct ion is M TPR_ PER FMON; for DI GITA L UNI X and Wind ows NT Alp ha, the instr uction is wr perf mon.
E–24 Al pha Architecture Handbook For the Windows NT Alpha Opera ting System When a cou nter ove rflows and inter rup t enabling cond itions are corre ct, the counter cau ses an interru pt to PALco de. The PALcode builds a frame on the kernel stack and dispatches to the kerne l at the inter rup t entry point .
Waivers and I mplementat ion-De pendent F unctiona lity E–25 E.2.3.3 OpenVMS Alpha and DIGIT AL UNIX Functions and Argument s The func tio ns execute only on a single (the cur rent runn ing) proc essor and ar e describe d in Table E–20.
E–26 Al pha Architecture Handbook Disable pe rfor mance monit ori n g DIGITAL UN IX Input: a 0 = 0 Function co de value a1 = ar g Argument from Table E–22 OpenVMS Alpha Input: R16 = 0 Function cod.
Waivers and I mplementat ion-De pendent F unctiona lity E–27 Write the c ount ers DIGITAL UN IX Input: a 0 = 6 Function co de value a1 = ar g Argument from Table E–25 OpenVMS Alpha Input: R16 = 6 .
E–28 Al pha Architecture Handbook T able E–23: 21264 Select Des ire d Events for OpenVMS Alpha and DIGIT AL UNIX R17/a1 Bits Meaning 4 3–2 T able E–24: 21264 Read Counters for OpenVMS Alpha an.
Waivers and I mplementat ion-De pendent F unctiona lity E–29 T able E–26: 21264 Enabl e and W rite Counters for O penVMS Alpha and DIGIT AL UNIX 5–2 Re se rved 1 When s et, write to Counter 1 0 .
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Index–1 Index A Aborts , forc in g , 6– 6 ACCESS(x, y) ope rat or , 3–7 Ad d in s t r u ct io n s add long word , 4–25 add qua dword , 4–27 add sca led longword , 4–2 6 add sca led qu adwo.
Index– 2 pr ogramming impl icat ions for , 5–30 TRAPB instr uct ion wit h , 4 –144 underf low , 4–78 , 4–81 underf low to z ero, disabl ing , 4– 80 underf low, dis abling , 4–8 0 un derf.
Index–3 Change d datu m , 5– 6 Cl ea r a regi s te r , A–1 2 CMOVEQ instru ction , 4–43 CMOVGE instru ction , 4–43 CMOVGT instru ction , 4–43 CMOVL BC ins t r u c tio n , 4– 43 CMOVLE in.
Index– 4 Dat a s t re am co ns id er a ti o n s , A–4 Da ta s tr uctur es, s ha re d , 5– 6 Data t ypes by te , 2–1 IEEE floa ting-po int , 2–6 longword , 2–2 longword integer , 2–1 1 qu.
Index–5 at p r oce ss or i nit ia liz at io n , 4–83 bit de scrip tio ns , 4–80 ins tructions to re ad/write , 4 –109 ope r at e in s t r u ct io n s th at use , 4–102 sa ving a nd resto rin.
Index– 6 I I/O devi ces, DMA MB and WMB with , 5 –22 reli ably com mu nic at ing wit h proc essor , 5–27 sha red memory lo ca tio ns wit h , 5–11 I/ O i nterfa ce ov ervi ew , 8–1 IEEE floa .
Index–7 Instruc tion stream. See I-str eam Inst ruc tions , overvie w , 1– 4 INSWH instruc tion , 4–55 INSW L in st r u c tio n , 4 –55 Integ er div ision , A–10 Integ er regis te rs defin e.
Index– 8 4–64 M /M opcode qual ifier, IEEE float ing- poin t , 4–67 MAP_F fun ction , 2– 4 MAP_S fun ction , 2– 7 MAP_x operat or , 3–8 Mas k byte i nstruc tions , 4–57 MAX, de fin ed fo.
Index–9 N NaN (Not -a-Numb er) conve rsion t o integer , 4–8 8 copyi ng, ge ne rating, propograting , 4–8 9 defin ed , 2–6 qu iet , 4 –64 signa ling , 4–64 NATURALLY ALIGNED data obj ects .
Index– 10 with , 4–138 Pixel error inst ruction , 4– 154 PKLB ( P ack l ongword s to byt es) ins t ructio n , 4– 155 PK W B ( Pa c k wo r ds t o by tes) in str u c ti o n , 4 –155 Pref etch data (FETC H instruc ti on) , 4–139 PRIORITY_ENCODE ope rator , 3–9 Pri vil e ged Archite cture Libra ry.
Index –11 Shi ft ari thmetic ins tru ct ions , 4–46 Si gn ext end in struc tions , 4– 60 Si ngle -pre cisi on flo at ing-p oint , 4–62 SL L ins t ruction , 4–4 5 Software consi derati ons , .
Index– 12 TRAPB (trap barrier ) instruc ti on des cribed , 4–144 with FPCR , 4 –84 True resu l t , 4–64 Tru e ze ro , 4–65 U UMULH i nstructi on , 4–36 with MULQ , 4–35 UNALIGNED data ob.
Index –13 XOR in st ruc tio n , 4–42 XOR operator , 3–10 Y YUV coordina te s , int erl ea ve d , 4– 151 Z ZAP in s t r u ct io n , 4–61 ZAP NOT ins tr uction , 4–61 Zero byte in struc tion.
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