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R PowerPC™ 405 Processor Block Reference Guide Embedded Development Kit UG018 (v2.0) August 20, 2004.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com UG0 1 8 (v2.0) August 20 , 2004 1-800- 255-7778 "Xilinx" and t he Xilinx logo sho wn abov e are regis tered trademar ks of Xil inx, Inc. Any rights no t expre ssly gra nted herei n are reserved.
UG018 (v 2. 0) Aug ust 20, 2004 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 PowerPC™ 405 Processor Block Ref erence Guide UG018 (v2.0) August 20, 2004 The following table shows the revision hist ory for this documen t.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com UG0 1 8 (v2.0) August 20 , 2004 1-800- 255-7778.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 5 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 R Instruction-Side PLB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Instruction-Side PLB I /O Signal Table .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 7 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R ISOCM Controller In struction Fetch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 DSOCM Ports . . .
8 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 R FCM Store Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 FCM Exception .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 9 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Pr efac e About This Guide This guide serves as a technical reference describing the har dware interface to the PowerPC ® 405 processor block.
10 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Preface: About This Guide R Addi tiona l Resour ces For additiona l in formation, go to http:// support.xilinx.com . The follo win g table lists some of the resources you can access fr om thi s website.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 11 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Online Docu ment The following conventions ar e us ed in thi s document: H.
12 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Preface: About This Guide R General Conventions Ta b l e 1 - 1 lists th e genera l notational conv entions used througho ut thi s document.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 13 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Te r m s TCR T im er - c on trol r egi ster TSR T imer-status register T a.
14 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Preface: About This Guide R exception An abnormal event or condition that requires the pr ocessor ’s attention. They can be caused by instr u ction execution or an external device.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 15 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R OEA The PowerPC operating-enviro n ment architectur e, which defines the m.
16 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Preface: About This Guide R UISA The PowerPC user instruction-set a rchitectur e.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 17 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Chapter 1 Intr oduction to the PowerPC 405 Pr ocessor The PowerPC 405 is a 32-bit implementation of the PowerPC em bedded -environment arch ite ctur e th at is derived from the PowerPC architecture.
18 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R The PowerPC architectur e r equires that all PowerPC implementations adhere to the UISA, offering compatibility a mong all PowerPC applicat ion programs.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 19 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R x Special-purpose r eg isters for controlling the use of debug res ou rces, timer resour ces, interrupts, real-mode storage attributes, memory- m anagem ent facilities, an d other architected pr o cessor r esour ces .
20 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R T able 1-2: OEA Feature.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 21 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R PowerPC 405 Sof tware Featu res The PowerPC 405 pro cessor core is an implementation of the PowerPC embedded- environment ar chitecture.
22 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R i W rite-ba ck and writ.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 23 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Real Mode In rea l mo de , programs address physical memory directly .
24 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R General-Purpose Registers The processor contains thirty -two 3 2-bit gene ral-purp ose re gisters (GPRs), id entified as r 0 through r 31.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 25 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R S pecial-Pur pose Registers The proces s or contains a number of 32-bit special-p urpose regist ers (SPRs).
26 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R Central-Processin g Uni.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 27 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R read ports and two write ports. During the decode stage, d ata is read out o f the GPRs for use by the execute unit. During the write-back stage, re sults are w ritten to the GPR.
28 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R Software manages the in itia lization a nd replacement of TLB entries.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 29 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R T imer Resources The PowerPC 405 contains a 64 -bit time base and thr ee timers. The time base is incremented synchronously using the CPU clock o r an external clock source.
30 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R x Device control re g i.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 31 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R caches and the tim e as sociated w ith perf orm ing cache-line fills an d flushes. Unless st ated otherwise, the number of cycles described applies to systems ha ving zero-wait-state memory access.
32 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 33 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Chapter 2 Input/Output Interfaces This chapt er describes all PowerPC 4 05.
34 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Appendix B, “S ign al Summary ,” alpha betica lly lists the sig na ls d e scribed in this chapter .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 35 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Clock an d Power Managem ent Interfa c e The clock and pow e r ma nagement (CPM) interf ace enables power-sensitive appl ications to control the processor clock using external logi c.
36 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R i The DBGC405D EBUGHAL T chi p-input sig nal (if provided) is asserted. Assert ion of this signal in dicates that an external debug tool w ants to control the PowerPC 405 pr ocessor .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 37 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R CPM Interface I/ O Signal Descriptions The following sections describe the operation of the CPM interface I/O signals. CPMC405CLOCK (Input) This signal is th e source clock for all PowerPC 405 logi c (including timers).
38 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R CPMC405TIMER TICK (Input) This signal is used to contr ol the update frequency of t he PowerPC 405 time base an d PIT (the FIT and WDT are timer events triggered by the time base).
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 39 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R C405CPMMSREE, C405CPMMSR C E, and C405CPMTIMERIR Q signals before using them to control the processor clocks.
40 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R x PLBCLK, primary PLB I/O Bus clock. x BRAMISOCMCLK, r efer ence clock for the I- Side OCM contro ller .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 41 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R clocks for the OCM cont rollers in the proce s sor block: BRAMDSOCMCLK (data side contr oller) and BRAMISOCMCLK (instr ucti on side contr ollers).
42 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R CPU Control I nterface I/O Signal Descriptions The following sections describe the operatio n of the CPU control-interface I/O signals.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 43 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R instructions foll owing the load require the loaded data. Dis abling operand forwa rding may improve the perform a n ce (clock fr equency) of the PowerPC 405.
44 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R JTGC405TR STNEG signal s for at least sixteen cl ock cycles. FPG A designers ca nnot mo dify the processor block power-on r eset mechanis m.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 45 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Reset In ter f ace I/ O S i gna l D es cr ip tio n s The following sections describe the oper ation of the reset interfa c e I/O si gnals.
46 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R RSTC405RESETSYS input to the pr ocessor block. When deasserted, no system-r eset request exists.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 47 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Ta b l e 2 - 5 , p a g e 4 4 s hows the valid combinati ons of the RSTC405RES ETCORE , RSTC405RES ETCHIP , an d RSTC4 05RESETSYS s ignals and their ef f ect on the DBSR[MRR ] field followin g reset.
48 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R x The r equest priority is indicated by C405PLBICUPRIORITY[0:1]. See “C 405P LBI CUPR I OR I TY[0 :1] (O utp ut)” .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 49 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R placed in the ICU fill bu f f er , but not in the in struction cache.
50 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R x The pre fetch addr ess does not fall outside the curre nt 1 KB physical page.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 51 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Instruct ion-Side PLB Interface I/O Signa l Descriptions The following sections describe the operatio n of the instructio n- side PLB interface I/O signals.
52 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R C405PLBICUREQUEST (Output) When asserted, this signal indicates the ICU is requesting instr u ction s from a PLB slave device.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 53 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R C405PLBICUSIZE[2:3 ] (Output) These signals are u sed to specify the line-transfe r si ze of the instruction-fetch request. A four- w ord transfer siz e is specified when C405PLBICUSIZ E[2:3] 0b01.
54 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R C405PLBICUU0A TTR (Output) This signal r eflects the value of the user-defined (U0) stora g e attribute for the tar get address .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 55 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R PLBC405ICUADDRACK (Input) When asserted, this signal indicates th e PLB slave acknowledges the ICU fetch request (indicated by the ICU assertion of C405PL BICUREQUEST).
56 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R x When a 64-bit PLB slave responds, an aligned doubleword is sent from the s lave to the ICU during each transf er cycl e.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 57 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R The ICU r eads either the low 32 bits or the high 32 bits of the 64-bit interfac e, depending on the value of PLBC405ICURDWDADDR[1:3].
58 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R transfer order is invalid if th is signal asserted. The en tries for a 32-bit PLB slave as sume the connection to a 64-bit master shown in Figure 2-5 , ab ove .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 59 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Following reset, the processor block prevents the ICU from fetching instructions until the busy signa l is deasserted f or the first time.
60 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R fastest rate at which a BIU can transfer instructions to the ICU (there is no limit to the number of cycles between two transfers).
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 61 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R ISPLB Non-Pipe l ined Cacheable Se quential Fetch (Case 1) The t iming di agram in Figure 2-6 shows two consecu tive eight-word line fetch es tha t are not addres s pipelined.
62 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R ISPLB Non-Pipe l ined Cacheable Se quential Fetch (Case 2) The t iming di agram in Figure 2-7 shows two consecu tive eight-word line fetch es tha t are not addres s pipelined.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 63 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R The first line r ead (rl1) is requested by th e ICU in cycle 3 in r esponse to a cache miss (repr ese nted by the miss1 transaction in cycles 1 and 2).
64 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R After the first miss is detected, the ICU p.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 65 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R in cycles 10 through 15). The line is not cacheable, so instructions are not transferr ed fr o m the fill buffer to the instruction cac h e.
66 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R ISPLB 2:1 Core-t o-PLB Line Fetch The t iming di agram in Figure 2-12 shows an eight-wor d lin e fetch in a system with a PLB clock that runs at one half the frequency of the PowerPC 405 clock.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 67 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R ISPLB 3:1 Core-t o-PLB Line Fetch The t iming di agram in Figure 2-13 shows an eight-wor d lin e fetch in a system with a PLB clock that runs at one thir d the frequency of the PowerPC 405 clock.
68 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Dat a-Side Processor Loc al Bus Interface T.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 69 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R x The target addr ess of the da ta to be a ccessed is specified by the a ddress bus, C405PLBDCUABUS [0:31]. See “C40 5P LBD CUAB US[ 0:31] (Out put) ” .
70 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R i An eight-word line transfer moves t he eight-word ca ch e line aligned on the addres s specified by C405PLBDCUABUS[0:26 ].
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 71 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R An eight-word line-write transfer occurs when the fill buffer r epl aces a n existing data- cache line containing modified data.
72 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Figure 2-15 : Data-Side PLB In terface Bloc.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 73 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Data -Side PLB Interface I/O Sig nal De script ions The following sections describe the operation of the data-s i de PLB interface I/O signals.
74 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R If the transfer s ize is a si n gl e word, C405PLBDCUBE[0: 7] is also valid when the req u est is asserted.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 75 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R An eight-word line t ransfer moves the ca ch e line a ligned on the add ress speci fied by C405PLBDCUABUS[0:2 6]. This cache line contai ns the target data accessed by the DCU.
76 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R C405PLBDCUU0A TTR (Output) This signal r eflects the value of the user-defined (U0) stora g e attribute for the tar get addres s.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 77 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Ta b l e 2 - 1 3 shows the possible values that can be pres ented by the byte enables and how they are interpr eted by th e PLB slave.
78 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R C405PLBDCUPRIORITY[0:1] (Output) These signals are u sed to specify the priority of the data- access request.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 79 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R an aborted data-write request. In this case, memory must no t be updated by the PLB slave and no further write acknowledgements can be pr esented by the PLB slave for the aborted req u e st .
80 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R PLBC405DCUADDRACK (Input) When as serted, this s ignal indica tes the P LB slave ac knowledges th e DCU data-access request (indicated by the DCU assertion of C405PLBD CUREQUEST).
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 81 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R must abort a DCU request (move no data) if the DCU assert s C405PLBDCUABORT in the same cycle the PLB slave acknowledges the r equest.
82 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R x During a sing le word write, the DCU replicates the data on the high and lo w words of the write data bus.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 83 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R PLBC405DCURDWDA DDR[1:3] (Input) These signals are u sed to specify the transfer or der .
84 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R is transferred fr om the DCU to the PLB slave. If this signal is deass erted, va lid data o n the write data bus has not been latched by the PLB slave.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 85 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R The PLB sla ve should latch error information in D CRs so tha t software diagnost ic routines can attempt to repo rt and recover fr om the error .
86 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R x The DCU act ivity is s hown only a s an aid e in describing the examples. The occurrence and duration of this acti vity is not observable on the DS PLB.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 87 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R The second line read (rl2) is requested by the DCU in cycle 4. Th e BIU responds to this request after it has comple ted all transactions ass ociated with the first request (rl1) .
88 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R is sent fro m the BIU to the DCU fill buffer in cycle 7. The DCU uses the byte enables to select the appropriate bytes fr o m the read-data bus.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 89 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R The second wor d read (rw2) is r equested by the DCU in cycle 7 and the BIU responds in the same cycle. A single wor d is sent from the BIU to the DCU in cy cle 8.
90 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R The third line write (wl3) cannot be star ted until the second request (wl2) is compl ete. This request is made by the DCU in cycle 13 in resp onse to the flus h3 request.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 91 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R DSPLB Three Consecut i ve W ord Write s The t iming di agram in Figure 2-22 shows three consecutive wor d writes.
92 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R DSPLB Line W rite/Line Read/W ord Write The t iming di agram in Figure 2-23 shows a sequen ce involving an eigh t- word line write, an eigh t-word lin e read, and a w ord wri t e.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 93 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R DSPLB W ord Write/W ord Read/Wor d Write/Line Read The timing diagram i n Figure 2-24 shows a sequence in volving a word write, a word read, another wo rd write, and an eight-wo rd line read.
94 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R DSPLB W ord Write/Lin e Read/Line Write The t iming di agram in Figure 2-25 shows a sequen ce involving a word write, an eigh t- word line r ead, and an eight-word line write.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 95 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R DSPLB 2:1 Core-to- PLB Line Read The timing diagram in Figure 2-26 show s a line read in a syst em with a PLB clock that runs at one half the fr equency of the PowerPC 405 clock.
96 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R DSPLB 3:1 Core-to- PLB Line Write The t iming di agram in Figure 2-27 shows a line write in a syst em with a PL B clock that runs at one thir d the frequency of the PowerPC 405 clock.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 97 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R DSPLB Abort ed Data-Access Request The t iming di agram in Figure 2-28 shows an aborted da ta-access request. The r equest is aborted because of a cor e reset.
98 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Device-Control Register Interfaces The devi.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 99 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Internal Device Contro l Register (DCR) Interface The PowerPC 405 Pr ocess.
100 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R In V irtex-II Pro/Pr oX, a DCR access addressing the internal DCR logic could be visibl e on the external DCR bus interface as an access.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 101 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R blocks that are associated with each PowerPC. Thus , this interface is not available to th e user for connection to the FPGA fabric.
102 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R In V irtex-II Pr o/ProX the PowerPC external D.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 103 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R (CPMC405CLOCK), the access ti mes out. No err or is flagged on time-out. The processor just continues to execute the next instruction.
104 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Virt ex-4-FX The external general pu rpose DC .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 105 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R External DCR Bus Interface I/O Signal Descriptions The followin g sections desc ribe the operation of the DC R interface I/O signals.
106 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R The processor does not begin drivin g a ne w DCR address until th e DCR acknowled ge signal correspondin g to the previous DCR access has been d easserted for at le ast one cycle.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 107 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R DCR Interface 1:1 Clocking, Latched Acknowledge The example in Figure 2-33 assum e s th e follow ing: x The PowerP C 405 and the periphera l containing t he DCR are cl ocked at the sa me fr equency .
108 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R DCR Interface 2:1 Clocking, Latched Acknowledg.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 109 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R DCR Interface 1:2 Clocking, Latched Acknowledge The example in Figure 2-36 assum e s th e follow ing: x The PowerPC 405 DCR interface is clocked at half the fr equency of the peripheral containing the addr essed DCR.
11 0 www .xilinx.com PowerPC™ 405 Processor Block Re fe ren ce Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R interrupts ahead of noncriti cal interrupts wh en they occur simult aneously ( c ert ain d e bug exceptions are handled at a lower priority).
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 111 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R EIC Interf ace I/O Signal Descriptio ns The following sections describe the operation of the EIC interface I/O signals.
11 2 www .xilinx.com PowerPC™ 405 Processor Block Re fe ren ce Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R JT AG Interface I/O Signal Descriptions The following sections describe the operation of the JT AG interface I/O signals.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 11 3 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R C405JTGSHIFTDR (Output) This output is asserted (logic High) when the PPC405 T AP is in the Shift-DR state. Most designs do n ot require this signal an d should leave it un connected.
11 4 www .xilinx.com PowerPC™ 405 Processor Block Re fe ren ce Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R The six least sign ificant bits of the pa rts Instruction Regi ster al ways compris e the FPGA Instruction Register .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 11 5 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R The PPC405 cor es do not have their own BSDL files; instead, the necessary INSTRUCTION_OP CODES and other info rmation are incorporated in the device BSDL file.
11 6 www .xilinx.com PowerPC™ 405 Processor Block Re fe ren ce Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Figure 2- 42: Corr ect Wiring of JT AG Chain .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 11 7 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Figure 2- 43: Correct Wiring of JT AG Chains with Individual P PC405 JT .
11 8 www .xilinx.com PowerPC™ 405 Processor Block Re fe ren ce Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Figure 2 -44: Correct Wirin g of JT AG C hain.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 11 9 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Connecting PPC405 JT AG L ogic in Series with the Dedicated Devi ce JT A.
120 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R When the PPC4 05 JT A G logic is con nected in se ries with the dedicated device JT AG logic, only one JT A G chain is required on the printed circuit board.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 121 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R For devices with more than one PPC405 core, users must connect the JT AG logic for ALL of the PPC405 cor es on the device when using th is connecti on style, even if some are not otherwise used.
122 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R ); end component begin -- Component Instantiation U_PPC1 : PPC405 port map ( .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 123 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R .C405JTGSHIFTDR (), .C405JTGUPDATEDR (), .
124 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R signal TDO_PPC : std_logic; signal TMS_PPC : std_logic; signal TDI_PPC : std_logic; signal TCK_PPC : std_logic; begin -- Component Instantiation U_PPC1 : PPC405 port map ( .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 125 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R .C405JTGTDO (TDO_PPC), .JTGC405BNDSCANTDO (), .C405JTGTDOEN (TDO_TS_PPC), .C405JTGEXTEST (), .C405JTGCAPTUREDR (), .C405JTGSHIFTDR (), .
126 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R component JTAGPPC port( TDOTSPPC : in std_logi.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 127 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R U_JTAG : JTAGPPC port map ( TDOTSPPC => TDO_TS_PPC, TDOPPC => TDO_O.
128 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R .JTGC405BNDSCANTDO (), .C405JTGTDOEN (TDO_TS_OUT2), .C405JTGEXTEST (), .C405JTGCAPTUREDR (), .C405JTGSHIFTDR (), .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 129 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Debug Int erface I/O Si gnal Descriptions The following sections describe the operation of the debug interface I/O signals.
130 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R In systems that deactivate the clocks to manage power , the debug halt signal should be used to restart th e clocks (if stopped) to enable an external debugger to operate the processor .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 131 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R C405DBGST OP ACK (Output) When asserted, this signal indicates th at the PowerPC 405 is in d ebu g ha lt mode. When deasserted, the processor is no t in debug halt mo de.
132 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R T race Inte rface I/O Signal Descriptions The following sections describe the operation of the trace i nterface I/O signals.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 133 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R FPGA logic can combine these signals wi th the trigger-event output signal to produce a qualif ied version of the trig ger signal.
134 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R C405TRCTRACEST A T US[0:3] (Output) These signal s provide additional in formation requ ir ed by a tra ce tool when reconstructin g an instruction execution sequence.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 135 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R PVR Interface I/ O Signal Descriptions The following sections describe the operation of the PVR-interface I/O signals. TIEPVRBIT8 (Input) When tied hig h sets Processor V ersi on Register bit 8 to 1.
136 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Additional F PGA Specific Signals Figure shows the block symbol for the additional FPGA signals used by the processor block.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 137 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R MCBTIMEREN (Input) When asserted, this signal indicates that the enable for the timer clock zone (CPMC405T IM ERCLKEN) should follo w (match the value of) the glo bal write enable (GWE) during the FPGA startup sequence.
138 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 139 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Chapter 3 PowerPC 405 OCM Contr oller Intr oducti on The On-Chip Memo ry (OCM) controller serves as a dedicated in terface between the FPGA BRAMs and the OCM signals contained w ithin the embedded PPC405 core.
140 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Comp arison of V irtex-II Pro an d Vir t ex-4 OCM Controllers The V irtex-4 OCM controller is com pletely backward compatible with the Virtex- I I Pr o OCM controller .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 141 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Features for Instru ction-Side OCM (ISOCM) The ISOCM interface con tains a 64 - b it read on ly po rt for instruction fetches and a 32-bit read and write port to initialize or test the ISBRAM.
142 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R OCM Controll er Operation The OCM contro ll er is distributed into two blocks, one fo r th e ISOCM interface and the other for the DSOCM interface, as shown in Figure 3-1 .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 143 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R up with t h e value on the in put ports: DSARCV ALUE[0:7] and ISARCV ALUE[0:7] respectively . The two registers can a lso be load ed us ing DCR write a ssembly instructions (mtdcr) .
144 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R register d efin e s the 16 MB memory region that is valid fo r the DSOCM.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 145 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R DSOCM Port s Figure 3-2 and Figure 3-3 ar e the block diagrams of the DSOCM in V irtex-4 and V irtex-II Pro. All signals are in big endian format.
146 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R DSOCM Input Ports Ta b l e 3 - 3 describes the Da t a Side OCM (D SOCM) input ports.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 147 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R DSOCM Input Ports: Attributes Attributes are inputs to th e OCM controller from the FP GA fabric that must be connected to initialize registers at FPG A power up, or following a processor reset.
148 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R DSOCM Output Ports Ta b l e 3 - 5 describes the data-side OCM (DSOCM) outpu t ports.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 149 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R DSOCM-to-BRAM Interfaces Figure 3-4 provides an example of a basic DSOCM-to-BRAM interface fo r V irtex-II Pro. V irtex-II P ro supports on ly fixed laten cy connec tions such as the on e shown.
150 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Figu re 3-4: DSOCM to BRAM Interfac e: .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 151 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Note: For back war d co mp atibility with V irtex-II Pro, w he n conn e.
152 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Figure 3-6 shows the extended feature in V irtex-4 for DSOCM-to-Memory-Mapped-Slave- Peripheral interface.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 153 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R ISOCM Input Ports Ta b l e 3 - 6 describes the Instruction Side OCM (ISOCM) input ports.
154 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R ISOCM Input Port s, Attributes Attribut.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 155 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R ISOCM Output Ports Ta b l e 3 - 8 describes th e instruction-sid e OC M (ISOCM) output ports .
156 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R ISOCMBRAMEVENW RITEEN Output Note: Option al. Used in du al-port BRAM inte rface design s only .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 157 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Figure 3-9 shows an example of an ISOCM-to-BR A M in terface in V irtex-II Pro. Figure 3-10 shows an example of an ISOCM-to-BRAM i nterface in V irtex-4.
158 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Note: See Ta b l e 3 - 8 for descriptions of the sign als shown in Ta b l e 3 - 1 0 , above.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 159 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R locations. These bits are decod ed agains t PPC405 address bits 0:7.
160 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R ISCNTL Registers Ta b l e 3 - 1 1 an d Ta b l e 3 - 1 2 describe the ISCNTL registers in V irtex-II Pro and V irtex-4 devices.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 161 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Features Int roduced in V irtex-4 and Comparison with Virte x -II Pro In V irtex-4 an optional aut o clo c k rati o detectio n feature was implemented on both the DSOCM and ISOCM .
162 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Figure 3-1 1: DSOCM DC R Registers for .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 163 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Figure 3-12 : DSOCM DC R Registers for Virtex-4 UG018_46b_042304 DSARC .
164 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Figure 3- 13: ISOCM DCR Registers for V.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 165 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R The following section describes th e DCR bit mapping durin g r ea d/write operation s on the ISINIT and ISFILL registers.
166 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R DCR Wri te Access As shown in Figur e 3 -15 , ISINIT is a 22-bit register (A8-A29) that is mapped to DCR write data bus bits D8-D29.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 167 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R DCR Read Access If the ISINIT r egi ster is read back on the DCR: x For.
168 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Figure 3 -16: ISOCM: I SINIT and IS FIL.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 169 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R BRAMs that interface with the ISOCM co nt roller can also be initialized thr ough the configuratio n bit-stream, during FPG A configurat ion.
170 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R routing delays, signal lo ading, BRAM mem ory access time, clock to ou tput times, and setup and hold times of the BRAM an d processor blocks.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 171 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R In multi-cycle mo de, initial wait cycles are inserted until the CPMC 4 05CLOCK and BRAMISOCMCLK ris ing edges are aligned.
172 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R In order to estimate the theoretical ma.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 173 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R mode and multi-cycle Mode. The timing interface betwee n the O CM controller and the memory is always w ith respect to the BRAMISOCMCLK.
174 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R DSOCM Data Load, Fixed Lat ency Figure 3-22 and Figure 3-23 s how two back- to-back loads f or single-cycle m ode and mu lti- cycle mode with a CPMC405 CLO CK:BRAMDSOCMCLK ratio of 2:1.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 175 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R In multi-cycle mo de, initial wait cycles are inserted until the CPMC 4 05CLOCK and BRAMDSO CMCLK rising edges are aligned .
176 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R In the figur es above, L_addr_ n refers.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 177 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R period should be used.
178 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R DSOCM Data Load, V ariable Latency Figu.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 179 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R DSOCM Data S tore, V ariable Latency Figure 3-28 and Figure 3-29 show two store operations with va ria ble latency for singl e- cycle mode and for multi-cycle mode wi th a CPMC405CLOCK:BRAMDSOCMCLK ratio of 2:1 .
180 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Figure 3-28 : Sin gle Cycle Mo de (1:1).
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 181 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Application Note s and Reference Desi gns Xilinx provides several appli cation notes and reference designs utiliz ing the OCM controllers.
182 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 183 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Chapter 4 PowerPC 405 APU Contr oller This chapter only a pplies to the.
184 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R The APU Contr o ller serves two purpose.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 185 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R has a config urable format an d is a true extension of the PowerPC in struction set arch i tecture (ISA).
186 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R Blocking Ins tr uctions Any non-autono mo us instruction that cann ot be predictably aborted and later re-issued must be blocking.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 187 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Instruct ion Decoding FCM instructions can be decod e d either by th e APU Co ntroller or by the FCM itself. APU Contr o ller decoding benefits fr om the higher clock frequencies possible i nside the hard core.
188 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R The decode d instructions require an FCM f loating po int unit to be us ed.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 189 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R The extended op-code for Lo ad/Stor e operations are described in Ta b l e 4 - 3 . APU Controller Load/S tore ins truction decodi ng can be disabled in the APU Contr o ller configuration register .
190 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R FCM User-Defined Instruction Deco ding User -defined instructions that are not recogn ized (i.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 191 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R FCM inter nal data hazar ds such as r ead-after -write (RA W) and write-af ter-wri te (W A W) are eliminated if the desi gner ensures that a ll FCM ins tructions compl ete in order .
192 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R UDI Configuration Registers The APU Controller includes eight U DI configuration registers.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 193 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R The reset value of the individual UDI r egisters can be defined using a ttribute inputs to the APU Contr oller . For deta ils see the “APU Controller Attributes” section in this chapter .
194 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R APU Controller Input Signals All APU Con troller input sig nals shou ld be s ynch ronized on the FCM clock (CPMFCMCLK).
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 195 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R FCMAP U DCDLDSTWD F CM decoded loa d/store instruction does w ord transfer . FCMAPUDCDLDSTDW F CM decoded load/stor e instruction do es double word tran sfer .
196 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R APU Controller Outpu t Signa ls All APU Con troller output signals are synchronou s wit h the FCM clo c k ( CPMFCMCLK).
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 197 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R APU Controller Attribut es The following input signal s are used as reset values for the APU Controller configurat ion registers.
198 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R T able 4-10: Bit Map Between TIEAP UCON.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 199 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R FCM Interface Timing S p ecification Auton omous T ransact ions Note: Actual timing result s may var y from those shown in Figu re 4-3 .
200 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R Note: Actual timing result s may var y from those shown in Figu re 4-4 . For exampl e, the operand s could c ome later than sho wn.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 201 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Blocking T ransact ions Note: Actual timing result s may var y from those shown in Figu re 4-5 . For exampl e, the operand s could c ome later than sho wn.
202 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R Non-Blocki ng T ransactions Note: Actual timing result s may var y from those shown in Figu re 4-6 .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 203 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R FCM Load Instruction Note: Load dat a can arri ve at the s ame time as the instruc tion or at a later cloc k cycle t han shown in Figure 4-7 .
204 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R Note: Load dat a can arri ve at the s ame time as the instruc tion or at a later cloc k cycle t han shown in Figure 4-8 .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 205 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R FCM Exception Note: FCMAPUEXEPTION m ay be sent at a ny time d uring the execu tion of a non-auto nomous instr ucti on.
206 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R FCM Decoding Using Decode Busy Signal F.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 207 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Appendix A RISCW atch and RISCT race Interfaces This appendix summarizes the interface r equirements between the PowerPC 405 and th e RISCW atch and RI SCT r ace tools .
208 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix A: RISC W atch a nd RISCT ra ce Interface s R T able A-1: JT AG Connector Signals for RISCWa tch Pin RISCW atch Descrip tion I/O Signal Name 1 I nput TDO J T AG test-da ta out.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 209 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R RISCT race Interface The RISCT race tool communicates with the PowerPC 405 using the trace i nterface.
210 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix A: RISC W atch a nd RISCT ra ce Interface s R T able A-3: T race Connector Signals for RISCT race Pin RISCT race Description I/O Sig nal Name 1N o Con nect Reserved 2N o Con nect Reserved 3 O utput T rcClk T race cycle.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 21 1 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R T able A-4: PowerPC 405 to RISCT race Signal Mapping PowerP C 405 RISC.
212 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix A: RISC W atch a nd RISCT ra ce Interface s R.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 213 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Appendix B Signal Summary Interface Signals Ta b l e B - 1 lists the PowerP C 405 interface signals in alphabetical order .
214 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Appendi x B: Signal Summa ry R APUFCMXERCA V- 4 O F C M N o Connect Ref lects th e XerCA bit use d for extended a r ithmetic.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 215 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R C405JTGCAP TU REDR (OUTPUT) V -II Pro and V -4 OJ T A G N o Connect Indicates the T AP controll er is in the capt ure- DR sta te.
216 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Appendi x B: Signal Summa ry R C405PL BICUABUS[0: 29] V -II Pr o and V -4 OI S P L B N o Connect Specifies the memory addr es s of the instruc tion-fetch re quest.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 217 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R CPMC 405TIMERCL KEN V -II Pro and V -4 I CPM 1 Enables the timer clock z one.
218 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Appendi x B: Signal Summa ry R EICC405EXTINPUTIRQ V -II Pro and V -4 I EIC 0 Indicate s an extern al noncrit ical inter rupt occurred.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 219 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R FCMAPU DONE V -4 I FCM 0 Indicates the completion of the instruc t ion in the FCM to t he APU Con trol ler FCMAPUEXCEPTION V -4 I FCM 0 FCM generate progr am exception on the pr ocessor (vector 0x0700) .
220 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Appendi x B: Signal Summa ry R IS OCMDC RBR AMR DSE LECT V -4 O ISOCM No Connect .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 221 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R PLBC40 5D CU WRDACK (INP UT) V -II Pro and V -4 I DSPLB 0 Indicates the da t a on t he DCU write- data bus is being ac c epted by the P LB slave.
222 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Appendi x B: Signal Summa ry R TIEC405DETERMIN ISTICMUL T (INPUT) V -II Pro and V -4 I Control 0 Required Specifi es whether all mult iply operations co mplete in a fixed number of cycles or have a n early -out capabili ty .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 223 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Appendix C Pr ocessor Block T iming Model This section explains all of the timing parameters associated with the IBM PPC405 Processor Block.
224 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix C: Proce ssor Block Timing Mo del R PowerPC misc el laneo u s (PPC ), T.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 225 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R T able C -2: P arameters Rel ative to th e Core C lock (CPMC4 05CLOCK) .
226 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix C: Proce ssor Block Timing Mo del R Clock: T CPWH Clock Pulse W idth, High State CPMC405CLOCK T CPWL Clock Pulse W idth, Low State CPMC405CLOCK a.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 227 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R T able C -3: P arameters Rel ative to the DCR Bu s Clock (CPMDC RCLK, V.
228 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix C: Proce ssor Block Timing Mo del R T able C -4: P arameter s Relative .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 229 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R T PCKD O _FCM Data Outputs APUFCMINSTRUCTION [0:31] APUFCMRADA TA[0:31].
230 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix C: Proce ssor Block Timing Mo del R T PCKD O _PLB Data outputs C405PL B.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 231 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Clock to Out: T PCKCO _ISOCM Con tr ol ou tputs ISOCMBRAMEN ISOCMBR AMO.
232 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix C: Proce ssor Block Timing Mo del R Figure C-2: Processor Block Timing .
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 233 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 A abort data-side PLB 78 , 97 instruction-side PLB 54 , 67 address ack no.
234 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 R cachea ble 49 non-cacheable request size 48 prefetching 49 without all oc ate 49 FIT description of 29 timer exception 39 upda te f req uency 38 fixed-interval timer See FIT.
PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 235 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R processor reset See core reset.
236 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 R.
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