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R Micr oBlaz e Pr ocessor Ref erence Guide Embed ded De velopment Kit EDK 8.2i UG081 (v6.0) June 1, 2006.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com UG081 (v6.0) June 1, 2006 1-800-255-7778 © 2006 Xilinx, Inc. All Rights Reser v ed. XILINX, the Xilinx logo , and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the proper ty of their respective o wners.
UG081 (v6.0) June 1, 2006 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 Micr oBlaze Processor Reference Guide UG081 (v6.0) J une 1, 2006 The following table shows the revision history for this document. Date V ersion Revision 10/01/02 1.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com UG081 (v6.0) June 1, 2006 1-800-255-7778.
UG081 (v6.0) June 1, 2006 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 Preface: About This Guide Manual Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UG081 (v6.0) June 1, 2006 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MicroBlaze I/O Overview .
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 7 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Pr eface About This Guide W elcome to the MicroBlaze Pr ocessor Reference Guide. This document provides information about the 32-bit soft processor Micr oBlaze, which is part of the Embedded Processor Development Kit (EDK).
8 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Pref ace: About This Guide R Con ventions This document uses the following conventions.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 9 UG081 (v6.0) June 1, 2006 1-800-255-7778 Con ventions R Online Document The following conventions are used in this document: V ertical ellipsis . . . Repetitive material that has been omitted IOB #1: Name = QOUT’ IOB #2: Name = CLKIN’ .
10 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Pref ace: About This Guide R.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 11 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Chapter 1 Micr oBlaze Ar chitectur e Overview The MicroBlaze embedded processor soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx field programmable gate arrays (FPGAs).
12 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R In addition to these fixed features the Micr oBlaze processor is parametrized to allow selective enabling of additional functionality .
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 13 UG081 (v6.0) June 1, 2006 1-800-255-7778 Data T ypes and Endianness R Data T ypes and Endianness MicroBlaze uses Big-Endian, bit-r eversed format to repr esent data. The hardwar e supported data types for MicroBlaze ar e word, half wor d, and byte.
14 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R T able 1-5: Instruction Set Nomenc lature Symbol Description Ra R.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 15 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R << x Bit shift left x bits and Logic AND or Logic OR xor Logic exclusive OR op1 if cond else op2 Perform op1 if condition cond is true, else perform op2 & Concatenate.
16 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R ADDIKC Rd,Ra,Imm 001 1 10 Rd Ra Imm Rd := s(Imm) + Ra + C RSUBIKC.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 17 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R PUT Ra,FSLx 01 101 1 00000 Ra 1000000000000 & FSLx FSLx := Ra (blocking data write).
18 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R MTS Sd,Ra 100101 00000 Ra 1 1 & Sd SPR[Sd] := Ra, where: • .
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 19 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R BGTD Ra,Rb 1001 1 1 10100 Ra Rb 00000000000 PC := PC + Rb if Ra > 0 BGED Ra,Rb 1001 .
20 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Registers MicroBlaze has an orthogonal instr uction set architecture. It has thirty-two 32-bit general purpose registers and up to seven 32-bit special purpose r egisters, depending on configured options.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 21 UG081 (v6.0) June 1, 2006 1-800-255-7778 Registers R General Pur pose Registers The thirty-two 32-bit General Purpose Registers are number ed R0 through R31. The register file is r eset on bit stream download (r eset value is 0x00000000).
22 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Machine Status Register (MSR) The Machine Status Register contains control and status bits for the pr ocessor . It can be read with an MFS instr uction.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 23 UG081 (v6.0) June 1, 2006 1-800-255-7778 Registers R 22 EIP Exception In Progress 0 No hardwar e exception in progr ess 1 Hardwar e exception i.
24 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Exception Address Register (EAR) The Exception Address Register stor es the full load/store addr ess that caused the exception.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 25 UG081 (v6.0) June 1, 2006 1-800-255-7778 Registers R Exception Status Register (ESR) The Exception Status Register contains status bits for the processor . When read with the MFS instruction the ESR is specified by setting Sa = 0x0005.
26 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Branch T arget Register (BTR) The Branch T arget Register only exists if the Micr oBlaze processor is configured to use exceptions.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 27 UG081 (v6.0) June 1, 2006 1-800-255-7778 Registers R Floating P oint Status Register (FSR) The Floating Point Status Register contains status bits for the floating point unit. It can be read with an MFS, and written with an MTS instruction.
28 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R T able 1-15: Pr ocessor V ersion Register 0 (PVR0) Bits Name Desc.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 29 UG081 (v6.0) June 1, 2006 1-800-255-7778 Registers R 25 OP0EXEC Generate exception for 0x0 illegal opcode C_OPCODE_0x0_ILLEGAL 26 UNEXEC Genera.
30 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R 8:10 ICLL Instruction cache line length 2^n C_ICACHE_LINE_LEN 1 1.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 31 UG081 (v6.0) June 1, 2006 1-800-255-7778 Pipeline Arc hitecture R Pipeline Ar chitecture MicroBlaze instr uction execution is pipelined. The pipeline is divided into five stages: Fetch (IF), Decode (OF), Execute (EX), Access Memory (MEM), and W riteback (WB).
32 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Branches Normally the instructions in the fetch and decode stages (as well as prefetch buf fer) are flushed when executing a taken branch.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 33 UG081 (v6.0) June 1, 2006 1-800-255-7778 Reset, Interrupts, Exceptions, and Break R Reset, Interrupts, Exceptions, and Break MicroBlaze supports r eset, interrupt, user exception, break, and har dware exceptions.
34 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Reset When a Reset or Debug_Rst (1) occurs, MicroBlaze will flush the pipeline and start fetching instructions fr om the reset vector (addr ess 0x0).
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 35 UG081 (v6.0) June 1, 2006 1-800-255-7778 Reset, Interrupts, Exceptions, and Break R • Unaligned Exception The unaligned exception is caused by a word access wher e the address to the data bus has bits 30 or 31 set, or a half-word access with bit 31 set.
36 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Software Breaks T o perform a software br eak, use the brk and brki instructions. Refer to Chapter 4, “MicroBlaze Instr uction Set Architectur e” for detailed information on software br eaks.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 37 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instruction Cache R PC ← 0x00000008 Instruction Cache Ov er view MicroBlaze may be used with an optional instruction cache for impr oved performance when executing code that resides outside the LMB addr ess range.
38 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R For example: in a MicroBlaze configur ed with C_ICACHE_BASEADDR=.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 39 UG081 (v6.0) June 1, 2006 1-800-255-7778 Data Cache R • Cache on and off contr olled using a bit in the MSR • Optional WDC instruction to i.
40 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R A load from an address within the cacheable range will, provided that the cache is enabled, trigger a check to determine if the requested data is curr ently cached.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 41 UG081 (v6.0) June 1, 2006 1-800-255-7778 Floating P oint Unit (FPU) R F or mat An IEEE 754 single precision floating point number is composed of the following thr ee fields: 1. 1-bit sign 2. 8-bit biased exponent 3.
42 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R Comparison The FPU implements the following floating point comparisons: • compare less-than, fcmp.lt • compare equal, fcmp.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 43 UG081 (v6.0) June 1, 2006 1-800-255-7778 Debug and T race R Figure 1-12: FSL used with HW accelerated function f x This method is similar to ex.
44 www .xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 1: MicroBlaze Ar chitecture R.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 45 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Chapter 2 Micr oBlaze Signal Interface Description Overview The MicroBlaze cor e is organized as a Harvar d architectur e with separate bus interface units for data accesses and instruction accesses.
46 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R Figure 2-1: MicroBlaze Core Bloc k Diagram DXCL_M.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 47 UG081 (v6.0) June 1, 2006 1-800-255-7778 MicroBlaze I/O Overview R IM_BE[0:3] IOPB O Instruction interface OPB byte enables IM_busLock IOPB O I.
48 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R On-Chip P eripheral Bus (OPB) Interface Description The MicroBlaze OPB interfaces ar e implemented as byte-enable capable masters.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 49 UG081 (v6.0) June 1, 2006 1-800-255-7778 Local Memory Bus (LMB) Interface Description R Local Memory Bus (LMB) Interface Description The LMB is a synchronous bus used primarily to access on-chip block RAM.
50 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R Data_Write[0:31] The write data bus is an output from the cor e and contains the data that is written to memory .
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 51 UG081 (v6.0) June 1, 2006 1-800-255-7778 Local Memory Bus (LMB) Interface Description R LMB T ransactions The following diagrams provide examples of LMB bus operations.
52 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R Back-to-Bac k Wr ite Operation Single Cycle Back-.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 53 UG081 (v6.0) June 1, 2006 1-800-255-7778 Local Memory Bus (LMB) Interface Description R Read and Write Data Steer ing The MicroBlaze data-side .
54 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R F ast Simplex Link (FSL) Interface Description The Fast Simplex Link bus provides a point-to-point communication channel between an output FIFO and an input FIFO.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 55 UG081 (v6.0) June 1, 2006 1-800-255-7778 Xilinx CacheLink (XCL) Interface Description R FSL T ransactions FSL BUS Write Operation A write to the FSL bus is performed by MicroBlaze using one of the flavors of the put instruction.
56 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R The MicroBlaze CacheLink interface can also conne.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 57 UG081 (v6.0) June 1, 2006 1-800-255-7778 Xilinx CacheLink (XCL) Interface Description R CacheLink T ransactions All individual CacheLink accesses follow the FSL FIFO based transaction protocol: • Access information is encoded over the FSL data and control signals (e.
58 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R The CacheLink solution uses one incoming (slave) and one outgoing (master) FSL per cache controller .
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 59 UG081 (v6.0) June 1, 2006 1-800-255-7778 Debug Interface Description R 0b01=byte1 or halfword0, 0x10=byte2, and 0x1 1=byte3 or halfword1. The selection of half-word or byte access is based on the contr ol bit for the data word in step 4.
60 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R T race_Reg_W rite 1 Instruction writes to the reg.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 61 UG081 (v6.0) June 1, 2006 1-800-255-7778 MicroBlaze Core Con fi gurability R Micr oBlaze Core Con fi gurability The MicroBlaze cor e has been developed to support a high degree of user configurability .
62 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R Parameters valid for MicroBlaze v5.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 63 UG081 (v6.0) June 1, 2006 1-800-255-7778 MicroBlaze Core Con fi gurability R C_USE_FPU Include hardware floating point unit (V irtex2 and lat.
64 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 2: MicroBlaze Signal Interface Description R C_ICACHE_HIGHADDR Instruction cache high address .
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 65 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Chapter 3 Micr oBlaze Application Binary Interface Scope This document describes MicroBlaze Application Binary Interface (ABI), which is important for developing software in assembly language for the soft pr ocessor .
66 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 3: MicroBlaze Application Binary Interface R Register Usage Con ventions The register usage convention for Micr oBlaze is given in T able 3-2 . The architectur e for MicroBlaze defines 32 general purpose r egisters (GPRs).
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 67 UG081 (v6.0) June 1, 2006 1-800-255-7778 Stack Con vention R • Certain registers ar e used as dedicated registers and pr ogrammers are not expected to use them for any other purpose.
68 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 3: MicroBlaze Application Binary Interface R Consider an example where Func1 calls Func2, which in turn calls Func3. The stack repr esentation at differ ent instances is depicted in Figure 3-2 .
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 69 UG081 (v6.0) June 1, 2006 1-800-255-7778 Memory Model R Figure 3-2: Stack Frame Calling Con v ention The caller function passes parameters to the callee function using either the registers (R5 through R10) or on its own stack frame.
70 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 3: MicroBlaze Application Binary Interface R Interrupt and Exception Handling MicroBlaze assumes certain addr ess locations for handling interrupts and exceptions as indicated in T able 3-3 .
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 71 UG081 (v6.0) June 1, 2006 1-800-255-7778 R Chapter 4 Micr oBlaze Instruction Set Ar chitectur e Summary This chapter provides a detailed guide to the Instr uction Set Architectur e of MicroBlaze™.
72 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R Formats MicroBlaze uses two instr uction formats: T ype A and T ype B. T ype A T ype A is used for register-r egister instructions.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 73 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R add Arithmetic Ad d Description The sum of the contents of registers rA and rB, is placed into r egister rD. Bit 3 of the instruction (labeled as K in the figure) is set to a one for the mnemonic addk.
74 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R addi Arithmetic Ad d Immediate Description The sum of the contents of registers rA and the value in the IMM field, sign-extended to 32 bits, is placed into register rD.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 75 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R and Logical AND Description The contents of register rA ar e ANDed with the contents of register rB; the r esult is placed into register rD.
76 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R andi Logial AND with Immediate Description The contents of register rA are ANDed with the value of the IMM field, sign-extended to 32 bits; the result is placed into r egister rD.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 77 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R andn Logical AND NO T Description The contents of register rA ar e ANDed with the logical complement of the contents of register rB; the r esult is placed into register rD.
78 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R andni Logical AND NO T with Immediate Description The IMM field is sign-extended to 32 bits.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 79 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R beq Branch if Equal Description Branch if rA is equal to 0, to the instruction located in the offset value of rB. The tar get of the branch will be the instruction at address PC + rB.
80 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R beqi Branch Immediate if Equal Description Branch if rA is equal to 0, to the instruction located in the offset value of IMM.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 81 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bge Branch if Greater or Equal Description Branch if rA is greater or equal to 0, to the instr uction located in the offset value of rB. The target of the branch will be the instr uction at address PC + rB.
82 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R bgei Branch Immediate if Greater or Equal Description Branch if rA is greater or equal to 0, to the instruction located in the of fset value of IMM.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 83 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bgt Branch if Greater Than Description Branch if rA is greater than 0, to the instr uction located in the offset value of rB. The tar get of the branch will be the instruction at address PC + rB.
84 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R bgti Branch Immediate if Greater Than Description Branch if rA is greater than 0, to the instr uction located in the offset value of IMM.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 85 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R ble Branch if Less or Equal Description Branch if rA is less or equal to 0, to the instruction located in the offset value of rB. The target of the branch will be the instr uction at address PC + rB.
86 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R blei Branc h Immediate if Less or Equal Description Branch if rA is less or equal to 0, to the instruction located in the offset value of IMM.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 87 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R blt Branch if Less Than Description Branch if rA is less than 0, to the instruction located in the offset value of rB. The tar get of the branch will be the instruction at address PC + rB.
88 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R blti Branc h Immediate if Less Than Description Branch if rA is less than 0, to the instruction located in the offset value of IMM.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 89 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bne Branch if Not Equal Description Branch if rA not equal to 0, to the instruction located in the offset value of rB. The tar get of the branch will be the instruction at address PC + rB.
90 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R bnei Branch Immediate if Not Equal Description Branch if rA not equal to 0, to the instruction located in the offset value of IMM.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 91 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R br Unconditional Branch Description Branch to the instruction located at address determined by rB. The mnemonics brld and brald will set the L bit.
92 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R Note The instructions brl and bral ar e not available. A delay slot must not be used by the following: IMM, branch, or break instructions.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 93 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bri Unconditional Branch Immediate Description Branch to the instruction located at address determined by IMM, sign-extended to 32 bits. The mnemonics brlid and bralid will set the L bit.
94 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R Notes The instructions brli and brali ar e not available. By default, T ype B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use as the immediate operand.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 95 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R brk Break Description Branch and link to the instruction located at address value in rB. The curr ent value of PC will be stored in rD. The BIP flag in the MSR will be set.
96 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R brki Break Immediate Description Branch and link to the instruction located at address value in IMM, sign-extended to 32 bits.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 97 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R bs Barrel Shift Description Shifts the contents of register rA by the amount specified in r egister rB and puts the result in register rD.
98 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R bsi Barrel Shift Immediate Description Shifts the contents of register rA by the amount specified by IMM and puts the r esult in register rD.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 99 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R cmp Integer Compare Description The contents of register rA is subtracted fr om the contents of register rB and the r esult is placed into register rD.
100 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R fadd Floating P oint Arithmetic Add Description The floating point sum of registers rA and rB, is placed into r egister rD.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 101 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R fr sub Reverse Floating P oint Arithmetic Subtraction Description The floating point value in rA is subtracted from the floating point value in rB and the result is placed into r egister rD.
102 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R fm ul Floating P oint Arithmetic Multiplication Description The floating point value in rA is multiplied with the floating point value in rB and the result is placed into r egister rD.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 103 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R fdiv Floating P oint Arithmetic Division Description The floating point value in rB is divided by the floating point value in rA and the result is placed into register rD.
104 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R fcmp Floating P oint Number Comparison Description The floating point value in rB is compared with the floating point value in rA and the comparison result is placed into r egister rD.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 105 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R Registers Altered • rD, unless an FP exception is generated, in which case the regis.
106 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R get get fr om fsl interface Description MicroBlaze will r ead from the FSLx interface and place the r esult in register rD.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 107 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R idiv Integer Divide Description The contents of register rB is divided by the contents of r egister rA and the result is placed into register rD.
108 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R imm Immediate Description The instruction imm loads the IMM value into a temporary r egister .
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 109 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R lb u Load Byte Unsigned Description Loads a byte (8 bits) from the memory location that r esults from adding the contents of registers rA and rB.
110 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R lb ui Load Byte Unsigned Immediate Description Loads a byte (8 bits) from the memory location that r esults from adding the contents of register rA with the value in IMM, sign-extended to 32 bits.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 111 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R lhu Load Halfwor d Unsigned Description Loads a halfword (16 bits) fr om the halfword aligned memory location that r esults from adding the contents of registers rA and rB.
112 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R lhui Load Halfwor d Unsigned Immediate Descript.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 113 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R lw Load W ord Description Loads a word (32 bits) fr om the word aligned memory location that r esults from adding the contents of registers rA and rB.
114 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R lw i Load W ord Immediate Description Loads a w.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 115 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R mfs Move Fr om Special Purpose Register Description Copies the contents of the special purpose register rS into r egister rD.
116 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R msr c lr Read MSR and clear bits in MSR Description Copies the contents of the special purpose register MSR into r egister rD.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 117 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R msr set Read MSR and set bits in MSR Description Copies the contents of the special purpose register MSR into r egister rD. Bit positions in the IMM value that are 1 ar e set in the MSR.
118 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R mts Move T o Special Purpose Register Description Copies the contents of register rD into the MSR or FSR.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 119 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R mu l Multiply Description Multiplies the contents of registers rA and rB and puts the r esult in register rD. This is a 32- bit by 32-bit multiplication that will produce a 64-bit r esult.
120 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R m uli Multiply Immediate Description Multiplies the contents of registers rA and the value IMM, sign-extended to 32 bits; and puts the result in r egister rD.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 121 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R or Logical OR Description The contents of register rA ar e ORed with the contents of register rB; the r esult is placed into register rD.
122 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R ori Logical OR with Immediate Description The contents of register rA ar e ORed with the extended IMM field, sign-extended to 32 bits; the result is placed into r egister rD.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 123 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R pcmpbf P attern Compare Byte Find Description The contents of register rA is bytewise compar ed with the contents in register rB.
124 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R pcmpeq P attern Compare Equal Description The contents of register rA is compar ed with the contents in register rB.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 125 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R pcmpne P attern Compare Not Equal Description The contents of register rA is compar ed with the contents in register rB.
126 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R put put to fsl interface Description MicroBlaze will write the value fr om register rA to the FSLx interface.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 127 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R r sub Arithmetic Reverse Subtract Description The contents of register rA is subtracted fr om the contents of register rB and the r esult is placed into register rD.
128 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R r subi Arithmetic Reverse Subtract Immediate Description The contents of register rA is subtracted fr om the value of IMM, sign-extended to 32 bits, and the result is placed into r egister rD.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 129 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R r tbd Return from Break rn from Interrupt Description Return from br eak will branch to the location specified by the contents of rA plus the IMM field, sign-extended to 32 bits.
130 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R r tid Return from Interrupt rn from Interrupt Description Return from interr upt will branch to the location specified by the contents of rA plus the IMM field, sign-extended to 32 bits.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 131 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R r ted Return from Exception Description Return from exception will branch to the location specified by the contents of rA plus the IMM field, sign-extended to 32 bits.
132 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R r tsd Return from Subr outine Description Return from subr outine will branch to the location specified by the contents of rA plus the IMM field, sign-extended to 32 bits.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 133 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R sb Store Byte Description Stores the contents of the least significant byte of register rD, into the memory location that results fr om adding the contents of registers rA and rB.
134 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R sbi Store Byte Immediate Description Stores the.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 135 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R se xt16 Sign Extend Halfwor d Description This instruction sign-extends a halfwor d (16 bits) into a word (32 bits). Bit 16 in rA will be copied into bits 0-15 of rD.
136 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R se xt8 Sign Extend Byte Description This instruction sign-extends a byte (8 bits) into a word (32 bits).
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 137 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R sh Store Halfwor d Description Stores the contents of the least significant halfwor d of register rD, into the halfwor d aligned memory location that results fr om adding the contents of registers rA and rB.
138 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R shi Store Halfwor d Immediate Description Store.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 139 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R sra Shift Right Arithmetic Description Shifts arithmetically the contents of register rA, one bit to the right, and places the r esult in rD.
140 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R sr c Shift Right with Carry Description Shifts the contents of register rA, one bit to the right, and places the r esult in rD.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 141 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R srl Shift Right Logical Description Shifts logically the contents of register rA, one bit to the right, and places the r esult in rD. A zero is shifted in the shift chain and placed in the most significant bit of rD.
142 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R sw Store W ord Description Stores the contents of r egister rD, into the word aligned memory location that r esults from adding the contents of registers rA and rB.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 143 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R sw i Store W ord Immediate Description Stores the contents of r egister rD, into the word aligned memory location that r esults from adding the contents of registers rA and the value IMM, sign-extended to 32 bits.
144 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R wdc Write to Data Cache Description W rite into the data cache tag. The register rB value is not used.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 145 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R wic Write to Instruction Cache Description W rite into the instruction cache tag. The r egister rB value is not used. Register rA contains the instruction addr ess.
146 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R xor Logical Exclusive OR Description The contents of register rA ar e XORed with the contents of register rB; the r esult is placed into register rD.
MicroBlaze Pr ocessor Reference Guide www .xilinx.com 147 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions R xori Logical Exclusive OR with Immediate Description The IMM field is extended to 32 bits by concatenating 16 0-bits on the left.
148 www .xilinx.com MicroBlaze Pr ocessor Reference Guide 1-800-255-7778 UG081 (v6.0) June 1, 2006 Chapter 4: MicroBlaze Instruction Set Ar chitecture R.
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