Benutzeranleitung / Produktwartung 3.2 des Produzenten Xilinx
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LogiCORE™ IP CAN v3.2 Getting Star ted Guide UG186 April 19, 2010.
CAN Getting Started Guide www .xilinx.com UG186 Apr il 19, 2010 Xilinx is providing this product documentation, hereinafter “Inf or mation, ” to you “AS IS” with no warr anty o f an y kind, express or implied.
CAN Getting Started Guide www .xilinx.com 3 UG186 Apr il 19, 2010 Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Preface: About This Guide Guide Contents . . . .
4 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design Directory and File Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 <project directory> .
CAN Getting Started Guide www .xilinx.com 5 UG186 Apr il 19, 2010 Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Quick Start Example Design Figure 3-1: Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010.
CAN Getting Started Guide www .xilinx.com 7 UG186 Apr il 19, 2010 Pr eface About This Guide The CAN v3.2 Getting Started Guide provides information about generating the LogiCORE™ IP CAN core, customizing and si mulating the cor e with the provide d example design, and r unning the design files thr ough implementation us ing the Xilinx tools.
8 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Pref ace: About This Guide Online Document The following li nking conventi ons ar e used in this document: Italic font V ariables in a s yntax statement for which you must supply values ngdbuild design_name References to other manuals See the User Guide for details.
CAN Getting Started Guide www .xilinx.com 9 UG186 Apr il 19, 2010 Chapter 1 Intr oduction The LogiCORE™ IP CAN v3. 2 core is a compact, full-featur ed targeted design platform that conforms to ISO 1 1898-1 , CAN2.0A and CAN2.0B standards. Bit rates of up to 1 M bps are suppor ted.
10 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 1: Introd uction Recommended Design Experience Although the CAN core is a fully-veri fied targ eted design platform, the challenge associated with implementing a complete CAN design vari es, depending on the application requir ements.
CAN Getting Started Guide www .xilinx.com 11 UG186 Apr il 19, 2010 Chapter 2 Licensing the Cor e This chapter provides instructions for obtaining a license for the CAN core, which you mu s t d o be f ore u si n g t h e c ore i n y o ur d es i gn s .
12 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 2: Licensing the Core Full The Full license k ey is available when y ou pur chase the cor e and provides full acce ss to all .
CAN Getting Started Guide www .xilinx.com 13 UG186 Apr il 19, 2010 Chapter 3 Quick Start Example Design This chapter pr ovides instructions to gene rate a CAN core quickly , run the design thr ough implementation with the Xilinx tools, and si mulate the example design using the provided demonstration test bench.
14 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 3: Quic k Start Example Design Generating the Core This section describes how to generate a CAN core with default values using the Xilinx CORE Generator™ tool. T o generate the core : 1.
CAN Getting Started Guide www .xilinx.com 15 UG186 Apr il 19, 2010 Implementing th e Example Design 7. In the Component Name field , enter a name for the cor e instance. This example uses the name quickstart . 8. After selecting the parameters from the GUI screens, click Finish.
16 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 3: Quic k Start Example Design Functional Simulation This section provide s instructions for running a functional simulation of the CAN core using either VHDL or V erilog. Functional simulation models ar e provided when the cor e is generated.
CAN Getting Started Guide www .xilinx.com 17 UG186 Apr il 19, 2010 Chapter 4 Detailed Example Design This chapter provides detailed information about the example design, including a description of fil.
18 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design Directory and File Contents The CAN v3.2 core dir ectories and their asso ciated files are defined in the following sections. <project director y> The <project dir ectory> contains all the CORE Generator software pr oject files.
CAN Getting Started Guide www .xilinx.com 19 UG186 Apr il 19, 2010 Directory and File Contents <component_name>e xample design The example design dir ectory contains the ex ample design files pr ovided with the core. <component_name>/doc The doc directory contains the PDF documentation provided with the core .
20 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design <component_name>/implement The implement directory contains the core impl ementation script fi les. Generated for Full- Sy s te m Ha rd w are E va l ua t io n an d F ul l l ic en s e ty p es .
CAN Getting Started Guide www .xilinx.com 21 UG186 Apr il 19, 2010 Directory and File Contents <component_name>/sim ulation/functional The functional directory contains functional simulation scripts pr ovided with the core.
22 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design simulation/timing The timing simulation directory is generated only for Full-System Hardware Evaluation and Full-license ty pes.
CAN Getting Started Guide www .xilinx.com 23 UG186 Apr il 19, 2010 Implementati on Scripts Implementation Scripts Note: Present only with a Full license. The implementation script is either a shell scri pt(.s h) or batch file (. bat) that pr ocesses the example design through the Xilinx tool flow .
24 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design Timing Simulation Note: Present only with a Full license. The test scripts ar e a ModelSim or a Cadence IES macro that automates the simulation of the test bench.
CAN Getting Started Guide www .xilinx.com 25 UG186 Apr il 19, 2010 Demonstration T est Benc h Demonstration T est Bench Figur e 4-2 illustrates the demonstration test be nch. T est Bench Functionality The demonstration test bench is a straightforw ard VHDL or V erilog file to exer cise the example design and the core itself.
26 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design • Five messages are written in seque nce: 1. The first message is written to the TXHPB and is a standar d data frame. 2. The second messag e is written t o the TX FIFO a nd is a stand ar d data frame.
CAN Getting Started Guide www .xilinx.com 27 UG186 Apr il 19, 2010 Demonstration T est Benc h • After the fourth message is transmitted and received, the Interrupt Enable Register is written to enable interr upts for TXOK, RXOK and TXBFLL. This regis t er is re ad fr om and the value r ead is compar ed with the value written.
28 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design.
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