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TMS320F20x/F24x DSP Embedded Flash Memory T echnical Reference This document contains preliminary data current as of publication date and is subject to change without notice.
IMPORT ANT NOTICE T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify , before placing orders, that information being relied on is current and complete.
iii PRELIMINARY Preface Read This First About This Manual This reference guide describes the operation of the embedded flash EEPROM module on the TMS320F20x/F24x digital signal processor (DSP) devices and provides sample code that you can use in developing your own software.
PRELIMINARY iv PRELIMINARY If you are looking for in- formation about: T urn to these locations: Over-erasure (depletion) and recovery Section 1.1, Basic Concepts of Flash Memory T echnology Section 2.7, Recovering From Over-Erasure (Flash-Write Operation) Section 3.
Related Documentation From T exas Instruments PRELIMINARY v Read This First PRELIMINARY Related Documentation From T exas Instruments The following books describe the ’F20x/24x and related support tools. T o ob- tain a copy of any of these TI documents, call the T exas Instruments Literature Response Center at (800) 477–8924.
Related Documentation From T exas Instruments PRELIMINARY vi PRELIMINARY TMS320C2xx C Source Debugger User ’s Guide (literature number SPRU151) tells you how to invoke the ’C2xx emulator and simulator ver- sions of the C source debugger interface.
If Y ou Need Assistance . . . PRELIMINARY vii Read This First PRELIMINARY If Y ou Need Assistance . . . - World-W ide Web Sites TI Online http://www .ti.com Semiconductor Product Information Center (PIC) http://www .ti.com/sc/docs/pic/home.htm DSP Solutions http://www .
PRELIMINARY viii PRELIMINARY.
Contents ix Contents 1 Introduction 1 Ć 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Discusses basic flash memory technology; summarizes the features and benefits of the TMS320F20x/F24x flash module 1.
Contents x A.1.1 Header File for Constants and V ariables, SV AR20.H A Ć 2 . . . . . . . . . . . . . . . . . . . . . A.1.2 Clear Algorithm, SCLR20.ASM A Ć 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1.3 Erase Algorithm, SERA20.
Figures xi Contents Figures 1–1 TMS320F20x/F24x Program Space Memory Maps 1 Ć 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Flash Memory Logic Levels During Programming and Erasing 2 Ć 4 . . . . . . . . . . . . . . . . . .
T ables xii T ables 1–1 TMS320 Devices With On-Chip Flash EEPROM 1 Ć 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Operations that Modify the Contents of the Flash Array 2 Ć 4 . . . . . . . . . . . . . . . . . . . . .
1-1 Introduction The TMS320F20x/F24x digital signal processors (DSPs) contain on-chip flash EEPROM (electrically-erasable programmable read-only memory). The em- bedded flash memory provides an attractive alternative to masked program ROM. Like ROM, flash memory is nonvolatile, but it has an advantage over ROM: in-system reprogrammability .
Basic Concepts of Flash Memory T echnology PRELIMINARY 1-2 PRELIMINARY 1.1 Basic Concepts of Flash Memory T echnology The term flash in this EEPROM technology refers to the speed of some of the operations performed on the memory (these operations will be described in greater detail later in this document).
TMS320F20x/F24x Flash Module PRELIMINARY 1-3 Introduction PRELIMINARY 1.2 TMS320F20x/F24x Flash Module The ’F20x/F24x flash EEPROM is implemented with one or two independent flash memory modules of 8K or 16K words.
TMS320F20x/F24x Flash Module PRELIMINARY 1-4 PRELIMINARY Simplified memory maps for the program space of the TMS320F20x/F24x de- vices are shown in Figure 1–1 to illustrate the location of the flash modules.
Benefits of Embedded Flash Memory in a DSP System PRELIMINARY 1-5 Introduction PRELIMINARY 1.3 Benefits of Embedded Flash Memory in a DSP System The circuitry density of flash memory is about half that of conventional EE- PROM memory , making it possible to approach DRAM densities with flash memory .
PRELIMINARY 1-6 PRELIMINARY.
2-1 Flash Operations and Control Registers The operations that modify the contents of the ’F20x/F24x flash array are per- formed in software through the use of dedicated programming algorithms. This chapter introduces the operations performed by these algorithms and explains the role of the control registers in this process.
Operations that Modify the Contents of the ’F20x/F24x Flash Array PRELIMINARY 2-2 PRELIMINARY 2.1 Operations that Modify the Contents of the ’F20x/F24x Flash Array Operations that modify the conte.
Operations that Modify the Contents of the ’F20x/F24x Flash Array PRELIMINARY 2-3 Flash Operations and Control Registers PRELIMINARY This procedure is discussed in complete detail in Chapter 3.
Operations that Modify the Contents of the ’F20x/F24x Flash Array PRELIMINARY 2-4 PRELIMINARY Figure 2–1. Flash Memory Logic Levels During Programming and Erasing Erase operation Depletion Mode Lo.
Accessing the Flash Module PRELIMINARY 2-5 Flash Operations and Control Registers PRELIMINARY 2.2 Accessing the Flash Module In addition to the flash memory array , each flash module has four registers that control operations on the flash array .
Accessing the Flash Module PRELIMINARY 2-6 PRELIMINARY Figure 2–2. Memory Maps in Register and Array Access Modes SEG_CTR register TST register W ADRS register WDA T A register Flash memory array Flash access control register (single bit) MODE = 1: Array-access mode MODE = 0: Register access mode 0100 .
Accessing the Flash Module PRELIMINARY 2-7 Flash Operations and Control Registers PRELIMINARY Although the function is the same, the access control registers of the ’F206 de- vice are mapped at different addresses from that of the ’F24x devices, and their values are modified in a different way .
Flash Module Control Registers PRELIMINARY 2-8 PRELIMINARY 2.3 Flash Module Control Registers T able 2–2 lists the control registers and their relative addresses within the four locations that repeat throughout the module’s address range. T able 2–2.
Flash Module Control Registers PRELIMINARY 2-9 Flash Operations and Control Registers PRELIMINARY T able 2–3. Segment Control Register Field Descriptions Bits Name Description 15–8 SEG7–SEG0 Segment enable bits.
Flash Module Control Registers PRELIMINARY 2-10 PRELIMINARY T able 2–4. Flash Array Segments Summary SEG7–SEG0 Bits ’F206/F240 Flash Module † ’F241 / F24 3 Arr ay Seg m e nt 15 14 13 12 11 1.
Flash Module Control Registers PRELIMINARY 2-1 1 Flash Operations and Control Registers PRELIMINARY 2.3.4 Write Data Register (WDA T A) The write data register (WDA T A) is a 16-bit register that contains the latched write data for a programming operation.
Read Modes PRELIMINARY 2-12 PRELIMINARY 2.4 Read Modes The ’F20x/F24x flash module uses four read modes and corresponding sets of reference levels: Standard V erify 0s (VER0) V erify 1s (VER1) Inverse-erase Read mode selection is accomplished through the verify bits (bits 3 and 4) in SEG_CTR during execution of the algorithms.
Program Operation PRELIMINARY 2-13 Flash Operations and Control Registers PRELIMINARY 2.5 Program Operation The program operation of the ’F20x/F24x flash module loads the application- specific data (a pattern of 0s) into the flash array . The basis of the operation is applying a program pulse to a single word of flash memory .
Erase Operation PRELIMINARY 2-14 PRELIMINARY 2.6 Erase Operation The erase operation of the ’F20x/F24x flash module prepares the flash array for programming and enables reprogrammability of the flash array . Before the array can be erased, all bits must be programmed to 0s.
Recovering From Over-Erasure (Flash-Write Operation) PRELIMINARY 2-15 Flash Operations and Control Registers PRELIMINARY 2.7 Recovering From Over-Erasure (Flash-Write Operation) Generally , not all bits in the flash array have the same amount of charge re- moved with each erase pulse.
Reading From the Flash Array PRELIMINARY 2-16 PRELIMINARY 2.8 Reading From the Flash Array Once the array is programmed, it is read in the same manner as other memory devices on the DSP memory interface. The flash module operates with zero wait states.
3-1 Algorithm Implementations and Software Considerations This chapter discusses the implementations of the algorithms for performing the operations described in the previous chapter . It also discusses items you must consider when incorporating the algorithms into your ’F20x/F24x DSP application code.
How the Algorithms Fit Into the Program-Erase-Reprogram Flow PRELIMINARY 3-2 PRELIMINARY 3.1 How the Algorithms Fit Into the Program-Erase-Reprogram Flow The algorithms discussed in this chapter can be used to reprogram the ’F20x/F24x flash module multiple times.
How the Algorithms Fit Into the Program-Erase-Reprogram Flow PRELIMINARY 3-3 Algorithm Implementations and Software Considerations PRELIMINARY Figure 3–1.
Programming (or Clear) Algorithm PRELIMINARY 3-4 PRELIMINARY 3.2 Programming (or Clear) Algorithm The programming algorithm sequentially writes any number of addresses with a specified bit pattern.This algorithm is used to program application code or data into the flash array .
Programming (or Clear) Algorithm PRELIMINARY 3-5 Algorithm Implementations and Software Considerations PRELIMINARY The main feature of the program/clear algorithm is the concept of program- ming an entire row of bits in a group. The ’F20x/F24x flash array is organized in rows of 32 words.
Programming (or Clear) Algorithm PRELIMINARY 3-6 PRELIMINARY Figure 3–3. Programming or Clear Algorithm Flow Same row Device failure Continue Current address > end address? No Ye s Row_done = tru.
Programming (or Clear) Algorithm PRELIMINARY 3-7 Algorithm Implementations and Software Considerations PRELIMINARY Another important consideration is the total amount of time required to do the programming.
Programming (or Clear) Algorithm PRELIMINARY 3-8 PRELIMINARY T able 3–1. Steps for V erifying Programmed Bits and Applying One Program or Clear Pulse (Continued) Step Description Action 7 Mask the data to program lower byte. Mask any bits in the lower byte that do not require programming (are al- ready read as zero), and mask off upper byte.
Programming (or Clear) Algorithm PRELIMINARY 3-9 Algorithm Implementations and Software Considerations PRELIMINARY Before each program pulse is applied, a read of the byte is performed to deter- mine which bits have reached the programmed level. Any bits that have reached the programmed level are masked (set to 1 in the WDA T A register).
Erase Algorithm PRELIMINARY 3-10 PRELIMINARY 3.3 Erase Algorithm The erase algorithm follows the clear algorithm in executing the entire initial- ization flow .
Erase Algorithm PRELIMINARY 3-1 1 Algorithm Implementations and Software Considerations PRELIMINARY T able 3–2. Steps for Applying One Erase Pulse Step Action Description 1 Power up the V CCP pin. Set V CCP pin to V DD. If the V CCP pin for the flash module to be erased is not set to V DD , then the array will not be erased properly .
Erase Algorithm PRELIMINARY 3-12 PRELIMINARY 4) The actual address is restored. 5) The contents of the restored address are read. The advantage of this approach is that it forces the worst-case switching condi- tion on the flash addressing logic during the reads, thus improving the margin of the erase.
Erase Algorithm PRELIMINARY 3-13 Algorithm Implementations and Software Considerations PRELIMINARY Figure 3–5. Erase Algorithm Flow Program array check Depletion Ye s No All 32 words = 0000h? Read f.
Flash-Write Algorithm PRELIMINARY 3-14 PRELIMINARY 3.4 Flash-W rite Algorithm The flash-write operation recovers bits in depletion mode, which can be caused by over-erasure. The flash-write algorithm’s place in the overall flow is highlighted in Figure 3–6.
Flash-Write Algorithm PRELIMINARY 3-15 Algorithm Implementations and Software Considerations PRELIMINARY T able 3–3. Steps for Applying One Flash-Write Pulse Steps Action Description 1 Power up the V CCP pin.
Flash-Write Algorithm PRELIMINARY 3-16 PRELIMINARY Figure 3–7. Flash-Write Algorithm Flow Start Depletion check No Ye s No Ye s Flash-write pulse count ≥ Max † ? Device failure Apply one flash-w.
Flash-Write Algorithm PRELIMINARY 3-17 Algorithm Implementations and Software Considerations PRELIMINARY The CPU frequency range for the application is an important consideration for the depletion test, as well as for the program and erase operations.
PRELIMINARY 3-18 PRELIMINARY.
A-1 Appendix A Assembly Source Listings and Program Examples The flash array is erased and programmed by code running on the DSP core. This code can originate from off-chip memory or can be loaded into on-chip RAM.
Assembly Source for Algorithms PRELIMINARY A-2 PRELIMINARY A.1 Assembly Source for Algorithms The algorithm source files implement the flows given in Chapter 3. Each algo- rithm is written as an assembly language subroutine, beginning with a label at an entry point and ending with a return instruction.
Assembly Source for Algorithms PRELIMINARY A-3 Assembly Source Listings and Program Examples PRELIMINARY ************************************************************** ** Variable declaration file ** * ** * TMS320F2XX Flash Utilities. ** * Revision: 2.
Assembly Source for Algorithms PRELIMINARY A-4 PRELIMINARY *CONSTANTS * ********************************************************* *Conditional assembly variable for F24X vs F206. * *If F24X = 1, then assemble for F24X; otherwise, * *assemble for F206.
Assembly Source for Algorithms PRELIMINARY A-5 Assembly Source Listings and Program Examples PRELIMINARY A.1.2 Clear Algorithm, SCLR20.ASM This code is an implementation of the clear (programming) algorithm de- scribed in section 3.
Assembly Source for Algorithms PRELIMINARY A-6 PRELIMINARY * programmed bits. For example, if the flash is programmed * * using a CLKOUT period of 50 ns, the flash can be read back * reliably over the CLKOUT period range of 50 ns to 150 ns * * (6.67 MHz–20 MHz).
Assembly Source for Algorithms PRELIMINARY A-7 Assembly Source Listings and Program Examples PRELIMINARY SACL FL_ST ;Save array start address. LACL FL_ADRS ;Get segment start address. NEWROW ;********Begin a new row.* SACL BASE_1 ;Save row start address.
Assembly Source for Algorithms PRELIMINARY A-8 PRELIMINARY * SPAD2 Flash program + EXE command. * ************************************************************* EXE_PGM ;* CALL ARRAY ;ACCESS ARRAY * *L.
Assembly Source for Algorithms PRELIMINARY A-9 Assembly Source Listings and Program Examples PRELIMINARY TBLW SPAD1 ;EXECUTE COMMAND * LAR AR6,#D10 ;SET DELAY * CALL DELAY,*,AR6 ;WAIT * CALL ARRAY ;AC.
Assembly Source for Algorithms PRELIMINARY A-10 PRELIMINARY A.1.3 Erase Algorithm, SERA20.ASM This code is an implementation of the erase algorithm described in section 3.
Assembly Source for Algorithms PRELIMINARY A-1 1 Assembly Source Listings and Program Examples PRELIMINARY * The erase pulse duration is 7ms, and a maximum of ** * 1000 pulses is applied to the array.
Assembly Source for Algorithms PRELIMINARY A-12 PRELIMINARY CLRC OVM ;Disable overflow mode. LACL SEG_ST ;Get segment start address. AND #04000h ;Get array start address. SACL FL_ST ;Save array start address. OR #03FFFh ;Get array end address. SACL FL_END ;Save array end address.
Assembly Source for Algorithms PRELIMINARY A-13 Assembly Source Listings and Program Examples PRELIMINARY ***** If here, then an error has occurred. EXIT SPLK #1,ERROR ;Update error flag SPLK #STOP,BASE_0 ;Stop command. CALL SET_MODE ;Disable any flash cmds.
Assembly Source for Algorithms PRELIMINARY A-14 PRELIMINARY * * * The following resources are used for temporary storage: * * BASE_0 Flash STOP command, and FFFF for WDATA.
Assembly Source for Algorithms PRELIMINARY A-15 Assembly Source Listings and Program Examples PRELIMINARY A.1.4 Flash-Write Algorithm, SFL W20.ASM This code is an implementation of the flash-write algorithm described in sec- tion 3.
Assembly Source for Algorithms PRELIMINARY A-16 PRELIMINARY * BASE_3 Used for EXE + flw cmd * ************************************************************** .include ”svar20.h” ;defines variables for flash0 ;or for flash1 array * MAX_FLW .set 10000 ;Allow only 10000 flw pulses.
Assembly Source for Algorithms PRELIMINARY A-17 Assembly Source Listings and Program Examples PRELIMINARY BCND FL_WRITE, NEQ ;If ACC<>0, then flwrite. *Else, continue until until done with row. BANZ NEXT_IVERS ;Loop 32 times. SPLK #STOP,BASE_0 ;Flash STOP command.
Assembly Source for Algorithms PRELIMINARY A-18 PRELIMINARY LAR AR0,#MAX_FLW CMPR 2 ;If AR1>MAX_FLW then BCND EXIT,TC ;Fail, don’t continue recovery. B INV_ERASE ;Else, perform iverase again. ************************************************** * SET_MODE: This routine sets the flash in the * * mode specified by the contents of BASE_0.
Assembly Source for Algorithms PRELIMINARY A-19 Assembly Source Listings and Program Examples PRELIMINARY A.1.5 Programming Algorithm, SPGM20.ASM This code is an implementation of the program algorithm described in section 3.
Assembly Source for Algorithms PRELIMINARY A-20 PRELIMINARY * bits. For example, if the flash is programmed using a * * CLKOUT period of 50 ns, the flash can be reliably read * * back over the CLKOUT period range of 50 ns to 150 ns * * (6.67MHz–20 MHz).
Assembly Source for Algorithms PRELIMINARY A-21 Assembly Source Listings and Program Examples PRELIMINARY * BASE_3 Used for buffer/row start addr * * BASE_4 Used for destination end addr * * BASE_5 Us.
Assembly Source for Algorithms PRELIMINARY A-22 PRELIMINARY BCND EXIT,TC ;fail, don’t continue. B SAMEROW ;else, go to beginning ;of same row. ** If row done, then check if Array done. * ROW_DONE LACL FL_ADRS ;Check if end of array. SUB BASE_4 ;Subtract end addr.
Assembly Source for Algorithms PRELIMINARY A-23 Assembly Source Listings and Program Examples PRELIMINARY SPLK #04000h,FL_ST ;FL_ST = FLASH1 CTRL REGS FL0 RET ************************************************************* .
Assembly Source for Algorithms PRELIMINARY A-24 PRELIMINARY LACL FL_ST ;ACC => FLASH * SPLK #VER0,SPAD1 ;ACTIVATE VER0 * TBLW SPAD1 ;EXECUTE COMMAND * LAR AR6,#D10 ;SET DELAY * CALL DELAY,*,AR6 ;WA.
Assembly Source for Algorithms PRELIMINARY A-25 Assembly Source Listings and Program Examples PRELIMINARY A.1.6 Subroutines Used By All Four Algorithms, SUTILS20.ASM This assembly file includes two subroutines that change the flash module ac- cess mode and one subroutine that performs software delays.
Assembly Source for Algorithms PRELIMINARY A-26 PRELIMINARY SPLK #0000h,SPAD2 ***********The next instruction is for F240 only************* .if F24X = 1 ;Assemble for F24X only. OUT SPAD2,F24X_ACCS ;Enable F240 flash reg mode. ;SPAD1 is dummy value. .
C-Callable Interface to Flash Algorithms PRELIMINARY A-27 Assembly Source Listings and Program Examples PRELIMINARY A.2 C-Callable Interface to Flash Algorithms The two functions erase() and program() are intended for in-application pro- gramming of the ’F20x/F24x flash module.
C-Callable Interface to Flash Algorithms PRELIMINARY A-28 PRELIMINARY ;**Variables included from flash algorithms. .include ”svar20.h” ;Variable declarations .ref GCLR ;References clear algo. .ref GPGMJ ;References program algo. .ref GERS ;References erase algo.
C-Callable Interface to Flash Algorithms PRELIMINARY A-29 Assembly Source Listings and Program Examples PRELIMINARY * passes, the flash is ready to be reprogrammed. The * * operations are performed on the segments of the flash * * module described by the parameter list: * * 1)PROTECT–defines which flash segments to protect.
C-Callable Interface to Flash Algorithms PRELIMINARY A-30 PRELIMINARY ADD #1 ;Increment fail count. SACL ERS_COUNT ;Save new count. SUB #10 ;CHECK for max of 10. BCND ers_error,GT ;If ers_cout>10 then hard fail. CALL FLWS ;Else, try to recover from depletion.
C-Callable Interface to Flash Algorithms PRELIMINARY A-31 Assembly Source Listings and Program Examples PRELIMINARY ;Begin C Preprocessing POPD *+ ; pop return address, push on s/w stack sar ar0,*+ ; .
Sample Assembly Code to Erase and Reprogram the TMS320F206 PRELIMINARY A-32 PRELIMINARY A.3 Sample Assembly Code to Erase and Reprogram the TMS320F206 The algorithm files can be used from assembly in a straightforward manner . In general, the algorithms can reside anywhere in program space.
Sample Assembly Code to Erase and Reprogram the TMS320F206 PRELIMINARY A-33 Assembly Source Listings and Program Examples PRELIMINARY ;data section used for * ;temporary variables, and * ;for passing parameters * ;to the flash algorithms. * ********************************************************* PROTECT .
Sample Assembly Code to Erase and Reprogram the TMS320F206 PRELIMINARY A-34 PRELIMINARY SUB #10 ;CHECK for max of 10. BCND ers_error,GT ;If ers_cout>10 then hard ;fail. CALL FLWS ;Else, try to recover from ;depletion. LACL ERROR ;Check for FLASH–WRITE error.
Sample Assembly Code to Erase and Reprogram the TMS320F206 PRELIMINARY A-35 Assembly Source Listings and Program Examples PRELIMINARY prg_error: ******************************************************** ** If here, then an error has occurred during ** ** programming.
Sample Assembly Code to Erase and Reprogram the TMS320F206 PRELIMINARY A-36 PRELIMINARY PAGE 1: /* DM – Data memory */ BLK_B2: origin = 0x60,length = 0x20 /*BLOCK B2 */ DSARAM: origin = 0xc00, lengt.
Sample C Code to Erase and Reprogram the TMS320F206 PRELIMINARY A-37 Assembly Source Listings and Program Examples PRELIMINARY A.4 Sample C Code to Erase and Reprogram the TMS320F206 Because the algorithm implementations do not follow the C-calling convention of the ’C2000 C environment, they cannot be used directly from C.
Sample C Code to Erase and Reprogram the TMS320F206 PRELIMINARY A-38 PRELIMINARY { /*Flash fails programming, EXIT*/ while(1){} /*Spin here forever*/ } } else { /*Flash fails erase, EXIT*/ while(1){} /*Spin here forever*/ } } A.
Sample C Code to Erase and Reprogram the TMS320F206 PRELIMINARY A-39 Assembly Source Listings and Program Examples PRELIMINARY FLASH0: origin = 0x0000, length = 0x3fff FLASH1: origin = 0x4000, length .
Sample Assembly Code to Erase and Reprogram the TMS320F240 PRELIMINARY A-40 PRELIMINARY A.5 Sample Assembly Code to Erase and Reprogram the TMS320F240 The algorithm files can be used from assembly in a straightforward manner . In general, the algorithms can reside anywhere in program space.
Sample Assembly Code to Erase and Reprogram the TMS320F240 PRELIMINARY A-41 Assembly Source Listings and Program Examples PRELIMINARY ;**Variables included from flash algorithms. .include ”svar20.h” ;Variable declarations .ref GCLR ;References clear algo.
Sample Assembly Code to Erase and Reprogram the TMS320F240 PRELIMINARY A-42 PRELIMINARY F240INIT: ;Set Data Page pointer to page 1 of the ;peripheral frame LDP #DP_PF1 ;Page DP_PF1 includes WET throug.
Sample Assembly Code to Erase and Reprogram the TMS320F240 PRELIMINARY A-43 Assembly Source Listings and Program Examples PRELIMINARY depletion: LACL ERS_COUNT ;Get erase fail count. ADD #1 ;Increment fail count. SACL ERS_COUNT ;Save new count. SUB #10 ;CHECK for max of 10.
Sample Assembly Code to Erase and Reprogram the TMS320F240 PRELIMINARY A-44 PRELIMINARY ************************************************************** ** Now that the data to be programmed is ready, the ** ** programming algorithm is invoked. Note: Four parameters ** ** must be initialized before calling the algorithm.
Sample Assembly Code to Erase and Reprogram the TMS320F240 PRELIMINARY A-45 Assembly Source Listings and Program Examples PRELIMINARY A.5.2 Linker Command File for TMS320F240 Sample Assembly Code /************************************************************/ /* Filename: ASMEXA24.
Sample Assembly Code to Erase and Reprogram the TMS320F240 PRELIMINARY A-46 PRELIMINARY /*All these sections are for flash programming.*/ fl_prg : {} > EXTRAM PAGE 0 /**Programming Algorithm*****/ .
Using the Algorithms With C Code to Erase and Reprogram the ’F240 PRELIMINARY A-47 Assembly Source Listings and Program Examples PRELIMINARY A.6 Using the Algorithms With C Code to Erase and Reprogr.
Using the Algorithms With C Code to Erase and Reprogram the ’F240 PRELIMINARY A-48 PRELIMINARY extern int erase(); /* Declare external func for flash erase.
Using the Algorithms With C Code to Erase and Reprogram the ’F240 PRELIMINARY A-49 Assembly Source Listings and Program Examples PRELIMINARY /************************Command Line Options**************************/ –cr /*Use Ram init model. */ –heap 0x0 /*No heap needed for this example.
Using the Algorithms With C Code to Erase and Reprogram the ’F240 PRELIMINARY A-50 PRELIMINARY .bss :{} > B1 PAGE 1 .cinit :{} > B1 PAGE 1 .const : load = EXTRAM PAGE 0, run = DSRAM PAGE 1 { /* GET RUN ADDRESS */ __const_run = .; /* MARK LOAD ADDRESS */ *(.
Using the Algorithms With C Code to Erase and Reprogram the ’F240 PRELIMINARY A-51 Assembly Source Listings and Program Examples PRELIMINARY OR #06fh ; set WDDIS bit and WDCHK2:0 bits, WDCLK to max. SACL WDCR ; write ACC out to WDTCR ***************************************************************************** * Step 9.
Using the Algorithms With C Code to Erase and Reprogram the ’F240 PRELIMINARY A-52 PRELIMINARY * Step 5. begin code that will initialize the ’240 registers * **************************************.
Index PRELIMINARY Index-1 PRELIMINARY Index A access modes code for changing A-25 array access 2-5, 2-10, 2-1 1, 2-16, 3-8 register access 2-5, 2-10, 2-1 1, 3-1 1 access–control register 2-5 to 2-7 .
Index PRELIMINARY Index-2 PRELIMINARY erase algorithm assembly code (SERA2x.ASM) A-10 described 3-10 to 3-13 flow diagram 3-13 in overall flow 3-10 erase() function (C code listing) A-27 erase operati.
Index PRELIMINARY Index-3 PRELIMINARY M margin determining 3-5, 3-1 1 ensuring data retention 1-2 improving 3-12 in programming 2-13 restoring after flash–write operation 2-15 special read modes for.
Index PRELIMINARY Index-4 PRELIMINARY subroutines used by all algorithms (SU- TILS2x.ASM) A-25 SUTILS2x.ASM file (code for subroutines) A-25 SV AR2x.H file (header file for constants and vari- ables) .
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