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TMS320C64x DSP V ideo Port /VCXO Interpolated Control (VIC) Port R e f e r e n c e G u i d e Literature Number: SPRU629 April 2003.
IMPORT ANT NOTICE T exas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
iii Contents SPRU629 Preface Read This First About This Manual This document describes the video port and VCXO interpolated control (VIC) port in the digital signal processors (DSPs) of the TMS320C6000 DSP family . Notational Conventions This document uses the following conventions.
T rademarks iv SPRU629 Code Composer Studio Application Programming Interface Reference Guide (literature number SPRU321) describes the Code Composer Studio application programming interface (API), which allows you to program custom plug-ins for Code Composer .
Contents v Contents SPRU629 Contents 1 Overview 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides an overview of the video port peripheral in the digital signal processors (DSPs) of the TMS320C6000 DSP family .
Contents vi SPRU629 2.6 Video Port Throughput and Latency 2-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 Video Capture Throughput 2-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents vii Contents SPRU629 3.8 TSI Capture Mode 3-37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 TSI Capture Features 3-37 . . . . . . . . . . . . . . . . . . . . . . . . .
Contents viii SPRU629 4 Video Display Port 4-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Discusses the video display port. 4.1 Video Display Mode Selection 4-2 . . . .
Contents ix Contents SPRU629 4.12.6 Video Display Field 1 V ertical Blanking End Register (VDVBLKE1) 4-64 . . . . . . . . 4.12.7 Video Display Field 2 V ertical Blanking Start Register (VDVBLKS2) 4-65 . . . . . . . 4.12.8 Video Display Field 2 V ertical Blanking End Register (VDVBLKE2) 4-67 .
Contents x SPRU629 6 VCXO Interpolated Control Port 6-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides an overview of the VCXO interpolated control (VIC) port. 6.1 Overview 6-2 . . . . . . .
Figures xi Figures SPRU629 Figures 1 – 1 Video Port Block Diagram 1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 – 2 BT .656 Video Capture FIFO Configuration 1-6 . . . . . . . . . .
Figures xii SPRU629 3 – 21 20-Bit Raw Data FIFO Packing 3-36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 – 22 Parallel TSI Capture 3-38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures xiii Figures SPRU629 4 – 17 10-Bit Y/C FIFO Unpacking 4-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 – 18 10-Bit Y/C Dense FIFO Unpacking 4-20 . . . . . . . . . . . . . . . . .
Figures xiv SPRU629 4 – 61 Video Display Clipping Register (VDCLIP) 4-85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 – 62 Video Display Default Display V alue Register (VDDEFV AL) 4-86 . . . . . . . . . . . . . .
T ables xv T ables SPRU629 T ables 1 – 1 Video Capture Signal Mapping 1-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 – 2 Video Display Signal Mapping 1-14 . . . . . . . . . . . . . . . . . .
T ables xvi SPRU629 3 – 24 TSI Capture Control Register (TSICTL) Field Descriptions 3-73 . . . . . . . . . . . . . . . . . . . . . . . . . 3 – 25 TSI Clock Initialization LSB Register (TSICLKINITL) Field Descriptions 3-74 . . . . . . . . . . . . .
T ables xvii T ables SPRU629 4 – 26 Video Display Counter Reload Register (VDRELOAD) Field Descriptions 4-83 . . . . . . . . . . . . 4 – 27 Video Display Display Event Register (VDDISPEVT) Field Descriptions 4-84 . . . . . . . . . . . . . 4 – 28 Video Display Clipping Register (VDCLIP) Field Descriptions 4-85 .
1-1 Overview This chapter provides an overview of the video port peripheral in the digital signal processors (DSPs) of the TMS320C6000 DSP family . Included are an overview of the video port functions, FIFO configurations, and signal mapping. T opic Page 1.
Video Port Overview 1-2 SPRU629 1.1 V ideo Port The video port peripheral can operate as a video capture port, video display port, or transport stream interface (TSI) capture port. It provides the following functions: - Video capture mode: J Capture rate up to 80 MHz.
Video Port 1-3 Overview SPRU629 - TSI capture mode: T ransport stream interface (TSI) from a front-end device such as demodulator or forward error correction device in 8-bit parallel format at up to 30 Mbytes/sec. - The port generates up to three events per channel and one interrupt to the DSP .
Video Port Overview 1-4 SPRU629 Figure 1–1. Video Port Block Diagram Internal peripheral bus Memory mapped registers Raw video display pipeline Channel B Channel A Raw video display pipeline Y/C video display pipeline BT .656 display pipeline Y/C video capture pipeline Capture/display buffer (2560 bytes) Raw video capture pipeline BT .
Video Port FIFO 1-5 Overview SPRU629 1.2 V ideo Port FIFO The video port includes a FIFO to store data coming into or out from the video port. The video port operates in conjunction with DMA transfers to move data between the video port FIFO and external or on-chip memory .
Video Port FIFO Overview 1-6 SPRU629 1.2.2 Video Capture FIFO Configurations During video capture operation, the video port FIFO has one of four configura- tions depending on the capture mode. For BT .656 operation, the FIFO is split into channel A and B, as shown in Figure 1 – 2.
Video Port FIFO 1-7 Overview SPRU629 For 8/10-bit raw video, the FIFO is split into channel A and B, as shown in Figure 1 – 3. Each FIFO is clocked independently with the channel A FIFO receiving data from the VDIN[9 – 0] half of the bus and the channel B FIFO receiving data from the VDIN[19 – 10] half of the bus.
Video Port FIFO Overview 1-8 SPRU629 For Y/C video capture, the FIFO is configured as a single channel split into sep- arate Y , Cb, and Cr buffers with separate write pointers and read registers (YSRCA, CBSRCA, and CRSRCA).
Video Port FIFO 1-9 Overview SPRU629 For 16/20-bit raw video, the FIFO is configured as a single buffer , as shown in Figure 1 – 5. The FIFO receives 16/20-bit data from the VDIN[19 – 0] bus. The FIFO has a single write pointer and read register (YSRCA).
Video Port FIFO Overview 1-10 SPRU629 For 8/10-bit raw video, the FIFO is configured as a single buffer as shown in Figure 1 – 7. The FIFO outputs data on the VDOUT[9 – 0] half of the bus. The FIFO has a single read pointer and write register (YDST A).
Video Port FIFO 1-1 1 Overview SPRU629 Figure 1 – 8. 8/10 Bit Locked Raw V ideo Display FIFO Configuration Buffer A (2560 bytes) YDST A VDOUT[9 – 0] 64 8/10 Display FIFO A Buffer B (2560 bytes) YDSTB VDOUT[19 – 10] 64 8/10 Display FIFO B For 16/20-bit raw video, the FIFO is configured as a single buffer , as shown in Figure 1 – 9.
Video Port Registers Overview 1-12 SPRU629 For Y/C video display , the FIFO is configured as a single channel split into sep- arate Y , Cb, and Cr buffers with separate read pointers and write registers (YDST A, CBDST , and CRDST).
Video Port Pin Mapping 1-13 Overview SPRU629 1.4 V ideo Port Pin Mapping The video port requires 21 external signal pins for full functionality . Pin usage and direction changes depend on the selected operating mode. Pin functional- ity detail for video capture mode is listed in T able 1 – 1.
Video Port Pin Mapping Overview 1-14 SPRU629 T able 1 – 2. V ideo Display Signal Mapping Usage Raw Data Display Mode Video Port Signal I/O BT .656 Display Mode Y/C Display Mode 8/10-Bit 16/20-Bit 8/.
Video Port Pin Mapping 1-15 Overview SPRU629 1.4.1 VDIN Bus Usage for Capture Modes The alignment and usage of data on the VDIN bus depends on the capture mode as shown in T able 1 – 3. T able 1 – 3. VDIN Data Bus Usage for Capture Modes Capture Mode BT .
Video Port Pin Mapping Overview 1-16 SPRU629 1.4.2 VDOUT Data Bus Usage for Display Modes The alignment and usage of data on the VDOUT bus depends on the display mode as shown in T able 1 – 4. T able 1 – 4. VDOUT Data Bus Usage for Display Modes Display Mode BT .
2-1 V ideo Port This chapter discusses the basic operation of the video port. Included is a discussion of the sources and types of resets, interrupt operation, DMA opera- tion, external clock inputs, video port throughput and latency , and the video port control registers.
Reset Operation Video Port 2-2 SPRU629 2.1 Reset Operation The video port has several sources and types of resets. The actions performed by these resets and the state of the port following the resets is described in the following sections. 2.1.1 Power-On Reset Power-on reset is an asynchronous hardware reset caused by a chip-level reset operation.
Reset Operation 2-3 Video Port SPRU629 If software sets the PEREN bit in PCR but the VPHL T bit in VPCTL remains set: - VCLK1, VCLK2, and STCLK are enabled to the port (allowing logic reset to complete). - Peripheral bus accesses are acknowledged (RREADY/WREADY returned) to prevent DMA lock-up.
Reset Operation Video Port 2-4 SPRU629 Once the port is configured and the VCEN bit is set, the setting of other VC x CTL bits (except VCEN, RSTCH, and BLKCAP) is prohibited and the capture counters begin counting. When BLKCAP is cleared, data capture and event generation may begin.
Interrupt Operation 2-5 Video Port SPRU629 2.2 Interrupt Operation The video port can generate an interrupt to the DSP core after any of the follow- ing events occur: - Capture complete (CCMP x ) bit is set. - Capture overrun (COVR x ) bit is set. - Synchronization byte error (SERR x ) bit is set.
DMA Operation Video Port 2-6 SPRU629 2.3 DMA Operation The video port uses up to three DMA events per channel for a total of six possible events. Each DMA event uses a dedicated event output. The outputs are: - VPYEVT A - VPCbEVT A - VPCrEVT A - VPYEVTB - VPCbEVTB - VPCrEVTB 2.
DMA Operation 2-7 Video Port SPRU629 Figure 2 – 1. Capture DMA Event Generation Flow Diagram Error Overflow error Ye s Overflow error FIFO overflow ? No Ye s Ye s Capture data, DMA active, new event.
DMA Operation Video Port 2-8 SPRU629 Because the capture FIFOs may hold multiple thresholds worth of data, a problem arises at the boundaries between fields.
DMA Operation 2-9 Video Port SPRU629 Figure 2 – 2. Display DMA Event Generation Flow Diagram Start of field FIFO empty Generate DMA event, new events disabled Display data, no DMA pending F ield com.
DMA Operation Video Port 2-10 SPRU629 A DMA event counter is used to track the number of DMA events generated in each field as programmed in the VDDISPEVT register . The DISPEVT1 or DISPEVT2 value (depending on the current display field) is loaded at the start of each field.
DMA Operation 2-1 1 Video Port SPRU629 Similarly if a subhorizontal line length is desired ( ½ line, for example), then the line length and threshold must be chosen such that the threshold is divisible by 2. (This can also be stated as the line length must be an even multiple of #DMAs/line × 8).
Clocks Video Port 2-12 SPRU629 2.4 Clocks The video port has three external clock inputs as shown in T able 2 – 1. No synchronization is required between the clocks sourced by the external pins. V CL K1 and V CL K2 clock frequencies should be less than the DMA interface clock.
Video Port Throughput and Latency 2-13 Video Port SPRU629 2.5.2 FIFO Size Some low-cost device implementations with narrow video ports width or restricted to lower video frequency operations may use a reduced FIFO size. FIFO size does not affect the DMA request mechanism.
Video Port Throughput and Latency Video Port 2-14 SPRU629 T able 2 – 2. Y/C V ideo Capture FIFO Capacity Sample 8-Bit 10-Bit Dense 10-Bit Y Samples 2560 1920 1280 Cb Samples 1280 960 640 Cr Samples 1280 960 640 Using these values and the formula above, the maximum time to empty the FIFO (t O ) may be calculated for each case.
Video Port Throughput and Latency 2-15 Video Port SPRU629 2.6.2 Video Display Throughput Video display throughput may be calculated in a manner similar to video capture. In this case, the time to fill the display FIFO must be less than the time to empty the FIFO or underflow occurs.
Video Port Control Registers Video Port 2-16 SPRU629 A DMA write throughput of at least 330 MBytes/s is required for the highest display rate operation supported by 20-bit implementations of the video port. C64x devices including the video port typically have more than enough DMA bandwidth to support this throughput requirement.
Video Port Control Registers 2-17 Video Port SPRU629 2.7.1 Video Port Control Register (VPCTL) The video port control register (VPCTL) determines the basic operation of the video port. The VPCTL is shown in Figure 2 – 3 and described in T able 2 – 5.
Video Port Control Registers Video Port 2-18 SPRU629 T able 2 – 5. V ideo Port Control Register (VPCTL) Field Descriptions (Continued) Bit Description V alue symval † field † 14 VPHL T Video port halt bit. This bit is set upon hardware or software reset.
Video Port Control Registers 2-19 Video Port SPRU629 T able 2 – 5. V ideo Port Control Register (VPCTL) Field Descriptions (Continued) Bit Description V alue symval † field † 2 TSI TSI capture mode select bit. NONE 0 TSI capture mode is disabled.
Video Port Control Registers Video Port 2-20 SPRU629 2.7.2 Video Port Status Register (VPST A T) The video port status register (VPST A T) indicates the current condition of the video port. The VPST A T is shown in Figure 2 – 4 and described in T able 2 – 7.
Video Port Control Registers 2-21 Video Port SPRU629 2.7.3 Video Port Interrupt Enable Register (VPIE) The video port interrupt enable register (VPIE) enables sources of the video port interrupt to the DSP . The VPIE is shown in Figure 2 – 5 and described in T able 2 – 8.
Video Port Control Registers Video Port 2-22 SPRU629 T able 2 – 8. V ideo Port Interrupt Enable Register (VPIE) Field Descriptions (Continued) Bit Description V alue symval † field † 20 VINTB1 Channel B field 1 vertical interrupt enable bit. DISABLE 0 Interrupt is disabled.
Video Port Control Registers 2-23 Video Port SPRU629 T able 2 – 8. V ideo Port Interrupt Enable Register (VPIE) Field Descriptions (Continued) Bit Description V alue symval † field † 10 STC System time clock interrupt enable bit. DISABLE 0 Interrupt is disabled.
Video Port Control Registers Video Port 2-24 SPRU629 2.7.4 Video Port Interrupt Status Register (VPIS) The video port interrupt status register (VPIS) displays the status of video port interrupts to the DSP . The interrupt is only sent to the DSP if the corresponding enable bit in VPIE is set.
Video Port Control Registers 2-25 Video Port SPRU629 T able 2 – 9. V ideo Port Interrupt Status Register (VPIS) Field Descriptions (Continued) Bit Description V alue symval field 22 SFDB Short field detected on channel B interrupt detected bit. BT .
Video Port Control Registers Video Port 2-26 SPRU629 T able 2 – 9. V ideo Port Interrupt Status Register (VPIS) Field Descriptions (Continued) Bit Description V alue symval field 18 CCMPB Capture complete on channel B interrupt detected bit. (Data is not in memory until the DMA transfer is complete.
Video Port Control Registers 2-27 Video Port SPRU629 T able 2 – 9. V ideo Port Interrupt Status Register (VPIS) Field Descriptions (Continued) Bit Description V alue symval field 13 DCMP Display complete. Indicates that the entire frame has been driven out of the port.
Video Port Control Registers Video Port 2-28 SPRU629 T able 2 – 9. V ideo Port Interrupt Status Register (VPIS) Field Descriptions (Continued) Bit Description V alue symval field 7 LFDA Long field detected on channel A interrupt detected bit.
Video Port Control Registers 2-29 Video Port SPRU629 T able 2 – 9. V ideo Port Interrupt Status Register (VPIS) Field Descriptions (Continued) Bit Description V alue symval field 3 SERRA Channel A synchronization error interrupt detected bit. BT .656 or Y/C capture mode – Synchronization parity error on channel A.
3-1 V ideo Capture Port Video capture works by sampling video data on the input pins and saving it to the video port FIFO. When the amount of captured data reaches a programmed threshold level, a DMA is performed to move data from the FIFO into DSP memory .
Video Capture Mode Selection Video Capture Port 3-2 SPRU629 3.1 V ideo Capture Mode Selection The video capture module operates in one of nine modes as listed in T able 3 – 1. The transport stream interface (TSI) selection is made using the TSI bit in the video port control register (VPCTL).
BT .656 Video Capture Mode 3-3 Video Capture Port SPRU629 3.2 BT .656 V ideo Capture Mode The BT .656 capture mode captures 8-bit or 10-bit 4:2:2 luma and chroma data multiplexed into a single data stream. Video data is conveyed in the order Cb,Y ,Cr ,Y ,Cb,Y ,Cr , etc.
BT .656 Video Capture Mode Video Capture Port 3-4 SPRU629 3.2.2 BT .656 Timing Reference Codes For standard digital video, there are two reference signals, one at the begin- ning of each video data block (start of active video, SA V), and one at the end of each video block (end of active video, EA V).
BT .656 Video Capture Mode 3-5 Video Capture Port SPRU629 Bits P0, P1, P2, and P3 have different states depending on the state of bits F , V , and H as shown in T able 3 – 3.
BT .656 Video Capture Mode Video Capture Port 3-6 SPRU629 T able 3 – 4. Error Correction by Protection Bits (Continued) Received P 3 – P 0 Bits Received F , V , and H Bits Received P 3 – P 0 Bit.
BT .656 Video Capture Mode 3-7 Video Capture Port SPRU629 Figure 3 – 1. V ideo Capture Parameters Capture Image Ystart Xstart Ystop Xstop Field 1 Capture Image Ystart Xstart Ystop Xstop Field 2 Hcou.
BT .656 Video Capture Mode Video Capture Port 3-8 SPRU629 For the BT .656 video capture mode, the FIFO buffer is divided into three sec- tions (three buffers). One section is 1280 bytes deep and is dedicated for stor- age of Y data samples. The other two sections are dedicated for storage of Cb and Cr data samples, respectively .
BT .656 Video Capture Mode 3-9 Video Capture Port SPRU629 3.2.5 BT .656 FIFO Packing Captured data is always packed into 64-bits before being written into the cap- ture FIFO(s). The packing and byte ordering is dependant upon the capture data size and the device endian mode.
BT .656 Video Capture Mode Video Capture Port 3-10 SPRU629 The 10-bit BT .656 mode uses three FIFOs for color separation. T wo samples are packed into each word with zero or sign extension as shown in Figure 3 – 3.
BT .656 Video Capture Mode 3-1 1 Video Capture Port SPRU629 The 10-bit BT .656 dense mode uses three FIFOs for color separation. Three samples are packed into each word with zero extension to provide increased DMA bandwidth as shown in Figure 3 – 4.
Y/C Video Capture Mode Video Capture Port 3-12 SPRU629 3.3 Y/C V ideo Capture Mode The Y/C capture mode is similar to the BT .656 capture mode but captures 8 or 10-bit 4:2:2 data on separate luma and chroma data streams.
Y/C Video Capture Mode 3-13 Video Capture Port SPRU629 3.3.3 Y/C Image Window and Capture The SDTV Y/C format (CCIR601) is an interlaced format consisting of two fields just like BT .656. HDTV Y/C formats may be interlaced or progressive scan. For interlaced capture, the capture windows are programmed identically to BT .
Y/C Video Capture Mode Video Capture Port 3-14 SPRU629 3.3.4 Y/C FIFO Packing Captured data is always packed into 64 bits before being written into the capture FIFO(s). The packing and byte ordering is dependant upon the capture data size and the device endian mode.
Y/C Video Capture Mode 3-15 Video Capture Port SPRU629 The 10-bit Y/C mode uses three FIFOs for color separation. T wo samples are packed into each word with zero or sign extension as shown in Figure 3 – 6.
Y/C Video Capture Mode Video Capture Port 3-16 SPRU629 The 10-bit Y/C dense mode uses three FIFOs for color separation. Three sam- ples are packed into each word with zero extension to provide increased DMA bandwidth as shown in Figure 3 – 7. Figure 3 – 7.
BT .656 and Y/C Mode Field and Frame Operation 3-17 Video Capture Port SPRU629 3.4 BT .656 and Y/C Mode Field and Frame Operation Because DMAs are used to transfer data from the capture FIFOs to memory , there is a large amount of flexibility in the way that capture fields and frames are transferred and stored in memory .
BT .656 and Y/C Mode Field and Frame Operation Video Capture Port 3-18 SPRU629 T able 3 – 6. BT .656 and Y/C Mode Capture Operation VC x CTL Bit CON FRAME CF2 CF1 Operation 0 0 0 0 Reserved 0 0 0 1 Noncontinuous field 1 capture. Capture only field 1.
BT .656 and Y/C Mode Field and Frame Operation 3-19 Video Capture Port SPRU629 T able 3 – 6. BT .656 and Y/C Mode Capture Operation (Continued) VC x CTL Bit CON Operation CF1 CF2 FRAME 1 0 1 0 Continuous field 2 capture. Capture only field 2. F2C is set after field 2 capture and causes CCMPx to be set (CCMPx interrupt can be disabled).
BT .656 and Y/C Mode Field and Frame Operation Video Capture Port 3-20 SPRU629 T able 3 – 7. V ertical Synchronization Programming VC x CTL Bit VMode EXC VRST V ertical Counter Reset Point 0 0 0 First EA V with V=1 after EA V with V=0 – beginning of vertical blanking period.
BT .656 and Y/C Mode Field and Frame Operation 3-21 Video Capture Port SPRU629 Figure 3 – 8. VCOUNT Operation Example (EXC = 0) VF 5 1 1 Line VRST=0 1 0 525 1 262 VCOUNT Field 1 Blanking Field 2 Bla.
BT .656 and Y/C Mode Field and Frame Operation Video Capture Port 3-22 SPRU629 3.4.3 Horizontal Synchronization Horizontal synchronization determines when the horizontal pixel/sample counter is reset. The EXC and HRST bits in VC x CTL allow you to program the event that triggers the start of a line.
BT .656 and Y/C Mode Field and Frame Operation 3-23 Video Capture Port SPRU629 Figure 3 – 9. HCOUNT Operation Example (EXC = 0) VDIN[9 – 0] 80.0 80.0 10.0 FF .C 00.0 00.0 Cb 0 Y 2 Cb 359 Cr 359 Y 719 Y 0 Cr 0 Y 1 Cb 1 One Line XY .0 10.0 80.0 10.0 FF .
BT .656 and Y/C Mode Field and Frame Operation Video Capture Port 3-24 SPRU629 3.4.4 Field Identification In order to properly synchronize to the source data stream and capture the correct fields, field identification needs to be performed. Field identification is made using one of three methods: EA V , field indicator input, or field detect logic.
BT .656 and Y/C Mode Field and Frame Operation 3-25 Video Capture Port SPRU629 The field detect method uses HYSNC and VSYNC based field detect logic. This is used for BT .656 or Y/C systems that provide only HSYNC and VSYNC. The field detect logic samples the state of the HSYNC input on the VSYNC active edge.
Video Input Filtering Video Capture Port 3-26 SPRU629 VCTL2 is a VSYNC (vertical sync) input, then a long field is always detected. (Even if VCYSTOP n is set to the last active line, VCOUNT usually increments past VCYSTOP n + 1 while it counts the vertical front porch lines that occur prior to VSYNC active.
Video Input Filtering 3-27 Video Capture Port SPRU629 3.5.2 Chrominance Resampling Operation Chrominance resampling computes chrominance values at sample points midway between the input luminance samples based on the input co-sited chrominance samples.
Video Input Filtering Video Capture Port 3-28 SPRU629 Figure 3 – 13. 1/2 Scaled Co-Sited Filtering YCbCr 4:2:2 co-sited input samples 1/2 scaled co-sited capture results Luma (Y) sample Y ’ h = ( .
Video Input Filtering 3-29 Video Capture Port SPRU629 3.5.4 Edge Pixel Replication Because the filters make use of preceding and trailing samples, filtering arti- facts can occur at the beginning of the BT .656 or Y/C active line because no samples exist before the SA V code, and at the end of the BT .
Video Input Filtering Video Capture Port 3-30 SPRU629 Figure 3 – 16 shows an example of a capture window that is smaller than the BT .656 active line.
Ancillary Data Capture 3-31 Video Capture Port SPRU629 3.6 Ancillary Data Capture The BT .656 and some Y/C specifications includes provision for carrying ancillary (nonvideo) data within the horizontal and vertical blanking regions. Horizontal ancillary (HANC) data appears between the EA V code and SA V codes.
Raw Data Capture Mode Video Capture Port 3-32 SPRU629 3.7 Raw Data Capture Mode In the raw data capture mode, the data is sampled by the interface only when the CAPEN signal is active. Data is captured at the rate of the sender ’ s clock, without any interpretation or start/stop of capture based on the data values.
Raw Data Capture Mode 3-33 Video Capture Port SPRU629 T able 3 – 1 1. Raw Data Mode Capture Operation VC x CTL Bit CON FRAME CF2 CF1 Operation 0 0 x x Noncontinuous frame capture. FRMC is set after data block capture and causes CCMPx to be set. Capture will halt upon completion of the next frame unless the FRMC bit is cleared.
Raw Data Capture Mode Video Capture Port 3-34 SPRU629 The 8-bit raw-data mode stores all data in a single FIFO. Four samples are packed into each word as shown in Figure 3 – 17.
Raw Data Capture Mode 3-35 Video Capture Port SPRU629 The 10-bit dense raw data mode stores all data into a single FIFO. Three sam- ples are packed into each word with zero extension as shown in Figure 3 – 19.
Raw Data Capture Mode Video Capture Port 3-36 SPRU629 The 20-bit raw data mode stores all data into a single FIFO. One sample is placed right justified in each word and zero or sign extended as shown in Figure 3 – 21.
TSI Capture Mode 3-37 Video Capture Port SPRU629 3.8 TSI Capture Mode The transport stream interface (TSI) capture mode captures MPEG-2 trans- port data. 3.8.1 TSI Capture Features The video port TSI capture mode supports the following features: - Supports SYNC detect using the P ACSTRT input from a front-end device.
TSI Capture Mode Video Capture Port 3-38 SPRU629 Figure 3 – 22. Parallel TSI Capture P ACSTRT VCLKIN CAPEN VDIN[9:2] Sync Byte Byte 1 Byte 2 Byte 3 Byte 4 Start Capture 3.8.3 TSI Capture Error Detection The video port checks for two types of errors during TSI capture.
TSI Capture Mode 3-39 Video Capture Port SPRU629 Figure 3 – 23. Program Clock Reference (PCR) Header Format 47 15 14 9 8 0 PCR Reserved PCR extension The video port, in conjunction with the VCXO int.
TSI Capture Mode Video Capture Port 3-40 SPRU629 The system time clock counter is initialized by software with the PCR of the first packet with a PCR header . After initialization, the counter can be reinitialized by software upon detecting a discontinuity in subsequent packet PCR header values.
TSI Capture Mode 3-41 Video Capture Port SPRU629 3.8.6 Writing to the FIFO The captured TSI packet data and the associated timestamps are written into the receive FIFO. The packet data is written first, followed by the timestamp. The FIFO controller controls both data writes and timestamp writes into the FIFO.
Capture Line Boundary Conditions Video Capture Port 3-42 SPRU629 Figure 3 – 27. TSI Timestamp Format (Big Endian) 63 56 55 48 47 40 39 32 PCR(7 – 0) PCR(15 – 8) PCR(23 – 16) PCR(31 – 24) 31 25 24 23 18 17 16 PCR extension (6 – 0) PCR32 Reserved PCR ext (8 – 7) 15 8 7 6 5 0 Reserved PERR PSTERR Reserved 3.
Capture Line Boundary Conditions 3-43 Video Capture Port SPRU629 In Figure 3 – 28 (8-bit Y/C mode), the line length is not a doubleword. When the condition HCOUNT = VCXSTOP occurs, the FIFO location is written even though 8 bytes have not been received.
Capturing Video in BT .656 or Y/C Mode Video Capture Port 3-44 SPRU629 3.10 Capturing V ideo in BT .656 or Y/C Mode In order to capture video in the BT .656 or Y/C format, the following steps are needed: 1) Set the last pixel to be captured in VC x STOP1 and VC x ST OP2 (set the VCXST OP and VCYST OP bits).
Capturing Video in BT .656 or Y/C Mode 3-45 Video Capture Port SPRU629 8) Write to VC x CTL to: - Set capture mode (CMODE = 00x for BT .656 input, 10x for Y/C input). - Set desired field/frame operation (CON, FRAME, CF2, CF1 bits). - Set sync and field ID control (VRST , HRST , FDD, FINV , VCTL1 bits).
Capturing Video in Raw Data Mode Video Capture Port 3-46 SPRU629 3.1 1 Capturing V ideo in Raw Data Mode In order to capture video in the raw data mode, the following steps are needed: 1) Set VC x STO.
Capturing Data in TSI Capture Mode 3-47 Video Capture Port SPRU629 3.1 1.1 Handling FIFO Overrun Condition in Raw Data Mode In case of a FIFO overrun, the COVR x bit is set in VPIS. This condition initiates an interrupt to the DSP , if the overrun interrupt is enabled (setting the COVR x bit in VPIE enables overrun interrupt).
Capturing Data in TSI Capture Mode Video Capture Port 3-48 SPRU629 6) Write to TSISTCMPL, TSISTCMPM, TSISTMSKL, and TSISTMSKM if needed to initiate an interrupt, based on STC absolute time. 7) Write to TSITICKS if an interrupt is desired every x cycles of STC.
Video Capture Registers 3-49 Video Capture Port SPRU629 3.13 Video Capture Registers The registers for controlling the video capture mode of operation are listed in T able 3 – 13. See the device-specific datasheet for the memory address of these registers.
Video Capture Registers Video Capture Port 3-50 SPRU629 T able 3 – 13. V ideo Capture Control Registers (Continued) Acronym Section Register Name TSISTCMPL TSI System T ime Clock Compare LSB Register 3.13.16 TSISTCMPM TSI System T ime Clock Compare MSB Register 3.
Video Capture Registers 3-51 Video Capture Port SPRU629 T able 3 – 14. V ideo Capture Channel x Status Register (VCxST A T) Field Descriptions Description Bit field † symval † V alue BT .656 or Y/C Mode Raw Data Mode TSI Mode 31 FSYNC Current frame sync bit.
Video Capture Registers Video Capture Port 3-52 SPRU629 T able 3 – 14. V ideo Capture Channel x Status Register (VCxST A T) Field Descriptions (Continued) Bit Description V alue symval † field † Bit TSI Mode Raw Data Mode BT .
Video Capture Registers 3-53 Video Capture Port SPRU629 3.13.2 Video Capture Channel A Control Register (VCACTL) Video capture is controlled by the video capture channel A control register (VCACTL) shown in Figure 3 – 30 and described in T able 3 – 15.
Video Capture Registers Video Capture Port 3-54 SPRU629 T able 3 – 15. V ideo Capture Channel A Control Register (VCACTL) Field Descriptions (Continued) Description Bit TSI Mode Raw Data Mode BT .656 or Y/C Mode V alue symval † field † 30 BLKCAP Block capture events bit.
Video Capture Registers 3-55 Video Capture Port SPRU629 T able 3 – 15. V ideo Capture Channel A Control Register (VCACTL) Field Descriptions (Continued) Description Bit TSI Mode Raw Data Mode BT .656 or Y/C Mode V alue symval † field † 18 FLDD Field detect method bit.
Video Capture Registers Video Capture Port 3-56 SPRU629 T able 3 – 15. V ideo Capture Channel A Control Register (VCACTL) Field Descriptions (Continued) Description Bit TSI Mode Raw Data Mode BT .656 or Y/C Mode V alue symval † field † 12 LFDE Long field detect enable bit.
Video Capture Registers 3-57 Video Capture Port SPRU629 T able 3 – 15. V ideo Capture Channel A Control Register (VCACTL) Field Descriptions (Continued) Description Bit TSI Mode Raw Data Mode BT .656 or Y/C Mode V alue symval † field † 6 FRAME ‡ Capture frame (data) bit.
Video Capture Registers Video Capture Port 3-58 SPRU629 3.13.3 Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTRT1) The captured image is a subset of the incoming image. The video capture channel x field 1 start register (VCASTRT1, VCBSTR T1) defines the start of the field 1 captured image.
Video Capture Registers 3-59 Video Capture Port SPRU629 T able 3 – 1 6 . Video Capture Channel x Field 1 Start Register (VCxSTRT1) Field Descriptions Description Bit field † symval † V alue BT .656 or Y/C Mode Raw Data Mode TSI Mode 31 – 28 Reserved – 0 Reserved.
Video Capture Registers Video Capture Port 3-60 SPRU629 3.13.4 Video Capture Channel x Field 1 Stop Register (VCAST OP1, VCBSTOP1) The video capture channel x field 1 stop register (VCASTOP1, VCBSTOP1) defines the end of the field 1-captured image or the end of the raw data or TSI packet.
Video Capture Registers 3-61 Video Capture Port SPRU629 3.13.5 Video Capture Channel x Field 2 Start Register (VCASTRT2, VCBSTRT2) The captured image is a subset of the incoming image. The video capture channel x field 2 start register (VCASTRT2, VCBSTR T2) defines the start of the field 2 captured image.
Video Capture Registers Video Capture Port 3-62 SPRU629 3.13.6 Video Capture Channel x Field 2 Stop Register (VCAST OP2, VCBSTOP2) The video capture channel x field 2 stop register (VCASTOP2, VCBSTOP2) defines the end of the field 2-captured image. VC x STOP2 is shown in Figure 3 – 34 and described in T able 3 – 19.
Video Capture Registers 3-63 Video Capture Port SPRU629 3.13.7 Video Capture Channel x V ertical Interrupt Register (VCA VINT , VCBVINT) The video capture channel x vertical interrupt register (VCA VINT , VCBVINT) controls the generation of vertical interrupts in each field.
Video Capture Registers Video Capture Port 3-64 SPRU629 T able 3 – 20. V ideo Capture Channel x Vertical Interrupt Register (VCxVINT) Field Descriptions Description Bit field † symval † V alue BT .656 or Y/C Mode Raw Data Mode TSI Mode 31 VIF2 Setting of VINT in field 2 enable bit.
Video Capture Registers 3-65 Video Capture Port SPRU629 3.13.8 Video Capture Channel x Threshold Register (VCA THRLD, VCBTHRLD) The video capture channel x threshold register (VCA THRLD, VCBTHRLD) determines when DMA requests are sent. VC x THRLD is shown in Figure 3 – 36 and described in T able 3 – 21.
Video Capture Registers Video Capture Port 3-66 SPRU629 Figure 3 – 36. Video Capture Channel x Threshold Register (VCA THRLD, VCBTHRLD) 31 26 25 16 Reserved VCTHRLD2 R-0 R/W-0 15 10 9 0 Reserved VCTHRLD1 R-0 R/W-0 Legend: R = Read only; R/W = Read/Write; - n = value after reset T able 3 – 21 .
Video Capture Registers 3-67 Video Capture Port SPRU629 3.13.9 Video Capture Channel x Event Count Register (VCAEVTCT , VCBEVTCT) The video capture channel x event count register (VCAEVTCT , VCBEVTCT) is programmed with the number of DMA events to be generated for each capture field.
Video Capture Registers Video Capture Port 3-68 SPRU629 3.13.10 Video Capture Channel B Control Register (VCBCTL) Video capture is controlled by the video capture channel B control register (VCBCTL) shown in Figure 3 – 38 and described in T able 3 – 23.
Video Capture Registers 3-69 Video Capture Port SPRU629 T able 3 – 23. V ideo Capture Channel B Control Register (VCBCTL) Field Descriptions (Continued) Description Bit TSI Mode Raw Data Mode BT .656 or Y/C Mode V alue symval † field † 30 BLKCAP Block capture events bit.
Video Capture Registers Video Capture Port 3-70 SPRU629 T able 3 – 23. V ideo Capture Channel B Control Register (VCBCTL) Field Descriptions (Continued) Description Bit TSI Mode Raw Data Mode BT .656 or Y/C Mode V alue symval † field † 16 HRST HCOUNT reset method bit.
Video Capture Registers 3-71 Video Capture Port SPRU629 T able 3 – 23. V ideo Capture Channel B Control Register (VCBCTL) Field Descriptions (Continued) Description Bit TSI Mode Raw Data Mode BT .656 or Y/C Mode V alue symval † field † 10 RESMPL Chroma resampling enable bit.
Video Capture Registers Video Capture Port 3-72 SPRU629 T able 3 – 23. V ideo Capture Channel B Control Register (VCBCTL) Field Descriptions (Continued) Description Bit TSI Mode Raw Data Mode BT .656 or Y/C Mode V alue symval † field † 4 CF1 ‡ Capture field 1 bit.
Video Capture Registers 3-73 Video Capture Port SPRU629 T able 3 – 24. TSI Capture Control Register (TSICTL) Field Descriptions Description Bit field † symval † V alue BT .656, Y/C Mode, or Raw Data Mode TSI Mode 31 – 6 Reserved – 0 Reserved.
Video Capture Registers Video Capture Port 3-74 SPRU629 3.13.12 TSI Clock Initialization LSB Register (TSICLKINITL) The transport stream interface clock initialization LSB register (TSICLKINITL) is used to initialize the hardware counter to synchronize with the system time clock.
Video Capture Registers 3-75 Video Capture Port SPRU629 3.13.13 TSI Clock Initialization MSB Register (TSICLKINITM) The transport stream interface clock initialization MSB register (TSICLKINITM) is used to initialize the hardware counter to synchronize with the system time clock.
Video Capture Registers Video Capture Port 3-76 SPRU629 3.13.14 TSI System Time Clock LSB Register (TSISTCLKL) The transport stream interface system time clock LSB register (TSISTCLKL) contains the 32 least-significant bits (LSBs) of the program clock reference (PCR).
Video Capture Registers 3-77 Video Capture Port SPRU629 3.13.15 TSI System Time Clock MSB Register (TSISTCLKM) The transport stream interface system time clock MSB register (TSISTCLKM) contains the most-significant bit (MSB) of the program clock reference (PCR) and the 9 bits of the PCR extension.
Video Capture Registers Video Capture Port 3-78 SPRU629 3.13.16 TSI System Time Clock Compare LSB Register (TSISTCMPL) The transport stream interface system time clock compare LSB register (TSISTCMPL) is used to generate an interrupt at some absolute time based on the STC.
Video Capture Registers 3-79 Video Capture Port SPRU629 3.13.17 TSI System Time Clock Compare MSB Register (TSISTCMPM) The transport stream interface system time clock compare MSB register (TSISTCMPM) is used to generate an interrupt at some absolute time based on the STC.
Video Capture Registers Video Capture Port 3-80 SPRU629 3.13.18 TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) The transport stream interface system time clock compare mask LSB register (TSISTMSKL) holds the 32 least-significant bits (LSBs) of the absolute time compare mask (A TCM).
Video Capture Registers 3-81 Video Capture Port SPRU629 3.13.19 TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) The transport stream interface system time clock compare mask MSB register (TSISTMSKM) holds the most-significant bit (MSB) of the absolute time compare mask (A TCM).
Video Capture Registers Video Capture Port 3-82 SPRU629 3.13.20 TSI System Time Clock Ticks Interrupt Register (TSITICKS) The transport stream interface system time clock ticks interrupt register (TSITICKS) is used to generate an interrupt after a certain number of ticks of the 27-MHz system time clock.
Video Capture FIFO Registers 3-83 Video Capture Port SPRU629 3.14 Video Capture FIFO Registers The capture FIFO mapping registers are listed in T able 3 – 34.
4-1 V ideo Display Port The video port peripheral can operate as a video capture port, video display port, or transport stream interface (TSI) capture port. This chapter discusses the video display port. T opic Page 4.1 Video Display Mode Selection 4-2 .
Video Display Mode Selection Video Display Port 4-2 SPRU629 4.1 V ideo Display Mode Selection The video display module operates in one of three modes as listed in T able 4 – 1.
Video Display Mode Selection 4-3 Video Display Port SPRU629 Figure 4 – 1. NTSC Compatible Interlaced Display Line 20 Line 21 Line 22 Line 261 Line 262 Line 263 Line 282 Line 283 Line 284 Line 523 Line 524 Line 525 Field 1 Field 2 Figure 4 – 2.
Video Display Mode Selection Video Display Port 4-4 SPRU629 Figure 4 – 3. Interlaced Blanking Intervals and Video Areas Field 1 V ertical Blanking Horizontal Blanking Field 1 Image Horiz.
Video Display Mode Selection 4-5 Video Display Port SPRU629 Figure 4 – 4. Progressive Blanking Intervals and V ideo Area Field 1 Image Width Field 1 Frame Field 1 Image Height Field 1 V ertical Blanking Field 1 Image V ertical Offset Field 1 Active Video 4.
Video Display Mode Selection Video Display Port 4-6 SPRU629 The image line counter (ILCOUNT) and the image pixel counter (IPCOUNT) track the visible image within the field. ILCOUNT begins counting at the first display image line in each field. IPCOUNT begins counting at the first dis- played image pixel on each line.
Video Display Mode Selection 4-7 Video Display Port SPRU629 Note that the signals can transition at any place along the video line (specified by the XST ART and XST OP bits of the appropriate registers). In this case, VBLNK starts at horizontal count VBLNKXST ART2 = 429 on scan line VBLNKYST ART2 = 263 (565/60 operation).
Video Display Mode Selection Video Display Port 4-8 SPRU629 4.1.4 External Sync Operation The video display module may be synchronized with an external video source using external sync signals. VCTL1 may be configured as an external horizon- tal sync input.
BT .656 Video Display Mode 4-9 Video Display Port SPRU629 4.2 BT .656 V ideo Display Mode The BT .656 display mode outputs 8-bit or 10-bit 4:2:2 co-sited luma and chroma data multiplexed into a single data stream. Pixels are output in pairs with each pair consisting of two luma samples and two chroma samples.
BT .656 Video Display Mode Video Display Port 4-10 SPRU629 Figure 4 – 10. 625/50 BT .656 Horizontal Blanking Timing One Line 861 862 863 0 1 2 718 719 720 721 722 723 720 721 722 723 FPCOUNT Active Video Blanking VCLKOUT Next Line 4 4 280 1440 VDOUT[9 – 0] 80.
BT .656 Video Display Mode 4-1 1 Video Display Port SPRU629 Figure 4 – 1 1. Digital Vertical F and V T ransitions Blanking Optional blanking Line 4 Image: Field 1 Blanking Line 266 Optional blanking.
BT .656 Video Display Mode Video Display Port 4-12 SPRU629 4.2.2 Blanking Codes The time between the EA V and SA V code on each line represents the horizontal blanking interval. During this time, the video port outputs digital video blanking values. These values are 10.
BT .656 Video Display Mode 4-13 Video Display Port SPRU629 4.2.4 BT .656 FIFO Unpacking Display data is always packed into the FIFOs in 64-bit words and must be unpacked before being sent to the video display data pipeline. The unpacking and byte ordering is dependant upon the display data size and the device endian mode.
BT .656 Video Display Mode Video Display Port 4-14 SPRU629 For 10-bit BT .656 operation, two samples are unpacked from each word as shown in Figure 4 – 13.
BT .656 Video Display Mode 4-15 Video Display Port SPRU629 In 10-bit BT .656 dense-pack mode, three samples are unpacked from each word in the FIFO as seen in Figure 4 – 14.
Y/C Video Display Mode Video Display Port 4-16 SPRU629 4.3 Y/C V ideo Display Mode The Y/C display mode is similar to the BT .656 display mode but outputs 8 or 10-bit data on separate luma and chroma data streams.
Y/C Video Display Mode 4-17 Video Display Port SPRU629 4.3.2 Y/C Blanking Codes The time between the EA V and SA V code on each line represents the horizon- tal blanking interval. During this time, the video port outputs the digital video blanking values.
Y/C Video Display Mode Video Display Port 4-18 SPRU629 The 8-bit Y/C mode uses three FIFOs for color separation. Four samples are unpacked from each word as shown in Figure 4 – 16.
Y/C Video Display Mode 4-19 Video Display Port SPRU629 For 10-bit operation, two samples are unpacked from each FIFO word. This is shown in Figure 4 – 17.
Y/C Video Display Mode Video Display Port 4-20 SPRU629 In 10-bit Y/C dense-pack mode, three samples are unpacked from each word in the FIFO as seen in Figure 4 – 18.
Video Output Filtering 4-21 Video Display Port SPRU629 4.4 V ideo Output Filtering The video output filter performs simple hardware scaling and resampling on outgoing 8-bit BT .656 or 8-bit Y/C data. Filtering hardware is disabled during 10-bit or raw data display modes.
Video Output Filtering Video Display Port 4-22 SPRU629 4.4.2 Chrominance Resampling Operation Chrominance resampling computes chrominance values at sample points corresponding to output luminance samples based on the input interspersed chrominance samples.
Video Output Filtering 4-23 Video Display Port SPRU629 Figure 4 – 20. 2x Co-Sited Scaling 2 × upscaled output YCbCr 4:2:2 co – sited source pixels Luma (Y) sample Y ’ d ’ = ( – 1Y c + 17Y d.
Video Output Filtering Video Display Port 4-24 SPRU629 Examples of luma edge and chroma edge replication for 2 × interspersed to co-sited output are shown in Figure 4 – 23 and Figure 4 – 24, respectively .
Ancillary Data Display 4-25 Video Display Port SPRU629 4.5 Ancillary Data Display The following sections discuss ancillary data display . No special previsions are made for the display of horizontal anc illary (HANC) or verti cal ancillary (V ANC), also called vertical blanking interval (VBI), data.
Raw Data Display Mode Video Display Port 4-26 SPRU629 4.6.1 Raw Mode RGB Output Support The raw data display mode has a special pixel count feature that allows the FPCOUNT increment rate to be set. FPCOUNT increments only when INCPIX samples have been sent out.
Raw Data Display Mode 4-27 Video Display Port SPRU629 For 10-bit operation, two samples are unpacked from each FIFO word. This is shown in Figure 4 – 26.
Raw Data Display Mode Video Display Port 4-28 SPRU629 Figure 4 – 28 shows the 16-bit raw mode. T wo samples are unpacked from each word of the FIFO. Figure 4 – 28.
Raw Data Display Mode 4-29 Video Display Port SPRU629 In 8-bit raw ¾ mode, three samples are unpacked from the FIFO and the remaining byte is ignored.
Video Display Field and Frame Operation Video Display Port 4-30 SPRU629 4.7 V ideo Display Field and Frame Operation As a video source, the video port always outputs entire frames of data and transmits continuous video control signals.
Video Display Field and Frame Operation 4-31 Video Display Port SPRU629 T able 4 – 4. Display Operation VDCTL Bit CON FRAME DF2 DF1 Operation 0 0 0 0 Reserved 0 0 0 1 Noncontinuous field 1 display . Display only field 1. F1D is set after field 1 display and causes DCMPx to be set.
Video Display Field and Frame Operation Video Display Port 4-32 SPRU629 T able 4 – 4. Display Operation (Continued) VDCTL Bit CON Operation DF1 DF2 FRAME 1 0 1 0 Continuous field 2 display . Display only field 2. F2D is set after field 2 display and causes DCMPx to be set (DCMPx interrupt can be dis- abled).
Display Line Boundary Conditions 4-33 Video Display Port SPRU629 4.8 Display Line Boundary Conditions In order to simplify DMA transfers, FIFO doublewords do not contain data from more than one display line.
Display Line Boundary Conditions Video Display Port 4-34 SPRU629 Figure 4 – 32. Display Line Boundary Example Y FIFO Cb FIFO Y 74 Y 76 Y 78 Y73 Y 75 Y 77 Y 79 VDOUT[9 – 2] VCLKOUT 63 5655 48 47 40.
Display Timing Examples 4-35 Video Display Port SPRU629 4.9 Display Timing Examples The following are examples of display output for several modes of operation. 4.9.1 Interlaced BT .656 Timing Example This section shows an example of BT .656 display output for a 704 × 408 inter- laced output image as might be generated by MPEG decoding.
Display Timing Examples 4-36 Video Display Port SPRU629 Figure 4 – 33. BT .656 Interlaced Display Horizontal Timing Example 720 721 722 723 735 736 799 800 855 856 857 0 1 7891 0 710 71 1 712 718 71.
Display Timing Examples 4-37 Video Display Port SPRU629 The interlaced BT .656 vertical output timing is shown in Figure 4 – 34. The BT .656 active field 1 is 244-lines high and active field 2 is 243-lines high. This example shows the 480-line image window centered in the screen.
Display Timing Examples Video Display Port 4-38 SPRU629 Figure 4 – 34. BT .656 Interlaced Display Vertical T iming Example 5 FLCOUNT 525 240 240 ILCOUNT Field 1 Blanking Field 2 Blanking Field 1 Act.
Display Timing Examples 4-39 Video Display Port SPRU629 4.9.2 Interlaced Raw Display Example This section shows an example of raw display output for the same 704 × 408 interlaced image.
Display Timing Examples 4-40 Video Display Port SPRU629 Figure 4 – 35. Raw Interlaced Display Horizontal Timing Example FLCOUNT VDOUT[19 – 0] § VCLKOUT VCLKIN IPCOUNT VCTL1 (HBLNK) † § VCTL1 (.
Display Timing Examples 4-41 Video Display Port SPRU629 The vertical output timing for raw mode is shown in Figure 4 – 36. This example outputs the same 480-line window . Note that the raw display mode is typically noninterlaced for output to a monitor .
Display Timing Examples Video Display Port 4-42 SPRU629 Figure 4 – 36. Raw Interlaced Display Vertical T iming Example 5 FLCOUNT 525 240 240 ILCOUNT Field 1 Blanking Field 2 Blanking Field 1 Active .
Display Timing Examples 4-43 Video Display Port SPRU629 4.9.3 Y/C Progressive Display Example This section shows an example of progressive display operation. The output format follows SMPTE 296M-2001 specifications for a 1280 × 720/60 system. The example is for a 1264 × 716 progressive output image.
Display Timing Examples 4-44 Video Display Port SPRU629 Figure 4 – 37. Y/C Progressive Display Horizontal Timing Example ‡ VCLKIN FPCOUNT IPCOUNT VCTL1 (HBLNK) † § VCTL1 (HSYNC) † § VCLKOUT .
Display Timing Examples 4-45 Video Display Port SPRU629 The vertical output timing is shown in Figure 4 – 38. SMPTE 296M has a single active field 1 that is 720-lines high. This example shows the 716-line image window with an IMGVOFF n of 3 lines and also results in a nondata line at the end of the field.
Display Timing Examples Video Display Port 4-46 SPRU629 Figure 4 – 38. Y/C Progressive Display Vertical T iming Example 5 FLCOUNT 750 716 716 ILCOUNT Field 1 Blanking Field 1 Blanking Field 1 Active.
Displaying Video in BT .656 or Y/C Mode 4-47 Video Display Port SPRU629 4.10 Displaying V ideo in BT .656 or Y/C Mode In order to display video in the BT .656 or Y/C format, the following steps are needed: 1) Set the frame size in VDFRMSZ. Set the number of lines per frame (FRMHIGHT) and the number of pixels per line (FRMWIDTH).
Displaying Video in BT .656 or Y/C Mode Video Display Port 4-48 SPRU629 12) Configure a DMA to move data from the Y buf fer in the DSP memory to YDST A (memory-mapped Y display FIFO). The transfers should be triggered by the YEVT . 13) Configure a DMA to move data from the Cb buf fer in the DSP memory to CBDST (memory-mapped Cb display FIFO).
Displaying Video in Raw Data Mode 4-49 Video Display Port SPRU629 22) If continuous display is enabled, the video port begins displaying again at the start of the next field or frame.
Displaying Video in Raw Data Mode Video Display Port 4-50 SPRU629 1 1) Set the horizontal synchronization in VDHSYNC. Specify the frame pixel counter value for a pixel where HSYNC gets asserted (HSYNCYST ART) and width of the HSYNC pulse (HSYNCSTOP) in frame pixel clocks.
Displaying Video in Raw Data Mode 4-51 Video Display Port SPRU629 22) If continuous display is enabled, the video port begins displaying again at the start of the next field or frame.
Video Display Registers Video Display Port 4-52 SPRU629 4.12 Video Display Registers The registers for controlling the video display mode of operation are listed in T able 4 – 5. See the device-specific datasheet for the memory address of these registers.
Video Display Registers 4-53 Video Display Port SPRU629 T able 4 – 5. Video Display Control Registers (Continued) Acronym Section Register Name VDDEFV AL Video Display Default Display V alue Register 4.12.24 VDVINT Video Display V ertical Interrupt Register 4.
Video Display Registers Video Display Port 4-54 SPRU629 T able 4 – 6. Video Display Status Register (VDST A T) Field Descriptions Bit field † symval † V alue Description 31 Reserved – 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Video Display Registers 4-55 Video Display Port SPRU629 4.12.2 Video Display Control Register (VDCTL) The video display is controlled by the video display control register (VDCTL). The VDCTL is shown in Figure 4 – 40 and described in T able 4 – 7.
Video Display Registers Video Display Port 4-56 SPRU629 T able 4 – 7. Video Display Control Register (VDCTL) Field Descriptions (Continued) Bit Description V alue symval † field † Bit Raw Data Mode BT .656 and Y/C Mode V alue symval † field † 30 BLKDIS Block display events bit.
Video Display Registers 4-57 Video Display Port SPRU629 T able 4 – 7. Video Display Control Register (VDCTL) Field Descriptions (Continued) Bit Description V alue symval † field † Bit Raw Data Mode BT .656 and Y/C Mode V alue symval † field † 21 HXS Horizontal external synchronization enable bit.
Video Display Registers Video Display Port 4-58 SPRU629 T able 4 – 7. Video Display Control Register (VDCTL) Field Descriptions (Continued) Bit Description V alue symval † field † Bit Raw Data Mode BT .656 and Y/C Mode V alue symval † field † 13 RGBX RGB extract enable bit.
Video Display Registers 4-59 Video Display Port SPRU629 T able 4 – 7. Video Display Control Register (VDCTL) Field Descriptions (Continued) Bit Description V alue symval † field † Bit Raw Data Mode BT .656 and Y/C Mode V alue symval † field † 6 FRAME ‡ Display frame bit.
Video Display Registers Video Display Port 4-60 SPRU629 4.12.3 Video Display Frame Size Register (VDFRMSZ) The video display frame size register (VDFRMSZ) sets the display channel frame size by setting the ending values for the frame line counter (FLCOUNT) and the frame pixel counter (FPCOUNT).
Video Display Registers 4-61 Video Display Port SPRU629 4.12.4 Video Display Horizontal Blanking Register (VDHBLNK) The video display horizontal blanking register (VDHBLNK) controls the display horizontal blanking. The VDHBLNK is shown in Figure 4 – 42 and described in T able 4 – 9.
Video Display Registers Video Display Port 4-62 SPRU629 T able 4 – 9. Video Display Horizontal Blanking Register (VDHBLNK) Field Descriptions Description Bit field † symval † V alue BT .656 and Y/C Mode Raw Data Mode 31 – 28 Reserved – 0 Reserved.
Video Display Registers 4-63 Video Display Port SPRU629 Figure 4 – 43. Video Display Field 1 V ertical Blanking Start Register (VDVBLKS1) 31 28 27 16 Reserved VBLNKYST ART1 R-0 R/W-0 15 12 1 1 0 Reserved VBLNKXST ART1 R-0 R/W-0 Legend: R = Read only; R/W = Read/Write; - n = value after reset T able 4 – 10.
Video Display Registers Video Display Port 4-64 SPRU629 4.12.6 Video Display Field 1 V ertical Blanking End Register (VDVBLKE1) The video display field 1 vertical blanking end register (VDVBLKE1) controls the end of vertical blanking in field 1. The VDVBLKE1 is shown in Figure 4 – 44 and described in T able 4 – 11 .
Video Display Registers 4-65 Video Display Port SPRU629 T able 4 – 1 1. Video Display Field 1 V ertical Blanking End Register (VDVBLKE1) Field Descriptions Description Bit field † symval † V alue BT .656 and Y/C Mode Raw Data Mode 31 – 28 Reserved – 0 Reserved.
Video Display Registers Video Display Port 4-66 SPRU629 Figure 4 – 45. Video Display Field 2 V ertical Blanking Start Register (VDVBLKS2) 31 28 27 16 Reserved VBLNKYST ART2 R-0 R/W-0 15 12 1 1 0 Reserved VBLNKXST ART2 R-0 R/W-0 Legend: R = Read only; R/W = Read/Write; - n = value after reset T able 4 – 12.
Video Display Registers 4-67 Video Display Port SPRU629 4.12.8 Video Display Field 2 V ertical Blanking End Register (VDVBLKE2) The video display field 2 vertical blanking end register (VDVBLKE2) controls the end of vertical blanking in field 2. The VDVBLKE2 is shown in Figure 4 – 46 and described in T able 4 – 13.
Video Display Registers Video Display Port 4-68 SPRU629 T able 4 – 13. V ideo Display Field 2 Vertical Blanking End Register (VDVBLKE2) Field Descriptions Description Bit field † symval † V alue BT .656 and Y/C Mode Raw Data Mode 31 – 28 Reserved – 0 Reserved.
Video Display Registers 4-69 Video Display Port SPRU629 Figure 4 – 47. Video Display Field 1 Image Offset Register (VDIMGOFF1) 31 30 28 27 16 NV Reserved IMGVOFF1 R/W-0 R-0 R/W-0 15 14 12 1 1 0 NH Reserved IMGHOFF1 R/W-0 R-0 R/W-0 Legend: R = Read only; R/W = Read/Write; - n = value after reset T able 4 – 14 .
Video Display Registers Video Display Port 4-70 SPRU629 4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1) The video display field 1 image size register (VDIMGSZ1) defines the field 1 image area and specifies the size of the displayed image within the active dis- play .
Video Display Registers 4-71 Video Display Port SPRU629 4.12.1 1 V ideo Display Field 2 Image Offset Register (VDIMGOFF2) The video display field 2 image offset register (VDIMGOFF2) defines the field 2 image offset and specifies the starting location of the displayed image relative to the start of the active display .
Video Display Registers Video Display Port 4-72 SPRU629 T able 4 – 16 . Video Display Field 2 Image Offset Register (VDIMGOFF2) Field Descriptions Description Bit field † symval † V alue BT .656 and Y/C Mode Raw Data Mode 31 NV Negative vertical image offset enable bit.
Video Display Registers 4-73 Video Display Port SPRU629 4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2) The video display field 2 image size register (VDIMGSZ2) defines the field 2 image area and specifies the size of the displayed image within the active dis- play .
Video Display Registers Video Display Port 4-74 SPRU629 4.12.13 Video Display Field 1 Timing Register (VDFLDT1) The video display field 1 timing register (VDFLDT1) sets the timing of the field identification signal. The VDFLDT1 is shown in Figure 4 – 51 and described in T able 4 – 18.
Video Display Registers 4-75 Video Display Port SPRU629 4.12.14 Video Display Field 2 Timing Register (VDFLDT2) The video display field 2 timing register (VDFLDT2) sets the timing of the field identification signal. The VDFLDT2 is shown in Figure 4 – 52 and described in T able 4 – 19.
Video Display Registers Video Display Port 4-76 SPRU629 4.12.15 Video Display Threshold Register (VDTHRLD) The video display threshold register (VDTHRLD) sets the display FIFO thresh- old to determine when to load more display data. The VDTHRLD is shown in Figure 4 – 53 and described in T able 4 – 20.
Video Display Registers 4-77 Video Display Port SPRU629 T able 4 – 20. V ideo Display Threshold Register (VDTHRLD) Field Descriptions Description Bit field † symval † V alue BT .656 and Y/C Mode Raw Data Mode 31 – 26 Reserved – 0 Reserved. The reserved bit location is always read as 0.
Video Display Registers Video Display Port 4-78 SPRU629 4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC) The video display horizontal synchronization register (VDHSYNC) controls the timing of the horizontal synchronization signal. The VDHSYNC is shown in Figure 4 – 54 and described in T able 4 – 21.
Video Display Registers 4-79 Video Display Port SPRU629 4.12.17 Video Display Field 1 V ertical Synchronization Start Register (VDVSYNS1) The video display field 1 vertical synchronization start register (VDVSYNS1) controls the start of vertical synchronization in field 1.
Video Display Registers Video Display Port 4-80 SPRU629 4.12.18 Video Display Field 1 V ertical Synchronization End Register (VDVSYNE1) The video display field 1 vertical synchronization end register (VDVSYNE1) controls the end of vertical synchronization in field 1.
Video Display Registers 4-81 Video Display Port SPRU629 4.12.19 Video Display Field 2 V ertical Synchronization Start Register (VDVSYNS2) The video display field 2 vertical synchronization start register (VDVSYNS2) controls the start of vertical synchronization in field 2.
Video Display Registers Video Display Port 4-82 SPRU629 4.12.20 Video Display Field 2 V ertical Synchronization End Register (VDVSYNE2) The video display field 2 vertical synchronization end register (VDVSYNE2) controls the end of vertical synchronization in field 2.
Video Display Registers 4-83 Video Display Port SPRU629 4.12.21 Video Display Counter Reload Register (VDRELOAD) When external horizontal or vertical synchronization are used, the video display counter reload register (VDRELOAD) determines what values are loaded into the counters when an external sync is activated.
Video Display Registers Video Display Port 4-84 SPRU629 4.12.22 Video Display Display Event Register (VDDISPEVT) The video display display event register (VDDISPEVT) is programmed with the number of DMA events to be generated for display field 1 and field 2.
Video Display Registers 4-85 Video Display Port SPRU629 4.12.23 Video Display Clipping Register (VDCLIP) The video display clipping register (VDCLIP) is shown in Figure 4 – 61 and described in T able 4 – 28. The video display module in the BT .656 and Y/C modes performs program- mable clipping.
Video Display Registers Video Display Port 4-86 SPRU629 4.12.24 Video Display Default Display V alue Register (VDDEFV AL) The video display default display value register (VDDEFV AL) defines the default value to be output during the portion of the active video window that is not part of the displayed image.
Video Display Registers 4-87 Video Display Port SPRU629 Figure 4 – 63 . Video Display Default Display V alue Register (VDDEFV AL) — Raw Data Mode 31 20 19 16 Reserved DEFV AL R/W-0 R/W -0 15 0 DEFV AL R/W-0 Legend: R/W = Read/Write; - n = value after reset T able 4 – 29 .
Video Display Registers Video Display Port 4-88 SPRU629 4.12.25 Video Display V ertical Interrupt Register (VDVINT) The video display vertical interrupt register (VDVINT) controls the generation of vertical interrupts in field 1 and field 2. The VDVINT is shown in Figure 4 – 64 and described in T able 4 – 30.
Video Display Registers 4-89 Video Display Port SPRU629 4.12.26 Video Display Field Bit Register (VDFBIT) The video display field bit register (VDFBIT) controls the F bit value in the EA V and SA V timing control codes. The VDFBIT is shown in Figure 4 – 65 and described in T able 4 – 31.
Video Display Registers Video Display Port 4-90 SPRU629 4.12.27 Video Display Field 1 V ertical Blanking Bit Register (VDVBIT1) The video display field 1 vertical blanking bit register (VDVBIT1) controls the V bit value in the EA V and SA V timing control codes for field 1.
Video Display Registers 4-91 Video Display Port SPRU629 T able 4 – 32. V ideo Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Field Descriptions Description Bit field † symval † V alue BT .656 and Y/C Mode Raw Data Mode 31 – 28 Reserved – 0 Reserved.
Video Display Registers Video Display Port 4-92 SPRU629 4.12.28 Video Display Field 2 V ertical Blanking Bit Register (VDVBIT2) The video display field 2 vertical blanking bit register (VDVBIT2) controls the V bit in the EA V and SA V timing control words for field 2.
Video Display Registers 4-93 Video Display Port SPRU629 T able 4 – 33. V ideo Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Field Descriptions Description Bit field † symval † V alue BT .656 and Y/C Mode Raw Data Mode 31 – 28 Reserved – 0 Reserved.
Video Display Registers Recommended V alues Video Display Port 4-94 SPRU629 4.13 Video Display Registers Recommended V alues Sample recommended values (decimal) for video display registers for BT .656 output are given in T able 4 – 34. T able 4 – 34.
Video Display Registers Recommended V alues 4-95 Video Display Port SPRU629 T able 4 – 34. V ideo Display Register Recommended Values (Continued) Register 625/50 V alue 525/60 V alue Field VDVSYNS2 .
Video Display FIFO Registers Video Display Port 4-96 SPRU629 4.14 Video Display FIFO Registers The display FIFO mapping registers are listed in T able 4 – 35.
5-1 General Purpose I/O Operation Signals not used for video display or video capture can be used as general- purpose input/output (GPIO) signals. T opic Page 5.1 GPIO Registers 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Registers General Purpose I/O Operation 5-2 SPRU629 5.1 GPIO Registers The GPIO register set includes required registers such as peripheral identifi- cation and emulation control. The GPIO registers are listed in T able 5 – 1. See the device-specific datasheet for the memory address of these registers.
GPIO Registers 5-3 General Purpose I/O Operation SPRU629 5.1.1 Video Port Peripheral Identification Register (VPPID) The video port peripheral identification register (VPPID) is a read-only register used to store information about the peripheral. The VPPID is shown in Figure 5 – 1 and described in T able 5 – 2.
GPIO Registers General Purpose I/O Operation 5-4 SPRU629 5.1.2 Video Port Peripheral Control Register (PCR) The video port peripheral control register (PCR) determines operation during emulation. The video port peripheral control register is shown in Figure 5 – 2 and described in T able 5 – 3.
GPIO Registers 5-5 General Purpose I/O Operation SPRU629 T able 5 – 3. Video Port Peripheral Control Register (PCR) Field Descriptions Bit field † symval † V alue Description 31 – 3 Reserved Reserved. The reserved bit location is always read as 0.
GPIO Registers General Purpose I/O Operation 5-6 SPRU629 5.1.3 Video Port Pin Function Register (PFUNC) The video port pin function register (PFUNC) selects the video port pins as GPIO. The PFUNC is shown in Figure 5 – 3 and described in T able 5 – 4.
GPIO Registers 5-7 General Purpose I/O Operation SPRU629 T able 5 – 4. Video Port Pin Function Register (PFUNC) Field Descriptions (Continued) Bit Description V alue symval † field † 20 PFUNC20 PFUNC20 bit determines if VCTL1 pin functions as GPIO.
GPIO Registers General Purpose I/O Operation 5-8 SPRU629 5.1.4 Video Port Pin Direction Register (PDIR) The video port pin direction register (PDIR) is shown in Figure 5 – 4 and described in T able 5 – 5. The PDIR controls the direction of IO pins in the video port for those pins set by PFUNC.
GPIO Registers 5-9 General Purpose I/O Operation SPRU629 T able 5 – 5. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued) Bit Description V alue symval † field † 21 PDIR21 PDIR21 bit controls the direction of the VCTL2 pin. VCTL2IN 0 Pin functions as input.
GPIO Registers General Purpose I/O Operation 5-10 SPRU629 T able 5 – 5. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued) Bit Description V alue symval † field † 8 PDIR8 PDIR8 bit controls the direction of the VDA T A[9 – 8] pins.
GPIO Registers 5-1 1 General Purpose I/O Operation SPRU629 5.1.5 Video Port Pin Data Input Register (PDIN) The read-only video port pin data input register (PDIN) is shown in Figure 5 – 5 and described in T able 5 – 6. PDIN reflects the state of the video port pins.
GPIO Registers General Purpose I/O Operation 5-12 SPRU629 T able 5 – 6. Video Port Pin Data Input Register (PDIN) Field Descriptions Bit field † symval † V alue Description 31 – 23 Reserved – 0 Reserved. The reserved bit location is always read as 0.
GPIO Registers 5-13 General Purpose I/O Operation SPRU629 5.1.6 Video Port Pin Data Output Register (PDOUT) The video port pin data output register (PDOUT) is shown in Figure 5 – 6 and described in T able 5 – 7. The bits of PDOUT determine the value driven on the corresponding GPIO pin, if the pin is configured as an output.
GPIO Registers General Purpose I/O Operation 5-14 SPRU629 T able 5 – 7. Video Port Pin Data Out Register (PDOUT) Field Descriptions Bit field † symval † V alue Description 31 – 23 Reserved – 0 Reserved. The reserved bit location is always read as 0.
GPIO Registers 5-15 General Purpose I/O Operation SPRU629 5.1.7 Video Port Pin Data Set Register (PDSET) The video port pin data set register (PDSET) is shown in Figure 5 – 7 and described in T able 5 – 8.
GPIO Registers General Purpose I/O Operation 5-16 SPRU629 T able 5 – 8. Video Port Pin Data Set Register (PDSET) Field Descriptions Bit field † symval † V alue Description 31 – 23 Reserved – 0 Reserved. The reserved bit location is always read as 0.
GPIO Registers 5-17 General Purpose I/O Operation SPRU629 5.1.8 Video Port Pin Data Clear Register (PDCLR) The video port pin data clear register (PDCLR) is shown in Figure 5 – 8 and described in T able 5 – 9.
GPIO Registers General Purpose I/O Operation 5-18 SPRU629 T able 5 – 9. Video Port Pin Data Clear Register (PDCLR) Field Descriptions Bit field † symval † V alue Description 31 – 23 Reserved – 0 Reserved. The reserved bit location is always read as 0.
GPIO Registers 5-19 General Purpose I/O Operation SPRU629 5.1.9 Video Port Pin Interrupt Enable Register (PIEN) The video port pin interrupt enable register (PIEN) is shown in Figure 5 – 9 and described in T able 5 – 10. The GPIOs can be used to generate DSP interrupts or DMA events.
GPIO Registers General Purpose I/O Operation 5-20 SPRU629 T able 5 – 10. V ideo Port Pin Interrupt Enable Register (PIEN) Field Descriptions Bit field † symval † V alue Description 31 – 23 Reserved – 0 Reserved. The reserved bit location is always read as 0.
GPIO Registers 5-21 General Purpose I/O Operation SPRU629 5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL) The video port pin interrupt polarity register (PIPOL) is shown in Figure 5 – 10 and described in T able 5 – 1 1. The PIPOL determines the GPIO pin signal polarity that generates an interrupt.
GPIO Registers General Purpose I/O Operation 5-22 SPRU629 T able 5 – 1 1. Video Port Pin Interrupt Polarity Register (PIPOL) Field Descriptions Bit field † symval † V alue Description 31 – 23 Reserved – 0 Reserved. The reserved bit location is always read as 0.
GPIO Registers 5-23 General Purpose I/O Operation SPRU629 5.1.1 1 Video Port Pin Interrupt Status Register (PIST A T) The video port pin interrupt status register (PIST A T) is shown in Figure 5 – 11 and described in T able 5 – 12. PIST A T is a read-only register that indicates the GPIO pin that has a pending interrupt.
GPIO Registers General Purpose I/O Operation 5-24 SPRU629 T able 5 – 12. V ideo Port Pin Interrupt Status Register (PIST A T) Field Descriptions Bit field † symval † V alue Description 31 – 23 Reserved – 0 Reserved. The reserved bit location is always read as 0.
GPIO Registers 5-25 General Purpose I/O Operation SPRU629 5.1.12 Video Port Pin Interrupt Clear Register (PICLR) The video port pin interrupt clear register (PICLR) is shown in Figure 5 – 12 and described in T able 5 – 13. PICLR is an alias of the video port pin interrupt status register (PIST A T) for writes only .
GPIO Registers General Purpose I/O Operation 5-26 SPRU629 T able 5 – 13. V ideo Port Pin Interrupt Clear Register (PICLR) Field Descriptions Bit field † symval † V alue Description 31 – 23 Reserved – 0 Reserved. The reserved bit location is always read as 0.
6-1 VCXO Interpolated Control Port SPRU629 VCXO Interpolated Control Port This chapter provides an overview of the VCXO interpolated control (VIC) port. T opic Page 6.1 Overview 6-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview VCXO Interpolated Control Port 6-2 SPRU629 6.1 Overview The VCXO interpolated control (VIC) port provides single-bit interpolated VCXO control with resolution from 9 bits to up to 16 bits. The frequency of inter- polation is dependent on the resolution needed.
Interface 6-3 VCXO Interpolated Control Port SPRU629 6.2 Interface The pin list for VIC port is shown in T able 6 – 1 (pins are 3.3V I/Os). T able 6 – 1. VIC Port Interface Signals VIC Port Signal Direction Description VCTL Output VCXO control STCLK Input System time clock 6.
Operational Details VCXO Interpolated Control Port 6-4 SPRU629 Any time a packet with a PCR is received, the timestamp for that packet is compared with the PCR value in software. A PLL is implemented in software to synchronize the STCLK with the system time clock.
Enabling VIC Port 6-5 VCXO Interpolated Control Port SPRU629 6.4 Enabling VIC Port Perform the following steps to enable the VIC port. 1) Clear the GO bit in the VIC control register (VICCTL) to 0. 2) Set the PRECISION bits in VICCTL to the desired precision.
VIC Port Registers VCXO Interpolated Control Port 6-6 SPRU629 6.5.1 VIC Control Register (VICCTL) The VIC control register (VICCTL) is shown in Figure 6 – 3 and described in T able 6 – 4.
VIC Port Registers 6-7 VCXO Interpolated Control Port SPRU629 T able 6 – 4. VIC Control Register (VICCTL) Field Descriptions (Continued) Bit Description V alue symval † field † 0 GO The GO bit can be written to at any time. 0 0 The VICDIV and VICCTL registers can be written to without affecting the operation of the VIC port.
VIC Port Registers VCXO Interpolated Control Port 6-8 SPRU629 6.5.2 VIC Input Register (VICIN) The DSP writes the input bits for VCXO interpolated control in the VIC input register (VICIN). The DSP decides how often to update VICIN. The DSP can write to VICIN only when the GO bit in the VIC control register (VICCTL) is set to 1.
VIC Port Registers 6-9 VCXO Interpolated Control Port SPRU629 6.5.3 VIC Clock Divider Register (VICDIV) The VIC clock divider register (VICDIV) defines the clock divider for the VIC interpolation frequency . The VIC interpolation frequency is obtained by divid- ing the module clock.
A-1 Appendix A V ideo Port Configuration Examples This appendix describes how to configure the video port in different modes with the help of examples. All examples in this appendix use the video port Chip Support Library (CSL). T opic Page A.1 Example 1: Noncontinuous Frame Capture for 525/60 Format A-2 .
Example 1: Noncontinuous Frame Capture for 525/60 Format Video Port Configuration Examples A-2 SPRU629 A.1 Example 1: Noncontinuous Frame Capture for 525/60 Format This is an example that explains how to configure the video port for 8-bit BT .656 noncontinuous frame capture on channel A for 525/60 format.
Example 1: Noncontinuous Frame Capture for 525/60 Format A-3 Video Port Configuration Examples SPRU629 /* –––––––––––––––––––––––––––––––––––––––––––– */ /* EDMA parameters for capture Y event that are */ /* specific to this example.
Example 1: Noncontinuous Frame Capture for 525/60 Format Video Port Configuration Examples A-4 SPRU629 /* Error flags */ volatile Uint32 capChaAOverrun = 0; volatile Uint32 capChaASyncError = 0; volat.
Example 1: Noncontinuous Frame Capture for 525/60 Format A-5 Video Port Configuration Examples SPRU629 /* Set last pixel to be captured in Field2 (VCA_STOP2 reg) */ VP_RSETH(vpCaptureHandle, VCASTOP2,.
Example 1: Noncontinuous Frame Capture for 525/60 Format Video Port Configuration Examples A-6 SPRU629 /* –––––––––––––– */ /* enable capture */ /* ––––––––.
Example 1: Noncontinuous Frame Capture for 525/60 Format A-7 Video Port Configuration Examples SPRU629 if(vpis & _VP_VPIS_SFDA_MASK) /* short field detect */ { capChaAShortFieldDetect++; VP_FSETH(.
Example 1: Noncontinuous Frame Capture for 525/60 Format Video Port Configuration Examples A-8 SPRU629 /* Configure Cb EDMA channel to move data from CbSRCA */ /* (FIFO) to Cb – data buffer, capChaA.
Example 1: Noncontinuous Frame Capture for 525/60 Format A-9 Video Port Configuration Examples SPRU629 void configVPCapEDMAChannel(EDMA_Handle *edmaHandle, Int32 eventId, Int32 *tccNum, Uint32 srcAddr.
Example 2: Noncontinuous Frame Display for 525/60 Format Video Port Configuration Examples A-10 SPRU629 A.2 Example 2: Noncontinuous Frame Display for 525/60 Format This is an example that explains how to configure the video port for 8-bit BT .656 noncontinuous frame display for 525/60 format.
Example 2: Noncontinuous Frame Display for 525/60 Format A-1 1 Video Port Configuration Examples SPRU629 /* ––––––––––––––––––––––––––––––.
Example 2: Noncontinuous Frame Display for 525/60 Format Video Port Configuration Examples A-12 SPRU629 /* –––––––––––––––––––––––––––––––.
Example 2: Noncontinuous Frame Display for 525/60 Format A-13 Video Port Configuration Examples SPRU629 /******************************************************************/ /* Description : 8 – bit BT.656 non – continuous frame display */ /* */ /* Some important field descriptions: */ /* */ /* DMODE = 000, 8 – bit BT.
Example 2: Noncontinuous Frame Display for 525/60 Format Video Port Configuration Examples A-14 SPRU629 /* –––––––––––––––––––––––––––––––.
Example 2: Noncontinuous Frame Display for 525/60 Format A-15 Video Port Configuration Examples SPRU629 /* set vertical blanking start for field2 */ VP_RSETH(vpDisplayHandle , VDVBLKS2, VP_VDVBLKS2_RM.
Example 2: Noncontinuous Frame Display for 525/60 Format Video Port Configuration Examples A-16 SPRU629 /* set vertical sync end for field2 (VCTL2S) */ VP_RSETH(vpDisplayHandle , VDVSYNE2, VP_VDVSYNE2.
Example 2: Noncontinuous Frame Display for 525/60 Format A-17 Video Port Configuration Examples SPRU629 /* –––––––––––––– */ /* enable display */ /* –––––––.
Example 2: Noncontinuous Frame Display for 525/60 Format Video Port Configuration Examples A-18 SPRU629 /* –––––––––––––––––––––––––––––––.
Example 2: Noncontinuous Frame Display for 525/60 Format A-19 Video Port Configuration Examples SPRU629 /* enable three EDMA channels */ EDMA_enableChannel(hEdmaVPDispY); EDMA_enableChannel(hEdmaVPDis.
Example 2: Noncontinuous Frame Display for 525/60 Format Video Port Configuration Examples A-20 SPRU629 /* Configure EDMA parameters */ EDMA_configArgs( *edmaHandle, EDMA_OPT_RMK( EDMA_OPT_PRI_MEDIUM,.
Index Index-1 SPRU629 Index A ancillary data capture 3-31 ancillary data display 4-25 architecture 1-3 A TC bit in TSISTCMPL 3-78 in TSISTCMPM 3-79 A TCM bit in TSISTMSKL 3-80 in TSISTMSKM 3-81 B BLKC.
Index Index-2 SPRU629 CbDEFV AL bits 4-86 CBDST 4-96 CBSRCx 3-83 CCMP A bit in VPIE 2-21 in VPIS 2-24 CCMPB bit in VPIE 2-21 in VPIS 2-24 CF1 bit in VCACTL 3-53 in VCBCTL 3-68 CF2 bit in VCACTL 3-53 i.
Index Index-3 SPRU629 F F1C bit 3-50 F1D bit 4-53 F2C bit 3-50 F2D bit 4-53 FBITCLR bits 4-89 FBITSET bits 4-89 FIFO overrun BT .656 mode 3-45 raw data mode 3-47 TSI capture mode 3-48 video display 4-51 Y/C mode 3-45 FIFO packing BT .656 mode 3-9 raw data mode 3-33 TSI capture mode 3-41 Y/C mode 3-14 FIFO unpacking BT .
Index Index-4 SPRU629 LFDE bit in VCACTL 3-53 in VCBCTL 3-68 M mode selection TSI capture 3-2 video capture 3-2 video display 4-2 N NH bit in VDIMGOFF1 4-69 in VDIMGOFF2 4-71 noncontinuous frame captu.
Index Index-5 SPRU629 registers (continued) VIC port 6-5 VIC clock divider register (VICDIV) 6-9 VIC control register (VICCTL) 6-6 VIC input register (VICIN) 6-8 video capture 3-49 Cb FIFO source regi.
Index Index-6 SPRU629 registers (continued) video display frame size register (VDFRMSZ) 4-60 horizontal blanking register (VDHBLNK) 4-61 horizontal synchronization register (VDHSYNC) 4-78 recommended .
Index Index-7 SPRU629 TSI clock initialization LSB register (TSICLKINITL) 3-74 TSI clock initialization MSB register (TSICLKINITM) 3-75 TSI system time clock compare LSB register (TSISTCMPL) 3-78 TSI .
Index Index-8 SPRU629 VDCLIP 4-85 VDCTL 4-55 VDDEFV AL 4-86 VDDISPEVT 4-84 VDEN 4-55 VDFBIT 4-89 VDFLD bit 4-53 VDFLDT1 4-74 VDFLDT2 4-75 VDFRMSZ 4-60 VDHBLNK 4-61 VDHSYNC 4-78 VDIMGOFF1 4-68 VDIMGOFF.
Index Index-9 SPRU629 video capture channel B vertical interrupt register (VCBVINT) 3-63 video capture FIFO configurations 1-6 video capture mode BT .656 3-3 raw data 3-32 TSI 3-37 Y/C 3-12 video disp.
Index Index-10 SPRU629 video port FIFO 1-5 video port interrupt enable register (VPIE) 2-21 video port interrupt status register (VPIS) 2-24 video port peripheral control register (PCR) 5-4 video port.
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