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TMS320DM643x DMP VLYNQ Port User's Guide Literature Number: SPRU938B September 2007.
2 SPRU938B – September 2007 Submit Documentation Feedback.
Contents Preface ............................................................................................................................... 7 1 Introduction .........................................................................................
A.2 Special 8b/10b Code Groups ................................................................................. 39 A.3 Supported Ordered Sets ....................................................................................... 39 A.4 VLYNQ 2.0 Packet Format .
List of Figures 1 VLYNQ Port Functional Block Diagram ................................................................................... 9 2 External Clock Block Diagram ................................................................................
List of Tables 1 VLYNQ Signal Descriptions ............................................................................................... 11 2 Address Translation Example (Single Mapped Region) ........................................................
Preface SPRU938B – September 2007 Read This First About This Manual This document describes the VLYNQ port in the TMS320DM643x Digital Media Processor (DMP). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h.
1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide SPRU938B – September 2007 VLYNQ Port The VLYNQ™ communications interface port is a low pin count, high-speed, point-to-point serial interface in the TMS320DM643x Digital Media Processor (DMP) used for connecting to host processors and other VLYNQ compatible devices.
www.ti.com 1.3 Functional Block Diagram Slave config bus Interface Master config Interface bus VL YNQmodule VL YNQregister access CPU/EDMA initiated transfersto remotedevice Offchip (remote) deviceaccess System CPU/EDMA memory System VL YNQ_SCRUN VL YNQ_CLOCK VL YNQ_RXD[3:0] VL YNQ_TXD[3:0] INT55 interruptcontroller VLQINT 1.
www.ti.com 2 Peripheral Architecture 2.1 Clock Control VL YNQ CLKDIR=0 DMxxxdevice VL YNQ_CLK VL YNQ CLKDIR=0 VL YNQdevice VL YNQ CLKDIR=1 DMxxxdevice VL YNQ_CLK VL YNQ CLKDIR=1 VL YNQdevice VL YNQ internal sysclk Don’t care Peripheral Architecture This section discusses the architecture and basic functions of the VLYNQ peripheral.
www.ti.com 2.2 Signal Descriptions 2.3 Pin Multiplexing 2.4 Protocol Description Peripheral Architecture The VLYNQ module on the DM643x device supports 1 to 4 bit-wide RX/TX configurations. Chip-level pin multiplexing registers control the configuration.
www.ti.com 2.5 VLYNQ Functional Description Address translation commands Outbound Outbound command FIFO data Return FIFO data FIFO Return command Inbound FIFO Registers translation Address TxSM 8B/10B.
www.ti.com 2.5.1 Write Operations Address translation commands Outbound Outbound command FIFO data Return FIFO data FIFO Return command Inbound FIFO Registers translation Address TxSM 8B/10B encoding .
www.ti.com 2.5.2 Read Operations Address translation commands Outbound Outbound command FIFO data Return FIFO data FIFO Return command Inbound FIFO Registers translation Address TxSM 8B/10B encoding S.
www.ti.com 2.6 Initialization 2.7 Auto-Negotiation Peripheral Architecture Note: Not servicing read operations results in deadlock. The only way to recover from a deadlock situation is to perform a hard reset.
www.ti.com 2.8 Address Translation Peripheral Architecture Remote VLYNQ device(s) are memory mapped to the local (host) device’s address space when a link is established (this is similar to any other on-chip peripherals).
www.ti.com Mapregion1 Mapregion2 Mapregion3 Mapregion4 0400:0000h (4C00:0000hon DM643xdevice) 0800:0000h 07FF:FFFFh 0800:0100h 0800:00FFh 0801:0100h 0801:00FFh 0841:00FFh.
www.ti.com Peripheral Architecture DM643x VLYNQ Module: 4C00 : 0054h Initial address at the slave configuration bus 0000 : 0054h Initial address [25:0] at the slave configuration bus interface subtrac.
www.ti.com 2.9 Flow Control Peripheral Architecture Example 1. Address Translation Example The remote address 0400:0154h (or 0000 0054h) was translated to 8200:0054h on the DM643x (local) device in this example.
www.ti.com 2.10 Reset Considerations 2.10.1 Software Reset Considerations 2.10.2 Hardware Reset Considerations 2.11 Interrupt Support 2.11.1 Interrupt Events and Requests Peripheral Architecture Peripheral clock and reset control is done through the power and sleep controller (PSC) module that is included with the device.
www.ti.com VL YNQinterrupt pending/setregister (INTPENDSET) VL YNQ Status/clear register (INTST A TCLR) OR T ransmitserial interruptpacket VLQINT (INT55) 14 0 INTLOCAL VL YNQcontrolregister(CTRL) Serialbuserror (LERROR/RERROR) CPUwrites Serialinterrupt packetfrom remotedevice INTLOCAL=1 INTLOCAL=0 2.
www.ti.com 2.11.3 Remote Interrupts 2.11.4 Serial Bus Error Interrupts 2.12 EDMA Event Support Peripheral Architecture Remote interrupts occur when an interrupt packet is received over the serial interface from a remote device.
www.ti.com 2.13 Power Management 2.14 Endianness Considerations 2.15 Emulation Considerations Peripheral Architecture The VLYNQ module can be placed in reduced-power modes to conserve power during periods of low activity. The power management of the VLYNQ module is controlled by the processor Power and Sleep Controller (PSC).
www.ti.com 3 VLYNQ Port Registers VLYNQ Port Registers Table 4 describes the address space for the VLYNQ registers and memory. Table 4. VLYNQ Register Address Space Block Name Start Address End Addres.
www.ti.com 3.1 Revision Register (REVID) VLYNQ Port Registers The revision register (REVID) contains the major and minor revisions for the VLYNQ module. The REVID is shown in Figure 9 and described in Table 6 . Figure 9. Revision Register (REVID) 31 16 ID R-1h 15 8 7 0 REVMAJ REVMIN R-2h R-6h LEGEND: R = Read only; - n = value after reset Table 6.
www.ti.com 3.2 Control Register (CTRL) VLYNQ Port Registers The control register (CTRL) determines operation of the VLYNQ module. The CTRL is shown in Figure 10 and described in Table 7 .
www.ti.com VLYNQ Port Registers Table 7. Control Register (CTRL) Field Descriptions (continued) Bit Field Value Description 7 INT2CFG Interrupt to configuration register. Determines which register is written with the status contained in interrupt packets that are received over the serial interface.
www.ti.com 3.3 Status Register (STAT) VLYNQ Port Registers The status register (STAT) is used to detect conditions that may be of interest to the system designer.
www.ti.com VLYNQ Port Registers Table 8. Status Register (STAT) Field Descriptions (continued) Bit Field Value Description 8 RERROR Remote Error. Write a 1 to this bit to clear it. 0 No error This bit indicates that a downstream VLYNQ module has detected a packet error.
www.ti.com 3.4 Interrupt Priority Vector Status/Clear Register (INTPRI) 3.5 Interrupt Status/Clear Register (INTSTATCLR) VLYNQ Port Registers The interrupt priority vector status/clear register (INTPRI) displays the highest priority vector with a pending interrupt when read.
www.ti.com 3.6 Interrupt Pending/Set Register (INTPENDSET) 3.7 Interrupt Pointer Register (INTPTR) VLYNQ Port Registers The interrupt pending/set register (INTPENDSET) indicates the pending interrupt status when the INTLOCAL bit in the control register (CTRL) is not set.
www.ti.com 3.8 Transmit Address Map Register (XAM) VLYNQ Port Registers The transmit address map register (XAM) is used to translate transmit packet addresses to remote device configuration bus addresses. The XAM is shown in Figure 16 and described in Table 13 .
www.ti.com 3.9 Receive Address Map Size 1 Register (RAMS1) 3.10 Receive Address Map Offset 1 Register (RAMO1) VLYNQ Port Registers The receive address map size 1 register (RAMS1) is used to identify the intended destination of inbound serial packets. The RAMS1 is shown in Figure 17 and described in Table 14 .
www.ti.com 3.11 Receive Address Map Size 2 Register (RAMS2) 3.12 Receive Address Map Offset 2 Register (RAMO2) VLYNQ Port Registers The receive address map size 2 register (RAMS2) is used to identify the intended destination of inbound serial packets.
www.ti.com 3.13 Receive Address Map Size 3 Register (RAMS3) 3.14 Receive Address Map Offset 3 Register (RAMO3) VLYNQ Port Registers The receive address map size 3 register (RAMS3) is used to identify the intended destination of inbound serial packets.
www.ti.com 3.15 Receive Address Map Size 4 Register (RAMS4) 3.16 Receive Address Map Offset 4 Register (RAMO4) VLYNQ Port Registers The receive address map size 4 register (RAMS4) is used to identify the intended destination of inbound serial packets.
www.ti.com 3.17 Chip Version Register (CHIPVER) 3.18 Auto Negotiation Register (AUTNGO) VLYNQ Port Registers VLYNQ allows inter-connection of many VLYNQ devices. In order for software to control the device functions, there must be a mechanism that allows the software to identify VLYNQ devices.
www.ti.com 4 Remote Configuration Registers Remote Configuration Registers The remote configuration registers listed in Table 24 are the same registers as previously described, but they are for the remote VLYNQ device.
www.ti.com Appendix A VLYNQ Protocol Specifications A.1 Introduction A.2 Special 8b/10b Code Groups A.3 Supported Ordered Sets Appendix A VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allow for in-band packet delineation and control.
www.ti.com A.3.1 Idle (/I/) A.3.2 End of Packet (/T/) A.3.3 Byte Disable (/M/) A.3.4 Flow Control Enable (/P/) A.3.5 Flow Control Disable (/C/) A.3.6 Error Indication (/E/) A.
www.ti.com VLYNQ 2.0 Packet Format Table A-3. Packet Format (10-bit Symbol Representation) Description Field Value Description PKTTYPE[3:0] This field indicates the packet type. 0000 Reserved 0001 Write with address increment. 0010 Reserved 0011 Write 32-bit word with address increment.
www.ti.com A.5 VLYNQ 2.X Packets VLYNQ 2.X Packets An example of what can happen to a write burst due to remote and local FIFO state changes and the link pulse timer expiring is shown in Example A-1 . This protocol can be extended to apply to multiple channels; therefore, the data return channel is logically isolated from the command channel.
www.ti.com VLYNQ 2.X Packets A command, length, address, and start receive data from the idle stream. A flow enable was received for the command channel, but there is data to return, so the flow is followed by a channel 1 descriptor (the command for return data actually indicates a channel 1), and the channel 1 packet is now under way.
www.ti.com Appendix B Write/Read Performance B.1 Introduction B.2 Write Performance Appendix B The following sections discuss the write versus read performance and how the throughput (read or write) should be calculated for a given data width and serial clock frequency.
www.ti.com Write Performance Table B-1. Scaling Factors Burst Size in 32-bit words Data Bytes Overhead Bytes Scaling Factor 1 4 6 40% 4 16 7 69.56% 8 32 7 82.05% 16 64 7 90.14% Table B-2. Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ) Interface Running at 76.
www.ti.com B.3 Read Performance Read Performance Since reads must complete a transmit-remote read-receive cycle before starting another read transaction, the data throughput is lower as compared to writes.
www.ti.com Appendix C Revision History Appendix C Table C-1 lists the changes made since the previous version of this document. Table C-1. Document Revision History Reference Additions/Modifications/Deletions Section 2.8 Changed fourth paragraph. Added NOTE.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
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