Benutzeranleitung / Produktwartung MSP430x1xx des Produzenten Texas Instruments
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2005 Mixed Signal Products User ’ s G uide SLAU049E.
IMPORT ANT NOTICE T exas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Related Documentation From T exas Instruments iii Preface About This Manual This manual discusses modules and peripherals of the MSP430x1xx family of devices. Each discussion presents the module or peripheral in a general sense.
Glossary iv Glossary ACLK Auxiliary Clock See Basic Clock Module ADC Analog-to-Digital Converter BOR Brown-Out Reset See System Resets, Interrupts, and Operating Modes BSL Bootstrap Loader See www .
Register Bit Conventions v Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Register Bit Accessibility and.
vi.
Contents vii 1 Introduction 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Architecture 1-2 . . . . . . . . . . . . . . . . . .
Contents viii 3 RISC 16-Bit CPU 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 CPU Introduction 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents ix 6 Supply V oltage Supervisor 6-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 SVS Introduction 6-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents x 10 W atchdog Timer 10-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 W atchdog Timer Introduction 10-2 . . . . . . . . . . . . . . . . . . . . . . . . .
Contents xi 14 USART Peripheral Interface, SPI Mode 14-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 USAR T Introduction: SPI Mode 14-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents xii 18 ADC10 18-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1 ADC10 Introduction 18-2 . . . . . . . . . . . . . . . . . . . . . . . . .
1-1 Introduction This chapter describes the architecture of the MSP430. T opic Page 1.1 Architecture 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Flexible Clock System 1-2 .
Architecture 1-2 Introduction 1.1 Architecture Th e MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clock system that interconnect using a von-Neumann common memory address bus (MAB) and memory data bus (MDB).
Embedded Emulation 1-3 Introduction Figure 1−1. MSP430 Architecture ACLK Bus Conv . Peripheral MAB 16-Bit MDB 16-Bit MCLK SMCLK Clock System Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral W atchdog RAM Flash/ RISC CPU 16-Bit JT AG/Debug ACLK SMCLK ROM MDB 8-Bit JT AG 1.
Address Space 1-4 Introduction 1.4 Address Space The MSP430 von-Neumann architecture has one address space shared with special function registers (SFRs), peripherals, RAM, and Flash/ROM memory as shown in Figure 1−2. See the device-specific data sheets for specific memory maps.
Address Space 1-5 Introduction 1.4.3 Peripheral Modules Peripheral modules are mapped into the address space. The address space from 0100 to 01FFh is reserved for 16-bit peripheral modules.
1-6 Introduction.
2-1 System Resets, Interrupts, and Operating Modes This chapter describes the MSP430x1xx system resets, interrupts, and operating modes.
System Reset and Initialization 2-2 System Resets, Interrupts, and Operating Modes 2.1 System Reset and Initialization Th e system reset circuitry shown in Figure 2−1 sources both a power-on reset (POR) and a power-up clear (PUC) signal.
System Reset and Initialization 2-3 System Resets, Interrupts, and Operating Modes 2.1.1 Power-On Reset (POR) When the V CC rise time is slow , the POR detector holds the POR signal active until V CC has risen above the V POR level, as shown in Figure 2−2.
System Reset and Initialization 2-4 System Resets, Interrupts, and Operating Modes 2.1.2 Brownout Reset (BOR) Some devices have a brownout reset circuit (see device-specific datasheet) that replaces the POR detect and POR delay circuits.
System Reset and Initialization 2-5 System Resets, Interrupts, and Operating Modes 2.1.3 Device Initial Conditions After System Reset After a POR, the initial MSP430 conditions are: - The RST /NMI pin is configured in the reset mode. - I/ O pins are switched to input mode as described in the Digital I/O chapter .
System Reset and Initialization 2-6 System Resets, Interrupts, and Operating Modes 2.2 Interrupts The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as shown in Figure 2−4. The nearer a module is to the CPU/NMIRS, the higher the priority .
System Reset and Initialization 2-7 System Resets, Interrupts, and Operating Modes 2.2.1 (Non)-Maskable Interrupts (NMI) (Non)-maskable NMI interrupts are not masked by the general interrupt enable bit (GIE), but are enabled by individual interrupt enable bits (NMIIE, ACCVIE, OFIE).
System Reset and Initialization 2-8 System Resets, Interrupts, and Operating Modes Figure 2−5. Block Diagram of (Non)-Maskable Interrupt Sources Flash Module KEYV System Reset Generator V CC POR PUC WDTQn EQU PUC POR PUC POR NMIRS Clear S WDTIFG IRQ WDTIE Clear IE1.
System Reset and Initialization 2-9 System Resets, Interrupts, and Operating Modes Flash Access Violation Th e flash ACCVIFG flag is set when a flash access violation occurs. The flash access violation can be enabled to generate an NMI interrupt by setting the ACCVIE bit.
System Reset and Initialization 2-10 System Resets, Interrupts, and Operating Modes Example of an NMI Interrupt Handler Th e NMI interrupt is a multiple-source interrupt. An NMI interrupt automatically resets the NMIIE, OFIE and ACCVIE interrupt-enable bits.
System Reset and Initialization 2-1 1 System Resets, Interrupts, and Operating Modes Each individual peripheral interrupt is discussed in the associated peripheral module chapter in this manual.
System Reset and Initialization 2-12 System Resets, Interrupts, and Operating Modes Return From Interrupt The interrupt handling routine terminates with the instruction: RETI (return from an interrupt service routine) The return from the interrupt takes 5 cycles to execute the following actions and is illustrated in Figure 2−8.
System Reset and Initialization 2-13 System Resets, Interrupts, and Operating Modes 2.2.4 Interrupt V ectors The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h as described in T able 2−1.
Operating Modes 2-14 System Resets, Interrupts, and Operating Modes 2.3 Operating Modes The MSP430 family is designed for ultralow-power applications and uses different operating modes shown in Figure 2−10.
Operating Modes 2-15 System Resets, Interrupts, and Operating Modes Figure 2−10. MSP430x1xx Operating Modes For Basic Clock System Active Mode CPU Is Active Peripheral Modules Are Active LPM0 CPU Of.
Operating Modes 2-16 System Resets, Interrupts, and Operating Modes 2.3.1 Entering and Exiting Low-Power Modes An enabled interrupt event wakes the MSP430 from any of the low-power operating modes.
Principles for Low - Power Applications 2-17 System Resets, Interrupts, and Operating Modes 2.4 Principles for Low - Power Applications Often, the most important factor for reducing power consumption is using the MSP430’ s clock system to maximize the time in LPM3.
2-18 System Resets, Interrupts, and Operating Modes.
3-1 RISC 16-Bit CPU ! This chapter describes the MSP430 CPU, addressing modes, and instruction set. T opic Page 3.1 CPU Introduction 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Introduction 3-2 RISC 16-Bit CPU 3.1 CPU Introduction The CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing and t h e use of high-level languages such as C. The CPU can address the complete address range without paging.
CPU Introduction 3-3 RISC 16-Bit CPU Figure 3−1. CPU Block Diagram 0 15 MDB − Memory Data Bus Memory Address Bus − MAB 16 Zero, Z Carry , C Overflow , V Negative, N 16−bit ALU dst src R8 Gener.
CPU Registers 3-4 RISC 16-Bit CPU 3.2 CPU Registers The CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 have dedicated functions. R4 to R15 are working registers for general use. 3.2.1 Program Counter (PC) The 16-bit program counter (PC/R0) points to the next instruction to be executed.
CPU Registers 3-5 RISC 16-Bit CPU 3.2.2 Stack Pointer (SP) The stack pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all instructions and addressing modes.
CPU Registers 3-6 RISC 16-Bit CPU 3.2.3 Status Register (SR) The status register (SR/R2), used as a source or destination register , can be used in the register mode only addressed with word instructions. The remain- ing combinations of addressing modes are used to support the constant gen- erator .
CPU Registers 3-7 RISC 16-Bit CPU 3.2.4 Constant Generator Registers CG1 and CG2 Six commonly-used constants are generated with the constant generator registers R2 and R3, without requiring an additional 16-bit word of program code. The constants are selected with the source-register addressing modes (As), as described in T able 3−2.
CPU Registers 3-8 RISC 16-Bit CPU 3.2.5 General−Purpose Registers R4 - R15 The twelve registers, R4−R15, are general-purpose registers. All of these registers can be used as data registers, address pointers, or index values a nd can be accessed with byte or word instructions as shown in Figure 3−7.
Addressing Modes 3-9 RISC 16-Bit CPU 3.3 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions. The bit numbers in T able 3−3 describe the contents of the As (source) and Ad (destination) mode bits.
Addressing Modes 3-10 RISC 16-Bit CPU 3.3.1 Register Mode The register mode is described in T able 3−4. T able 3−4. Register Mode Description Assembler Code Content of ROM MOV R10,R11 MOV R10,R11 Length: One or two words Operation: Move the content of R10 to R1 1.
Addressing Modes 3-1 1 RISC 16-Bit CPU 3.3.2 Indexed Mode The indexed mode is described in T able 3−5. T able 3−5. Indexed Mode Description Assembler Code Content of ROM MOV 2(R5),6(R6) MOV X(R5),.
Addressing Modes 3-12 RISC 16-Bit CPU 3.3.3 Symbolic Mode The symbolic mode is described in T able 3−6. T able 3−6. Symbolic Mode Description Assembler Code Content of ROM MOV EDE,TONI MOV X(PC),Y.
Addressing Modes 3-13 RISC 16-Bit CPU 3.3.4 Absolute Mode The absolute mode is described in T able 3−7. T able 3−7. Absolute Mode Description Assembler Code Content of ROM MOV &EDE,&TONI MOV X(0),Y(0) X = EDE Y = TONI Length: T wo or three words Operation: Move the contents of the source address EDE to the destination address TONI.
Addressing Modes 3-14 RISC 16-Bit CPU 3.3.5 Indirect Register Mode The indirect register mode is described in T able 3−8. T able 3−8. Indirect Mode Description Assembler Code Content of ROM MOV @R.
Addressing Modes 3-15 RISC 16-Bit CPU 3.3.6 Indirect Autoincrement Mode The indirect autoincrement mode is described in T able 3−9. T able 3−9. Indirect Autoincrement Mode Description Assembler Co.
Addressing Modes 3-16 RISC 16-Bit CPU 3.3.7 Immediate Mode The immediate mode is described in T able 3−10. T able 3−10. Immediate Mode Description Assembler Code Content of ROM MOV #45h,TONI MOV @PC+,X(PC) 45 X = TONI − PC Length: T wo or three words It is one word less if a constant of CG1 or CG2 can be used.
Instruction Set 3-17 RISC 16-Bit CPU 3.4 Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24 emulated instructions.
Instruction Set 3-18 RISC 16-Bit CPU 3.4.1 Double-Operand (Format I) Instructions Figure 3−9 illustrates the double-operand instruction format. Figure 3−9. Double Operand Instruction Format B/W D-Reg 15 0 Op-code Ad S-Reg 87 14 13 12 1 1 10 9 6 5 4 3 2 1 As T able 3−1 1 lists and describes the double operand instructions.
Instruction Set 3-19 RISC 16-Bit CPU 3.4.2 Single-Operand (Format II) Instructions Figure 3−10 illustrates the single-operand instruction format. Figure 3−10. Single Operand Instruction Format B/W D/S-Reg 15 0 Op-code 87 14 13 12 1 1 10 9 6 5 4 3 2 1 Ad T able 3−12 lists and describes the single operand instructions.
Instruction Set 3-20 RISC 16-Bit CPU 3.4.3 Jumps Figure 3−1 1 shows the conditional-jump instruction format. Figure 3−1 1. Jump Instruction Format C 10-Bit PC Of fset 15 0 Op-code 87 14 13 12 1 1 10 9 6 5 4 3 2 1 T able 3−13 lists and describes the jump instructions.
Instruction Set 3-21 RISC 16−Bit CPU ADC[.W] Add carry to destination ADC.B Add carry to destination Syntax ADC dst or ADC.W dst ADC.B dst Operation dst + C −> dst Emulation ADDC #0,dst ADDC.B #0,dst Description The carry bit (C) is added to the destination operand.
Instruction Set 3-22 RISC 16−Bit CPU ADD[.W] Add source to destination ADD.B Add source to destination Syntax ADD src,dst or ADD.W src,dst ADD.B src,dst Operation src + dst −> dst Description The source operand is added to the destination operand.
Instruction Set 3-23 RISC 16−Bit CPU ADDC[.W] Add source and carry to destination ADDC.B Add source and carry to destination Syntax ADDC src,dst or ADDC.W src,dst ADDC.B src,dst Operation src + dst + C −> dst Description Th e source operand and the carry bit (C) are added to the destination operand.
Instruction Set 3-24 RISC 16−Bit CPU AND[.W] Source AND destination AND.B Source AND destination Syntax AND src,dst or AND.W src,dst AND.B src,dst Operation src .AND. dst −> dst Description The source operand and the destination operand are logically ANDed.
Instruction Set 3-25 RISC 16−Bit CPU BIC[.W] Clear bits in destination BIC.B Clear bits in destination Syntax BIC src,dst or BIC.W src,dst BIC.B src,dst Operation .NOT .src .AND. dst −> dst Description The inverted source operand and the destination operand are logically ANDed.
Instruction Set 3-26 RISC 16−Bit CPU BIS[.W] Set bits in destination BIS.B Set bits in destination Syntax BIS src,dst or BIS.W src,dst BIS.B src,dst Operation src .OR. dst −> dst Description The source operand and the destination operand are logically ORed.
Instruction Set 3-27 RISC 16−Bit CPU BIT[.W] T est bits in destination BIT .B T est bits in destination Syntax BIT src,dst or BIT .W src,dst Operation src .AND. dst Description The source and destination operands are logically ANDed. The result affects only the status bits.
Instruction Set 3-28 RISC 16−Bit CPU * BR, BRANCH Branch to .......... destination Syntax BR dst Operation dst −> PC Emulation MOV dst,PC Description An unconditional branch is taken to an address anywhere in the 64K address space. All source addressing modes can be used.
Instruction Set 3-29 RISC 16−Bit CPU CALL Subroutine Syntax CALL dst Operation dst −> tmp dst is evaluated and stored SP − 2 −> SP PC −> @SP PC updated to TOS tmp −> PC dst saved to PC Description A subroutine call is made to an address anywhere in the 64K address space.
Instruction Set 3-30 RISC 16−Bit CPU * CLR[.W] Clear destination * CLR.B Clear destination Syntax CLR dst or CLR.W dst CLR.B dst Operation 0 −> dst Emulation MOV #0,dst MOV .B #0,dst Description The destination operand is cleared. Status Bits Status bits are not af fected.
Instruction Set 3-31 RISC 16−Bit CPU * CLRC Clear carry bit Syntax CLRC Operation 0 −> C Emulation BIC #1,SR Description The carry bit (C) is cleared. The clear carry instruction is a word instruction. Status Bits N: Not af fected Z: Not affected C: Cleared V : Not affected Mode Bits OSCOFF , CPUOFF , and GIE are not affected.
Instruction Set 3-32 RISC 16−Bit CPU * CLRN Clear negative bit Syntax CLRN Operation 0 → N or (.NOT .src .AND. dst −> dst) Emulation BIC #4,SR Description The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand.
Instruction Set 3-33 RISC 16−Bit CPU * CLRZ Clear zero bit Syntax CLRZ Operation 0 → Z or (.NOT .src .AND. dst −> dst) Emulation BIC #2,SR Description The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination.
Instruction Set 3-34 RISC 16−Bit CPU CMP[.W] Compare source and destination CMP .B Compare source and destination Syntax CMP src,dst or CMP .W src,dst CMP .B src,dst Operation dst + .NOT .src + 1 or (dst − src) Description The source operand is subtracted from the destination operand.
Instruction Set 3-35 RISC 16−Bit CPU * DADC[.W] Add carry decimally to destination * DADC.B Add carry decimally to destination Syntax DADC dst or DADC.W src,dst DADC.B dst Operation dst + C −> dst (decimally) Emulation DADD #0,dst DADD.B #0,dst Description The carry bit (C) is added decimally to the destination.
Instruction Set 3-36 RISC 16−Bit CPU DADD[.W] Source and carry added decimally to destination DADD.B Source and carry added decimally to destination Syntax DADD src,dst or DADD.
Instruction Set 3-37 RISC 16−Bit CPU * DEC[.W] Decrement destination * DEC.B Decrement destination Syntax DEC dst or DEC.W dst DEC.B dst Operation dst − 1 −> dst Emulation SUB #1,dst Emulation SUB.B #1,dst Description The destination operand is decremented by one.
Instruction Set 3-38 RISC 16−Bit CPU * DECD[.W] Double-decrement destination * DECD.B Double-decrement destination Syntax DECD dst or DECD.W dst DECD.B dst Operation dst − 2 −> dst Emulation SUB #2,dst Emulation SUB.B #2,dst Description Th e destination operand is decremented by two.
Instruction Set 3-39 RISC 16−Bit CPU * DINT Disable (general) interrupts Syntax DINT Operation 0 → GIE or (0FFF7h .AND. SR → SR / .NOT .src .AND. dst −> dst) Emulation BIC #8,SR Description All interrupts are disabled. Th e constant 08h is inverted and logically ANDed with the status register (SR).
Instruction Set 3-40 RISC 16−Bit CPU * EINT Enable (general) interrupts Syntax EINT Operation 1 → GIE or (0008h .OR. SR −> SR / .src .OR. dst −> dst) Emulation BIS #8,SR Description All interrupts are enabled. The constant #08h and the status register SR are logically ORed.
Instruction Set 3-41 RISC 16−Bit CPU * INC[.W ] Increment destination * INC.B Increment destination Syntax INC dst or INC.W dst INC.B dst Operation dst + 1 −> dst Emulation ADD #1,dst Description Th e destination operand is incremented by one. The original contents are lost.
Instruction Set 3-42 RISC 16−Bit CPU * INCD[.W] Double-increment destination * INCD.B Double-increment destination Syntax INCD dst or INCD.W dst INCD.B dst Operation dst + 2 −> dst Emulation ADD #2,dst Emulation ADD.B #2,dst Example The destination operand is incremented by two.
Instruction Set 3-43 RISC 16−Bit CPU * INV[.W] Invert destination * INV .B Invert destination Syntax INV dst INV .B dst Operation .NOT .dst −> dst Emulation XOR #0FFFFh,dst Emulation XOR.B #0FFh,dst Description The destination operand is inverted.
Instruction Set 3-44 RISC 16−Bit CPU JC Jump if carry set JHS Jump if higher or same Syntax JC label JHS label Operation If C = 1: PC + 2 × offset −> PC If C = 0: execute following instruction Description The status register carry bit (C) is tested.
Instruction Set 3-45 RISC 16−Bit CPU JEQ, JZ Jump if equal, jump if zero Syntax JEQ label, JZ label Operation If Z = 1: PC + 2 × offset −> PC If Z = 0: execute following instruction Description The status register zero bit (Z) is tested.
Instruction Set 3-46 RISC 16−Bit CPU JGE Jump if greater or equal Syntax JGE label Operation If (N .XOR. V) = 0 then jump to label: PC + 2 × offset −> PC If (N .XOR. V) = 1 then execute the following instruction Description The status register negative bit (N) and overflow bit (V) are tested.
Instruction Set 3-47 RISC 16−Bit CPU JL Jump if less Syntax JL label Operation If (N .XOR. V) = 1 then jump to label: PC + 2 × offset −> PC If (N .XOR. V) = 0 then execute following instruction Description The status register negative bit (N) and overflow bit (V) are tested.
Instruction Set 3-48 RISC 16−Bit CPU JMP Jump unconditionally Syntax JMP label Operation PC + 2 × offset −> PC Description The 10-bit signed offset contained in the instruction LSBs is added to the program counter . Status Bits Status bits are not af fected.
Instruction Set 3-49 RISC 16−Bit CPU JN Jump if negative Syntax JN label Operation if N = 1: PC + 2 × offset −> PC if N = 0: execute following instruction Description Th e negative bit (N) of the status register is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter .
Instruction Set 3-50 RISC 16−Bit CPU JNC Jump if carry not set JLO Jump if lower Syntax JNC label JLO label Operation if C = 0: PC + 2 × offset −> PC if C = 1: execute following instruction Description The status register carry bit (C) is tested.
Instruction Set 3-51 RISC 16−Bit CPU JNE Jump if not equal JNZ Jump if not zero Syntax JNE label JNZ label Operation If Z = 0: PC + 2 × offset −> PC If Z = 1: execute following instruction Description The status register zero bit (Z) is tested.
Instruction Set 3-52 RISC 16−Bit CPU MOV[.W] Move source to destination MOV .B Move source to destination Syntax MOV src,dst or MOV .W src,dst MOV .B src,dst Operation src −> dst Description The source operand is moved to the destination. The source operand is not affected.
Instruction Set 3-53 RISC 16−Bit CPU * NOP No operation Syntax NOP Operation None Emulation MOV #0, R3 Description No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times.
Instruction Set 3-54 RISC 16−Bit CPU * POP[.W] Pop word from stack to destination * POP .B Pop byte from stack to destination Syntax POP dst POP .B dst Operation @SP −> temp SP + 2 −> SP temp −> dst Emulation MOV @SP+,dst or MOV .W @SP+,dst Emulation MOV .
Instruction Set 3-55 RISC 16−Bit CPU PUSH[.W] Push word onto stack PUSH.B Push byte onto stack Syntax PUSH src or PUSH.W src PUSH.B src Operation SP − 2 → SP src → @SP Description The stack pointer is decremented by two, then the source operand is moved to the RAM word addressed by the stack pointer (TOS).
Instruction Set 3-56 RISC 16−Bit CPU * RET Return from subroutine Syntax RET Operation @SP → PC SP + 2 → SP Emulation MOV @SP+,PC Description The return address pushed onto the stack by a CALL instruction is moved to th e program counter . The program continues at the code address following the subroutine call.
Instruction Set 3-57 RISC 16−Bit CPU RETI Return from interrupt Syntax RETI Operation TOS → SR SP + 2 → SP TOS → PC SP + 2 → SP Description The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents.
Instruction Set 3-58 RISC 16−Bit CPU * RLA[.W] Rotate left arithmetically * RLA.B Rotate left arithmetically Syntax RLA dst or RLA.W dst RLA.B dst Operation C <− MSB <− MSB−1 .... LSB+1 <− LSB <− 0 Emulation ADD dst,dst ADD.B dst,dst Description The destination operand is shifted left one position as shown in Figure 3−14.
Instruction Set 3-59 RISC 16−Bit CPU * RLC[.W] Rotate left through carry * RLC.B Rotate left through carry Syntax RLC dst or RLC.W dst RLC.B dst Operation C <− MSB <− MSB−1 .... LSB+1 <− LSB <− C Emulation ADDC dst,dst Description The destination operand is shifted left one position as shown in Figure 3−15.
Instruction Set 3-60 RISC 16−Bit CPU RRA[.W] Rotate right arithmetically RRA.B Rotate right arithmetically Syntax RRA dst or RRA.W dst RRA.B dst Operation MSB −> MSB, MSB −> MSB−1, ... LSB+1 −> LSB, LSB −> C Description The destination operand is shifted right one positi on as shown in Figure 3−16.
Instruction Set 3-61 RISC 16−Bit CPU RRC[.W] Rotate right through carry RRC.B Rotate right through carry Syntax RRC dst or RRC.W dst RRC dst Operation C −> MSB −> MSB−1 .... LSB+1 −> LSB −> C Description The destination operand is shifted right one position as shown in Figure 3−17.
Instruction Set 3-62 RISC 16−Bit CPU * SBC[.W] Subtract source and borrow/.NOT . carry from destination * SBC.B Subtract source and borrow/.NOT . carry from destination Syntax SBC dst or SBC.W dst SBC.B dst Operation dst + 0FFFFh + C −> dst dst + 0FFh + C −> dst Emulation SUBC #0,dst SUBC.
Instruction Set 3-63 RISC 16−Bit CPU * SETC Set carry bit Syntax SETC Operation 1 −> C Emulation BIS #1,SR Description The carry bit (C) is set. Status Bits N: Not affected Z: Not affected C: Set V : Not affected Mode Bits OSCOFF , CPUOFF , and GIE are not affected.
Instruction Set 3-64 RISC 16−Bit CPU * SETN Set negative bit Syntax SETN Operation 1 −> N Emulation BIS #4,SR Description The negative bit (N) is set. Status Bits N: Set Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF , CPUOFF , and GIE are not affected.
Instruction Set 3-65 RISC 16−Bit CPU * SETZ Set zero bit Syntax SETZ Operation 1 −> Z Emulation BIS #2,SR Description The zero bit (Z) is set. Status Bits N: Not af fected Z: Set C: Not af fected V : Not affected Mode Bits OSCOFF , CPUOFF , and GIE are not affected.
Instruction Set 3-66 RISC 16−Bit CPU SUB[.W] Subtract source from destination SUB.B Subtract source from destination Syntax SUB src,dst or SUB.W src,dst SUB.
Instruction Set 3-67 RISC 16−Bit CPU SUBC[.W]SBB[.W] Subtract source and borrow/.NOT . carry from destination SUBC.B,SBB.B Subtract source and borrow/.NOT . carry from destination Syntax SUBC src,dst or SUBC.W src,dst or SBB src,dst or SBB.W src,dst SUBC.
Instruction Set 3-68 RISC 16−Bit CPU SWPB Swap bytes Syntax SWPB dst Operation Bits 15 to 8 <−> bits 7 to 0 Description The destination operand high and low bytes are exchanged as shown in Figure 3−18. Status Bits Status bits are not af fected.
Instruction Set 3-69 RISC 16−Bit CPU SXT Extend Sign Syntax SXT dst Operation Bit 7 −> Bit 8 ......... Bit 15 Description Th e sign of the low byte is extended into the high byte as shown in Figure 3−19.
Instruction Set 3-70 RISC 16−Bit CPU * TST[.W] T est destination * TST .B T est destination Syntax TST dst or TST .W dst TST .B dst Operation dst + 0FFFFh + 1 dst + 0FFh + 1 Emulation CMP #0,dst CMP .B #0,dst Description Th e destination operand is compared with zero.
Instruction Set 3-71 RISC 16−Bit CPU XOR[.W] Exclusive OR of source with destination XOR.B Exclusive OR of source with destination Syntax XOR src,dst or XOR.W src,dst XOR.B src,dst Operation src .XOR. dst −> dst Description Th e source and destination operands are exclusive ORed.
Instruction Set 3-72 RISC 16−Bit CPU 3.4.4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used - not the instruction itself. The number of clock cycles refers to the MCLK.
Instruction Set 3-73 RISC 16−Bit CPU Format-I (Double Operand) Instruction Cycles and Lengths T able 3−16 lists the length and CPU cycles for all addressing modes of format-I instructions. T able 3−16. Format 1 Instruction Cycles and Lengths Addressing Mode No.
Instruction Set 3-74 RISC 16−Bit CPU 3.4.5 Instruction Set Description The instruction map is shown in Figure 3−20 and the complete instruction set is summarized in T able 3−17.
Instruction Set 3-75 RISC 16−Bit CPU T able 3−17. MSP430 Instruction Set Mnemonic Description V N Z C ADC(.B) † dst Add C to destination dst + C → dst * * * * ADD(.B) src,dst Add source to destination src + dst → dst * * * * ADDC(.B) src,dst Add source and C to destination src + dst + C → dst * * * * AND(.
3-76.
4-1 Basic Clock Module "# " The basic clock module provides the clocks for MSP430x1xx devices. This chapter describes the operation of the basic clock module. The basic clock module is implemented in all MSP430x1xx devices.
Basic Clock Module Introduction 4-2 Basic Clock Module 4.1 Basic Clock Module Introduction The basic clock module supports low system cost and ultralow-power consumption. Using three internal clock signals, the user can select the best balance of performance and low power consumption.
Basic Clock Module Introduction 4-3 Basic Clock Module Figure 4−1. Basic Clock Block Diagram Divider /1/2/4/8 DIV Ax MCLK CPUOFF DCOCLK XIN XOUT DCOR P2.
Basic Clock Module Operation 4-4 Basic Clock Module 4.2 Basic Clock Module Operation After a PUC, MCLK and SMCLK are sourced from DCOCLK at ~800 kHz (see device-specific datasheet for parameters) and ACLK is sourced from LFXT1 in LF mode.
Basic Clock Module Operation 4-5 Basic Clock Module 4.2.2 LFXT1 Oscillator The LFXT1 oscillator supports ultralow-current consumption using a 32,768-Hz watch crystal in LF mode (XTS = 0). A watch crystal connects to XIN and XOUT without any other external components.
Basic Clock Module Operation 4-6 Basic Clock Module 4.2.3 XT2 Oscillator Some devices have a second crystal oscillator , XT2. XT2 sources XT2CLK and its characteristics are identical to LFXT1 in HF mode. The XT2OFF bit disables the XT2 oscillator if XT2CLK is not used for MCLK or SMCLK as shown in Figure 4−3.
Basic Clock Module Operation 4-7 Basic Clock Module Adjusting the DCO frequency After a PUC, the internal resistor is selected for the DC generator , RSELx = 4, and DCOx = 3, allowing the DCO to start at a mid-range frequency . MCLK and SMCLK are sourced from DCOCLK.
Basic Clock Module Operation 4-8 Basic Clock Module Using an External Resistor (R OSC ) for the DCO Th e DCO temperature coefficient can be reduced by using an external resistor R OSC tied to DV CC to source the current for the DC generator . Figure 4−6 shows the typical relationship of f DCO vs.
Basic Clock Module Operation 4-9 Basic Clock Module 4.2.5 DCO Modulator The modulator mixes two DCO frequencies, f DCO and f DCO+1 to produce an intermediate effective frequency between f DCO and f DCO+1 and spread the clock energy , reducing electromagnetic interference (EMI) .
Basic Clock Module Operation 4-10 Basic Clock Module 4.2.6 Basic Clock Module Fail-Safe Operation The basic clock module incorporates an oscillator-fault detection fail-safe feature. The oscillator fault detector is an analog circuit that monitors the LFXT1CLK (in HF mode) and the XT2CLK.
Basic Clock Module Operation 4-1 1 Basic Clock Module Oscillator Fault Detection Signal XT_OscFault triggers the OFIFG flag as shown in Figure 4−10. The LFXT1_OscFault signal is low when LFXT1 is in LF mode. On devices without XT2, the OFIFG flag cannot be cleared when LFXT1 is in LF mode.
Basic Clock Module Operation 4-12 Basic Clock Module Sourcing MCLK from a Crystal After a PUC, the basic clock module uses DCOCLK for MCLK. If required, MCLK may be sourced from LFXT1 or XT2.
Basic Clock Module Operation 4-13 Basic Clock Module 4.2.7 Synchronization of Clock Signals When switching MCLK or SMCLK from one clock source to the another , the switch is synchronized to avoid critical race conditions as shown in Figure 4−1 1: 1) The current clock cycle continues until the next rising edge.
Basic Clock Module Registers 4-14 Basic Clock Module 4.3 Basic Clock Module Registers The basic clock module registers are listed in T able 4−1: T able 4−1.
Basic Clock Module Registers 4-15 Basic Clock Module DCOCTL, DCO Control Register 76543 210 DCOx MODx rw−0 rw−1 rw−1 rw−0 rw−0 rw−0 rw−0 rw−0 DCOx Bits 7-5 DCO frequency select. These bits select which of the eight discrete DCO frequencies of the RSELx setting is selected.
Basic Clock Module Registers 4-16 Basic Clock Module BCSCTL2, Basic Clock System Control Register 2 76543 210 SELMx DIVMx SELS DIVSx DCOR rw−(0) rw−(0) rw−(0) rw−(0) rw−0 rw−0 rw−0 rw−0 SELMx Bits 7-6 Select MCLK. These bits select the MCLK source.
Basic Clock Module Registers 4-17 Basic Clock Module IE1, Interrupt Enable Register 1 76543 210 OFIE rw−0 Bits 7-2 These bits may be used by other modules. See device-specific datasheet. OFIE Bit 1 Oscillator fault interrupt enable. This bit enables the OFIFG interrupt.
4-18 Basic Clock Module.
5-1 Flash Memory Controller " "" This chapter describes the operation of the MSP430 flash memory controller . T opic Page 5.1 Flash Memory Introduction 5-2 . . . . . . . . . . . . .
Flash Memory Introduction 5-2 Flash Memory Controller 5.1 Flash Memory Introduction The MSP430 flash memory is bit-, byte-, and word-addressable and programmable. The flash memory module has an integrated controller that controls programming and erase operations.
Flash Memory Segmentation 5-3 Flash Memory Controller 5.2 Flash Memory Segmentation MSP430 flash memory is partitioned into segments. Single bits, bytes, or words can be written to flash memory , but the segment is the smallest size of flash memory that can be erased.
Flash Memory Operation 5-4 Flash Memory Controller 5.3 Flash Memory Operation The default mode of the flash memory is read mode. In read mode, the flash memory is not being erased or written, the flash timing generator and voltage generator are off, and the memory operates identically to ROM.
Flash Memory Operation 5-5 Flash Memory Controller 5.3.2 Erasing Flash Memory Th e erased level of a flash memory bit is 1. Each bit can be programmed from 1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle. The smallest amount of flash that can be erased is a segment.
Flash Memory Operation 5-6 Flash Memory Controller Initiating an Erase from Within Flash Memory An y erase cycle can be initiated from within flash memory or from RAM. When a flash segment erase operation is initiated from within flash memory , all timing is controlled by the flash controller , and the CPU is held while the erase cycle completes.
Flash Memory Operation 5-7 Flash Memory Controller Initiating an Erase from RAM Any erase cycle may be initiated from RAM. In this case, the CPU is not held and can continue to execute code from RAM. The BUSY bit must be polled to determine the end of the erase cycle before the CPU can access any flash address again.
Flash Memory Operation 5-8 Flash Memory Controller 5.3.3 Writing Flash Memory The write modes, selected by the WRT and BLKWR T bits, are listed in T able 5−1.
Flash Memory Operation 5-9 Flash Memory Controller In byte/word mode, the internally-generated programming voltage is applied to the complete 64-byte block, each time a byte or word is written, for 32 of the 35 f FTG cycles. With each byte or word write, the amount of time the block is subjected to the programming voltage accumulates.
Flash Memory Operation 5-10 Flash Memory Controller Initiating a Byte/Word Write from RAM The flow to initiate a byte/word write from RAM is shown in Figure 5−9.
Flash Memory Operation 5-1 1 Flash Memory Controller Block Write The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed. The flash programming voltage remains on for the duration of writing the 64-byte block.
Flash Memory Operation 5-12 Flash Memory Controller Block Write Flow and Example A block write flow is shown in Figure 5−8 and the following example.
Flash Memory Operation 5-13 Flash Memory Controller ; Write one block starting at 0F000h. ; Must be executed from RAM, Assumes Flash is already erased.
Flash Memory Operation 5-14 Flash Memory Controller 5.3.4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and while BUSY=1, the CPU may not read or write to or from any flash location. Otherwise, an access violation occurs, ACCVIFG is set, and the result is unpredictable.
Flash Memory Operation 5-15 Flash Memory Controller 5.3.5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX. Setting the EMEX bit stops the active operation immediately and stops the flash controller .
Flash Memory Operation 5-16 Flash Memory Controller Programming Flash Memory via JT AG MSP430 devices can be programmed via the JT AG port. The JT AG interface requires four signals (5 signals on 20- and 28-pin devices), ground and optionally V CC and RST /NMI.
Flash Memory Registers 5-17 Flash Memory Controller 5.4 Flash Memory Registers The flash memory registers are listed in T able 5−4. T able 5−4. Flash Memory Registers Register Short Form Register .
Flash Memory Registers 5-18 Flash Memory Controller FCTL1, Flash Memory Control Register 15 14 13 12 1 1 10 9 8 FRKEY , Read as 096h FWKEY , Must be written as 0A5h 76543 210 BLKWRT WRT Reserved Reserved Reserved MERAS ERASE Reserved rw−0 rw−0 r0 r0 r0 rw−0 rw−0 r0 FRKEY/ FWKEY Bits 15-8 FCTLx password.
Flash Memory Registers 5-19 Flash Memory Controller FCTL2, Flash Memory Control Register 15 14 13 12 1 1 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 76543 210 FSSELx FNx rw−0 rw−1 rw-0 rw-0 rw-0 rw−0 rw-1 rw−0 FWKEYx Bits 15-8 FCTLx password.
Flash Memory Registers 5-20 Flash Memory Controller FCTL3, Flash Memory Control Register FCTL3 15 14 13 12 1 1 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 76543 210 Reserved Reserved EMEX LOCK W AIT ACCVIFG KEYV BUSY r0 r0 rw-0 rw-1 r-1 rw−0 rw-(0) r(w)−0 FWKEYx Bits 15-8 FCTLx password.
Flash Memory Registers 5-21 Flash Memory Controller IE1, Interrupt Enable Register 1 76543 210 ACCVIE rw−0 Bits 7-6, 4-0 These bits may be used by other modules. See device-specific datasheet. ACCVIE Bit 5 Flash memory access violation interrupt enable.
5-22 Flash Memory Controller.
6-1 Supply V oltage Supervisor " $ " % This chapter describes the operation of the SVS. The SVS is implemented in MSP430x15x and MSP430x16x devices. T opic Page 6.1 SVS Introduction 6−2 .
SVS Introduction 6-2 Supply V oltage Supervisor 6.1 SVS Introduction The supply voltage supervisor (SVS) is used to monitor the A V CC supply voltage or an external voltage. The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a user-selected threshold.
SVS Introduction 6-3 Supply V oltage Supervisor Figure 6−1. SVS Block Diagram + − 1.25V Brownout Reset VCC Set SVSFG t Reset ~ 50us Reset SVSCTL Bits 0001 0010 001 1 1111 1 101 1 100 G D S SVSOUT .
SVS Operation 6-4 Supply V oltage Supervisor 6.2 SVS Operation Th e SVS detects if the A V CC voltage drops below a selectable level. It can be configured t o provide a POR or set a flag, when a low-voltage condition occurs. The SVS is disabled after a brownout reset to conserve current consumption.
SVS Operation 6-5 Supply V oltage Supervisor 6.2.3 Changing the VLDx Bits When the VLDx bits are changed, two settling delays are implemented to allows the SVS circuitry to settle. During each delay , the SVS will not set SVSFG. The delays, t d(SVSon) and t settle, are shown in Figure 6−2.
SVS Operation 6-6 Supply V oltage Supervisor 6.2.4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltage changes when A V CC is close to the threshold. The SVS operation and SVS/Brownout interoperation are shown in Figure 6−3 .
SVS Registers 6-7 Supply V oltage Supervisor 6.3 SVS Registers The SVS registers are listed in T able 6−1. T able 6−1. SVS Registers Register Short Form Register T ype Address Initial State SVS Co.
6-8 Supply V oltage Supervisor.
7-1 Hardware Multiplier &'"" This chapter describes the hardware multiplier . The hardware multiplier is implemented in MSP430x14x and MSP430x16x devices. T opic Page 7.1 Hardware Multiplier Introduction 7-2 .
Hardware Multiplier Introduction 7-2 Hardware Multiplier 7.1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU. This means, its activities do not interfere with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU instructions.
Hardware Multiplier Operation 7-3 Hardware Multiplier 7.2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply , signed multiply , unsigned multiply accumulate, and signed multiply accumulate operations. The type of operation is selected by the address the first operand is written to.
Hardware Multiplier Operation 7-4 Hardware Multiplier 7.2.2 Result Registers Th e result low register RESLO holds the lower 16-bits of the calculation result. The result high register RESHI contents depend on the multiply operation and are listed in T able 7−2.
Hardware Multiplier Operation 7-5 Hardware Multiplier 7.2.3 Software Examples Examples for all multiplier modes follow . All 8x8 modes use the absolute address for the registers because the assembler will not allow .B access to word registers when using the labels from the standard definitions file.
Hardware Multiplier Operation 7-6 Hardware Multiplier 7.2.4 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access the result registers, At least one inst.
Hardware Multiplier Registers 7-7 Hardware Multiplier 7.3 Hardware Multiplier Registers The hardware multiplier registers are listed in T able 7−4. T able 7−4.
7-8 Hardware Multiplier.
8-1 () "" The DMA controller module transfers data from one address to another without CPU intervention. This chapter describes the operation of the DMA controller. The DMA controller is implemented in MSP430x15x and MSP430x16x devices.
8-2 8.1 DMA Introduction The direct memory access (DMA) controller transfers data from one address to another , without CPU intervention, across the entire address range. For example, the DMA controller can move data from the ADC12 conversion memory to RAM.
8-3 Figure 8−1. DMA Controller Block Diagram DMA Priority And Control ENNMI DT DMA Channel 2 DMASRSBYTE DMA2SZ DMA2DA DMA2SA DMADSTBYTE DMASRCINCRx DMADSTINCRx 2 2 3 DMADTx DMAEN DT DMA Channel 1 DM.
8-4 8.2 DMA Operation The DMA controller is configured with user software. The setup and operation of the DMA is discussed in the following sections. 8.2.1 DMA Addressing Modes The DMA controller has four addressing modes. The addressing mode for each DMA channel is independently configurable.
8-5 8.2.2 DMA T ransfer Modes The DMA controller has six transfer modes selected by the DMADTx bits as listed in T able 8−1. Each channel is individually configurable for its transfer mode.
8-6 Single T ransfer In single transfer mode, each byte/word transfer requires a separate trigger . The single transfer state diagram is shown in Figure 8−3.
8-7 Figure 8−3. DMA Single T ransfer State Diagram Reset W ait for T rigger Idle Hold CPU, T ransfer one word/byte [+T rigger AND DMALEVEL = 0 ] OR [T rigger=1 AND DMALEVEL=1] DMAABORT=0 DMAABORT = .
8-8 Block T ransfers In block transfer mode, a transfer of a complete block of data occurs after one trigger . When DMADTx = 1, the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can be triggered.
8-9 Figure 8−4. DMA Block T ransfer State Diagram Reset W ait for T rigger Idle Hold CPU, T ransfer one word/byte [+T rigger AND DMALEVEL = 0 ] OR [T rigger=1 AND DMALEVEL=1] DMAABORT=0 DMAABORT = 1.
8-10 Burst-Block T ransfers In burst-block mode, transfers are block transfers with CPU activity interleaved. The CPU executes 2 MCLK cycles after every four byte/word transfers of the block resulting in 20% CPU execution capacity . After the burst-block, CPU execution resumes at 100% capacity and the DMAEN bit is cleared.
8-1 1 Figure 8−5. DMA Burst-Block T ransfer State Diagram 2 x MCLK Reset W ait for T rigger Idle Hold CPU, T ransfer one word/byte Burst State (release CPU for 2xMCLK) [+T rigger AND DMALEVEL = 0 ] .
8-12 8.2.3 Initiating DMA T ransfers Each DMA channel is independently configured for its trigger source with the DMAxTSELx bits as described in T able 8−2.The DMAxTSELx bits should be modified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictable DMA triggers may occur .
8-13 T able 8−2. DMA T rigger Operation DMAxTSELx Operation 0000 A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset when the transfer starts 0001 A transfer is triggered when the T ACCR2 CCIFG flag is set. The T ACCR2 CCIFG flag is automatically reset when the transfer starts.
8-14 8.2.4 Stopping DMA T ransfers There are two ways to stop DMA transfers in progress: - A single, block, or burst-block transfer may be stopped with an NMI interrupt, if the ENNMI bit is set in register DMACTL1. - A burst-block transfer may be stopped by clearing the DMAEN bit.
8-15 8.2.6 DMA T ransfer Cycle Time The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or complete block or burst-block transfer . Each byte/word transfer requires two MCLK cycles after synchronization, and one cycle of wait time after the transfer .
8-16 8.2.7 Using DMA with System Interrupts DMA transfers are not interruptible by system interrupts. System interrupts remain pending until the completion of the transfer . NMI interrupts can interrupt the DMA controller if the ENNMI bit is set. System interrupt service routines are interrupted by DMA transfers.
8-17 8.2.9 Using the I 2 C Module with the DMA Controller The I 2 C module provides two trigger sources for the DMA controller . The I 2 C module can trigger a transfer when new I 2 C data is received and the when the transmit data is needed. The TXDMAEN and RXDMAEN bits enable or disable the use of the DMA controller with the I 2 C module.
8-18 8.3 DMA Registers The DMA registers are listed in T able 8−4: T able 8−4. DMA Registers Register Short Form Register T ype Address Initial State DMA control 0 DMACTL0 Read/write 0122h Reset w.
8-19 DMACTL0, DMA Control Register 0 15 14 13 12 1 1 10 9 8 Reserved DMA2TSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 76543 210 DMA1TSELx DMA0TSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Reserved Bits 15−12 Reserved DMA2 TSELx Bits 1 1−8 DMA trigger select.
8-20 DMACTL1, DMA Control Register 1 15 14 13 12 1 1 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 76543 210 0 0 0 0 0 DMA ONFETCH ROUND ROBIN ENNMI r0 r0 r0 r0 r0 rw−(0) rw−(0) rw−(0) Reserved Bits 15−3 Reserved. Read only . Always read as 0.
8-21 DMAxCTL, DMA Channel x Control Register 15 14 13 12 1 1 10 9 8 Reserved DMADTx DMADSTINCRx DMASRCINCRx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 76543 210 DMA DSTBYT.
8-22 DMA SRCBYTE Bit 6 DMA source byte. This bit selects the source as a byte or word. 0 Word 1 Byte DMA LEVEL Bit 5 DMA level. This bit selects between edge-sensitive and level-sensitive triggers.
8-23 DMAxDA, DMA Destination Address Register 15 14 13 12 1 1 10 9 8 DMAxDAx rw rw rw rw rw rw rw rw 76543 210 DMAxDAx rw rw rw rw rw rw rw rw DMAxDAx Bits 15−0 DMA destination address. The destination address register points to the destination address for single transfers or the first address for block transfers.
8-24.
9-1 Digital I/O ("* This chapter describes the operation of the digital I/O ports. Ports P1-P2 are implemented in MSP430x1 1xx devices. Ports P1-P3 are implemented in MSP430x12xx devices. Ports P1-P6 are implemented in MSP430x13x, MSP430x14x, MSP430x15x, and MSP430x16x devices.
Digital I/O Introduction 9-2 Digital I/O 9.1 Digital I/O Introduction MSP430 devices have up to 6 digital I/O ports implemented, P1 - P6. Each port has eight I/O pins. Every I/O pin is individually configurable for input or output direction, and each I/O line can be individually read or written to.
Digital I/O Operation 9-3 Digital I/O 9.2 Digital I/O Operation Th e digital I/O is configured with user software. The setup and operation of the digital I/O is discussed in the following sections.
Digital I/O Operation 9-4 Digital I/O 9.2.4 Function Select Registers PxSEL Port pins are often multiplexed with other peripheral module functions. See the device-specific data sheet to determine pin functions. Each PxSEL bit is used to select the pin function − I/O port or peripheral module function.
Digital I/O Operation 9-5 Digital I/O 9.2.5 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability , configured with the PxIFG, PxIE, and PxIES registers. All P1 pins source a single interrupt vector , and all P2 pins source a different single interrupt vector .
Digital I/O Operation 9-6 Digital I/O Interrupt Edge Select Registers P1IES, P2IES Each PxIES bit selects the interrupt edge for the corresponding I/O pin.
Digital I/O Registers 9-7 Digital I/O 9.3 Digital I/O Registers Seven registers are used to configure P1 and P2. Four registers are used to configure ports P3 - P6.
9-8 Digital I/O.
10-1 Watchdog Timer + The watchdog timer is a 16-bit timer that can be used as a watchdog or as an interval timer . This chapter describes the watchdog timer . The watchdog timer is implemented in all MSP430x1xx devices.
Watchdog Timer Introduction 10-2 Watchdog Timer 10.1 W atchdog Timer Introduction The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated.
Watchdog Timer Introduction 10-3 Watchdog Timer Figure 10−1. Watchdog T imer Block Diagram WDTQn Y 1 2 3 4 Q6 Q9 Q13 Q15 16−bit Counter CLK A B 1 1 AE N PUC SMCLK ACLK Clear Password Compare 0 0 0 0 1 1 1 1 WDTCNTCL WDTTMSEL WDTNMI WDTNMIES WDTIS1 WDTSSEL WDTIS0 WDTHOLD EQU EQU Write Enable Low Byte R / W MDB LSB MSB WDTCTL (Asyn) Int.
Watchdog Timer Operation 10-4 Watchdog Timer 10.2 W atchdog Timer Operation Th e WDT module can be configured as either a watchdog or interval timer with the WDTCTL register . The WDTCTL register also contains control bits to configure the RST /NMI pin.
Watchdog Timer Operation 10-5 Watchdog Timer 10.2.4 W atchdog Timer Interrupts The WDT uses two bits in the SFRs for interrupt control. - The WDT interrupt flag, WDTIFG, located in IFG1.0 - The WDT interrupt enable, WDTIE, located in IE1.0 When using the WDT in the watchdog mode, the WDTIFG flag sources a reset vector interrupt.
Watchdog Timer Operation 10-6 Watchdog Timer 10.2.5 Operation in Low-Power Modes The MSP430 devices have several low-power modes. Different clock signals are available in different low-power modes. The requirements of the user’s application and the type of clocking used determine how the WDT should be configured.
Watchdog T imer Registers 10-7 Watchdog Timer 10.3 W atchdog Timer Registers The watchdog timer module registers are listed in T able 10−1. T able 10−1.
Watchdog T imer Registers 10-8 Watchdog Timer WDTCTL, W atchdog Timer Register 15 14 13 12 1 1 10 9 8 Read as 069h WDTPW , must be written as 05Ah 76543 210 WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTISx rw−0 rw−0 rw−0 rw−0 r0(w) rw−0 rw−0 rw−0 WDTPW Bits 15-8 W atchdog timer password.
Watchdog T imer Registers 10-9 Watchdog Timer IE1, Interrupt Enable Register 1 76543 210 NMIIE WDTIE rw−0 rw−0 Bits 7-5 These bits may be used by other modules. See device-specific datasheet. NMIIE Bit 4 NMI interrupt enable. This bit enables the NMI interrupt.
Watchdog T imer Registers 10-10 Watchdog Timer IFG1, Interrupt Flag Register 1 76543 210 NMIIFG WDTIFG rw−(0) rw−(0) Bits 7-5 These bits may be used by other modules. See device-specific datasheet. NMIIFG Bit 4 NMI interrupt flag. NMIIFG must be reset by software.
1 1-1 Timer_A ,) T imer_A is a 16-bit timer/counter with three capture/compare registers. This chapter describes T imer_A. T imer_A is implemented in all MSP430x1xx devices. T opic Page 1 1.1 T imer_A Introduction 1 1-2 . . . . . . . .
Timer_A Introduction 1 1-2 Timer_A 1 1.1 Timer_A Introduction T imer_A is a 16-bit timer/counter with three capture/compare registers. T imer_A can support multiple capture/compares, PWM outputs, and interval timing. T imer_A also has extensive interrupt capabilities.
Timer_A Introduction 1 1-3 Timer_A Figure 1 1−1. Timer_A Block Diagram Compararator 2 CCI 15 0 CCISx OUTMODx Capture Mode CMx Sync SCS COV logic Output Unit2 D Set Q EQU0 OUT OUT2 Signal Reset GND V.
Timer_A Operation 1 1-4 Timer_A 1 1.2 Timer_A Operation The T imer_A module is configured with user software. The setup and operation of T imer_A is discussed in the following sections.
Timer_A Operation 1 1-5 Timer_A 1 1.2.2 Starting the Timer The timer may be started, or restarted in the following ways: - The timer counts when MCx > 0 and the clock source is active. - When the timer mode is either up or up/down, the timer may be stopped by writing 0 to T ACCR0.
Timer_A Operation 1 1-6 Timer_A Up Mode Th e up mode is used if the timer period must be dif ferent from 0FFFFh counts. The timer repeatedly counts up to the value of compare register T ACCR0, which defines the period, as shown in Figure 1 1−2. The number of timer counts in the period is T ACCR0+1.
Timer_A Operation 1 1-7 Timer_A Continuous Mode In the continuous mode, the timer repeatedly counts up to 0FFFFh and restarts from zero as shown in Figure 1 1−4. The capture/compare register T ACCR0 works the same way as the other capture/compare registers.
Timer_A Operation 1 1-8 Timer_A Use of the Continuous Mode Th e continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the T ACCRx register in the interrupt service routine.
Timer_A Operation 1 1-9 Timer_A Up/Down Mode The up/down mode is used if the timer period must be different from 0FFFFh counts, and if symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare register T ACCR0 and back down to zero, as shown in Figure 1 1−7.
Timer_A Operation 1 1-10 Timer_A Changing the Period Register T ACCR0 When changing T ACCR0 while the timer is running, and counting in the down direction, the timer continues its descent until it reaches zero. The new period takes affect after the counter counts down to zero.
Timer_A Operation 1 1-1 1 Timer_A 1 1.2.4 Capture/Compare Blocks Three identical capture/compare blocks, T ACCRx, are present in T imer_A. Any of the blocks may be used to capture the timer data, or to generate time intervals. Capture Mode Th e capture mode is selected when CAP = 1.
Timer_A Operation 1 1-12 Timer_A Figure 1 1−1 1. Capture Cycle Second Capture T aken COV = 1 Capture T aken No Capture T aken Read T aken Capture Clear Bit COV in Register T ACCTLx Idle Idle Capture Capture Read and No Capture Capture Capture Read Capture Capture Initiated by Software Captures can be initiated by software.
Timer_A Operation 1 1-13 Timer_A 1 1.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals.
Timer_A Operation 1 1-14 Timer_A Output Example — Timer in Up Mode The OUTx signal is changed when the timer counts up to the T ACCRx value, and rolls from T ACCR0 to zero, depending on the output mode. An example is shown in Figure 1 1−12 using T ACCR0 and T ACCR1.
Timer_A Operation 1 1-15 Timer_A Output Example — Timer in Continuous Mode The OUTx signal is changed when the timer reaches the T ACCRx and T ACCR0 values, depending on the output mode. An example is shown in Figure 1 1−13 using T ACCR0 and T ACCR1.
Timer_A Operation 1 1-16 Timer_A Output Example — Timer in Up/Down Mode The OUTx signal changes when the timer equals T ACCRx in either count direction and when the timer equals T ACCR0, depending on the output mode. An example is shown in Figure 1 1−14 using T ACCR0 and T ACCR2.
Timer_A Operation 1 1-17 Timer_A 1 1.2.6 Timer_A Interrupts T wo interrupt vectors are associated with the 16-bit T imer_A module: - T ACCR0 interrupt vector for T ACCR0 CCIFG - T AIV interrupt vector for all other CCIFG flags and T AIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated T ACCRx register .
Timer_A Operation 1 1-18 Timer_A T AIV Software Example Th e following software example shows the recommended use of T AIV and the handling overhead. The T AIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction.
Timer_A Registers 1 1-19 Timer_A 1 1.3 Timer_A Registers The T imer_A registers are listed in T able 1 1−3: T able 1 1−3. Timer_A Registers Register Short Form Register T ype Address Initial State.
Timer_A Registers 1 1-20 Timer_A T ACTL, Timer_A Control Register 15 14 13 12 1 1 10 9 8 Unused T ASSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 76543 210 IDx MCx Unuse.
Timer_A Registers 1 1-21 Timer_A T AR, Timer_A Register 15 14 13 12 1 1 10 9 8 T ARx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 76543 210 T ARx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) T ARx Bits 15-0 T imer_A register .
Timer_A Registers 1 1-22 Timer_A T ACCTLx, Capture/Compare Control Register 15 14 13 12 1 1 10 9 8 CMx CCISx SCS SCCI Unused CAP rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−(0) r−(0) rw−(0) 7.
Timer_A Registers 1 1-23 Timer_A CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled CCI Bit 3 Capture/compare input. The selected input signal can be read by this bit.
1 1-24 Timer_A.
12-1 Timer_B , T imer_B i s a 16-bit timer/counter with multiple capture/compare registers. This chapter describes T imer_B. T imer_B3 (three capture/compare registers) is implemented in MSP430x13x and MSP430x15x devices. T imer_B7 (seven capture/compare registers) is implemented in MSP430x14x and MSP430x16x devices.
Timer_B Introduction 12-2 Timer_B 12.1 T imer_B Introduction T imer_B is a 16-bit timer/counter with three or seven capture/compare registers. T imer_B can support multiple capture/compares, PWM outputs, and interval timing. T imer_B also has extensive interrupt capabilities.
Timer_B Introduction 12-3 Timer_B Figure 12−1. Timer_B Block Diagram CCR6 Compararator 6 CCI 15 0 OUTMODx Capture Mode CMx Sync COV logic Output Unit6 D Set Q EQU0 OUT OUT6 Signal Reset POR EQU6 Div.
Timer_B Operation 12-4 Timer_B 12.2 T imer_B Operation The T imer_B module is configured with user software. The setup and operation of T imer_B is discussed in the following sections.
Timer_B Operation 12-5 Timer_B 12.2.2 Starting the T imer The timer may be started or restarted in the following ways: - The timer counts when MCx > 0 and the clock source is active. - When the timer mode is either up or up/down, the timer may be stopped by loading 0 to TBCL0.
Timer_B Operation 12-6 Timer_B Up Mode T h e up mode is used if the timer period must be dif ferent from TBR (max) counts. The timer repeatedly counts up to the value of compare latch TBCL0, which defines the period, as shown in Figure 12−2. The number of timer counts in the period is TBCL0+1.
Timer_B Operation 12-7 Timer_B Continuous Mode In continuous mode the timer repeatedly counts up to TBR (max) and restarts from zero as shown in Figure 12−4. The compare latch TBCL0 works the same way as the other capture/compare registers. Figure 12−4.
Timer_B Operation 12-8 Timer_B Use of the Continuous Mode Th e continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TBCLx latch in the interrupt service routine.
Timer_B Operation 12-9 Timer_B Up/Down Mode Th e up/down mode is used if the timer period must be dif ferent from TBR (max) counts, and if symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare latch TBCL0, and back down to zero, as shown in Figure 12−7.
Timer_B Operation 12-10 Timer_B Changing the V alue of Period Register TBCL0 When changing TBCL0 while the timer is running, and counting in the down direction, and when the TBCL0 load mode is immediate , the timer continues its descent until it reaches zero.
Timer_B Operation 12-1 1 Timer_B 12.2.4 Capture/Compare Blocks Three or seven identical capture/compare blocks, TBCCRx, are present in T imer_B. Any of the blocks may be used to capture the timer data or to generate time intervals. Capture Mode Th e capture mode is selected when CAP = 1.
Timer_B Operation 12-12 Timer_B Figure 12−1 1. Capture Cycle Second Capture T aken COV = 1 Capture T aken No Capture T aken Read T aken Capture Clear Bit COV in Register TBCCTLx Idle Idle Capture Capture Read and No Capture Capture Capture Read Capture Capture Initiated by Software Captures can be initiated by software.
Timer_B Operation 12-13 Timer_B Compare Latch TBCLx The TBCCRx compare latch, TBCLx, holds the data for the comparison to the timer value in compare mode. TBCLx is buffered by TBCCRx. The buf fered compare latch gives the user control over when a compare period updates.
Timer_B Operation 12-14 Timer_B 12.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals.
Timer_B Operation 12-15 Timer_B Output Example—Timer in Up Mode Th e OUTx signal is changed when the timer counts up to the TBCLx value, and rolls from TBCL0 to zero, depending on the output mode. An example is shown in Figure 12−12 using TBCL0 and TBCL1.
Timer_B Operation 12-16 Timer_B Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCL0 values, depending on the output mode, An example is shown in Figure 12−13 using TBCL0 and TBCL1. Figure 12−13.
Timer_B Operation 12-17 Timer_B Output Example − Timer in Up/Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCL0, depending on the output mode. An example is shown in Figure 12−14 using TBCL0 and TBCL3.
Timer_B Operation 12-18 Timer_B 12.2.6 Timer_B Interrupts T wo interrupt vectors are associated with the 16-bit T imer_B module: - TBCCR0 interrupt vector for TBCCR0 CCIFG - TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode, any CCIFG flag is set when a timer value is captured in the associated TBCCRx register .
Timer_B Operation 12-19 Timer_B TBIV , Interrupt Handler Examples Th e following software example shows the recommended use of TBIV and the handling overhead. The TBIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU clock cycles for each instruction.
Timer_B Registers 12-20 Timer_B 12.3 T imer_B Registers The T imer_B registers are listed in T able 12−5: T able 12−5. Timer_B Registers Register Short Form Register T ype Address Initial State T .
Timer_B Registers 12-21 Timer_B Timer_B Control Register TBCTL 15 14 13 12 1 1 10 9 8 Unused TBCLGRPx CNTLx Unused TBSSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 76543.
Timer_B Registers 12-22 Timer_B Unused Bit 3 Unused TBCLR Bit 2 Timer_B clear . Setting this bit resets TBR, the TBCLK divider , and the count direction. The TBCLR bit is automatically reset and is always read as zero. TBIE Bit 1 Timer_B interrupt enable.
Timer_B Registers 12-23 Timer_B TBCCTLx, Capture/Compare Control Register 15 14 13 12 1 1 10 9 8 CMx CCISx SCS CLLDx CAP rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−(0) rw−(0) 76543 21.
Timer_B Registers 12-24 Timer_B CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled CCI Bit 3 Capture/compare input. The selected input signal can be read by this bit.
Timer_B Registers 12-25 Timer_B TBIV , Timer_B Interrupt V ector Register 15 14 13 12 1 1 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 76543 210 0 0 0 0 TBIVx 0 r0 r0 r0 r0 r−(0) r−(0) r−(0) r.
12-26 Timer_B.
13-1 USART Peripheral Interface, UAR T Mode !) " - !) The universal synchronous/asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module.
USART Introduction: UAR T Mode 13-2 USART Peripheral Interface, UAR T Mode 13.1 USART Introduction: UART Mode In asynchronous mode, the USART connects the MSP430 to an external system via two external pins, URXD and UTXD. UAR T mode is selected when the SYNC bit is cleared.
USART Introduction: UAR T Mode 13-3 USART Peripheral Interface, UAR T Mode Figure 13−1. USART Block Diagram: UAR T Mode Receiver Shift Register T ransmit Shift Register Receiver Buffer UxRXBUF T ran.
USART Operation: UAR T Mode 13-4 USART Peripheral Interface, UAR T Mode 13.2 USART Operation: UART Mode In UART mode, the USAR T transmits and receives characters at a bit rate asynchronous to another device. T iming for each character is based on the selected baud rate of the USART .
USART Operation: UAR T Mode 13-5 USART Peripheral Interface, UAR T Mode 13.2.3 Asynchronous Communication Formats When two devices communicate asynchronously , the idle-line format is used for the protocol. When three or more devices communicate, the USART supports the idle-line and address-bit multiprocessor communication formats.
USART Operation: UAR T Mode 13-6 USART Peripheral Interface, UAR T Mode The URXWIE bit is used to control data reception in the idle-line multiprocessor format. When the URXWIE bit is set, all non-address characters are assembled but not transferred into the UxRXBUF , and interrupts are not generated.
USART Operation: UAR T Mode 13-7 USART Peripheral Interface, UAR T Mode Address - Bit Multiprocessor Format When MM = 1, the address-bit multiprocessor format is selected. Each processed character contains an extra bit used as an address indicator shown in Figure 13−4.
USART Operation: UAR T Mode 13-8 USART Peripheral Interface, UAR T Mode Automatic Error Detection Glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time t τ (approximately 300 ns) will be ignored.
USART Operation: UAR T Mode 13-9 USART Peripheral Interface, UAR T Mode 13.2.4 USART Receive Enable Th e receive enable bit, URXEx, enables or disables data reception on URXDx as shown in Figure 13−5.
USART Operation: UAR T Mode 13-10 USART Peripheral Interface, UAR T Mode 13.2.5 USART T ransmit Enable When UTXEx is set, the UAR T transmitter is enabled. T ransmission is initiated by writing data to UxTXBUF . The data is then moved to the transmit shift register on the next BITCLK after the TX shift register is empty , and transmission begins.
USART Operation: UAR T Mode 13-1 1 USART Peripheral Interface, UAR T Mode 13.2.6 UART Baud Rate Generation The USART baud rate generator is capable of producing standard baud rates from non-standard source frequencies. The baud rate generator uses one prescaler/divider and a modulator as shown in Figure 13−7.
USART Operation: UAR T Mode 13-12 USART Peripheral Interface, UAR T Mode Baud Rate Bit Timing Th e first stage of the baud rate generator is the 16-bit counter and comparator . At the beginning of each bit transmitted or received, the counter is loaded with INT(N/2) where N is the value stored in the combination of UxBR0 and UxBR1.
USART Operation: UAR T Mode 13-13 USART Peripheral Interface, UAR T Mode T ransmit Bit Timing The timing for each character is the sum of the individual bit timings.
USART Operation: UAR T Mode 13-14 USART Peripheral Interface, UAR T Mode Receive Bit Timing Receive timing consists of two error sources. The first is the bit-to-bit timing error . The second is the error between a start edge occurring and the start edge being accepted by the USART .
USART Operation: UAR T Mode 13-15 USART Peripheral Interface, UAR T Mode For example, the receive errors for the following conditions are calculated: Baud rate = 2400 BRCLK = 32,768 Hz (ACLK) UxBR = 13, since the ideal division factor is 13.
USART Operation: UAR T Mode 13-16 USART Peripheral Interface, UAR T Mode T ypical Baud Rates and Errors Standard baud rate frequency data for UxBRx and UxMCTL are listed in T able 13−2 for a 32,768-Hz watch crystal (ACLK) and a typical 1,048,576-Hz SMCLK.
USART Operation: UAR T Mode 13-17 USART Peripheral Interface, UAR T Mode 13.2.7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. USART T ransmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character .
USART Operation: UAR T Mode 13-18 USART Peripheral Interface, UAR T Mode USART Receive Interrupt Operation Th e URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF . An interrupt request is generated if URXIEx and GIE are also set.
USART Operation: UAR T Mode 13-19 USART Peripheral Interface, UAR T Mode Receive-Start Edge Detect Operation The URXSE bit enables the receive start-edge detection feature. The recommended usage of the receive-start edge feature is when BRCLK is sourced by the DCO and when the DCO is off because of low-power mode operation.
USART Operation: UAR T Mode 13-20 USART Peripheral Interface, UAR T Mode Receive-Start Edge Detect Conditions When URXSE = 1, glitch suppression prevents the USART from being accidentally started.
USART Registers: UAR T Mode 13-21 USART Peripheral Interface, UAR T Mode 13.3 USART Registers: UART Mode T able 13−3 lists the registers for all devices implementing a USART module. T able 13−4 applies only to devices with a second USART module, USART1.
USART Registers: UAR T Mode 13-22 USART Peripheral Interface, UAR T Mode UxCTL, USART Control Register 76543 210 PENA PEV SPB CHAR LISTEN SYNC MM SWRST rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 PENA Bit 7 Parity enable 0 Parity disabled.
USART Registers: UAR T Mode 13-23 USART Peripheral Interface, UAR T Mode UxTCTL, USART T ransmit Control Register 76543 210 Unused CKPL SSELx URXSE TXW AKE Unused TXEPT rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 Unused Bit 7 Unused CKPL Bit 6 Clock polarity select 0 UCLKI = UCLK 1 UCLKI = inverted UCLK SSELx Bits 5-4 Source select.
USART Registers: UAR T Mode 13-24 USART Peripheral Interface, UAR T Mode UxRCTL, USART Receive Control Register 76543 210 FE PE OE BRK URXEIE URXWIE RXWAKE RXERR rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 FE Bit 7 Framing error flag 0 No error 1 Character received with low stop bit PE Bit 6 Parity error flag.
USART Registers: UAR T Mode 13-25 USART Peripheral Interface, UAR T Mode UxBR0, USART Baud Rate Control Register 0 76543 210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 rw rw rw rw rw rw rw rw UxBR1, USART Baud R.
USART Registers: UAR T Mode 13-26 USART Peripheral Interface, UAR T Mode UxRXBUF , USART Receive Buffer Register 76543 210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 r r r r r r r r UxRXBUFx Bits 7−0 The receive-data buffer is user accessible and contains the last received character from the receive shift register .
USART Registers: UAR T Mode 13-27 USART Peripheral Interface, UAR T Mode ME1, Module Enable Register 1 76543 210 UTXE0 † URXE0 † rw−0 rw−0 UTXE0 † Bit 7 USART0 transmit enable. This bit enables the transmitter for USAR T0. 0 Module not enabled 1 Module enabled URXE0 † Bit 6 USART0 receive enable.
USART Registers: UAR T Mode 13-28 USART Peripheral Interface, UAR T Mode IE1, Interrupt Enable Register 1 76543 210 UTXIE0 † URXIE0 † rw−0 rw−0 UTXIE0 † Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled URXIE0 † Bit 6 USART0 receive interrupt enable.
USART Registers: UAR T Mode 13-29 USART Peripheral Interface, UAR T Mode IFG1, Interrupt Flag Register 1 76543 210 UTXIFG0 † URXIFG0 † rw−1 rw−0 UTXIFG0 † Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty . 0 No interrupt pending 1 Interrupt pending URXIFG0 † Bit 6 USART0 receive interrupt flag.
USART Registers: UAR T Mode 13-30 USART Peripheral Interface, UAR T Mode UTXIFG0 ‡ Bit 1 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty . 0 No interrupt pending 1 Interrupt pending URXIFG0 ‡ Bit 0 USART0 receive interrupt flag.
13-31 USART Peripheral Interface, UAR T Mode.
14-1 USART Peripheral Interface, SPI Mode !)"- The universal synchronous/asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module.
USART Introduction: SPI Mode 14-2 USART Peripheral Interface, SPI Mode 14.1 USART Introduction: SPI Mode In synchronous mode, the USART connects the MSP430 to an external system via three or four pins: SIMO, SOMI, UCLK, and STE. SPI mode is selected when the SYNC bit is set and the I2C bit is cleared.
USART Introduction: SPI Mode 14-3 USART Peripheral Interface, SPI Mode Figure 14−1. USART Block Diagram: SPI Mode Receiver Shift Register T ransmit Shift Register Receiver Buffer UxRXBUF T ransmit B.
USART Operation: SPI Mode 14-4 USART Peripheral Interface, SPI Mode 14.2 USART Operation: SPI Mode In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master . An additional pin, STE, is provided as to enable a device to receive and transmit data and is controlled by the master .
USART Operation: SPI Mode 14-5 USART Peripheral Interface, SPI Mode 14.2.2 Master Mode Figure 14−2. USART Master and External Slave Receive Buffer UxRXBUF Receive Shift Register MSB LSB T ransmit Buffer UxTXBUF T ransmit Shift Register MSB LSB SPI Receive Buffer Data Shift Register (DSR) MSB LSB SOMI SOMI SIMO SIMO MASTER SLA VE Px.
USART Operation: SPI Mode 14-6 USART Peripheral Interface, SPI Mode 14.2.3 Slave Mode Figure 14−3. USART Slave and External Master Receive Buffer UxRXBUF Receive Shift Register LSB MSB T ransmit Buffer UxTXBUF T ransmit Shift Register LSB MSB SPI Receive Buffer Data Shift Register DSR LSB MSB SOMI SOMI SIMO SIMO MASTER SLA VE Px.
USART Operation: SPI Mode 14-7 USART Peripheral Interface, SPI Mode 14.2.4 SPI Enable The SPI transmit/receive enable bit USPIEx enables or disables the USART in SPI mode. When USPIEx = 0, the USART stops operation after the current transfer completes, or immediately if no operation is active.
USART Operation: SPI Mode 14-8 USART Peripheral Interface, SPI Mode Receive Enable The SPI receive enable state diagrams are shown in Figure 14−6 and Figure 14−7. When USPIEx = 0, UCLK is disabled from shifting data into the RX shift register . Figure 14−6.
USART Operation: SPI Mode 14-9 USART Peripheral Interface, SPI Mode 14.2.5 Serial Clock Control UCLK is provided by the master on the SPI bus. When MM = 1, BITCLK is provided by the USART baud rate generator on the UCLK pin as shown in Fig ur e 14− 8.
USART Operation: SPI Mode 14-10 USART Peripheral Interface, SPI Mode Serial Clock Polarity and Phase The polarity and phase of UCLK are independently configured via the CKPL and CKPH control bits of the USART . T iming for each case is shown in Figure 14−9.
USART Operation: SPI Mode 14-1 1 USART Peripheral Interface, SPI Mode 14.2.6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. SPI T ransmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character .
USART Operation: SPI Mode 14-12 USART Peripheral Interface, SPI Mode SPI Receive Interrupt Operation Th e URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF as shown in Figure 14−1 1 and Figure 14−12. An interrupt request is generated if URXIEx and GIE are also set.
USART Registers: SPI Mode 14-13 USART Peripheral Interface, SPI Mode 14.3 USART Registers: SPI Mode The USAR T registers, shown in T able 14−1 and T able 14−2, are byte structured and should be accessed using byte instructions.
USART Registers: SPI Mode 14-14 USART Peripheral Interface, SPI Mode UxCTL, USART Control Register 76543 210 Unused Unused I2C † CHAR LISTEN SYNC MM SWRST rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 Unused Bits 7−6 Unused I2C † Bit 5 I2C mode enable.
USART Registers: SPI Mode 14-15 USART Peripheral Interface, SPI Mode UxTCTL, USART T ransmit Control Register 76543 210 CKPH CKPL SSELx Unused Unused STC TXEPT rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 CKPH Bit 7 Clock phase select. Controls the phase of UCLK.
USART Registers: SPI Mode 14-16 USART Peripheral Interface, SPI Mode UxRCTL, USART Receive Control Register 76543 210 FE Unused OE Unused Unused Unused Unused Unused rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 FE Bit 7 Framing error flag. This bit indicates a bus conflict when MM = 1 and STC = 0.
USART Registers: SPI Mode 14-17 USART Peripheral Interface, SPI Mode UxBR0, USART Baud Rate Control Register 0 76543 210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 rw rw rw rw rw rw rw rw UxBR1, USART Baud Rate .
USART Registers: SPI Mode 14-18 USART Peripheral Interface, SPI Mode UxRXBUF , USART Receive Buffer Register 76543 210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 r r r r r r r r UxRXBUFx Bits 7−0 The receive-data buffer is user accessible and contains the last received character from the receive shift register .
USART Registers: SPI Mode 14-19 USART Peripheral Interface, SPI Mode ME1, Module Enable Register 1 76543 210 USPIE0 † rw−0 Bit 7 This bit may be used by other modules. See device-specific datasheet. USPIE0 † Bit 6 USART0 SPI enable. This bit enables the SPI mode for USAR T0.
USART Registers: SPI Mode 14-20 USART Peripheral Interface, SPI Mode IE1, Interrupt Enable Register 1 76543 210 UTXIE0 † URXIE0 † rw−0 rw−0 UTXIE0 † Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled URXIE0 † Bit 6 USART0 receive interrupt enable.
USART Registers: SPI Mode 14-21 USART Peripheral Interface, SPI Mode UTXIE0 ‡ Bit 1 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled URXIE0 ‡ Bit 0 USART0 receive interrupt enable.
USART Registers: SPI Mode 14-22 USART Peripheral Interface, SPI Mode IFG1, Interrupt Flag Register 1 76543 210 UTXIFG0 † URXIFG0 † rw−1 rw−0 UTXIFG0 † Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty . 0 No interrupt pending 1 Interrupt pending URXIFG0 † Bit 6 USART0 receive interrupt flag.
14-23 USART Peripheral Interface, SPI Mode.
15-1 USART Peripheral Interface, I 2 C Mode !) " - . The universal synchronous/asynchronous receive/transmit (USART) peripheral interface supports I 2 C communication in USART0.
I 2 C Module Introduction 15-2 USART Peripheral Interface, I 2 C Mode 15.1 I 2 C Module Introduction The inter-IC control (I 2 C) module provides an interface between the MSP430 and I 2 C-compatible devices connected by way of the two-wire I 2 C serial bus.
I 2 C Module Introduction 15-3 USART Peripheral Interface, I 2 C Mode Figure 15−1. USART Block Diagram: I 2 C Mode Receive Shift Register T ransmit Shift Register SDA I2C Clock Generator I2CEN SCL M.
I 2 C Module Operation 15-4 USART Peripheral Interface, I 2 C Mode 15.2 I 2 C Module Operation The I 2 C module supports any slave or master I 2 C-compatible device. Figure 15−2 shows an example of an I 2 C bus. Each I 2 C device is recognized by a unique address and can operate as either a transmitter or a receiver .
I 2 C Module Operation 15-5 USART Peripheral Interface, I 2 C Mode 15.2.1 I 2 C Module Initialization The I 2 C module is part of the USART peripheral. Individual bit definitions when using USAR T0 in I 2 C mode are dif ferent from that in SPI or UART mode.
I 2 C Module Operation 15-6 USART Peripheral Interface, I 2 C Mode 15.2.2 I 2 C Serial Data One clock pulse is generated by the master device for each data bit transferred. The I 2 C module operates with byte data. Data is transferred most significant bit first as shown in Figure 15−3.
I 2 C Module Operation 15-7 USART Peripheral Interface, I 2 C Mode 15.2.3 I 2 C Addressing Modes The I 2 C module supports 7-bit and 10-bit addressing modes. 7-Bit Addressing In the 7-bit addressing format, shown in Figure 15−5, the first byte is the 7-bit slave address and the R/W bit.
I 2 C Module Operation 15-8 USART Peripheral Interface, I 2 C Mode 15.2.4 I 2 C Module Operating Modes The I 2 C module operates in master transmitter , master receiver , slave transmitter , or slave receiver mode.
I 2 C Module Operation 15-9 USART Peripheral Interface, I 2 C Mode Figure 15−8. Master T ransmitter Mode IDLE Generate ST ART I2CBUSY Is Set 4 x I2CPSC I2CBB Is Set I2CSTT Is Cleared 8 x I2CPSC Send.
I 2 C Module Operation 15-10 USART Peripheral Interface, I 2 C Mode Figure 15−9. Master Receiver Mode IDLE Generate ST ART 4 x I2CPSC I2CBB Is Set I2CSTT Is Cleared 8 x I2CPSC Send Slave Address Bit.
I 2 C Module Operation 15-1 1 USART Peripheral Interface, I 2 C Mode Arbitration If two or more master transmitters simultaneously start a transmission on the bus, an arbitration procedure is invoked. Figure 15−10 illustrates the arbitration procedure between two devices.
I 2 C Module Operation 15-12 USART Peripheral Interface, I 2 C Mode Automatic Data Byte Counting Automatic data byte counting is supported in master mode with the I2CNDA T register . When I2CRM = 0, the number of bytes to be received or transmitted is written to I2CNDA T .
I 2 C Module Operation 15-13 USART Peripheral Interface, I 2 C Mode Figure 15−1 1. Slave T ransmitter I2CBB Is Cleared Send Data Low Byte T o Master 2nd Start Detected? Send Data High Byte T o Maste.
I 2 C Module Operation 15-14 USART Peripheral Interface, I 2 C Mode Figure 15−12. Slave Receiver IDLE I2CBB Is Cleared 4 x I2CPSC Ye s Receive Data Low Byte From Master REST ART Detected ? Send Ackn.
I 2 C Module Operation 15-15 USART Peripheral Interface, I 2 C Mode 15.2.5 The I 2 C Data Register I2CDR The I2CDR register can be accessed as an 8-bit or 16-bit register selected by the I2CWORD bit. The I2CDR register functions as described in T able 15−2.
I 2 C Module Operation 15-16 USART Peripheral Interface, I 2 C Mode 15.2.6 I 2 C Clock Generation and Synchronization The I 2 C module is operated with the clock source selected by the I2CSSELx bits.
I 2 C Module Operation 15-17 USART Peripheral Interface, I 2 C Mode 15.2.7 Using the I 2 C Module with Low Power Modes The I 2 C module can be used with MSP430 low-power modes. When the internal clock source for the I 2 C module is present, the module operates normally regardless of the MSP430 operating mode.
I 2 C Module Operation 15-18 USART Peripheral Interface, I 2 C Mode 15.2.8 I 2 C Interrupts The I 2 C module has one interrupt vector for eight interrupt flags listed in T able 15−3. Each interrupt flag has its own interrupt enable bit. When an interrupt is enabled, and the GIE bit is set, the interrupt flag will generate an interrupt request.
I 2 C Module Operation 15-19 USART Peripheral Interface, I 2 C Mode I2CIV , Interrupt V ector Generator The I 2 C interrupt flags are prioritized and combined to source a single interrupt vector . The interrupt vector register I2CIV is used to determine which flag requested an interrupt.
I 2 C Module Registers 15-20 USART Peripheral Interface, I 2 C Mode 15.3 I 2 C Module Registers The I 2 C module registers are listed in T able 15−4.
I 2 C Module Registers 15-21 USART Peripheral Interface, I 2 C Mode U0CTL, USART0 Control Register-I 2 C Mode 76543 210 RXDMAEN TXDMAEN I2C XA LISTEN SYNC MST I2CEN rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 RXDMAEN Bit 7 Receive DMA enable.
I 2 C Module Registers 15-22 USART Peripheral Interface, I 2 C Mode I2CTCTL, I 2 C T ransmit Control Register 76543 210 I2CWORD I2CRM I2CSSELx I2CTRX I2CSTB I2CSTP I2CSTT rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Modifiable only when I2CEN = 0 I2CWORD Bit 7 I 2 C word mode.
I 2 C Module Registers 15-23 USART Peripheral Interface, I 2 C Mode I2CDCTL, I 2 C Data Control Register 76543 210 Unused Unused I2CBUSY I2C SCLLOW I2CSBD I2CTXUDF I2CRXOVR I2CBB r0 r0 r−0 r−0 r−0 r−0 r−0 r−0 Unused Bits 7−6 Unused. Always read as 0.
I 2 C Module Registers 15-24 USART Peripheral Interface, I 2 C Mode I2CDRW , I2CDRB, I 2 C Data Register 15 14 13 12 1 1 10 9 8 I2CDRW High Byte rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 76543 210 I2CDRW Low Byte I2CDRB rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 I2CDRW/ I2CDRB Bits 15−8 I 2 C Data.
I 2 C Module Registers 15-25 USART Peripheral Interface, I 2 C Mode I2CPSC, I 2 C Clock Prescaler Register 76543 210 I2CPSCx rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Modifiable only when I2CEN = 0 I2CPSCx Bits 7−0 I 2 C clock prescaler .
I 2 C Module Registers 15-26 USART Peripheral Interface, I 2 C Mode I2CSCLH, I 2 C Shift Clock High Register 76543 210 I2CSCLHx rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Modifiable only when I2CEN = 0 I2CSCLHx Bits 7−0 I 2 C shift clock high.
I 2 C Module Registers 15-27 USART Peripheral Interface, I 2 C Mode I2COA, I 2 C Own Address Register , 7-Bit Addressing Mode 15 14 13 12 1 1 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 76543 210 0 I2COAx r0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Modifiable only when I2CEN = 0 I2COAx Bits 15-0 I 2 C own address.
I 2 C Module Registers 15-28 USART Peripheral Interface, I 2 C Mode I2CSA, I 2 C Slave Address Register , 7-Bit Addressing Mode 15 14 13 12 1 1 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 76543 210 0 I2CSAx r0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 I2CSAx Bits 15-0 I 2 C slave address.
I 2 C Module Registers 15-29 USART Peripheral Interface, I 2 C Mode I2CIE, I 2 C Interrupt Enable Register 76543 210 STTIE GCIE TXRDYIE RXRDYIE ARDYIE OAIE NACKIE ALIE rw−0 rw−0 rw−0 rw−0 rw.
I 2 C Module Registers 15-30 USART Peripheral Interface, I 2 C Mode I2CIFG, I 2 C Interrupt Flag Register 76543 210 STTIFG GCIFG TXRDYIFG RXRDYIFG ARDYIFG OAIFG NACKIFG ALIFG rw−0 rw−0 rw−0 rw.
I 2 C Module Registers 15-31 USART Peripheral Interface, I 2 C Mode I2CIV , I 2 C Interrupt V ector Register 15 14 13 12 1 1 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 76543 210 0 0 0 I2CIVx 0 r0 .
15-32 USART Peripheral Interface, I 2 C Mode.
16-1 Comparator_A ,) Comparator_A is an analog voltage comparator . This chapter describes Comparator_A. Comparator_A is implemented in MSP430x1 1x1, MSP430x12x, MSP430x13x, MSP430x14x, MSP430x15x and MSP430x16x devices. T opic Page 16.
Comparator_A Introduction 16-2 Comparator_A 16.1 Comparator_A Introduction The comparator_A module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals.
Comparator_A Introduction 16-3 Comparator_A Figure 16−1. Comparator_A Block Diagram CAOUT + − CAEX 0.5x 0.25x Set_CAIFG CA1 CCI1B + − 0V G D S P2CA0 P2CA1 CAF CARSEL CAON CAREFx 10 00 01 10 11 00 01 10 11 1 0 1 0 1 0 1 0 1 0 0V 10 V CAREF CA0 0 1 0 1 V CC V CC V CC T au ~ 2.
Comparator_A Operation 16-4 Comparator_A 16.2 Comparator_A Operation The comparator_A module is configured with user software. The setup and operation of comparator_A is discussed in the following sections. 16.2.1 Comparator The comparator compares the analog voltages at the + and – input terminals.
Comparator_A Operation 16-5 Comparator_A 16.2.3 Output Filter The output of the comparator can be used with or without internal filtering. When control bit CAF is set, the output is filtered with an on-chip RC-filter . Any comparator output oscillates if the voltage difference across the input terminals is small.
Comparator_A Operation 16-6 Comparator_A 16.2.5 Comparator_A, Port Disable Register CAPD Th e comparator input and output functions are multiplexed with the associated I/O port pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic current can flow from V CC to GND.
Comparator_A Operation 16-7 Comparator_A 16.2.7 Comparator_A Used to Measure Resistive Elements The Comparator_A can be optimized to precisely measure resistive elements using single slope analog-to-digital conversion.
Comparator_A Operation 16-8 Comparator_A The thermistor measurement is based on a ratiometric conversion principle. The ratio of two capacitor discharge times is calculated as shown in Figure 16−6. Figure 16−6. Timing for T emperature Measurement Systems V C V CC 0.
Comparator_A Registers 16-9 Comparator_A 16.3 Comparator_A Registers The Comparator_A registers are listed in T able 16−1: T able 16−1. Comparator_A Registers Register Short Form Register T ype Ad.
Comparator_A Registers 16-10 Comparator_A CACTL1, Comparator_A Control Register 1 76543 210 CAEX CARSEL CAREFx CAON CAIES CAIE CAIFG rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) CAEX Bit 7 Comparator_A exchange. This bit exchanges the comparator inputs and inverts the comparator output.
Comparator_A Registers 16-1 1 Comparator_A CACTL2, Comparator_A, Control Register 76543 210 Unused P2CA1 P2CA0 CAF CAOUT rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−(0) Unused Bits 7-4 Unused. P2CA1 Bit 3 Pin to CA1. This bit selects the CA1 pin function.
16-12 Comparator_A.
17-1 ADC12 )(. The ADC12 module is a high-performance 12-bit analog-to-digital converter . This chapter describes the ADC12. The ADC12 is implemented in the MSP430x13x, MSP430x14x, MSP430x15x, and MSP430x16x devices. T opic Page 17.1 ADC12 Introduction 17-2 .
ADC12 Introduction 17-2 ADC12 17.1 ADC12 Introduction The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer .
ADC12 Introduction 17-3 ADC12 Figure 17−1. ADC12 Block Diagram Sample and Hold Ve REF+ 12−bit SAR V R− − 16 x 12 Memory Buffer − − 16 x 8 Memory Control − V R+ V REF+ Ve REF− V REF− / ADC12S C TA 1 TB1 TB0 Divider /1 .. /8 ADC12DIVx ADC12CLK ENC MSC SHP SHT0x SAMPCON SHI S/H Convert Sync Sample T imer /4 .
ADC12 Operation 17-4 ADC12 17.2 ADC12 Operation Th e ADC12 module is configured with user software. The setup and operation of the ADC12 is discussed in the following sections. 17.2.1 12-Bit ADC Core The ADC core converts an analog input to its 12-bit digital representation and stores the result in conversion memory .
ADC12 Operation 17-5 ADC12 17.2.2 ADC12 Inputs and Multiplexer Th e eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer . The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching as shown in Figure 17−2.
ADC12 Operation 17-6 ADC12 17.2.3 V oltage Reference Generator The ADC12 module contains a built-in voltage reference with two selectable voltage levels, 1.5 V and 2.5 V . Either of these reference voltages may be used internally and externally on pin V REF+ .
ADC12 Operation 17-7 ADC12 17.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of the sample input signal SHI.
ADC12 Operation 17-8 ADC12 Pulse Sample Mode The pulse sample mode is selected when SHP = 1. The SHI signal is used to trigger the sampling timer . The SHT0x and SHT1x bits in ADC12CTL0 control the interval of the sampling timer that defines the SAMPCON sample period t sample.
ADC12 Operation 17-9 ADC12 Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can be modeled as an RC low-pass filter during the sampling time t sample , as shown below in Figure 17−5.
ADC12 Operation 17-10 ADC12 17.2.6 Conversion Memory There are 16 ADC12MEMx conversion memory registers to store conversion results. Each ADC12MEMx is configured with an associated ADC12MCTLx control register . The SREFx bits define the voltage reference and the INCHx bits select the input channel.
ADC12 Operation 17-1 1 ADC12 Single-Channel Single-Conversion Mode A single channel is sampled and converted once. The ADC result is written to the ADC12MEMx defined by the CST AR T ADDx bits. Figure 17−6 shows the flow of the Single-Channel, Single-Conversion mode.
ADC12 Operation 17-12 ADC12 Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The ADC results are written to the conversion memories starting with the ADCMEMx defined by the CST ART ADDx bits. The sequence stops after the measurement of the channel with a set EOS bit.
ADC12 Operation 17-13 ADC12 Repeat-Single-Channel Mode A single channel is sampled and converted continuously . The ADC results are written to the ADC12MEMx defined by the CST ART ADDx bits. It is necessary to read the result after the completed conversion because only one ADC12MEMx memory is used and is overwritten by the next conversion.
ADC12 Operation 17-14 ADC12 Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly . The ADC results are written to the conversion memories starting with the ADC12MEMx defined b y the CST A RT ADDx bits.
ADC12 Operation 17-15 ADC12 Using the Multiple Sample and Convert (MSC) Bit T o configure the converter to perform successive conversions automatically an d as quickly as possible, a multiple sample and convert function is available.
ADC12 Operation 17-16 ADC12 17.2.8 Using the Integrated T emperature Sensor T o use the on-chip temperature sensor , the user selects the analog input channel INCHx = 1010. Any other configuration is done as if an external channel was selected, including reference selection, conversion-memory selection, etc.
ADC12 Operation 17-17 ADC12 17.2.9 ADC12 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise.
ADC12 Operation 17-18 ADC12 17.2.10 ADC12 Interrupts The ADC12 has 18 interrupt sources: - ADC12IFG0-ADC12IFG15 - ADC12OV , ADC12MEMx overflow - ADC12TOV , ADC12 conversion time overflow The ADC12IFGx bits are set when their corresponding ADC12MEMx memory register is loaded with a conversion result.
ADC12 Operation 17-19 ADC12 ADC12 Interrupt Handling Software Example The following software example shows the recommended use of ADC12IV and the handling overhead. The ADC12IV value is added to the PC to automatically jump to the appropriate routine.
ADC12 Registers 17-20 ADC12 17.3 ADC12 Registers The ADC12 registers are listed in T able 17−2: T able 17−2. ADC12 Registers Register Short Form Register T ype Address Initial State ADC12 control .
ADC12 Registers 17-21 ADC12 ADC12CTL0, ADC12 Control Register 0 15 14 13 12 1 1 10 9 8 SHT1x SHT0x rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 76543 210 MSC REF2_5V REFON A.
ADC12 Registers 17-22 ADC12 MSC Bit 7 Multiple sample and conversion. V alid only for sequence or repeated modes. 0 The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion.
ADC12 Registers 17-23 ADC12 ADC12CTL1, ADC12 Control Register 1 15 14 13 12 1 1 10 9 8 CST ART ADDx SHSx SHP ISSH rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 76543 210 ADC1.
ADC12 Registers 17-24 ADC12 ADC12 SSELx Bits 4-3 ADC12 clock source select 00 ADC12OSC 01 ACLK 10 MCLK 1 1 SMCLK CONSEQx Bits 2-1 Conversion sequence mode select 00 Single-channel, single-conversion 01 Sequence-of-channels 10 Repeat-single-channel 1 1 Repeat-sequence-of-channels ADC12 BUSY Bit 0 ADC12 busy .
ADC12 Registers 17-25 ADC12 ADC12MCTLx, ADC12 Conversion Memory Control Registers 76543 210 EOS SREFx INCHx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 EOS Bit 7 End of sequence. Indicates the last conversion in a sequence.
ADC12 Registers 17-26 ADC12 ADC12IE, ADC12 Interrupt Enable Register 15 14 13 12 1 1 10 9 8 ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE1 1 ADC12IE10 ADC12IE9 ADC12IE8 rw−(0) rw−(0) rw−(0) rw.
ADC12 Registers 17-27 ADC12 ADC12IV , ADC12 Interrupt V ector Register 15 14 13 12 1 1 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 76543 210 0 0 ADC12IVx 0 r0 r0 r−(0) r−(0) r−(0) r−(0) r.
17-28 ADC12.
18-1 ADC10 )(/ The ADC10 module is a high-performance 10-bit analog-to-digital converter . This chapter describes the ADC10. The ADC10 is implemented in the MSP430x1 1x2, MSP430x12x2 devices. T opic Page 18.1 ADC10 Introduction 18-2 . . . . . . .
ADC10 Introduction 18-2 ADC10 18.1 ADC10 Introduction The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator , and data transfer controller (DTC). The DTC allows ADC10 samples to be converted and stored anywhere in memory without CPU intervention.
ADC10 Introduction 18-3 ADC10 Figure 18−1. ADC10 Block Diagram 1001 1000 0010 0001 001 1 0100 0101 01 10 01 1 1 Sample and Hold 10−bit SAR Divider /1 .
ADC10 Operation 18-4 ADC10 18.2 ADC10 Operation Th e ADC10 module is configured with user software. The setup and operation of the ADC10 is discussed in the following sections. 18.2.1 10-Bit ADC Core The ADC core converts an analog input to its 10-bit digital representation and stores the result in the ADC10MEM register .
ADC10 Operation 18-5 ADC10 18.2.2 ADC10 Inputs and Multiplexer Th e eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer . The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching as shown in Figure 18−2.
ADC10 Operation 18-6 ADC10 18.2.3 V oltage Reference Generator The ADC10 module contains a built-in voltage reference with two selectable voltage levels. Setting REFON = 1 enables the internal reference. When REF2_5V = 1, the internal reference is 2.5 V .
ADC10 Operation 18-7 ADC10 18.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of sample input signal SHI.
ADC10 Operation 18-8 ADC10 Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can be modeled as an RC low-pass filter during the sampling time t sample , as shown below in Figure 18−4.
ADC10 Operation 18-9 ADC10 18.2.6 Conversion Modes The ADC10 has four operating modes selected by the CONSEQx bits as discussed in T able 18−1. T able 18−1. Conversion Mode Summary CONSEQx Mode Operation 00 Single channel single-conversion A single channel is converted once.
ADC10 Operation 18-10 ADC10 Single-Channel Single-Conversion Mode A single channel selected by INCHx is sampled and converted once. The ADC result is written to ADC10MEM. Figure 18−5 shows the flow of the single-channel, single-conversion mode. When ADC10SC triggers a conversion, successive conversions can be triggered by the ADC10SC bit.
ADC10 Operation 18-1 1 ADC10 Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The sequence begins with the channel selected by INCHx and decrements to channel A0. Each ADC result is written to ADC10MEM. The sequence stops after conversion of channel A0.
ADC10 Operation 18-12 ADC10 Repeat-Single-Channel Mode A single channel selected by INCHx is sampled and converted continuously . Each ADC result is written to ADC10MEM.
ADC10 Operation 18-13 ADC10 Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly . The sequence begins with the channel selected by INCHx and decrements to channel A0. Each ADC result is written to ADC10MEM. The sequence ends after conversion of channel A0, and the next trigger signal re-starts the sequence.
ADC10 Operation 18-14 ADC10 Using the MSC Bit T o configure the converter to perform successive conversions automatically an d as quickly as possible, a multiple sample and convert function is available. When MSC = 1 and CONSEQx > 0 the first rising edge of the SHI signal triggers the first conversion.
ADC10 Operation 18-15 ADC10 18.2.7 ADC10 Data T ransfer Controller The ADC10 includes a data transfer controller (DTC) to automatically transfer conversion results from ADC10MEM to other on-chip memory locations. The DTC is enabled by setting the ADC10DTC1 register to a nonzero value.
ADC10 Operation 18-16 ADC10 One-Block T ransfer Mode The one-block mode is selected if the ADC10TB is reset. The value n in ADC10DTC1 defines the total number of transfers for a block. The block start address is defined anywhere in the MSP430 address range using the 16-bit register ADC10SA.
ADC10 Operation 18-17 ADC10 Figure 18−10. State Diagram for Data T ransfer Control in One-Block T ransfer Mode DTC idle DTC reset n=0 (ADC10DTC1) Initialize Start Address in ADC10SA W ait until ADC1.
ADC10 Operation 18-18 ADC10 T wo-Block T ransfer Mode The two-block mode is selected if the ADC10TB bit is set. The value n in ADC10DTC1 defines the number of transfers for one block. The address range of the first block is defined anywhere in the MSP430 address range with the 16-bit register ADC10SA.
ADC10 Operation 18-19 ADC10 Figure 18−12. State Diagram for Data T ransfer Control in T wo-Block T ransfer Mode DTC idle DTC reset ADC10B1 = 0 ADC10TB = 1 n=0 (ADC10DTC1) Initialize Start Address in.
ADC10 Operation 18-20 ADC10 Continuous T ransfer A continuous transfer is selected if ADC10CT bit is set. The DTC will not stop after block one in (one-block mode) or block two (two-block mode) has been transferred. The internal address pointer and transfer counter are set equal to ADC10SA and n respectively .
ADC10 Operation 18-21 ADC10 18.2.8 Using the Integrated T emperature Sensor T o use the on-chip temperature sensor , the user selects the analog input channel INCHx = 1010. Any other configuration is done as if an external channel was selected, including reference selection, conversion-memory selection, etc.
ADC10 Operation 18-22 ADC10 18.2.9 ADC10 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise.
ADC10 Operation 18-23 ADC10 18.2.10 ADC10 Interrupts One interrupt and one interrupt vector are associated with the ADC10 as shown in Figure 18−17. When the DTC is not used (ADC10DTC1 = 0) ADC10IFG is set when conversion results are loaded into ADC10MEM.
ADC10 Registers 18-24 ADC10 18.3 ADC10 Registers The ADC10 registers are listed in T able 18−3. T able 18−3. ADC10 Registers Register Short Form Register T ype Address Initial State ADC10 Input en.
ADC10 Registers 18-25 ADC10 ADC10CTL0, ADC10 Control Register 0 15 14 13 12 1 1 10 9 8 SREFx ADC10SHTx ADC10SR REFOUT REFBURST rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 7.
ADC10 Registers 18-26 ADC10 MSC Bit 7 Multiple sample and conversion. V alid only for sequence or repeated modes. 0 The sampling requires a rising edge of the SHI signal to trigger each sample-and-conversion.
ADC10 Registers 18-27 ADC10 ADC10CTL1, ADC10 Control Register 1 15 14 13 12 1 1 10 9 8 INCHx SHSx ADC10DF ISSH rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) 76543 210 ADC10DI.
ADC10 Registers 18-28 ADC10 ADC10DIVx Bits 7-5 ADC10 clock divider 000 /1 001 /2 010 /3 01 1 /4 100 /5 101 /6 11 0 / 7 111 / 8 ADC10 SSELx Bits 4-3 ADC10 clock source select 00 ADC10OSC 01 ACLK 10 MCL.
ADC10 Registers 18-29 ADC10 ADC10MEM, Conversion-Memory Register , Binary Format 15 14 13 12 1 1 10 9 8 0 0 0 0 0 0 Conversion Results r0 r0 r0 r0 r0 r0 r r 76543 210 Conversion Results r r r r r r r r Conversion Results Bits 15-0 The 10-bit conversion results are right justified, straight-binary format.
ADC10 Registers 18-30 ADC10 ADC10DTC0, Data T ransfer Control Register 0 76543 210 Reserved ADC10TB ADC10CT ADC10B1 ADC10 FETCH r0 r0 r0 r0 rw−(0) rw−(0) rw−(0) rw−(0) Reserved Bits 7-4 Reserved. Always read as 0. ADC10TB Bit 3 ADC10 two-block mode.
ADC10 Registers 18-31 ADC10 ADC10DTC1, Data T ransfer Control Register 1 76543 210 DTC T ransfers rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) DTC T ransfers Bits 7-0 DTC transfers. These bits define the number of transfers in each block.
18-32 ADC10.
19-1 DAC12 (). Th e DAC12 module is a 12-bit, voltage output digital-to-analog converter . This chapter describes the DAC12. T wo DAC12 modules are implemented in the MSP430x15x and MSP430x16x devices. T opic Page 19.1 DAC12 Introduction 19-2 . .
DAC12 Introduction 19-2 DAC12 19.1 DAC12 Introduction The DAC12 module is a 12-bit, voltage output DAC. The DAC12 can be configured in 8 - o r 12-bit mode and may be used in conjunction with the DMA controller . When multiple DAC12 modules are present, they may be grouped together for synchronous update operation.
DAC12 Introduction 19-3 DAC12 Figure 19−1. DAC12 Block Diagram DAC12_0 DAC12_0OUT 2.5V or 1.5V reference from ADC12 DAC12SREFx V R− V R+ DAC12_0DA T DAC12_0Latch DAC12_1 DAC12LSELx V R− V R+ DAC.
DAC12 Operation 19-4 DAC12 19.2 DAC12 Operation Th e DAC12 module is configured with user software. The setup and operation of the DAC12 is discussed in the following sections. 19.2.1 DAC12 Core The DAC12 can be configured to operate in 8- or 12-bit mode using the DAC12RES bit.
DAC12 Operation 19-5 DAC12 19.2.2 DAC12 Reference The reference for the DAC12 is configured to use either an external reference voltage or the internal 1.
DAC12 Operation 19-6 DAC12 19.2.4 DAC12_xDA T Data Format The DAC12 supports both straight binary and 2’s compliment data formats. When using straight binary data format, the full-scale output value is 0FFFh in 12-bit mode (0FFh in 8-bit mode) as shown in Figure 19−2.
DAC12 Operation 19-7 DAC12 19.2.5 DAC12 Output Amplifier Offset Calibration The offset voltage of the DAC12 output amplifier can be positive or negative. When the of fset is negative, the output amplifier attempts to drive the voltage negative, but cannot do so.
DAC12 Operation 19-8 DAC12 19.2.6 Grouping Multiple DAC12 Modules Multiple DAC12s can be grouped together with the DAC12GRP bit to synchronize the update of each DAC12 output. Hardware ensures that all DAC12 modules in a group update simultaneously independent of any interrupt or NMI event.
DAC12 Operation 19-9 DAC12 19.2.7 DAC12 Interrupts The DAC12 interrupt vector is shared with the DMA controller . Software must check the DAC12IFG and DMAIFG flags to determine the source of the interrupt. The DAC12IFG bit is set when DAC12LSELx > 0 and DAC12 data is latched from the DAC12_xDA T register into the data latch.
DAC12 Registers 19-10 DAC12 19.3 DAC12 Registers The DAC12 registers are listed in T able 19−2: T able 19−2. DAC12 Registers Register Short Form Register T ype Address Initial State DAC12_0 contro.
DAC12 Registers 19-1 1 DAC12 DAC12_xCTL, DAC12 Control Register 15 14 13 12 1 1 10 9 8 Reserved DAC12SREFx DAC12RES DAC12LSELx DAC12 CALON DAC12IR rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0).
DAC12 Registers 19-12 DAC12 DAC12 AMPx Bits 7-5 DAC12 amplifier setting. These bits select settling time vs. current consumption for the DAC12 input and output amplifiers.
DAC12 Registers 19-13 DAC12 DAC12_xDA T , DAC12 Data Register 15 14 13 12 1 1 10 9 8 0 0 0 0 DAC12 Data r(0) r(0) r(0) r(0) rw−(0) rw−(0) rw−(0) rw−(0) 76543 210 DAC12 Data rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Unused Bits 15-12 Unused.
19-14 DAC12.
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