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SMSC LAN9312 DA T ASHEET Revision 1.4 (08-19-08) Datasheet PRODUCT FEA TURES LAN9312 High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Highlight s High pe.
ORDER NUMBERS: LAN9312-NU FOR 128-PIN, VTQFP LEAD-FRE E ROHS COMPLIANT P ACKAGE (0 TO 70 ° C TEMP RANGE) LAN9312-NZW FOR 128-PIN, XVTQFP LEAD-FREE ROHS CO MPLIANT P ACKAGE (0 TO 70 ° C TEMP RANGE) High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 3 Revision 1.4 (08-19-08) DA T ASHEET T able of Content s Chapter 1 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 4 SMSC LAN9312 DA T ASHEET 5.2.7 General Purpose Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 5 Revision 1.4 (08-19-08) DA T ASHEET 7.2.1.6 100M Phase Lock Loop (PLL) ...................... ................ ................ .. ..
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 6 SMSC LAN9312 DA T ASHEET 9.2 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 7 Revision 1.4 (08-19-08) DA T ASHEET 10.2.4.3.1 Host MA C Address Rel oad ........... ................ ................ ..............
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 8 SMSC LAN9312 DA T ASHEET 14.2.4.1 EEPROM Command Register (E2P_CMD) .......................... .................... . .....
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 9 Revision 1.4 (08-19-08) DA T ASHEET 14.4.2 Port 1 & 2 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 10 SMSC LAN9312 DA T ASHEET 14.5.3.15 Switch Engine DIFF SERV Table Command Status Register (S WE_DIFFSERV _TBL_CMD_STS ) ...
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 1 1 Revision 1.4 (08-19-08) DA T ASHEET 15.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 12 SMSC LAN9312 DA T ASHEET List of Figures Figure 2.1 Internal LAN9312 Block Diagram . . . . . . . . . . . . . . . . . . . .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 13 Revision 1.4 (08-19-08) DA T ASHEET Figure 14.1 LAN93 12 Base Register Memory Ma p. . . . . . . . . . . . . . . . . . . . . . . . . .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 14 SMSC LAN9312 DA T ASHEET List of T ables Table 1.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 15 Revision 1.4 (08-19-08) DA T ASHEET Table 14.3 Switch Fabric CS R to SWITCH_CSR_DIRECT_D ATA Address Range Map . . . . . . . . . . .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 16 SMSC LAN9312 DA T ASHEET Chapter 1 Preface 1.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 17 Revision 1.4 (08-19-08) DA T ASHEET MII Media Independent Interface MIIM Media Independent Interface Mana gement MIL MAC Interface Layer MLD Multicast Listening Discovery ML T -3 Multi-Level T ransmissi on Encoding (3-Levels).
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 18 SMSC LAN9312 DA T ASHEET 1.2 Buffer T ypes T able 1.1 describes the pin buffer type notation used in Chapter 3, "Pin Description and Configu ration," on page 2 6 and throughout this document.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 19 Revision 1.4 (08-19-08) DA T ASHEET 1.3 Register Nomenclature T able 1.2 describes the register bit attribute notation used throughout this document.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 20 SMSC LAN9312 DA T ASHEET Chapter 2 Introduction 2.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interfac e Datasheet Revision 1.4 (08-19-08) 21 SMSC LAN9312 DA T ASHEET 2.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 22 SMSC LAN9312 DA T ASHEET 2.2.1 System Clocks/R eset/PME Controller A clock module con t ained within the LAN9312 generate s all the system clocks required by the device.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 23 Revision 1.4 (08-19-08) DA T ASHEET Software (general purpose) A dedicated programmabl e IRQ interrupt output pin is provided for external indication of any LAN9312 interrupts.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 24 SMSC LAN9312 DA T ASHEET System CSRs Access Interrupt Support 2.2.6 Host MAC The Host MAC incorporates the essential protocol requirements for operati ng an Ethern et/IEEE 802.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 25 Revision 1.4 (08-19-08) DA T ASHEET 2.2.9 GPIO/LED Controller The LAN9312 provides 12 config urable general-purpos e input/outpu t pins which are controlled via this module.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 26 SMSC LAN9312 DA T ASHEET Chapter 3 Pin Description and Configuration 3.1 Pin Diagrams 3.1.1 128-VTQFP Pin Diagram Figure 3.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 27 Revision 1.4 (08-19-08) DA T ASHEET 3.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 28 SMSC LAN9312 DA T ASHEET 3.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 29 Revision 1.4 (08-19-08) DA T ASHEET Note 3.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 30 SMSC LAN9312 DA T ASHEET 122,125 +3.3V Port 2 Analog Power Supply VDD33A2 P +3.3V Port 2 Analog Power Supply Refer to the LAN 9312 application no te for additional connection info rmation.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 31 Revision 1.4 (08-19-08) DA T ASHEET Note: Refer to Chapter 8, "Host Bus Interface (HBI)," on p age 99 for additional info rmation regarding the use of these signals.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 32 SMSC LAN9312 DA T ASHEET Note 3.3 The IS buffer type is valid only during the time specified in Section 15.5 .2, "Reset and Configuration S t rap T iming," on page 444 .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 33 Revision 1.4 (08-19-08) DA T ASHEET Note: For more information on conf iguration straps, refer to Section 4.2.4, "Configuration S traps," on page 40 .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 34 SMSC LAN9312 DA T ASHEET Note 3.7 The input buffers are enabled when configured as GPIO inputs only . 75 T est 1 TEST1 AI T est 1: This pin must be tied to VDD 33IO for proper operation.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 35 Revision 1.4 (08-19-08) DA T ASHEET Note 3.8 Plus external pad for 128-XVTQFP package only 18,48,80, 97,1 12,1 13, 128 Note 3.8 Common Ground VSS P Common Grou nd T able 3.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 36 SMSC LAN9312 DA T ASHEET Chapter 4 Clocking, Reset s, and Power Management 4.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 37 Revision 1.4 (08-19-08) DA T ASHEET Note 4.1 In the case of a soft reset, the EEPROM L oader is run, but loads only the MAC address into the Host MAC.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 38 SMSC LAN9312 DA T ASHEET A POR reset typically t akes approximately 23mS, plus additional time (91uS for I 2 C, 28uS for Microwire) per byte of da ta loaded from the EEPROM via the EEPROM Load er .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 39 Revision 1.4 (08-19-08) DA T ASHEET 4.2.2.2 Sof t Reset (SRST) A soft reset is performed by setting the SRST bit of the Hardw are Configuration Register (HW_CFG) .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 40 SMSC LAN9312 DA T ASHEET Note: When using the Reset bit to re set the Port 1 PHY , register bits designate d as NASR are not reset.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 41 Revision 1.4 (08-19-08) DA T ASHEET T abl e 4.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 42 SMSC LAN9312 DA T ASHEET speed_strap_1 Port 1 Speed Select Strap: Configures the defa ult value for the S peed Select LSB (PHY_SPEED_SEL_LSB) bit in the PHY_BASIC_CTRL_1 register (See Section 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 43 Revision 1.4 (08-19-08) DA T ASHEET manual_FC_strap_1 Port 1 Manual Flow Control .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 44 SMSC LAN9312 DA T ASHEET speed_strap_2 Port 2 Speed Select Strap: Configures the defa ult value for the S peed Select LSB (PHY_SPEED_SEL_LSB) bit in the PHY_BASIC_CTRL_2 register (See Section 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 45 Revision 1.4 (08-19-08) DA T ASHEET 4.2.4.2 Hard-Str aps Hard-straps are latched upon Power-On Reset (POR) or pin rese t (nRST) only .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 46 SMSC LAN9312 DA T ASHEET 4.3 Power Management The LAN9312 Port 1 and Po rt 2 PHYs and the Host MAC supp ort several power management a nd wakeup features.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 47 Revision 1.4 (08-19-08) DA T ASHEET 4.3.1 Port 1 & 2 PHY Power Management The Port 1 & 2 PHYs provide independent gene ral power-down and e nergy-detect power-down modes which reduce PHY power consumption.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 48 SMSC LAN9312 DA T ASHEET The Port 1 & 2 PHY energy-detect events ar.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 49 Revision 1.4 (08-19-08) DA T ASHEET Chapter 5 System Interrupt s 5.1 Functional Overview This chapter describes the system interrupt struct ure o f the LAN9312.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 50 SMSC LAN9312 DA T ASHEET Figure 5.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 51 Revision 1.4 (08-19-08) DA T ASHEET The following sections detail each category of interrupts and their related registers.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 52 SMSC LAN9312 DA T ASHEET 5.2.3 Ethernet PHY Interrupts The Port 1 and Port 2 PHYs each provi de a set of identical i nterrupt sources.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 53 Revision 1.4 (08-19-08) DA T ASHEET TX S tatus FIFO Overflow Receive W at.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 54 SMSC LAN9312 DA T ASHEET 5.2.8 Sof tware Interrupt A general purpose software interrupt is provid ed in the top level In terrupt S tatus Register (INT_STS) and Inte rrupt Enable Register (INT_EN) .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 55 Revision 1.4 (08-19-08) DA T ASHEET Chapter 6 Switch Fabric 6.1 Functional Overview At the core of the LAN9312 is the high pe rformance, high efficiency 3 port Etherne t switch fabric.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 56 SMSC LAN9312 DA T ASHEET 6.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 57 Revision 1.4 (08-19-08) DA T ASHEET 6.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 58 SMSC LAN9312 DA T ASHEET 6.2.3 Flow Control Enable Logic Each switch fabric port (0,1,2) is provided wit h two flow control enable inputs per po rt, one for transmission and one for re ception.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 59 Revision 1.4 (08-19-08) DA T ASHEET register . When Auto-neg otiation is enabled and the MANUAL_FC _x bit is cleared, the switch port flow control enables during fu ll-duplex are determined b y Auto-negotiation.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 60 SMSC LAN9312 DA T ASHEET Per Ta b l e 6 . 1 , the following cases are possible: Case 1 - Auto-negoti ation is still in progress.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 61 Revision 1.4 (08-19-08) DA T ASHEET "Flow Control Enable Logic," on page 58 . Pause frames are consumed by the MAC and not sent to the switch engine.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 62 SMSC LAN9312 DA T ASHEET 6.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 63 Revision 1.4 (08-19-08) DA T ASHEET T ot al multicast packets ( Section 14.5.2.37, on page 358 ) T ot al packets with a late coll ision ( Section 1 4.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 64 SMSC LAN9312 DA T ASHEET 6.4.1.1 Learning/Aging/Migration The ALR adds new MAC addresses u pon ingress along with th e associated receive port.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 65 Revision 1.4 (08-19-08) DA T ASHEET The following procedure sh ould be followed in orde r to add, delete, an d modify the ALR entries: 1.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 66 SMSC LAN9312 DA T ASHEET 6.4.2 Forwarding Rules Upon ingress, packets are filtered or forwarded based on the follow ing rules: If the destination port equal s the source por t (local traffic), the packet is filtered.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 67 Revision 1.4 (08-19-08) DA T ASHEET 6.4.3 T ransmit Priori ty Queue Selection The transmit priority queu e may be selected from five option s.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 68 SMSC LAN9312 DA T ASHEET The transmit queue priority is based on the pa cket type and device configuration as shown in Figure 6.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 69 Revision 1.4 (08-19-08) DA T ASHEET 6.4.3.1 Port Default Priority As detailed in Figure 6.5 , the default priority is based on the in gr ess ports priority bits in its port VID value.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 70 SMSC LAN9312 DA T ASHEET 6.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 71 Revision 1.4 (08-19-08) DA T ASHEET 6.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 72 SMSC LAN9312 DA T ASHEET After each p acket is received, th e bucket is decremented. If the Co mmitted Burst bucket has sufficient tokens, it is debit ed and the packet is colored Green.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 73 Revision 1.4 (08-19-08) DA T ASHEET The ingress flow calculation is based on the packe t type and the device config uration as shown in Figure 6.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 74 SMSC LAN9312 DA T ASHEET 6.4.7 Broadcast Storm Control In addition to ingress rate limi ting, the LAN9 312 supports hardware broadcast storm control on a per port basis.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 75 Revision 1.4 (08-19-08) DA T ASHEET (SWE_GLOBAL_INGRSS_CFG) .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 76 SMSC LAN9312 DA T ASHEET Note: When specifying Po rt 0 as the destination port, t he VID will be set to 0. A VID o f 0 is normally considered a priority tagged packet.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 77 Revision 1.4 (08-19-08) DA T ASHEET 6.5 Buffer Manager (BM) The buf fer manager (BM) provides control of the fr ee buf fer space, the multipl e priority transmit queues, transmission scheduling, and packet dropping.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 78 SMSC LAN9312 DA T ASHEET 6.5.4 T ransmit Priori ty Queue Servicing When a transmit queue is non-empty , it is serviced and the packet is read from the buffer RAM and sent to the transmit MAC.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 79 Revision 1.4 (08-19-08) DA T ASHEET 6.5.6 Adding, Removing, and Changing VLAN T ags Based on the port configuration and the received pa cket formation, a VLAN tag can be added to , removed from, or modified in a packet.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 80 SMSC LAN9312 DA T ASHEET Hybrid tagging is summarized in Figure 6.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 81 Revision 1.4 (08-19-08) DA T ASHEET 6.5.7 Counters A counter is maintained per port that contains the number of packets dropped due to buffer space limit s and ingress rate limit disca rding (Red and random Y ellow dropping).
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 82 SMSC LAN9312 DA T ASHEET Chapter 7 Ethernet PHYs 7.1 Functional Overview The LAN9312 contains three PHYs: Port 1 PHY , Port 2 PHY and a Virtual PHY .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 83 Revision 1.4 (08-19-08) DA T ASHEET 7.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 84 SMSC LAN9312 DA T ASHEET 7.2.1 100BASE-TX T ransmit The 100BASE-TX transmit data p ath is shown in Figure 7.2 . Shaded blocks are those which are internal to the PHY .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 85 Revision 1.4 (08-19-08) DA T ASHEET T able 7.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 86 SMSC LAN9312 DA T ASHEET 7.2.1.3 Scrambler and PISO Repeated data patterns (especially the IDLE code-group) can have power spectral den sities with large narrow-band peaks.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 87 Revision 1.4 (08-19-08) DA T ASHEET 7.2.2 100BASE-TX Receive The 100BASE-TX rece ive data path is shown in Figure 7.3 . Shaded blocks are th ose whi ch are intern al to the PHY .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 88 SMSC LAN9312 DA T ASHEET 7.2.2.3 NRZI and ML T -3 Decoding The DSP generates t he ML T -3 recovered levels that are fed to th e ML T -3 converter .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 89 Revision 1.4 (08-19-08) DA T ASHEET 7.2.3 10BASE-T T ransmit Data to be transmitted comes fr om the switch fabric MAC. The 10BASE-T tr ansmitter receives 4-bit nibbles from the internal MII at a rate of 2.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 90 SMSC LAN9312 DA T ASHEET (PHY_SPECIAL_CONTROL_ST A T_IND_x) . The 10M PLL locks onto the received Manchester signal and generates the rece ived 20MHz clock from it.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 91 Revision 1.4 (08-19-08) DA T ASHEET 10M PLL (analog) 10M TX Driver (analo.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 92 SMSC LAN9312 DA T ASHEET 7.2.5.1 PHY Pause Flow Control The Port 1 & 2 PHYs are capable of generating and receiving pause flow control frame s per the IEEE 802.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 93 Revision 1.4 (08-19-08) DA T ASHEET 7.2.5.5 Half Vs. Full-Duplex Half-duplex o peration relies on the CSMA/CD (Carrier Sense Mul tiple Access / Collision Det ect) protocol to handle network t raf fic and collisions .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 94 SMSC LAN9312 DA T ASHEET For a transmissi on, the switch fabric MAC drives the transmit d ata onto the internal MII T XD bus and asserts TXEN to indicate va lid data.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 95 Revision 1.4 (08-19-08) DA T ASHEET Note: The power-down modes of each PHY ( Port 1 PHY and Port 2 PHY) are controlled independently .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 96 SMSC LAN9312 DA T ASHEET 7.2.10.2 PHY Software Re set via PHY_BASIC_CTRL_x The PHY can also be reset by s etting bit 15 (P HY_RST) of th e Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 97 Revision 1.4 (08-19-08) DA T ASHEET 1. Bit 5 (Auto-Negotiation Complete) is set in the Virtual PHY Basic S tatus Register (VPHY_BASIC_ST A TUS) .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 98 SMSC LAN9312 DA T ASHEET 7.3.1.3 Virtual PHY Paus e Flow Control The Virtual PHY supports pause flow control per the IEEE 802.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 99 Revision 1.4 (08-19-08) DA T ASHEET Chapter 8 Host Bus Interface (HBI) 8.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 100 SMSC LAN9312 DA T ASHEET Data path operations for the supported endian configuration s are illustrated in Figure 8.1, "Little Endi an Byte Ordering" and Fi gure 8.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 101 Revision 1.4 (08-19-08) DA T ASHEET 8.4 Host Interface Ti ming This section details the characteri stics and special restrictions of the various supported host cycles.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 102 SMSC LAN9312 DA T ASHEET T able 8.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 103 Revision 1.4 (08-19-08) DA T ASHEET 1588_CLOCK_LO_TX_CAPTURE_1 00 1588_SEQ_ID_SR.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 104 SMSC LAN9312 DA T ASHEET 1588_CONFIG 45 1 1588_INT_STS_EN 45 1 MANUAL_.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 105 Revision 1.4 (08-19-08) DA T ASHEET 8.4.3 Special Restrictions on Back-to-Back Read Cycles There are also re strictions on specific back-to-ba ck host read opera tions.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 106 SMSC LAN9312 DA T ASHEET 8.4.4 PIO Reads PIO reads can be used to access Syst em CSR’s or RX Data and RX/TX St atus FIFOs.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 107 Revision 1.4 (08-19-08) DA T ASHEET 8.4.5 PIO Burst Reads In this mode, performance is improved by allowi ng up to 8 DWORD read cycles back-to-back.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 108 SMSC LAN9312 DA T ASHEET 8.4.6 RX Data FIFO Direct PIO Reads In this mode only A[2] is decoded, and any read of the LAN9312 will read the RX Data FIFO.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 109 Revision 1.4 (08-19-08) DA T ASHEET 8.4.7 RX Data FIFO Direct PIO Burst Reads In this mode only A[2] is decoded, and any burst read of the LAN9312 will rea d the RX Data FIFO.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 1 10 SMSC LAN9312 DA T ASHEET 8.4.8 PIO Writes PIO writes are used for all LAN9312 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR).
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 1 1 1 Revision 1.4 (0 8-19-08) DA T ASHEET 8.4.9 TX Dat a FIFO Direct PIO Writes In this mode only A[2] is decoded, and any write to the LAN9312 will write the TX Data FIFO.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 1 12 SMSC LAN9312 DA T ASHEET Chapter 9 Host MAC 9.1 Functional Overview The Host MAC incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 1 13 Revision 1.4 (08-19- 08) DA T ASHEET 9.2 Flow Control The Host MAC supports full-duplex flow control using t he pause operation and control frame.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 1 14 SMSC LAN9312 DA T ASHEET both are set to the same value, VLAN1 is given hi gher preceden ce and the maximum lega l frame length is set to 1522.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 1 15 Revision 1.4 (08-19- 08) DA T ASHEET 9.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 1 16 SMSC LAN9312 DA T ASHEET 9.4.4 Inverse Filtering In inverse filtering, the Host MAC packet filter a ccepts incoming frames (f rom switch Port 0) with a destination address n ot matching the perf ect address (i.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 1 17 Revision 1.4 (08-19- 08) DA T ASHEET The Filter i Byte Mask defines which in coming frame bytes F ilter i will examine t o determine whether or not this is a wake-up frame.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 1 18 SMSC LAN9312 DA T ASHEET The Filter i Offset register defin es the offset in the frame’s destination address field fro m which the frames are examined by Filt er i.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 1 19 Revision 1.4 (08-19- 08) DA T ASHEET Destination Address Source Ad dress …….
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 120 SMSC LAN9312 DA T ASHEET Note: By convention, the right nibb le of the left most byte of the Ethernet address (in this example, the 2 of the 12h) is t he most significant nibble and is transmitted /received first.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 121 Revision 1.4 (08-19-08) DA T ASHEET reception, the data must be moved int o the RX FIFOs before the host can access the data.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 122 SMSC LAN9312 DA T ASHEET 9.8 TX Dat a Path Operation Data is queue d for transmission by writing it into the TX Data FIFO.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 123 Revision 1.4 (08-19-08) DA T ASHEET The LAN931 2 can be program med to strip p adding fr om the end of a tr ansmit pa cket in the event that the end of the packet does not align with the host burst bounda ry .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 124 SMSC LAN9312 DA T ASHEET 9.8.1 TX Buffer Format TX buf fers exist in the host’s memory in a give n format. The host w rites a TX comma nd word into the TX data buffer before moving the Ethernet packet data.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 125 Revision 1.4 (08-19-08) DA T ASHEET Both TX command ‘A ’ and TX command ‘B’ are r equired for each buffer in a given packet.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 126 SMSC LAN9312 DA T ASHEET 9.8.2.2 TX Command ‘B’ 9.8.3 TX Dat a Format The TX data section begins at the third DWORD in t he TX buffer (after TX command ‘A ’ and TX command ‘B’).
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 127 Revision 1.4 (08-19-08) DA T ASHEET The MIL operates in store-and-f orward mode and has specific rules with respect to fragmented packet s.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 128 SMSC LAN9312 DA T ASHEET 9.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 129 Revision 1.4 (08-19-08) DA T ASHEET 16-Byte “Buf fer End Alignment” Figure 9.5 illustrates the TX command stru cture for this example, and al so shows how data is p assed to the TX Data FIFO.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 130 SMSC LAN9312 DA T ASHEET 9.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 131 Revision 1.4 (08-19-08) DA T ASHEET 9.8.7 T ransmitter Errors If the Transmitter Error (TXE) fla g is asserted for any rea son, the transmitte r will continue op eration.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 132 SMSC LAN9312 DA T ASHEET 9.9 RX Dat a Path Operation When an Ethernet Packe t is received, the Host MAC In terface Layer (MIL) f irst begins to transfer the RX data.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 133 Revision 1.4 (08-19-08) DA T ASHEET Figure 9.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 134 SMSC LAN9312 DA T ASHEET 9.9.1.1 Receive Dat a FIFO Fast Forward The RX data p ath implements an automati c data discard function.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 135 Revision 1.4 (08-19-08) DA T ASHEET read them as shown in Figure 9.9 . It is assumed that the host has previously read the associated status word from the RX S tatus FIFO, to ascertain the data size and any error conditions.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 136 SMSC LAN9312 DA T ASHEET 9.9.4 Stopping and S tarting the Receiver T o stop the receiver , the host must clear the RXEN bit in the Host MAC Control Register (HMAC_CR) .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 137 Revision 1.4 (08-19-08) DA T ASHEET Chapter 10 Serial Management 10.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 138 SMSC LAN9312 DA T ASHEET 10.2.1 EEPROM Controller Operation I 2 C and Microwire master EEPROM opera tions are performed using the EEPROM Command Register (E2P_CMD) and EEPROM Data Register (E2P_DA T A) .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 139 Revision 1.4 (08-19-08) DA T ASHEET Figure 10.1 illustrates the process required to perform an EEPROM read or w rite operation. 10.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 140 SMSC LAN9312 DA T ASHEET controller drives all the address bits as requeste d regardless of the actual size of the EEPROM.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 141 Revision 1.4 (08-19-08) DA T ASHEET Figure 10.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 142 SMSC LAN9312 DA T ASHEET 10.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 143 Revision 1.4 (08-19-08) DA T ASHEET Sequential reads are use d by the EEPROM Loader . Refer to Section 10.2.4, "EEPROM Loader" for additional info rmation.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 144 SMSC LAN9312 DA T ASHEET 10.2.3 Microwire EEPROM Based on the configurat ion strap eeprom_type_ strap, various sized Microwire EEPROMs are supported.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 145 Revision 1.4 (08-19-08) DA T ASHEET 10.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 146 SMSC LAN9312 DA T ASHEET 10.2.3.3 ERAL (Erase All) If erase/write operat ions are enabled in the EEPROM, thi s comm and will initiate a bulk erase of the entire EEPROM.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 147 Revision 1.4 (08-19-08) DA T ASHEET 10.2.3.5 EWEN (Erase/W rite Enable) This command enables the EEPROM for erase and write operations .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 148 SMSC LAN9312 DA T ASHEET 10.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 149 Revision 1.4 (08-19-08) DA T ASHEET 10.2.4 EEPROM Loader The EEPROM Loader i nterfaces to the I 2 C/Microwire EEPROM controller , the PHYs, and to the system CSRs (via the Register Access MUX).
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 150 SMSC LAN9312 DA T ASHEET Figure 10.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 151 Revision 1.4 (08-19-08) DA T ASHEET 10.2.4.2 EEPROM V alid Flag Following the release of nRST , POR, DIGIT AL_ RST , or a RELOAD co mmand, the EEPROM Loader start s by reading the first byte of data from the EEPR OM.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 152 SMSC LAN9312 DA T ASHEET The Port x PHY Auto-N egotiation Adverti sement Register (PHY_AN_ADV_x) is written with the new defaults as detailed in Section 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 153 Revision 1.4 (08-19-08) DA T ASHEET 8-bits number_of_bursts repeat (number_of_bu.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 154 SMSC LAN9312 DA T ASHEET Chapter 1 1 IEEE 1588 Hardware T ime St amp Unit 1 1.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 155 Revision 1.4 (08-19-08) DA T ASHEET 1 1.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 156 SMSC LAN9312 DA T ASHEET 1 1.2 IEEE 1588 T ime St amp The LAN9312 contains three identical IEEE 1588 T ime St amp blocks as shown in Figure 1 1.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 157 Revision 1.4 (08-19-08) DA T ASHEET Clock synchronization and hardware processing between the net work data and the time stamp capture hardware causes the time stamp point to be slight ly delayed .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 158 SMSC LAN9312 DA T ASHEET 1 1.2.2 PTP Message Detection In order to pro vide the most flexi bility , loose packet type mat ching is used by th e LAN9312.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 159 Revision 1.4 (08-19-08) DA T ASHEET 1 1.3 IEEE 1588 Clock The 64-bit IEEE 1588 clock is the time source for all IEEE 1588 related functions of the LAN9312.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 160 SMSC LAN9312 DA T ASHEET 1 1.4 IEEE 1588 Clock/Event s The IEEE 1588 Clock/Events block is re sponsible for generating and controlling a ll IEEE 1588 clock related events.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 161 Revision 1.4 (08-19-08) DA T ASHEET Chapter 12 General Purpose T imer & Free-Running Clock This chapter details th e LAN9312 General Purpose T imer (GPT) and the Free-Running Clock.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 162 SMSC LAN9312 DA T ASHEET Chapter 13 GPIO/LED Controller 13.1 Functional Overview The GPIO/LED Controller provides 12 configurabl e general purpose inpu t/output pins, GPIO[ 1 1:0].
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 163 Revision 1.4 (08-19-08) DA T ASHEET 13.2.1 GPIO IEEE 1588 Timest amping T wo of the GPIO pins, GPIO[9:8], have the option to be used for IEEE 1588 time stamp functions.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 164 SMSC LAN9312 DA T ASHEET GPIO_INT_POL[9:8] bits also determin e the polarity of the clock events as described in Section 13.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 165 Revision 1.4 (08-19-08) DA T ASHEET The various LED indica tion functions show n in T able 13.1 are described below: TX Port 0 - The signal is pulsed low for 80mS to indicate activity from the switch fabric to the Host MAC.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 166 SMSC LAN9312 DA T ASHEET Chapter 14 Register Descriptions This section describes the various LAN9312 control an d status registers (CSR’s ).
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 167 Revision 1.4 (08-19-08) DA T ASHEET 14.1 TX/RX FIFO Port s The LAN9312 cont ains four host-accessible FIFO’ s: TX S tatus, RX S tatus, TX Dat a, and RX Dat a.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 168 SMSC LAN9312 DA T ASHEET 14.2 System Contro l and S t atus Registers The System CSR’s are directly addressable memo ry mapped registers with a base address of fset range of 050h to 2DCh.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 169 Revision 1.4 (08-19-08) DA T ASHEET 09Ch FREE_RUN Free Running Counter Register , Section 14.2.9.7 0A0h RX_DROP Host MAC RX Dropped Frames Counter Register , Section 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 170 SMSC LAN9312 DA T ASHEET 13Ch 1588_SRC_UUID_ LO_TX_CAPTURE_2 Port 2 1588 Source UUID Low-DWORD Transmit Capture Register , Section 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 171 Revision 1.4 (08-19-08) DA T ASHEET 1A0h MANUAL_FC_1 Port 1 Manual Flow Control Reg ister , Section 14.2.6.1 1A4h MANUAL_FC_2 Port 2 Manual Flow Control Reg ister , Section 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 172 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 173 Revision 1.4 (08-19-08) DA T ASHEET Note 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 174 SMSC LAN9312 DA T ASHEET 14.2.1.2 Interrupt St atus Register (IN T_STS) This register contains the current status of the generated interrupts.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 175 Revision 1.4 (08-19-08) DA T ASHEET 19 GP Timer (GPT_INT) This interrupt is issued when t he General Purpos e T imer Count Regist er (GPT_CNT) wrap s past zero to FFFFh.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 176 SMSC LAN9312 DA T ASHEET 4 RX St atus FIFO Full Interrupt (RSFF) This interrupt is genera ted when the RX S tatus FIFO is full.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 177 Revision 1.4 (08-19-08) DA T ASHEET 14.2.1.3 Interrupt Enable Regi ster (INT_EN) This register contains the interrupt enables fo r the IRQ output pin.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 178 SMSC LAN9312 DA T ASHEET 5 RESERVED - This bit must be wri tten with 0b for proper operation.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 179 Revision 1.4 (08-19-08) DA T ASHEET 14.2.1.4 FIFO Level Interrupt Reg ister (FIFO_INT) This read/write registe r configures the limits wh er e the RX/TX Data and S tatus FIFO’s will generate system interrupts.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 180 SMSC LAN9312 DA T ASHEET 14.2.2 Host MAC & FIFO’ s This section details the Host MAC and TX/RX FIFO related System CSR’s.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 181 Revision 1.4 (08-19-08) DA T ASHEET 14:13 RESERVED RO - 12:8 RX Data Of fset (RXDOFF) This field controls th e of fset value, in bytes, that is added to t he beginning of an RX data packet.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 182 SMSC LAN9312 DA T ASHEET 14.2.2.2 T ransmit Configurat ion Register (T X_CFG) This register controls the Host MAC transmit functions.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 183 Revision 1.4 (08-19-08) DA T ASHEET 14.2.2.3 Receive Dat apath Control Register (RX_DP_CTRL) This register is used to discard unwanted receive frames.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 184 SMSC LAN9312 DA T ASHEET 14.2.2.4 RX FIFO Information Register (RX_F IFO_INF) This register contains the indicat ion of used space in the RX FI FO’s.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 185 Revision 1.4 (08-19-08) DA T ASHEET 14.2.2.5 TX FIFO Information Register (TX_FIFO_INF) This register contains th e indication of free space in the TX Data FIFO and t he used space in the TX S tatus FIFO.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 186 SMSC LAN9312 DA T ASHEET 14.2.2.6 Host MAC RX Dropped Frames Counter Register (RX_DROP) This register indi cates the numb er of receive fr ames that have been dro pped by the Host MAC.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 187 Revision 1.4 (08-19-08) DA T ASHEET 14.2.2.7 Host MAC CSR Interface Command Register (MAC_CSR_CMD) This read-write registe r is used to control the read and write operatio ns to/from the Host MAC.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 188 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 189 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 190 SMSC LAN9312 DA T ASHEET 3 Flow Control on Multicast Frame (FCMUL T) When this bit is se t, the Host MAC wi ll assert back pres sure when the AFC level is reached and a multicast frame is received.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 191 Revision 1.4 (08-19-08) DA T ASHEET 8h 250uS 252.2uS 9h 300uS 302.2uS Ah 350uS 352.2uS Bh 400uS 402.2uS Ch 450uS 452.2uS Dh 500uS 502.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 192 SMSC LAN9312 DA T ASHEET 14.2.3 GPIO/LED This section details the Ge neral Purpose I/O (GPIO) and L ED related System CSR’s.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 193 Revision 1.4 (08-19-08) DA T ASHEET 12 GPIO 8 Clock Event Polari ty (GPIO_EV ENT_POL_8) This bit determines i f the 1588 clo c k event outp ut on GPIO 8 is active high or low .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 194 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 195 Revision 1.4 (08-19-08) DA T ASHEET 14.2.3.3 General Purpose I/O Interrupt S tatus and Enable Register (GPIO_INT_ST S_EN) This read/w rite register cont ains the GPIO interrup t status bi ts.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 196 SMSC LAN9312 DA T ASHEET 14.2.3.4 LED Configuration Register (L ED_CFG) This read/write regist er configures the GPIO[7:0] pins as LED[7:0] pins and sets their f unctionality .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 197 Revision 1.4 (08-19-08) DA T ASHEET 14.2.4 EEPROM This section details the EEPROM re l ated System CSR’ s. These regist ers should only be us ed if an EEPROM has been connected to th e LAN9312.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 198 SMSC LAN9312 DA T ASHEET 30:28 EEPROM Controller Co mmand (EPC_COMMAND) This field is used to issue comm ands to the EEPROM controller .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 199 Revision 1.4 (08-19-08) DA T ASHEET 18 EEPROM Loader Address Over flow (LOADER_OVERFLOW) This bit indicates that the EEPROM Load er tried to read p a st the end of the EEPROM address space.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 200 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 201 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 202 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 203 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 204 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 205 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 206 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 207 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 208 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 209 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 210 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 21 1 Revision 1.4 (0 8-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 212 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 213 Revision 1.4 (08-19-08) DA T ASHEET 14.2.5.1 3 1 588 Clock High-DWORD Register (1 588_CLOCK_HI) This read/write regi ster combined with 1588 Clock Low-DWORD Reg ister (158 8_CLOCK_LO) form t he 64-bit 1588 Clock value.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 214 SMSC LAN9312 DA T ASHEET 14.2.5.1 4 1 588 Clock Low -DWORD Register (1588_CLOCK_LO) This read/write regi ster combined with 1588 Clock High-DWORD Re gister (1588_CLOCK_HI) form the 64-bit 1588 Clock value.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 215 Revision 1.4 (08-19-08) DA T ASHEET 14.2.5.15 1588 Clock Addend Register (1588_CLOCK_ADDEND) This read/write register is resp onsible for ad justing the 64-b it 1588 Clock frequency .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 216 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 217 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 218 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 219 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 220 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 221 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 222 SMSC LAN9312 DA T ASHEET 14.2.5.22 1588 Configuration Regis ter (1588_CONFIG) This read/write regist er is responsible for the configuration of the 1588 timestamps for all ports.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 223 Revision 1.4 (08-19-08) DA T ASHEET 23 Master/Slave Port 1 (M_nS_1) When set, Port 1 is a time clock master and captu res timestamps when a Sync packet is transmitted and when a Delay_Req is received .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 224 SMSC LAN9312 DA T ASHEET 13 Alternate MAC Address 1 Enab le Port 0(Host MA C) (MAC_AL T1 _EN_MII) This bit enables/ disables the alternate MAC address 1 on Port 0.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 225 Revision 1.4 (08-19-08) DA T ASHEET 5 Lock Enable GPIO 8 (LOCK_GPIO _8) This bit enable s/disables the GPIO 8 lock.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 226 SMSC LAN9312 DA T ASHEET 14.2.5.2 3 1 588 Interrupt S tatu s and Enable Register (1588_INT_STS_EN) This read/write register con tains the IEEE 1588 interrupt status and enable bits.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 227 Revision 1.4 (08-19-08) DA T ASHEET 3 1588 Port 0(Host MAC) TX Interr upt (1588_.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 228 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 229 Revision 1.4 (08-19-08) DA T ASHEET 14.2.6 Switch Fabric This section details the memo ry mapped System CSR’s which are related to the Switch Fabric.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 230 SMSC LAN9312 DA T ASHEET Note 14.4 The default value of th is field is determined b y the BP_EN_stra p_1 configuration st rap.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 231 Revision 1.4 (08-19-08) DA T ASHEET 14.2.6.2 Port 2 Manual Flow Control Register (MANUAL_FC_2) This read/writ e register allo ws for the manual configuration of the switch Port 2 flow control .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 232 SMSC LAN9312 DA T ASHEET Note 14.8 The default value of th is field is determined b y the BP_EN_stra p_2 configuration st rap.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 233 Revision 1.4 (08-19-08) DA T ASHEET 14.2.6.3 Port 0(Host MAC ) Manual Fl ow Control Register (MANUAL_FC_MII) This read/write regist er allows f or the manual con figurat ion of th e swi tch Port 0 (H ost MAC) flo w control.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 234 SMSC LAN9312 DA T ASHEET Note 14.12 The default value of this field is de termined by the BP_EN_st rap_mii configuration st rap.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 235 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 236 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 237 Revision 1.4 (08-19-08) DA T ASHEET 19:16 CSR Byte Enable (CSR_BE[3:0]) This field is a 4-b it byte enable used f or selection of valid byt es during write operations.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 238 SMSC LAN9312 DA T ASHEET 14.2.6.6 Switch Fabric MAC Address High Register (SWITCH _MAC_ADDRH) This register contains the upper 16-bits of the MAC address used by the switch for Pause frames.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 239 Revision 1.4 (08-19-08) DA T ASHEET 14.2.6.7 Switch Fabric MAC Addres s Low Register (SWITCH_MAC _ADDRL) This register contains the lower 32-bits of the MA C address used b y the switch for Paus e frames.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 240 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 241 Revision 1.4 (08-19-08) DA T ASHEET MAC_TX_CFG_2 0C40h 22Ch MAC_TX_FC_SETTINGS_2.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 242 SMSC LAN9312 DA T ASHEET BM_FC_RESUM E_L VL 1C03h 2A4h BM_BCST_L VL 1C.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 243 Revision 1.4 (08-19-08) DA T ASHEET 14.2.7 PHY Management Interface (PMI) The PMI registers are used (by the EEPROM Lo ader only) to indirectly access the PHY regi sters.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 244 SMSC LAN9312 DA T ASHEET 14.2.7.2 PHY Management Interf ace Access Regist er (PMI_ACCESS) This register is used to cont rol the management cycles to the PHYs.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 245 Revision 1.4 (08-19-08) DA T ASHEET 14.2.8 Virtual PHY This section det ails the Virtual PHY Syste m CSR’s. These registers p rovide status and control information similar to that of a real PHY while maintaining IEEE 802.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 246 SMSC LAN9312 DA T ASHEET 14.2.8.1 Virtu al PHY Basic Cont rol Register (VPHY_BASIC_CTRL) This read/write regist er is used to configure th e Virtual PHY .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 247 Revision 1.4 (08-19-08) DA T ASHEET Note 14.16 The reserved bits 31-16 are used to pad the register to 32-bits so that each reg ister is on a DWORD boundary .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 248 SMSC LAN9312 DA T ASHEET 14.2.8.2 Virtu al PHY Basic St atus Register (VPHY_BASIC_ST A TUS) This register is used to monitor the status of the Virtual PHY .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 249 Revision 1.4 (08-19-08) DA T ASHEET Note 14.17 The reserved bits 31-16 are used to pad the register to 32-bits so that each reg ister is on a DWORD boundary .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 250 SMSC LAN9312 DA T ASHEET 14.2.8.3 Virtual PH Y Identifica ti on MSB Register (VPHY_ID_MSB) This read/wri te register co ntains the MSB of the Virtual PHY Orga nizationally Unique Id entifier (OUI).
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 251 Revision 1.4 (08-19-08) DA T ASHEET 14.2.8.4 Virtual PH Y Identifica ti on LSB Register (VPHY_ID_LSB) This read/write register cont ains the LSB of the V irtual PHY Organizationally Unique Identifie r (OUI).
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 252 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 253 Revision 1.4 (08-19-08) DA T ASHEET Note 14.27 The reserved bits 31-16 are used to pad the register to 32-bits so that each reg ister is on a DWORD boundary .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 254 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 255 Revision 1.4 (08-19-08) DA T ASHEET Note 14.33 The reserved bits 31-16 are used to pad the register to 32-bits so that each reg ister is on a DWORD boundary .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 256 SMSC LAN9312 DA T ASHEET 14.2.8.7 Virtual PHY Auto-Negotiation Exp a nsion Register (VPHY_AN_EXP) This register is used in t he Auto-Negotiation process.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 257 Revision 1.4 (08-19-08) DA T ASHEET 14.2.8.8 Virtual PHY S pecial Control/St atus Register (VPHY_SPECIAL_CONTROL_ST A TUS) This read/writ e register cont ains a current li nk speed/duplex in dicator and SQE control .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 258 SMSC LAN9312 DA T ASHEET Note 14.42 The reserved bits 31-16 are used to pad the register to 32-bits so that each reg ister is on a DWORD boundary .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 259 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 260 SMSC LAN9312 DA T ASHEET 14.2.9.2 Byte Order T est Register (BYTE_TEST) This read-only regist er can be used to determine th e byte ordering of th e current configuration.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 261 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 262 SMSC LAN9312 DA T ASHEET Note 14.47 The default value of this field is determined by the configuration strap auto_mdi x_strap_2.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 263 Revision 1.4 (08-19-08) DA T ASHEET 14.2.9.4 Power Management Co ntrol Register (PMT_CTRL) This read-write register controls the pow er mana gement features an d the PME pin of the LAN9312 .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 264 SMSC LAN9312 DA T ASHEET 8:7 RESER VED RO - 6 PME Buffer T ype (PME_TYPE) When this bit is cle ared, the PME pin funct ions as an open-drain buffer for use in a wired-or configura tion.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 265 Revision 1.4 (08-19-08) DA T ASHEET 14.2.9.5 General Purpose T imer Configuration Register (GPT_CFG) This read/write register configures the LAN9312 General Purpose T imer (GPT).
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 266 SMSC LAN9312 DA T ASHEET 14.2.9.6 General Purpose T imer Count Register (GPT_CNT) This read-only register reflects the current general purpose timer (GPT) value.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 267 Revision 1.4 (08-19-08) DA T ASHEET 14.2.9.7 Free Running 25MHz Counter Register (FREE_RUN) This read-only register reflects the current value of the free-running 25MHz coun ter .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 268 SMSC LAN9312 DA T ASHEET 14.2.9.8 Reset Control Register ( RESET_CTL) This register contains so ftware controlle d resets.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 269 Revision 1.4 (08-19-08) DA T ASHEET 14.3 Host MAC Contro l and St atus Registers This section details the Host MA C Syst em CSR’s.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 270 SMSC LAN9312 DA T ASHEET 14.3.1 Host MAC Control Register (HMAC_CR) This read/write re gister establishes the RX and TX operat ion modes and controls for address filtering and pa cket filtering.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 271 Revision 1.4 (08-19-08) DA T ASHEET 16 Pass Bad Frames (P ASSBAD) When set, all inco ming frames that passed address filterin g are received, including runt frames and collided frames.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 272 SMSC LAN9312 DA T ASHEET 7:6 BackOff Limit (BOLMT) The BOLMT bits allow the user to set the back-off limit in a relaxed or aggressive mode.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 273 Revision 1.4 (08-19-08) DA T ASHEET 14.3.2 Host MAC Address Hi gh Register (HMAC_ADDRH) This read/write regi ster contains the up per 16-bits of the physical address of the Ho st MAC.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 274 SMSC LAN9312 DA T ASHEET 14.3.3 Host MAC Address Low Register (HMAC_ADDRL) This read/write register cont ains the lower 32-bits of the physical address of the Host MAC.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 275 Revision 1.4 (08-19-08) DA T ASHEET 14.3.4 Host MAC Multicast Hash T a ble High Register (HMAC_HASHH) The 64-bit Multicast table is used for group address fi ltering.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 276 SMSC LAN9312 DA T ASHEET 14.3.5 Host MAC Multicast Hash T a ble Low Register (HMAC_HASHL) This read/write regist er defines the lower 32-bits of the Multicast Hash T able.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 277 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 278 SMSC LAN9312 DA T ASHEET 14.3.7 Host MAC MII Dat a Re gister (HMAC_MII_DA T A) This read/write regist er is used in conjunction with the Host MAC MII Access Register (HMAC_MII_ACC) to access the internal PHY registers.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 279 Revision 1.4 (08-19-08) DA T ASHEET 14.3.8 Host MAC Flow Cont rol Register (HMAC_FLOW) This read/write re gister controls the generation and reception of the Control (Pause command) fr ames by the Host MAC’s flow control b lock.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 280 SMSC LAN9312 DA T ASHEET 0 Flow Control Busy (FCBSY) In full-duplex mod e, this bit should re ad logical 0 befo re writing to the Ho st MAC Flow Control (HMAC_FLOW) regist er .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 281 Revision 1.4 (08-19-08) DA T ASHEET 14.3.9 Host MAC VLAN1 T ag Register (HMAC_VLAN1) This read/write register contains the VLAN tag field to identify VLAN1 fra mes.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 282 SMSC LAN9312 DA T ASHEET 14.3.10 Host MAC VLAN2 T ag Register (HMAC_VLAN2) This read/write register contains the VLAN tag field to identify VLAN2 fra mes.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 283 Revision 1.4 (08-19-08) DA T ASHEET 14.3.1 1 Host MAC W ake-u p Frame Filter Register (HMAC_WUFF) This write-only registe r is used to configure th e wake-up frame filter .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 284 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 285 Revision 1.4 (08-19-08) DA T ASHEET 14.4 Ethernet PHY Cont rol and S t atus Registers This section details the various LAN9312 Ethernet P HY control and status re gisters.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 286 SMSC LAN9312 DA T ASHEET 17 PHY_MODE_CONTROL_ST A TUS_x Port x PHY Mo de Control/S tatus Register , Section 14.4.2.8 18 PHY_SPECIAL_MODES_x Port x PHY S pecial Modes Register , Section 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 287 Revision 1.4 (08-19-08) DA T ASHEET 14.4.2.1 Port x PHY Basic Co ntro l Register (PHY_BASIC_CONTROL_x) This read/write register is used to configure the Port x PHY .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 288 SMSC LAN9312 DA T ASHEET Note 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 289 Revision 1.4 (08-19-08) DA T ASHEET 14.4.2.2 Port x PHY Basic S tatus Register (PHY_BASIC_ST A TUS_ x) This register is used to monitor the status of the Port x PHY .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 290 SMSC LAN9312 DA T ASHEET Note 14.52 The PHY supports 100BASE-TX (half and full duplex) and 10BA SE-T (half and full duplex) only .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 291 Revision 1.4 (08-19-08) DA T ASHEET 14.4.2.3 Port x PHY Identif icati on MS B Register (P HY_ID_MSB_x) This read/write register con t a ins the MSB of the Organizationally Unique Identifier (OUI) for the Port x PHY .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 292 SMSC LAN9312 DA T ASHEET 14.4.2.4 Port x PHY Identif icati on LSB Register (PHY_ID_LSB_x) This read/wri te register co ntains the LSB of the Or ganizationally Uni que Ident ifier (OUI) for the Port x PHY .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 293 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 294 SMSC LAN9312 DA T ASHEET Note 14.53 The Pause and Asymmetric Pause bits are loaded into the PHY register s by the EEPROM Loader .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 295 Revision 1.4 (08-19-08) DA T ASHEET 11 1 T able 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 296 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 297 Revision 1.4 (08-19-08) DA T ASHEET Note 14.57 The Port 1 & 2 PHY’s support only IEEE 802.3. 6 10BASE-T Full Duplex This bit indicate s the link partner PHY 10BASE-T full duplex capability .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 298 SMSC LAN9312 DA T ASHEET 14.4.2.7 Port x PHY Auto-Negot iation Exp ansion Register (PHY_AN_EXP_x) This read/write register is used in the Auto-Negotiation process between the l ink partner and the Port x PHY .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 299 Revision 1.4 (08-19-08) DA T ASHEET 14.4.2.8 Port x PHY Mode Control/S tatus Register (PHY_MODE_CONTROL_ST A TUS_x) This read/write regist er is used to control an d monitor various Port x PH Y configuration options.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 300 SMSC LAN9312 DA T ASHEET 14.4.2.9 Port x PHY Special Mode s Register (PHY_SPECIAL_MODES_x) This read/write regist er is used to control the special modes of the Port x PHY .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 301 Revision 1.4 (08-19-08) DA T ASHEET 01 1 100BASE-TX Full Dupl ex. Auto-negotiation disabled. CRS is active during Receive. 1001 N/A 100 100BASE-TX Half Duplex is adverti sed.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 302 SMSC LAN9312 DA T ASHEET 14.4.2.10 Port x PHY Special Control/S tatus In dication Register (PHY_ SPECIAL_CONTROL_ST A T_IND_x) This read/write regist er is used to control various op tions of the Port x PHY .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 303 Revision 1.4 (08-19-08) DA T ASHEET T able 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 304 SMSC LAN9312 DA T ASHEET 14.4.2.1 1 Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT _SOURCE_x) This read-only register is used to det ermine to so urce of various Port x PHY interrupts.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 305 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 306 SMSC LAN9312 DA T ASHEET 14.4.2.13 Port x PHY S pecial Control /St atus Register (PHY_SPEC IAL_CONTROL_ST A TUS_x) This read/write regist er is used to control and mon itor various options of th e Port x PHY .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 307 Revision 1.4 (08-19-08) DA T ASHEET 14.5 Switch Fabric Cont rol and S t atus Registers This section details the various LAN9312 switch control and status registers that reside within the switch fabric.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 308 SMSC LAN9312 DA T ASHEET 0414h MAC_RX_256_ TO_51 1_ CNT_MII Port 0 MAC Receive 256 to 51 1 Byte Coun t Register , Section 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 309 Revision 1.4 (08-19-08) DA T ASHEET 0455h MAC_TX_65_TO_127_ CNT_MII Port 0 MAC T ransmit 65 to 127 Byte C ount Register , Section 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 310 SMSC LAN9312 DA T ASHEET 0812h MAC_RX_65_TO_127_CNT_1 Port 1 MAC Receive 65 to 127 Byte C ount Register , Section 14.5. 2.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 31 1 Revision 1.4 (0 8-19-08) DA T ASHEET 0852h MAC_TX_P AUSE_CNT_1 Port 1 MAC Transmit Pause Count Register , Secti on 14.5.2.26 0853h MAC_TX_PKTOK_CNT_1 Port 1 MAC Tr ansmit OK Count Re gister , Se ction 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 312 SMSC LAN9312 DA T ASHEET 0C10h MAC _RX_UNDSZE_CNT_2 Port 2 MAC Receive Undersize Co unt Register , Section 14.5. 2.3 0C1 1h MAC_ RX_64_CNT_2 Port 2 MAC Receive 64 Byte Count Register , Section 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 313 Revision 1.4 (08-19-08) DA T ASHEET 0C42h-0C50h RESERVED Rese rved for Future Use 0C51h MAC_TX_DEFER_CNT_2 Port 2 MAC Transmit Deferred Count Register , Section 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 314 SMSC LAN9312 DA T ASHEET Switch Engine CSRs 1800h SWE_ALR_CMD Switch Engin e ALR Command Register , Section 14.5. 3.1 1801h SWE_ALR_WR_DA T_ 0 Switch Engine ALR Write Data 0 Register , Secti on 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 315 Revision 1.4 (08-19-08) DA T ASHEET 1847h SWE_INGRESS _PORT_TYP Switch Engine Ingress Port T ype Register , Section 14.5. 3.22 1848h SWE_BCST_THROT Switch Engine Broadcast Throttling Register, Section 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 316 SMSC LAN9312 DA T ASHEET 1C02h BM_FC_P AUSE_L VL Buf fer Manager Flow Control Pause Le vel Register , Section 14.5. 4.3 1C03h BM_FC_RESUME_L VL Buffe r Manager Flow Co ntrol Resume Le vel Register , Section 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 317 Revision 1.4 (08-19-08) DA T ASHEET 1C20h BM_IMR Buffer Manager Interru pt Mask Register , Section 14.5.4 .26 1C21h BM_IP R Buf fer Manager Interrupt Pendi ng Register , Secti on 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 318 SMSC LAN9312 DA T ASHEET 14.5.1 General Switch CSRs This section details the gen eral switch fabric CSRs. These registers control the main reset and interrupt fu nctions of the swi tch fabric.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 319 Revision 1.4 (08-19-08) DA T ASHEET 14.5.1.2 Switch Reset Register (SW_RESET) This register contains the switch fabri c global reset.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 320 SMSC LAN9312 DA T ASHEET 14.5.1.3 Switch Global Interr upt Mask Register (SW_IMR) This read/write register co ntains the global interr upt mask for the switch fabric interrupts.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 321 Revision 1.4 (08-19-08) DA T ASHEET 14.5.1.4 Switch Global Interr upt Pe nding Register (SW_IPR) This read-only register con tains the pending global interrupts for the switch f abric.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 322 SMSC LAN9312 DA T ASHEET 14.5.2 Switch Port 0, Port 1, and Port 2 CSRs This section details the switch Port 0(Host MAC) , Port 1, and Port 2 CSRs.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 323 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.2 Port x MAC Receive Confi guration Register (MAC_RX_CFG _x) This read/write register con figures the packet type passing parameters of the port.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 324 SMSC LAN9312 DA T ASHEET 14.5.2.3 Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x) This register provides a counter of undersized packets received by the port.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 325 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.4 Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_ x) This register provides a count er of 64 byte packets received by the port.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 326 SMSC LAN9312 DA T ASHEET 14.5.2.5 Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_ CNT_x) This register provides a counter of received packets between the size of 65 to 127 bytes.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 327 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.6 Port x MAC Receive 128 to 255 Byte Count Register (M AC_RX_128_TO _255_CNT_x) This register provides a counte r of received packets between the size of 128 to 255 bytes.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 328 SMSC LAN9312 DA T ASHEET 14.5.2.7 Port x MAC Receive 256 to 51 1 Byte Count Register (MAC_RX_256_TO_51 1_CNT_x) This register provides a counter of received packets between the size of 25 6 to 51 1 bytes.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 329 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.8 Port x MAC Receive 512 to 1023 Byte Count Register (MAC _RX_512_T O_1023_CNT_x) This register pro vides a counter of received packets between the size of 512 to 1023 bytes.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 330 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 331 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.10 Port x MAC Receive Oversize Count Register (M AC_RX_OVRSZ E_CNT_x) This register provides a counter of received packet s with a size greater than the max imum byte size.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 332 SMSC LAN9312 DA T ASHEET 14.5.2.1 1 Port x MAC Receive OK Co unt Register (MAC_ RX_PKTOK_CNT_x) This register provides a counter of rece ived packets that are or proper length and are free of e rrors.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 333 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.12 Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x) This register provides a counter of received packets that with CRC erro rs.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 334 SMSC LAN9312 DA T ASHEET 14.5.2.13 Port x MAC Receive Multicast Count Register (M AC_RX_MULCST_CNT_x) This register provides a counter of valid rece ived packets with a multicast destination a ddress.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 335 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.14 Port x MAC Receive Broadcast Count Register (M AC_RX_BRDCST_CNT_x) This register provides a counter of valid received packets with a broadcast destination address.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 336 SMSC LAN9312 DA T ASHEET 14.5.2.15 Port x MAC Receive Pause Fram e Count Register (MAC_RX_P AUSE_CNT_x) This register provides a counter of vali d received pause frame packets.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 337 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.16 Port x MAC Receive Fragment Er ror Count Register (MAC_RX_FRAG _CNT_x) This register provides a cou nter of received packets of less than 64 bytes and a FCS error .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 338 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 339 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.18 Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x) This register provides a counter of received packets with 64 bytes t o the maximum allowable, and a FCS error .
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 340 SMSC LAN9312 DA T ASHEET 14.5.2.19 Port x MAC Receive Packet Lengt h Count Register (M AC_RX_PKTLEN_CNT_x) This register provides a cou nter of total bytes received.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 341 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.20 Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_C NT_x) This register p rovides a counter o f total bytes received in good p ackets.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 342 SMSC LAN9312 DA T ASHEET 14.5.2.21 Port x MAC Receive Symbol Erro r Count Register (MAC_RX_SYMBOL_ CNT_x) This register prov ides a counter of received packe ts with a symbol error .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 343 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.22 Port x MAC Receive Control Fram e Count Register (MAC_RX_ CTLFRM_CNT_x) This register provides a co unter of good packets with a type field of 8808h.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 344 SMSC LAN9312 DA T ASHEET 14.5.2.23 Port x MAC T ransmit Conf iguration Register (MAC_TX_CFG_x) This read/write regist er configures the transmit packet parameters of the port.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 345 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.24 Port x MAC T ransmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x) This read/write regist er configures the flow control settings of the port.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 346 SMSC LAN9312 DA T ASHEET 14.5.2.25 Port x MAC T ransmit Deferred Count Register (MAC_T X_DEFER_CNT_x) This register provide s a counter deferred packets.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 347 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.26 Port x MAC T ransmit Pause Count Register (MAC_TX_P AUSE_CNT_x) This register provides a counter of transmit ted pause packets.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 348 SMSC LAN9312 DA T ASHEET 14.5.2.27 Port x MAC T ransmit OK C ount Register (MAC_TX_PKT OK_CNT_x) This register provides a counter of successful transmissions.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 349 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.28 Port x MAC T ransmit 64 Byte Count Register (MAC_TX_64_CNT_x) This register provides a cou nter of 64 byte packe ts transmitted by the port.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 350 SMSC LAN9312 DA T ASHEET 14.5.2.29 Port x MAC T ransmit 65 to 127 By te Count Register (MAC_TX_65 _TO_12 7_CNT_x) This register provide s a counter of transmitted packets between the size of 65 to 127 bytes.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 351 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.30 Port x MAC T ransmit 128 to 255 Byte Count Register (MAC_TX_128_T O_255_CNT_x) This register prov ides a counter of tra nsmitted packets between the size of 12 8 to 255 bytes.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 352 SMSC LAN9312 DA T ASHEET 14.5.2.31 Port x MAC T ransmit 256 to 51 1 Byte Count Register (MAC_TX_256_T O_51 1_CNT_x) This register provides a counter of transmitted p a ckets bet ween the size of 256 to 5 1 1 bytes.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 353 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.32 Port x MAC T ransmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x) This register provides a counter of t ransmitted packets between the size of 512 to 1023 byt es.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 354 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 355 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.34 Port x MAC T ransmit Undersiz e Count Regist er (MAC_TX_UNDSZE_CNT_x) This register provides a counter of undersize d packe ts transmitted by the port.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 356 SMSC LAN9312 DA T ASHEET 14.5.2.35 Port x MAC T ransmit Packet Leng th Count Register (MAC_TX_PKTLEN_CNT_x) This register provides a counter of total bytes transmitted.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 357 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.36 Port x MAC T ransmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x) This register provides a counter of transmitt ed broadcast packets.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 358 SMSC LAN9312 DA T ASHEET 14.5.2.37 Port x MAC T ransmit Multicast Count Register (MAC_T X_MULCST_CNT_x) This register provides a cou nter of transmitted mu lt icast packets.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 359 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.38 Port x MAC T ransmit Late Collision Count Registe r (MAC_TX_LA TECOL_CNT_x) This register provides a counter of transmitted pa ckets which experien ced a late collision.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 360 SMSC LAN9312 DA T ASHEET 14.5.2.39 Port x MAC T ransmit Excessive Coll ision C ount Regi ster (MAC_TX_EXCCOL_CN T_x) This register provides a counter of transmitted packets which experienced 16 collisi ons.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 361 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.40 Port x MAC T ransmit Single Collisi on Count Register (MAC_TX_SNGLECOL_CNT_x) This register provides a counter of transmitted packets which ex perienced exactly 1 collision.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 362 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 363 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.42 Port x MAC T ransmit T ot al Collis ion Count Register (MAC_TX_TO T ALCOL_CNT_x) This register provides a counter of total collisions including late collisi ons.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 364 SMSC LAN9312 DA T ASHEET 14.5.2.43 Port x MAC Interrupt Mask Register (MAC_IMR_x) This register contains the Port x interru pt mask.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 365 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.44 Port x MAC Interrupt Pending Register (MAC_IPR_x) This read-only registe r cont ains the pendi ng Port x interrupts.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 366 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 367 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 368 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 369 Revision 1.4 (08-19-08) DA T ASHEET 18:16 Port These bits indicate the p ort(s) associated with this MAC address. When bit 18 is cleared, a single port i s selected.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 370 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 371 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 372 SMSC LAN9312 DA T ASHEET 18:16 Port These bits indicate the p ort(s) associated with this MAC address. When bit 18 is cleared, a single port i s selected.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 373 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.6 Switch Engine ALR Command S ta tus Register (SWE_ALR_CMD_STS) This register indica tes the current ALR command status.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 374 SMSC LAN9312 DA T ASHEET 14.5.3.7 Switch Engine ALR Config uration Register (SWE_ALR_CFG) This register contro ls the ALR aging timer duration .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 375 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.8 Switch Engine VLAN Command Register (SWE_VLAN_CMD) This register is used to read and writ e the VLAN or Port VID tables.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 376 SMSC LAN9312 DA T ASHEET 14.5.3.9 Switch Engine VLAN W rite Data Register (SWE_VLAN_WR_DA T A) This register is used writ e the VLAN or Port VID tables.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 377 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.10 Switch Engine VLAN Read Dat a Register (SWE_VLAN_RD_DA T A) This register is used to read the VLAN or Port VID tables.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 378 SMSC LAN9312 DA T ASHEET 14.5.3.1 1 Switch Engine VLAN Command St atus Register (SWE_VLAN_CMD_STS) This register indica tes the current VLAN command status.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 379 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.12 Switch Engine DIFFSERV T able Command Register (SWE_DIFFSER V_TBL_CFG) This register is used t o read and write the DIFFSERV t able.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 380 SMSC LAN9312 DA T ASHEET 14.5.3.13 Switch Engine DIFFSERV T able W rit e Dat a Register (SWE_DIFFSERV_TBL_WR_DA T A) This register is used to write th e DIFFSERV table.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 381 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.14 Switch Engine DIFFSERV T able Read Dat a Register (SWE_DIFFSERV_TBL_RD_DA T A) This register is used to read the DIFFSERV table.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 382 SMSC LAN9312 DA T ASHEET 14.5.3.15 Switch Engine DIFFSER V T able Command St atus Register (SWE_DIFFSER V_TBL_CMD_STS) This register indi cates the current DIF FSERV command status.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 383 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.16 Switch Engine Global Ingress Conf iguration Register (SWE_GLOBAL_ INGRSS_CFG) This register is used to configure the global in gress rules.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 384 SMSC LAN9312 DA T ASHEET 1 VL Higher Priority When this bit is set and VLANs are enabled, the priority fr om the VLAN tag has higher priority than the IP TOS/SC fiel d.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 385 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.17 Switch Engine Port Ingress Conf iguration Register (SWE_PORT_INGRSS_CFG ) This register is used to configure the per port ingress rules.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 386 SMSC LAN9312 DA T ASHEET 14.5.3.18 Switch Engine Admit Only VLAN Register (SWE_ADMT_ONL Y_VLAN) This register is used to configure the per port ingress rule for allowing on ly VLAN tagged packets .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 387 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.19 Switch Engine Port St ate Register (SWE_PORT_ST A T E) This register is used to configure the per po rt spanning tree state.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 388 SMSC LAN9312 DA T ASHEET 14.5.3.2 0 Switch Engine Pr iority to Queue Register (SWE_PRI_TO_QU E) This register specifies the T r affic Class table that maps the p acket priority into t he egress queues.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 389 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.21 Switch Engine Port Mi rroring Register (SWE_PORT_MIRROR) This register is used to configure port mirrorin g.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 390 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 391 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.23 Switch Engine Broadcast Thr ottling Regi ster (SWE_BC ST_THROT) This register configure s the broadcast input rate t hrottling.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 392 SMSC LAN9312 DA T ASHEET 14.5.3.24 Switch Engine Admit Non Member Register (SWE_ADMT_N_MEMBER) This register is used to allow access to a VLAN even if the ingress port is not a member .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 393 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 394 SMSC LAN9312 DA T ASHEET 14.5.3.26 Switch Engine Ingress Rate Co m mand Register (SWE_INGRSS_RA TE_C MD) This register is used to indirectly read and write t he ingress rate metering/color table registe rs.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 395 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 396 SMSC LAN9312 DA T ASHEET 14.5.3.27 Switch Engine Ingres s Rate Command St atus Register (SWE_INGRSS_RA TE_CMD_STS) This register indica tes the current ingress rat e command status.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 397 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.28 Switch Engine Ingress Rate Write Dat a Register (SWE_INGRSS _RA TE_WR_DA T A) This register is used to write the ingress rate table registers.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 398 SMSC LAN9312 DA T ASHEET 14.5.3.29 Switch Engine Ingress Rate Re ad Dat a Register (SWE_INGRSS_RA TE_RD_DA T A) This register is used to read the ingress rate table registers.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 399 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.30 Switch Engine Port 0 Ingress Filt ered Count Register (SWE_FIL TERED_CNT_MII) This register counts the number of packets filtered at ingress on Port 0(Host MAC).
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 400 SMSC LAN9312 DA T ASHEET 14.5.3.31 Switch Engine Port 1 Ingress Filt ered Count Register (SWE_FIL TERED_CNT_1) This register counts the number of packets filtered at ingress on Port 1.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 401 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.32 Switch Engine Port 2 Ingress Filt ered Count Register (SWE_FIL TERED_CNT_2) This register counts the number of packets filtered at ingress on Port 2.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 402 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 403 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 404 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 405 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 406 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 407 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 408 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 409 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.40 Switch Engine Interr upt Pending Register (SWE_I PR) This register contains the Switch Engine int errupt status.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 410 SMSC LAN9312 DA T ASHEET 10:9 Source Port B When bit 8 is set, these bits indicate the source port on which the packet was dropped.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 41 1 Revision 1.4 (0 8-19-08) DA T ASHEET 14.5.4 Buffer Manager CSRs This section details the Buffer Manager (BM) regi sters. These registers allow configu ration and monitoring of the switch buffe r levels and usage.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 412 SMSC LAN9312 DA T ASHEET 14.5.4.2 Buff er Manager Dr op Level Regi ster (BM_DR OP_L VL) This register configure s the overall buffer usage limits.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 413 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.3 Buffer Manager Flow Co ntrol Pause Level Reg ister (BM_FC_P AUSE_L VL) This register configure s the buffer usage level when a Pause frame or b ackpressure is sent.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 414 SMSC LAN9312 DA T ASHEET 14.5.4.4 Buffer Manager Flow Control Re sume Le vel Register (BM_FC_RESUME_L VL) This register configure s the buffer usage level when a Pause f rame with a pause value of 1 is sent.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 415 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.5 Buffer Manager Broadcast Buffer Le vel Register (BM_BCST_L VL) This register configure s the buffer usage limits for broadcasts, multicasts, and unknown unicasts.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 416 SMSC LAN9312 DA T ASHEET 14.5.4.6 Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_ MII) This register counts the number of packets dropped by the Buffer Manager that were received on Port 0(Host MAC).
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 417 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.7 Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_ 1) This register counts the number of packets dropped by the Buffer Manager that were received on Port 1.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 418 SMSC LAN9312 DA T ASHEET 14.5.4.8 Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_ 2) This register counts the number of packets dropped by the Buffer Manager that were received on Port 2.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 419 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.9 Buffer Manager Reset S ta tus Register (BM_RST_STS) This register indica tes when the Buffer Manager has be en initialized by the rese t process.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 420 SMSC LAN9312 DA T ASHEET 14.5.4.10 Buffer Manager Random Discard T abl e Command Register (BM_RNDM_DSCRD_TBL_CMD) This register is used to read and write the Random Discard Weight table.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 421 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.1 1 Buffer Manager Random Discard T able Write Data Register (BM_RNDM_DSCRD_TBL_WDA T A) This register is used to write the Random Discard Weight table.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 422 SMSC LAN9312 DA T ASHEET 14.5.4.12 Buffer Manager Random Discard T able Re ad Dat a Register (BM_RNDM_DSCRD_TBL_ RDA T A) This register is used to read the Random Di scard Weight table.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 423 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.1 3 Buffer Manager Egress Port T ype Register (BM_EGRSS_PORT_TYPE) This register is used to configur e the egress VLAN tagging rules.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 424 SMSC LAN9312 DA T ASHEET 17:16 Egress Port T ype Port 2 These bits set the egress po rt type which det ermine s the tagging/un-tagging rules.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 425 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 426 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 427 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 428 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 429 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 430 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 431 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.20 Buffer Manager Port 0 Default VLAN ID and Priority Registe r (BM_VLAN_MII) This register is used to specify the default VLAN ID and priority of Port 0(Host MAC).
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 432 SMSC LAN9312 DA T ASHEET 14.5.4.21 Buffer Manager Port 1 Default VLAN ID and Priority Registe r (BM_VLAN_1) This register is used to specify the default VLAN ID and priority of Port 1.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 433 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.22 Buffer Manager Port 2 Default VLAN ID and Priority Registe r (BM_VLAN_2) This register is used to specify the default VLAN ID and priority of Port 2.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 434 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 435 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 436 SMSC LAN9312 DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 437 Revision 1.4 (08-19-08) DA T ASHEET 14.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 438 SMSC LAN9312 DA T ASHEET 14.5.4.2 7 Buffer Manager Int err upt Pending Register (BM_IPR) This register contains the Buffer Manager interrupt status.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 439 Revision 1.4 (08-19-08) DA T ASHEET 6:3 Drop Reason A When bit 0 is set, th ese bits indicate the reaso n a packet was dropped. See the Drop Reason B description above for definitions o f each value of this field.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 440 SMSC LAN9312 DA T ASHEET Chapter 15 Operational Characteristics 15.1 Absolute Maximum Ratings* Supply V oltage (VDD33A1, VDD 33A2, VDD33BIAS, VDD33IO) ( Note 15 .
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 441 Revision 1.4 (08-19-08) DA T ASHEET 15.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 442 SMSC LAN9312 DA T ASHEET 15.4 DC Specifications Note 15.5 This specification applies to all IS type inputs and tri-stated bi-direct ional pins.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 443 Revision 1.4 (08-19-08) DA T ASHEET Note 15.7 Measured at line side of transfo rmer , line rep laced by 100 Ω (+/- 1%) resistor . Note 15.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 444 SMSC LAN9312 DA T ASHEET 15.5.2 Reset and Configuration Strap T iming This diagram illustrates the nRST pin timing req uirements and its relation to the configuration strap pins and output d rive.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 445 Revision 1.4 (08-19-08) DA T ASHEET 15.5.3 Power-On Configurat ion Strap V alid T iming This diagram ill ustrates the configura tion strap valid timing requirements in relation to powe r-on.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 446 SMSC LAN9312 DA T ASHEET 15.5.4 PIO Read Cycle Timing Please refer to Section 8.4.4, "PIO Reads, " on page 1 06 for a functional de scription of this mode.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 447 Revision 1.4 (08-19-08) DA T ASHEET 15.5.5 PIO Burst Re ad Cycle Timing Please refer to Section 8.4.5, "PIO Burst Reads, " on page 107 for a functional description of this mode.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 448 SMSC LAN9312 DA T ASHEET 15.5.6 RX Data FIFO Direct PIO Read Cycle T iming Please refer to Section 8.4.6, "RX Da ta FIFO Direct PIO Reads," on page 108 for a functional description of this mode.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 449 Revision 1.4 (08-19-08) DA T ASHEET 15.5.7 RX Dat a FIFO Direct PIO Burst Read Cycle Timing Please refer to Section 8.4.7, "RX Data FIFO Direct PIO Burst Reads," on page 109 for a functional description of this mode.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 450 SMSC LAN9312 DA T ASHEET 15.5.8 PIO Write Cycle T iming Please refer to Section 8.4.8, "PIO Writes," on page 1 10 for a functional descripti on of this mode.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 451 Revision 1.4 (08-19-08) DA T ASHEET 15.5.9 TX Dat a FIFO Direct PIO Write Cycle T iming Please refer to Section 8.4.9, "TX Data FIFO Direct PIO Writes," on page 1 1 1 for a functional description of this mode.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 452 SMSC LAN9312 DA T ASHEET 15.5.10 Microwire T iming This section specifies the Microwire EEPROM in terface timing requirements.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 453 Revision 1.4 (08-19-08) DA T ASHEET 15.6 Clock Circuit The LAN931 2 can accept e ither a 25MHz cryst al (preferred) or a 25 MHz single-ended clock oscillator (+/- 50ppm) input.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 454 SMSC LAN9312 DA T ASHEET Chapter 16 Package Outlines 16.1 128-VTQFP Package Outline Figure 16.1 LAN9312 128-VTQFP Package De finition T ab le 16.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 455 Revision 1.4 (08-19-08) DA T ASHEET Notes: 1. All dimensions are in milli meters unless otherwise noted. 2. Dimensions b & c apply to the flat section of the lead foot between 0.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 456 SMSC LAN9312 DA T ASHEET 16.
High Performance T wo Port 10/100 Managed Etherne t Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 457 Revision 1.4 (08-19-08) DA T ASHEET Notes: 1. All dimensions are in milli meters unless otherwise noted. 2. Dimensions b & c apply to the flat section of the lead foot between 0.
High Performance T wo Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 458 SMSC LAN9312 DA T ASHEET Chapter 17 Revision History T able 17.1 Customer Revision History REVISION LEVEL & DATE SECTI ON/FIGURE/ENTRY CORRECTION Rev .
Ein wichtiger Punkt beim Kauf des Geräts SMSC LAN9312 (oder sogar vor seinem Kauf) ist das durchlesen seiner Bedienungsanleitung. Dies sollten wir wegen ein paar einfacher Gründe machen:
Wenn Sie SMSC LAN9312 noch nicht gekauft haben, ist jetzt ein guter Moment, um sich mit den grundliegenden Daten des Produkts bekannt zu machen. Schauen Sie zuerst die ersten Seiten der Anleitung durch, die Sie oben finden. Dort finden Sie die wichtigsten technischen Daten für SMSC LAN9312 - auf diese Weise prüfen Sie, ob das Gerät Ihren Wünschen entspricht. Wenn Sie tiefer in die Benutzeranleitung von SMSC LAN9312 reinschauen, lernen Sie alle zugänglichen Produktfunktionen kennen, sowie erhalten Informationen über die Nutzung. Die Informationen, die Sie über SMSC LAN9312 erhalten, werden Ihnen bestimmt bei der Kaufentscheidung helfen.
Wenn Sie aber schon SMSC LAN9312 besitzen, und noch keine Gelegenheit dazu hatten, die Bedienungsanleitung zu lesen, sollten Sie es aufgrund der oben beschriebenen Gründe machen. Sie erfahren dann, ob Sie die zugänglichen Funktionen richtig genutzt haben, aber auch, ob Sie keine Fehler begangen haben, die den Nutzungszeitraum von SMSC LAN9312 verkürzen könnten.
Jedoch ist die eine der wichtigsten Rollen, die eine Bedienungsanleitung für den Nutzer spielt, die Hilfe bei der Lösung von Problemen mit SMSC LAN9312. Sie finden dort fast immer Troubleshooting, also die am häufigsten auftauchenden Störungen und Mängel bei SMSC LAN9312 gemeinsam mit Hinweisen bezüglich der Arten ihrer Lösung. Sogar wenn es Ihnen nicht gelingen sollte das Problem alleine zu bewältigen, die Anleitung zeigt Ihnen die weitere Vorgehensweise – den Kontakt zur Kundenberatung oder dem naheliegenden Service.
