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SMSC LAN931 1/LAN931 1i DA T ASHEET Revision 1.4 (08-19- 08) Datasheet PRODUCT FEA TURES LAN931 1/LAN931 1i T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Highlight s H.
ORDER NUMBERS: LAN931 1-NU FOR 128-PIN, VTQFP LEAD-FREE ROHS COMPLIANT P ACKAGE (0 TO 70 ° C TEMP RANGE) LAN931 1-NZW FOR 128-PIN, XVTQFP LE AD-FR EE ROHS COMPLIANT P ACKAGE (0 TO 70 ° C TEMP RA NGE.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 3 Revision 1.4 (08-19-08) DA T ASHEET T able of Content s Chapter 1 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 4 SMSC LAN931 1/LAN931 1i DA T ASHEET 5.2.7 General Purpose Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 5 Revision 1.4 (08-19-08) DA T ASHEET 7.2.1.6 100M Phase Lock Loop (PLL) .................... .. ................ .. ................ ........
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 6 SMSC LAN931 1/LAN931 1i DA T ASHEET 8.6 HBI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 7 Revision 1.4 (08-19-08) DA T ASHEET 10.2.3.7 WRITE (W rite Locat ion) ............ ........... ............. .......... .............. .....
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 8 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.3 GPIO/LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 9 Revision 1.4 (08-19-08) DA T ASHEET 14.3.10 Host MAC VLAN2 Tag Regist er (H MAC_VLAN2) . . . . . . . . . . . . . . . . . . . . . . . . . . .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 10 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.8 Switch Engine VLAN Command Regist er (SWE_VLAN_CMD)................ . ............... . ......
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 1 1 Revision 1.4 (0 8-19-08) DA T ASHEET 15.5.7 RX Data FIFO Direct PIO Burst Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 12 SMSC LAN931 1/LAN931 1i DA T ASHEET List of Figures Figure 2 .1 Internal L AN9311/LAN9 311i Block D iagram . . . . . . . . . . . . . . . . .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 13 Revision 1.4 (08-19-08) DA T ASHEET Figure 14.1 LAN93 11/LAN9311i Base Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 14 SMSC LAN931 1/LAN931 1i DA T ASHEET List of T ables Table 1.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 15 Revision 1.4 (08-19-08) DA T ASHEET Table 14.3 Switch Fabric CS R to SWITCH_CSR_DIRECT_D ATA Address Range Map . . . . . . . . . . . . 241 Table 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 16 SMSC LAN931 1/LAN931 1i DA T ASHEET Chapter 1 Preface 1.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 17 Revision 1.4 (08-19-08) DA T ASHEET MII Media Independent Interface MIIM Media Independent Interface Mana gement MIL MAC Interface Layer MLD Multicast Listening Discovery ML T -3 Multi-Level Transmission Encoding (3-Levels).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 18 SMSC LAN931 1/LAN931 1i DA T ASHEET 1.2 Buffer T ypes T able 1 .1 describes the pin buffer type notation used in Chapter 3, "Pin Description and Configu ration," on page 2 6 and throughout this document.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 19 Revision 1.4 (08-19-08) DA T ASHEET 1.3 Register Nomenclature T able 1 .2 describes the register bit attribute notation used throughout this document.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 20 SMSC LAN931 1/LAN931 1i DA T ASHEET Chapter 2 Introduction 2.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 21 SMSC LAN931 1/LAN931 1i DA T ASHEET 2.2 Block Diagram Figure 2.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 22 SMSC LAN931 1/LAN931 1i DA T ASHEET 2.2.1 System Clocks/R eset/PME Controller A clock module contained within t he LAN931 1/LAN931 1i generates a ll the system clocks required by the device.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 23 Revision 1.4 (08-19-08) DA T ASHEET General Purpos e Timer Software (general purpose) A dedicated programmable IRQ interrupt output pi n is provided for external indicatio n of any LAN931 1/LAN931 1i interrupts.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 24 SMSC LAN931 1/LAN931 1i DA T ASHEET System CSRs Access Interrupt Support 2.2.6 Host MAC The Host MAC incorporates the essential protocol requirements for operati ng an Ethern et/IEEE 802.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 25 Revision 1.4 (08-19-08) DA T ASHEET 2.2.9 GPIO/LED Controller The LAN931 1/LAN931 1i provides 12 con figurable general-pu rpose input/outpu t pins which are controlled via this module.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 26 SMSC LAN931 1/LAN931 1i DA T ASHEET Chapter 3 Pin Description and Configuration 3.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 27 Revision 1.4 (08-19-08) DA T ASHEET 3.1.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 28 SMSC LAN931 1/LAN931 1i DA T ASHEET 3.2 Pin Descriptions This section contains the descriptions of the LAN 931 1/LAN931 1i pins.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 29 Revision 1.4 (08-19-08) DA T ASHEET Note 3.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 30 SMSC LAN931 1/LAN931 1i DA T ASHEET 122,125 +3.3V Port 2 Analog Power Supply VDD33A2 P +3.3V Port 2 Analog Power Supply Refer to the LAN 931 1 /LAN931 1i applicatio n note for additional conne ction informatio n.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 31 Revision 1.4 (08-19-08) DA T ASHEET Note: Refer to Chapter 8, "Host Bus Interface (HBI)," on p age 99 for additional info rmation regarding the use of these signals.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 32 SMSC LAN931 1/LAN931 1i DA T ASHEET Note 3.3 The IS buffer type is valid only during the time specified in Section 15.5 .2, "Reset and Configuration S t rap T iming," on page 446 .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 33 Revision 1.4 (08-19-08) DA T ASHEET Note: For more information on conf iguration straps, refer to Section 4.2.4, "Configuration S traps," on page 40 .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 34 SMSC LAN931 1/LAN931 1i DA T ASHEET Note 3.7 The input buffers are enabled when configured as GPIO inputs only . 75 T est 1 TEST1 AI T est 1 : This pin must be tied to VDD33I O for proper operation.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 35 Revision 1.4 (08-19-08) DA T ASHEET Note 3.8 Plus external pad for 128-XVTQFP package only 18,48,80, 97,1 12,1 13, 128 Note 3.8 Common Ground VSS P Common Grou nd T able 3.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 36 SMSC LAN931 1/LAN931 1i DA T ASHEET Chapter 4 Clocking, Reset s, and Power Management 4.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 37 Revision 1.4 (08-19-08) DA T ASHEET Note 4.1 In the case of a soft reset, the EEPROM L oader is run, but loads only the MAC address into the Host MAC.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 38 SMSC LAN931 1/LAN931 1i DA T ASHEET A POR reset typically t akes approximately 23mS, plus additional time (91uS for I 2 C, 28uS for Microwire) per byte of da ta loaded from the EEPROM via the EEPR OM Loader .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 39 Revision 1.4 (08-19-08) DA T ASHEET 4.2.2.2 Sof t Reset (SRST) A soft reset is performed by setting the SRST bit of the Hardware Configuration Register (HW_CFG) .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 40 SMSC LAN931 1/LAN931 1i DA T ASHEET Note: When using the Reset bit to re set the Port 1 PHY , register bits designated as NASR are not reset.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 41 Revision 1.4 (08-19-08) DA T ASHEET T abl e 4.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 42 SMSC LAN931 1/LAN931 1i DA T ASHEET speed_strap_1 Port 1 Speed Select Strap: Configures the defa ult value for the S peed Select LSB (PHY_SPEED_SEL_LSB) bit in the PHY_BASIC_CTRL_1 register (See Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 43 Revision 1.4 (08-19-08) DA T ASHEET manual_FC_strap_1 Port 1 Manual Flow Control Enable .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 44 SMSC LAN931 1/LAN931 1i DA T ASHEET speed_strap_2 Port 2 Speed Select Strap: Configures the defa ult value for the S peed Select LSB (PHY_SPEED_SEL_LSB) bit in the PHY_BASIC_CTRL_2 register (See Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 45 Revision 1.4 (08-19-08) DA T ASHEET 4.2.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 46 SMSC LAN931 1/LAN931 1i DA T ASHEET 4.3 Power Management The LAN931 1/LAN931 1 i Port 1 and Port 2 PHYs an d the Host MAC support several powe r management and wakeup fea tures.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 47 Revision 1.4 (08-19-08) DA T ASHEET 4.3.1 Port 1 & 2 PHY Power Management The Port 1 & 2 PHYs provide independent gene ral power-down and e nergy-detect power-down modes which reduce PHY power consumption.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 48 SMSC LAN931 1/LAN931 1i DA T ASHEET The Port 1 & 2 PHY energy-detect events are capa.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 49 Revision 1.4 (08-19-08) DA T ASHEET Chapter 5 System Interrupt s 5.1 Functional Overview This chapter describes the sy stem interrupt structure of the LAN931 1/L AN931 1i.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 50 SMSC LAN931 1/LAN931 1i DA T ASHEET Figure 5.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 51 Revision 1.4 (08-19-08) DA T ASHEET The following sections detail each category of interrupts and their related registers.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 52 SMSC LAN931 1/LAN931 1i DA T ASHEET 5.2.3 Ethernet PHY Interrupts The Port 1 and Port 2 PHYs each provi de a set of identical i nterrupt sources.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 53 Revision 1.4 (08-19-08) DA T ASHEET TX S tatus FIFO Overflow Receive W atchdog T.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 54 SMSC LAN931 1/LAN931 1i DA T ASHEET 5.2.8 Sof tware Interrupt A general purpose software interrupt is provid ed in the top level Interrupt S tatus Register (INT_STS) and In terrupt Enable Register (INT_EN) .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 55 Revision 1.4 (08-19-08) DA T ASHEET Chapter 6 Switch Fabric 6.1 Functional Overview At the core of the LAN931 1/LAN931 1i is the high performance, hi gh efficiency 3 port Ethernet switch fabric.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 56 SMSC LAN931 1/LAN931 1i DA T ASHEET 6.2.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 57 Revision 1.4 (08-19-08) DA T ASHEET 6.2.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 58 SMSC LAN931 1/LAN931 1i DA T ASHEET 6.2.3 Flow Control Enable Logic Each switch fabric port (0,1,2) is provided wit h two flow control enable inputs per po rt, one for transmission and one for re ception.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 59 Revision 1.4 (08-19-08) DA T ASHEET register . When Auto-neg otiation is enabled and the MANUAL _FC_x bit is cleared, the switch port fl ow control enables during fu ll-duplex are determin ed by Auto-negotiation.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 60 SMSC LAN931 1/LAN931 1i DA T ASHEET Per Ta b l e 6 . 1 , the following cases are possible: Case 1 - Auto-negoti ation is still in progress.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 61 Revision 1.4 (08-19-08) DA T ASHEET "Flow Control Enable Logic," on page 58 . Pause frames are consumed by the MAC and not sent to the switch engine.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 62 SMSC LAN931 1/LAN931 1i DA T ASHEET 6.3.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 63 Revision 1.4 (08-19-08) DA T ASHEET T otal multicast packet s ( Section 14.5.2.37, on page 360 ) T otal packets with a late collision ( Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 64 SMSC LAN931 1/LAN931 1i DA T ASHEET 6.4.1.1 Learning/Aging/Migration The ALR adds new MAC addresses u pon ingress along with the associated receive po rt.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 65 Revision 1.4 (08-19-08) DA T ASHEET The following procedure sh ould be followed in order to add, d elete, and modify the ALR entri es: 1.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 66 SMSC LAN931 1/LAN931 1i DA T ASHEET 6.4.2 Forwarding Rules Upon ingress, packets are filtered or forwarded based on the follow ing rules: If the destination port equal s the source por t (local traffic), the packet is filtered.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 67 Revision 1.4 (08-19-08) DA T ASHEET 6.4.3 T ransmit Priori ty Queue Selection The transmit priority queu e may be selected from five option s.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 68 SMSC LAN931 1/LAN931 1i DA T ASHEET The transmit queue priority is based on the pa cket type and device configuration as shown in Figure 6.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 69 Revision 1.4 (08-19-08) DA T ASHEET 6.4.3.1 Port Default Priority As detailed in Figure 6.5 , the default priority is based on the in gr ess ports priority bits in its port VID value.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 70 SMSC LAN931 1/LAN931 1i DA T ASHEET 6.4.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 71 Revision 1.4 (08-19-08) DA T ASHEET 6.4.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 72 SMSC LAN931 1/LAN931 1i DA T ASHEET After each p acket is received, th e bucket is decremented. If the Co mmitted Burst bucket has sufficient tokens, it is debit ed and the packet is colored Green.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 73 Revision 1.4 (08-19-08) DA T ASHEET The ingress flow calculation is based on the packe t type and the devi ce configuration as shown in Figure 6.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 74 SMSC LAN931 1/LAN931 1i DA T ASHEET 6.4.7 Broadcast Storm Control In addition to ingress rate limiti ng, the LAN931 1/ LAN9 31 1i supports hardware broadcast storm control on a per port basis.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 75 Revision 1.4 (08-19-08) DA T ASHEET Normally , packets are never transmitted back to the receiving port.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 76 SMSC LAN931 1/LAN931 1i DA T ASHEET Note: When specifying Po rt 0 as the destination port, t he VID will be set to 0. A VID o f 0 is normally considered a priority tagged packet.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 77 Revision 1.4 (08-19-08) DA T ASHEET 6.5 Buffer Manager (BM) The buf fer manager (BM) provides control of the fr ee buf fer space, the multipl e priority transmit queues, transmission scheduling, and packet dropping.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 78 SMSC LAN931 1/LAN931 1i DA T ASHEET 6.5.4 T ransmit Priori ty Queue Servicing When a transmit queue is non-empty , it is serviced and the packet is read from the buffer RAM and sent to the transmit MAC.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 79 Revision 1.4 (08-19-08) DA T ASHEET 6.5.6 Adding, Removing, and Changing VLAN T ags Based on the port configuration and the received pa cket formation, a VLAN tag can be added to , removed from, or modified in a packet.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 80 SMSC LAN931 1/LAN931 1i DA T ASHEET Hybrid tagging is summarized in Figure 6.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 81 Revision 1.4 (08-19-08) DA T ASHEET 6.5.7 Counters A counter is maintained per port that contains the number of packets dropped due to buffer space limit s and ingress rate limit disca rding (Red and random Y ellow dropping).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 82 SMSC LAN931 1/LAN931 1i DA T ASHEET Chapter 7 Ethernet PHYs 7.1 Functional Overview The LAN931 1/LAN931 1i contains three PHYs: Port 1 PHY , Port 2 PHY and a Virtual PHY .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 83 Revision 1.4 (08-19-08) DA T ASHEET 7.2 Port 1 & 2 PHYs Functionally , each PHY can .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 84 SMSC LAN931 1/LAN931 1i DA T ASHEET 7.2.1 100BASE-TX T ransmit The 100BASE-TX transmit data p ath is shown in Figure 7.2 . Shaded blocks are those which are internal to the PHY .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 85 Revision 1.4 (08-19-08) DA T ASHEET T able 7.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 86 SMSC LAN931 1/LAN931 1i DA T ASHEET 7.2.1.3 Scrambler and PISO Repeated data patterns (especially the IDLE code-group) can have power spectral den sities with large narrow-band peaks.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 87 Revision 1.4 (08-19-08) DA T ASHEET 7.2.2 100BASE-TX Receive The 100BASE-TX rece ive data path is shown in Figure 7.3 . Shaded blocks are th ose whi ch are intern al to the PHY .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 88 SMSC LAN931 1/LAN931 1i DA T ASHEET 7.2.2.3 NRZI and ML T -3 Decoding The DSP generates t he ML T -3 reco vered levels that are fed to th e ML T -3 converter.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 89 Revision 1.4 (08-19-08) DA T ASHEET 7.2.3 10BASE-T T r ansmit Data to be transmitted comes fr om the switch fabric MAC. The 10BASE-T tr ansmitter receives 4-bit nibbles from the internal MII at a rate of 2.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 90 SMSC LAN931 1/LAN931 1i DA T ASHEET (PHY_SPECIAL_CONTROL_ST A T_IND_x) . The 10M PLL locks onto the received Manchester signal and generates the rece ived 20MHz clock from it.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 91 Revision 1.4 (08-19-08) DA T ASHEET 10M PLL (analog) 10M TX Driver (analog) Auto.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 92 SMSC LAN931 1/LAN931 1i DA T ASHEET 7.2.5.1 PHY Pause Flow Control The Port 1 & 2 PHYs are capable of generating and receiving pause flow control frame s per the IEEE 802.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 93 Revision 1.4 (08-19-08) DA T ASHEET 7.2.5.5 Half Vs. Full-Duplex Half-duplex o peration relies on the CSMA/CD (Carrier Sense Mul tiple Access / Collision Det ect) protocol to handle network t raf fic and collisions .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 94 SMSC LAN931 1/LAN931 1i DA T ASHEET For a transmissi on, the switch fabri c MAC drives the tr ansmit data onto the internal MII TXD bus and asserts TXEN to indicate va lid data.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 95 Revision 1.4 (08-19-08) DA T ASHEET Note: The power-down modes of each PHY ( Port 1 PHY and Port 2 PHY) are controlled independently . Note: The PHY power-down mod es do not reload or reset th e PHY registers.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 96 SMSC LAN931 1/LAN931 1i DA T ASHEET 7.2.10.2 PHY Software Reset via PHY_BASIC_CTRL_x The PHY can also be reset by s etting bit 15 (P HY_RST) of th e Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 97 Revision 1.4 (08-19-08) DA T ASHEET The emulated auto-ne gotiation process is much simpler than the rea l process and can be categorized into three step s: 1.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 98 SMSC LAN931 1/LAN931 1i DA T ASHEET (VPHY_BASIC_CTRL) . The speed and duplex bits in the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) should be ignored when auto-negotiatio n is enabled.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 99 Revision 1.4 (08-19-08) DA T ASHEET Chapter 8 Host Bus Interface (HBI) 8.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 100 SMSC LAN931 1/LAN931 1i DA T ASHEET 8.3.1 16-Bit Bus Writes The host is required t o perform two contiguous 16-b it writes to complete a single DWORD transfer .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 101 Revision 1.4 (08-19-08) DA T ASHEET . .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 102 SMSC LAN931 1/LAN931 1i DA T ASHEET 8.5 Host Interface Ti ming This section details the characteri stics and special restrictions of the various supported host cycles.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 103 Revision 1.4 (08-19-08) DA T ASHEET T able 8.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 104 SMSC LAN931 1/LAN931 1i DA T ASHEET 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_1 00 1588_SRC_UU.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 105 Revision 1.4 (08-19-08) DA T ASHEET 1588_CONFIG 45 1 1588_INT_STS_EN 45 1 MANUAL_FC_1 4.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 106 SMSC LAN931 1/LAN931 1i DA T ASHEET 8.5.3 Special Restrictions on Back-to-Back Read Cycles There are also re strictions on specifi c back-to-ba ck host read operations.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 107 Revision 1.4 (08-19-08) DA T ASHEET 8.5.4 PIO Reads PIO reads can be used to access Syst em CSR’s or RX Data and RX/TX St atus FIFOs. PI O reads can be performed using Chip Select (nCS) or Read Enable (nRD ).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 108 SMSC LAN931 1/LAN931 1i DA T ASHEET 8.5.5 PIO Burst Reads In this mode, performance is improved by allowi ng up to 16 WO RD read cycles back-to-back.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 109 Revision 1.4 (08-19-08) DA T ASHEET 8.5.6 RX Data FIFO Direct PIO Reads In this mode on ly A[2:1] are d ecoded, and any read of the L AN931 1 /LAN931 1i will read t he RX Data FIFO.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 1 10 SMSC LAN931 1/LAN931 1i DA T ASHEET 8.5.7 RX Data FIFO Direct PIO Burst Reads In this mode only A[2:1] are decoded, and any burst read of t he LAN931 1/ LAN931 1i will read the RX Data FIFO.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 1 1 1 Revision 1.4 (0 8-19-08) DA T ASHEET 8.5.8 PIO Writes PIO writes are used for all L AN931 1 /LAN931 1i write cycles. PIO writes ca n be performed usin g Chip Select (nCS) or Write Enable (nWR).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 1 12 SMSC LAN931 1/LAN931 1i DA T ASHEET 8.5.9 TX Dat a FIFO Direct PIO Writes In this mode only A[2:1] are decoded, and any write to the LAN931 1/LAN931 1i will write the TX Data FIFO.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 1 13 Revision 1.4 (08-19-08) DA T ASHEET Chapter 9 Host MAC 9.1 Functional Overview The Host MAC incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 1 14 SMSC LAN931 1/LAN931 1i DA T ASHEET 9.2 Flow Control The Host MAC supports full-duplex flow control using t he pause operation and control frame .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 1 15 Revision 1.4 (08-19-08) DA T ASHEET should be uniq ue. If both are set to t he same value, VLAN 1 is given higher p recedence and the maximum legal frame length is set to 1522.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 1 16 SMSC LAN931 1/LAN931 1i DA T ASHEET 9.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 1 17 Revision 1.4 (08-19-08) DA T ASHEET 9.4.4 Inverse Filtering In inverse filtering, the Host MAC packet filter a ccepts incoming frames (f rom switch Port 0) with a destination address n ot matching the perfect address (i.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 1 18 SMSC LAN931 1/LAN931 1i DA T ASHEET The Filter i Byte Mask defines which incoming frame byte s Filter i will examine to determine wh ether or not this is a wake-up frame.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 1 19 Revision 1.4 (08-19-08) DA T ASHEET The Filter i Offset register defin es the offset in the frame’s destinati on address field from which the frames are examined by Filt er i.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 120 SMSC LAN931 1/LAN931 1i DA T ASHEET Destination Address Source Ad dress …………….
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 121 Revision 1.4 (08-19-08) DA T ASHEET Note: By convention, the right nibb le of the left most byte of the Ethe rnet address (in this example, the 2 of the 12h) is t he most significa nt nibble and is tra nsmitted/received first.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 122 SMSC LAN931 1/LAN931 1i DA T ASHEET operation s, the MIL op erates in store-and- forward mode and will queue a n entire fra me before beginning transmi ssion.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 123 Revision 1.4 (08-19-08) DA T ASHEET 9.8 TX Dat a Path Operation Data is queue d for transmission by writing it into the TX Data FIFO. Each pa cket to be transmitted may be divided a mong multiple buf fers.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 124 SMSC LAN931 1/LAN931 1i DA T ASHEET The LAN931 1/LAN931 1i can b e programmed to stri p p a dding from the end of a transmit packet in the event that the end of the p acket does not align wit h the host burst boundary .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 125 Revision 1.4 (08-19-08) DA T ASHEET 9.8.1 TX Buffer Format TX buf fers exist in the host’s memory in a give n format. The host w rites a TX comma nd word into the TX data buffer before moving the Ethernet packet data.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 126 SMSC LAN931 1/LAN931 1i DA T ASHEET Both TX command ‘A ’ and TX command ‘B’ are r equired for each buffer in a given packet. TX command ‘B’ must be identical f or every buffer in a given packet.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 127 Revision 1.4 (08-19-08) DA T ASHEET 9.8.2.2 TX Command ‘B’ 9.8.3 TX Dat a Format The TX data section begins at the third DWORD in t he TX buffer (after TX command ‘A ’ and TX command ‘B’).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 128 SMSC LAN931 1/LAN931 1i DA T ASHEET DWORDs (2,036 byte s total).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 129 Revision 1.4 (08-19-08) DA T ASHEET 9.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 130 SMSC LAN931 1/LAN931 1i DA T ASHEET Figure 9.5 illustrates the TX command stru cture for this example, and al so shows how data is p assed to the TX Data FIFO.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 131 Revision 1.4 (08-19-08) DA T ASHEET 9.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 132 SMSC LAN931 1/LAN931 1i DA T ASHEET 9.8.7 T ransmitter Errors If the Transmitter Error (TXE) fla g is asserted for a ny reason, the tra nsmitter will con tinue operation.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 133 Revision 1.4 (08-19-08) DA T ASHEET 9.9 RX Dat a Path Operation When an Ethernet Packe t is received, the Host MAC In terface Layer (MIL) f irst begins to transfer the RX data.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 134 SMSC LAN931 1/LAN931 1i DA T ASHEET Figure 9.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 135 Revision 1.4 (08-19-08) DA T ASHEET 9.9.1.1 Receive Dat a FIFO Fast Forward The RX data p ath implements an automati c data discard function.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 136 SMSC LAN931 1/LAN931 1i DA T ASHEET 9.9.3 RX St atus Format Note: Though the Host MAC is communicating locally with t he switch fabric MAC, the events described in the RX St atus word may still occur .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 137 Revision 1.4 (08-19-08) DA T ASHEET 9.9.4 Stopping and S tarting the Receiver T o stop the recei ver , the host must clear th e RXEN bit in the Host MAC Control Register (HMAC_CR ) .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 138 SMSC LAN931 1/LAN931 1i DA T ASHEET Chapter 10 Serial Management 10.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 139 Revision 1.4 (08-19-08) DA T ASHEET 10.2.1 EEPROM Controller Operation I 2 C and Microwire master EEPROM opera tions are performed using the EEPROM Command Register (E2P_CMD) and EEPROM Data Register (E2P_DA T A) .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 140 SMSC LAN931 1/LAN931 1i DA T ASHEET Figure 10.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 141 Revision 1.4 (08-19-08) DA T ASHEET controller drives all the address bits as requeste d regardless of the actual size of the EEPROM. The supported size ranges for I 2 C op eration are shown in T able 10.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 142 SMSC LAN931 1/LAN931 1i DA T ASHEET Figure 10.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 143 Revision 1.4 (08-19-08) DA T ASHEET 10.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 144 SMSC LAN931 1/LAN931 1i DA T ASHEET Sequential reads are use d by the EEPROM Loader . Refer to Section 10.2.4, "EEPROM Loader" for additional info rmation.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 145 Revision 1.4 (08-19-08) DA T ASHEET 10.2.3 Microwire EEPROM Based on the configurat ion strap eeprom_type_ strap, various sized Microwire EEPROMs are supported.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 146 SMSC LAN931 1/LAN931 1i DA T ASHEET 10.2.3.2 ERASE (Erase Location) If erase/write operations are en abled in the EEPROM, th is command will erase the location selected by the EPC_ADDRESS field of the EEPROM Command Register (E2P_CMD) .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 147 Revision 1.4 (08-19-08) DA T ASHEET 10.2.3.3 ERAL (Erase All) If erase/write operat ions are enabled in the EEPROM, thi s comm and will initiate a bulk erase of the entire EEPROM.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 148 SMSC LAN931 1/LAN931 1i DA T ASHEET 10.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 149 Revision 1.4 (08-19-08) DA T ASHEET 10.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 150 SMSC LAN931 1/LAN931 1i DA T ASHEET 10.2.4 EEPROM Loader The EEPROM Loader i nterfaces to the I 2 C/Microwire EEPROM controller , the PHYs, and to the system CSRs (via the Register Access MUX).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 151 Revision 1.4 (08-19-08) DA T ASHEET Figure 10.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 152 SMSC LAN931 1/LAN931 1i DA T ASHEET 10.2.4.2 EEPROM V alid Flag Following the release of nRST , POR, DIGIT AL_ RST , or a RELOAD co mmand, the EEPROM Loader start s by reading the first byte of data from the EEPR OM.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 153 Revision 1.4 (08-19-08) DA T ASHEET The Port x PHY Auto-N egotiation Adve rtisement Register (PHY_AN_ADV_ x) is written with the new defaults as detailed in Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 154 SMSC LAN931 1/LAN931 1i DA T ASHEET 8-bits number_of_bursts repeat (number_of_bursts) 1.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 155 Revision 1.4 (08-19-08) DA T ASHEET Chapter 1 1 IEEE 1588 Hardware Time S t amp Unit 1 1.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 156 SMSC LAN931 1/LAN931 1i DA T ASHEET 1 1.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 157 Revision 1.4 (08-19-08) DA T ASHEET 1 1.2 IEEE 1588 T ime S t amp The LAN931 1/LAN931 1i contains three identical IEEE 1588 T ime S tamp blocks as sh own in Figure 1 1.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 158 SMSC LAN931 1/LAN931 1i DA T ASHEET Clock synchronization and hardware processing between the net work data and the time stamp capture hardware causes the time stamp point to be slight ly delayed .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 159 Revision 1.4 (08-19-08) DA T ASHEET 1 1.2.2 PTP Message Detection In order to p rovide the most flexibility , loose packe t type matching is used by the LAN931 1/LAN931 1i.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 160 SMSC LAN931 1/LAN931 1i DA T ASHEET 1 1.3 IEEE 1588 Clock The 64-bit IEEE 1588 clock is the time source for all IEEE 1588 related functions of the LAN931 1/LAN931 1i.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 161 Revision 1.4 (08-19-08) DA T ASHEET 1 1.4 IEEE 1588 Clock/Event s The IEEE 1588 Clock/Events block is re sponsible for ge nerating and controllin g all IEEE 1588 clock related events.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 162 SMSC LAN931 1/LAN931 1i DA T ASHEET Chapter 12 General Purpose T imer & Free-Running Clock This chapter details the LAN931 1/LAN931 1i General Purpose T imer (GPT) and the Free-R unning Clock.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 163 Revision 1.4 (08-19-08) DA T ASHEET Chapter 13 GPIO/LED Controller 13.1 Functional Overview The GPIO/LED Controller provides 12 configurabl e general pu rpose input/outpu t pins, GPIO[1 1:0].
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 164 SMSC LAN931 1/LAN931 1i DA T ASHEET 13.2.1 GPIO IEEE 1588 Timest amping T wo of the GPIO pins, GPIO[9:8], have the option to be used for IEEE 1588 time stamp functions.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 165 Revision 1.4 (08-19-08) DA T ASHEET GPIO_INT_POL[9:8] bits also determin e the polarity of the clock events as described in Section 13.2. 1.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 166 SMSC LAN931 1/LAN931 1i DA T ASHEET The various LED indica tion functio ns shown in T able 13.1 are describe d below: TX Port 0 - The signal is pulsed low for 80mS to indicate activity from the switch fabric to the Host MAC.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 167 Revision 1.4 (08-19-08) DA T ASHEET Chapter 14 Register Descriptions This section describes the various LAN931 1/LAN931 1i control and status registers (CSR’s).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 168 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.1 TX/RX FIFO Port s The LAN931 1/LAN931 1i contains four h ost-accessible FIFO’s: TX S tatus, RX S tatus, TX Data, and RX Data.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 169 Revision 1.4 (08-19-08) DA T ASHEET 14.2 System Contro l and S t atus Registers The System CSR’s are directly addressable memo ry mapped registers with a base address of fset range of 050h to 2DCh.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 170 SMSC LAN931 1/LAN931 1i DA T ASHEET 09Ch FREE_RUN Free Running Counter Register , Section 14.2.9.7 0A0h RX_DROP Host MAC RX Dropped Frames Counter Register , Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 171 Revision 1.4 (08-19-08) DA T ASHEET 13Ch 1588_SRC_UUID_ LO_TX_CAPTURE_2 Port 2 1588 Source UUID Low-DWORD Transmit Capture Register , Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 172 SMSC LAN931 1/LAN931 1i DA T ASHEET 1A0h MANUAL_FC_1 Port 1 Manual Flow Control Reg ister , Section 14.2.6.1 1A4h MANUAL_FC_2 Port 2 Manual Flow Control Reg ister , Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 173 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 174 SMSC LAN931 1/LAN931 1i DA T ASHEET Note 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 175 Revision 1.4 (08-19-08) DA T ASHEET 14.2.1.2 Interrupt St atus Register (IN T_STS) This register contains the current status of the generated interrupts.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 176 SMSC LAN931 1/LAN931 1i DA T ASHEET 19 GP Timer (GPT_INT) This interrupt is issued when t he General Purpose T imer Count Regi ster (GPT_CNT) wrap s past zero to FFFFh.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 177 Revision 1.4 (08-19-08) DA T ASHEET 4 RX St atus FIFO Full Interrupt (RSFF) This interrupt is genera ted when the RX S tatus FIFO is full.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 178 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.1.3 Interrupt Enable Regi ster (INT_EN) This register contains the interrupt enables fo r the IRQ output pin.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 179 Revision 1.4 (08-19-08) DA T ASHEET 5 RESERVED - This bit must be wri tten with 0b for proper operation.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 180 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.1.4 FIFO Level Interr upt Regi ster (FIFO_ INT) This read/write registe r configures the limits wh e re the RX/TX Data and S tatus FI FO’s will generate system interrupts.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 181 Revision 1.4 (08-19-08) DA T ASHEET 14.2.2 Host MAC & FIFO’ s This section details the Host MAC and TX/RX FIFO related System CSR’s.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 182 SMSC LAN931 1/LAN931 1i DA T ASHEET 14:13 RESERVED RO - 12:8 RX Data Of fset (RXDOFF) This field controls th e of fset value, in bytes, that is added to t he beginning of an RX data packet.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 183 Revision 1.4 (08-19-08) DA T ASHEET 14.2.2.2 T ransmit Configurat ion Register (T X_CFG) This register controls the Host MAC transmit functions.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 184 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.2.3 Receive Dat apath Control Register (RX_DP_CTRL) This register is used to discard unwanted receive fr ames.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 185 Revision 1.4 (08-19-08) DA T ASHEET 14.2.2.4 RX FIFO Information Register (RX_F IFO_INF) This register contains the indicat ion of used space in the RX F IFO’s.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 186 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.2.5 TX FIFO Information Register (TX_FIFO_INF) This register contains th e indication of free space in the TX Data FIFO and the used space in the TX S tatus FIFO.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 187 Revision 1.4 (08-19-08) DA T ASHEET 14.2.2.6 Host MAC RX Dropped Frames Counter Register (RX_DROP) This register indi cates the numb er of receive fr ames that have been dropped by the Host MAC.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 188 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.2.7 Host MAC CSR Interface Command Register (MAC_CSR_CMD) This read-write registe r is used to control the read and write operatio ns to/from the Host MAC.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 189 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 190 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 191 Revision 1.4 (08-19-08) DA T ASHEET 3 Flow Control on Multicast Frame (FCMUL T) When this bit is se t, the Host MAC wi ll assert back pres sure when the AFC level is reached and a multicast frame is received.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 192 SMSC LAN931 1/LAN931 1i DA T ASHEET 9h 300uS 302.2uS Ah 350uS 3 52.2uS Bh 400uS 4 02.2uS Ch 450uS 452.2uS Dh 500uS 502.2uS Eh 550uS 5 52.2uS Fh 600uS 602.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 193 Revision 1.4 (08-19-08) DA T ASHEET 14.2.3 GPIO/LED This section details the Ge neral Purpose I/O (GPIO) a nd LED related System CSR’s. 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 194 SMSC LAN931 1/LAN931 1i DA T ASHEET 11 : 0 GPIO Buffer T ype 1 1-0 (GPIOBUF[1 1:0]) This field sets the buffer types of th e 12 GPIO pins.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 195 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 196 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.3.3 General Purpose I/O Interrupt St atus and Enable Register (GPIO_INT_STS_ EN) This read/w rite register cont ains the GPIO interrupt st atus bits.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 197 Revision 1.4 (08-19-08) DA T ASHEET 14.2.3.4 LED Configuration Register (LED_CFG) This read/write regist er configures the GPIO[7: 0] pins as LED[7:0] pi ns and sets their functionality .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 198 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.4 EEPROM This section details the EEPROM re l ated System CSR’ s. These regist ers should only be us ed if an EEPROM has been connected to the LAN931 1/LAN931 1i.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 199 Revision 1.4 (08-19-08) DA T ASHEET 30:28 EEPROM Controller Co mmand (EPC_COMMAND) This field is used to issue comm ands to the EEPROM controller .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 200 SMSC LAN931 1/LAN931 1i DA T ASHEET 18 EEPROM Loader Address Over flow (LOADER_OVERFLOW) This bit indicates that the EEPROM Load er tried to read p a st the end of the EEPROM address space.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 201 Revision 1.4 (08-19-08) DA T ASHEET 14.2.4.2 EEPROM Data Register (E2P_DA T A) This read/write register is used in conjun ction with the EEPROM Command Register (E2P_CMD) to perform read and write operat ions with the serial EEPR OM.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 202 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 203 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 204 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 205 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 206 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 207 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 208 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 209 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 210 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 21 1 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 212 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 213 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 214 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.5.1 3 1 588 Clock High-DWORD Register (1 588_CLOCK_HI) This read/write regi ster combined with 1588 Clock Low-DWORD Reg ister (158 8_CLOCK_LO) form t he 64-bit 1588 Clock value.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 215 Revision 1.4 (08-19-08) DA T ASHEET 14.2.5.1 4 1 588 Clock Low -DWORD Register (1588_CLOCK_LO) This read/write regi ster combined with 1588 Clock High-DWORD Re gister (1588_CLOCK_HI) form the 64-bit 1588 Clock value.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 216 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.5.15 1588 Clock Addend Register (1588_CLOCK_ADDE ND) This read/write register is resp onsible for ad justing the 64-b it 1588 Clock frequency .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 217 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 218 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 219 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 220 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 221 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 222 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 223 Revision 1.4 (08-19-08) DA T ASHEET 14.2.5.22 1588 Configuration Regis ter (1588_CONFIG) This read/write regist er is responsible fo r the configurat ion of the 1588 timestamps for all ports.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 224 SMSC LAN931 1/LAN931 1i DA T ASHEET 22 Primary MAC Address Enable Por t 1 (MAC_PRI_EN_1) This bit enables/disab les the primary MAC address on Port 1 .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 225 Revision 1.4 (08-19-08) DA T ASHEET 13 Alternate MAC Address 1 Enab le Port 0(Host MA C) (MAC_AL T1 _EN_MII) This bit enables/ disables the alternate MAC address 1 on Port 0 .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 226 SMSC LAN931 1/LAN931 1i DA T ASHEET 5 Lock Enable GPIO 8 (LOCK_GPIO _8) This bit enable s/disables the GPI O 8 lock.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 227 Revision 1.4 (08-19-08) DA T ASHEET 14.2.5.2 3 1 588 Interrupt S tatu s and Enable Register (1588_INT_ STS_EN) This read/write register con tains the IEEE 1588 interrupt status and enable bits.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 228 SMSC LAN931 1/LAN931 1i DA T ASHEET 3 1588 Port 0(Host MAC) TX Interr upt (1588_MII_TX_.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 229 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 230 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.6 Switch Fabric This section details the memo ry mapped System CSR’s which are related to the Switch Fabric.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 231 Revision 1.4 (08-19-08) DA T ASHEET Note 14.4 The default value of th is field is determine d by the BP_ E N_st rap_1 configurat ion strap.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 232 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.6.2 Port 2 Manual Flow Control Register (MANUAL_FC_2) This read/writ e register allo ws for the manual config uration of the switch Port 2 f low control.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 233 Revision 1.4 (08-19-08) DA T ASHEET Note 14.8 The default value of th is field is determine d by the BP_ E N_st rap_2 configurat ion strap.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 234 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.6.3 Port 0(Host MAC ) Manual F l ow Control Regi ster (MANUAL_FC_MII) This read/write regist er allows f or the manual con figurat ion of th e swi tch Port 0 (H ost MAC) flo w control.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 235 Revision 1.4 (08-19-08) DA T ASHEET Note 14.12 The default valu e of this fiel d is determined by the BP_EN_strap_mii co nfiguration strap.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 236 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 237 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 238 SMSC LAN931 1/LAN931 1i DA T ASHEET 19:16 CSR Byte Enable (CSR_BE[3:0]) This field is a 4-b it byte enable used f or selection of valid byt es during write operations.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 239 Revision 1.4 (08-19-08) DA T ASHEET 14.2.6.6 Switch Fabric MAC Address High Register (SWITCH _MAC_ADDRH) This register contains the upper 16-bits of the MAC address used by the switch for Pause frames.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 240 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.6.7 Switch Fabric MAC Addres s Low Register (SWITCH_MAC _ADDRL) This register contains the lower 32-bits of the MA C address used b y the switch for Paus e frames.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 241 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 242 SMSC LAN931 1/LAN931 1i DA T ASHEET MAC_TX_CFG_2 0C40h 22Ch MAC_TX_FC_SETTINGS_2 0C41h .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 243 Revision 1.4 (08-19-08) DA T ASHEET BM_FC_RESUM E_L VL 1C03h 2A4h BM_BCST_L VL 1C04h 2A.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 244 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.7 PHY Management Interface (PMI) The PMI registers are used (by the EEPROM Lo ader only) to indirectly access the PHY regi sters.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 245 Revision 1.4 (08-19-08) DA T ASHEET 14.2.7.2 PHY Management Interf ace Access Regist er (PMI_ACCESS) This register is used to cont rol the management cycles to the PHYs.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 246 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.8 Virtual PHY This section det ails the Virtual PHY Syste m CSR’s. These registers p rovide status and control information similar to that of a real PHY while maintaining IEEE 802.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 247 Revision 1.4 (08-19-08) DA T ASHEET 14.2.8.1 Virtual PHY Basic Cont rol Register (VPHY_BASIC_CTRL) This read/write regist er is used to configure th e Virtual PHY .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 248 SMSC LAN931 1/LAN931 1i DA T ASHEET Note 14.16 The reserved bits 31-16 are used to pad the regist er to 32-bits so that each register is on a DWORD boundary .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 249 Revision 1.4 (08-19-08) DA T ASHEET 14.2.8.2 Virtu al PHY Basic St atus Register (VPHY_BASIC_ST A TUS) This register is used to monitor the status of the Virtual PHY .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 250 SMSC LAN931 1/LAN931 1i DA T ASHEET Note 14.17 The reserved bits 31-16 are used to pad the regist er to 32-bits so that each register is on a DWORD boundary .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 251 Revision 1.4 (08-19-08) DA T ASHEET 14.2.8.3 Virtual PH Y Identifica ti on MSB Register (VPHY_ID_MSB) This read/wri te register co ntains the MSB of the Virtual PHY Organizationall y Unique Identifier (OUI).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 252 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.8.4 Virtual PH Y Identifica ti on LSB Register (VPHY_ID_LSB) This read/write register cont ains the LSB of the V irtual PHY Organizationally Un ique Identifie r (OUI).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 253 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 254 SMSC LAN931 1/LAN931 1i DA T ASHEET Note 14.27 The reserved bits 31-16 are used to pad the regist er to 32-bits so that each register is on a DWORD boundary .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 255 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 256 SMSC LAN931 1/LAN931 1i DA T ASHEET Note 14.33 The reserved bits 31-16 are used to pad the regist er to 32-bits so that each register is on a DWORD boundary .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 257 Revision 1.4 (08-19-08) DA T ASHEET 14.2.8.7 Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP) This register is used in t he Auto-Negotiation process.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 258 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.8.8 Virtual PHY Special Control/St atu s Register (VPHY_SPECIAL_CONTROL_ST A TUS) This read/writ e register cont ains a current li nk speed/duplex in dicator and SQE control .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 259 Revision 1.4 (08-19-08) DA T ASHEET Note 14.42 The reserved bits 31-16 are used to pad the regist er to 32-bits so that each register is on a DWORD boundary .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 260 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 261 Revision 1.4 (08-19-08) DA T ASHEET 14.2.9.2 Byte Order T est Register (BYTE_TEST) This read-only regist er can be used to determine th e byte ordering of the current configuration .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 262 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 263 Revision 1.4 (08-19-08) DA T ASHEET Note 14.47 The default value of this f ield is determined by the configuratio n strap auto_mdix_strap_2.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 264 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.9.4 Power Management Control Register (PMT_ CTRL) This read-write register controls the power management features and the PME pin of the LAN931 1/LAN931 1i.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 265 Revision 1.4 (08-19-08) DA T ASHEET 9 W ake-On-LAN Enable (WOL_EN) When set, the PME signal (if enabl ed via the PME_EN bit) will be asserted in accordance with the PME_IND bit upon a WOL event.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 266 SMSC LAN931 1/LAN931 1i DA T ASHEET 0 Device R eady (READY) When set, this bi t indicates th at the LAN931 1/LAN 931 1i is rea dy to be accessed.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 267 Revision 1.4 (08-19-08) DA T ASHEET 14.2.9.5 General Purpose Timer Configura tion Register (GPT_CFG) This read/write register co nfigures the LAN931 1/LAN931 1i General Purpose Timer (GPT ).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 268 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.9.6 General Purpose T imer Count Register (GPT_CNT) This read-only register reflects the current general purpose timer (GPT) value.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 269 Revision 1.4 (08-19-08) DA T ASHEET 14.2.9.7 Free Running 25MHz Counter Register (FREE_RUN) This read-only register reflects the current value of the free-running 25MHz coun ter .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 270 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.2.9.8 Reset Control Register ( RESET_CTL) This register contains so ftware controlle d resets. Note: This register can be read while the LAN931 1/ LAN931 1i is in the reset or no t ready states.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 271 Revision 1.4 (08-19-08) DA T ASHEET 14.3 Host MAC Contro l and St atus Registers This section details the Host MA C Syst em CSR’s. These registers are locat ed in the Host MAC a nd are accessed indirectly via the HBI system CSR’s.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 272 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.3.1 Host MAC Control Register (HMAC_CR) This read/write re gister establishes the RX and TX op eration modes and con trols for address filt ering and pa cket filtering.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 273 Revision 1.4 (08-19-08) DA T ASHEET 16 Pass Bad Frames (P ASSBAD) When set, all inco ming frames that passed address filt ering are received, including runt frames and collided frames.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 274 SMSC LAN931 1/LAN931 1i DA T ASHEET 7:6 BackOff Limit (BOLMT) The BOLMT bits allow the user to set the back-off limit in a relaxe d or aggressive mode.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 275 Revision 1.4 (08-19-08) DA T ASHEET 14.3.2 Host MAC Address Hi gh Register (HMAC_ADDRH) This read/write regi ster contains the up per 16-bits of the physical address of the Ho st MAC.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 276 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.3.3 Host MAC Address Low Register (HMAC_ADDRL) This read/write register cont ains the lower 32-bits of the physical address of the Host MAC.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 277 Revision 1.4 (08-19-08) DA T ASHEET 14.3.4 Host MAC Multicast Hash T a ble High Register (HMAC_HASHH) The 64-bit Multicast table is used for group address fi ltering.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 278 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.3.5 Host MAC Multicast Hash T a ble Low Register (HMAC_HASHL) This read/write regist er defines the l ower 32-bits of the Mult icast Hash T able.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 279 Revision 1.4 (08-19-08) DA T ASHEET 14.3.6 Host MAC MII Access Register (HMAC_MII_ACC) This read/wri te regist er i s used in co njun ction w it h t he Host MAC MII Data Register (HMAC_MII_DA T A) to access the internal PHY registers.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 280 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.3.7 Host MAC MII Dat a Re gister (HMAC_MII_DA T A) This read/write regist er is used in conjun ction with the Host MAC MII Access Register (HMAC_MII_ACC) to access the internal PHY registers.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 281 Revision 1.4 (08-19-08) DA T ASHEET 14.3.8 Host MAC Flow Cont rol Register (HMAC_FLOW) This read/write re gister controls the generation and reception of the Control (Pause command) fr ames by the Host MAC’s flow control b lock.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 282 SMSC LAN931 1/LAN931 1i DA T ASHEET 0 Flow Control Busy (FCBSY) In full-duplex mod e, this bit should read logical 0 before writing to the Host MAC Flow Control (HMAC_FLOW) regist er .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 283 Revision 1.4 (08-19-08) DA T ASHEET 14.3.9 Host MAC VLAN1 T ag Register (HMAC_VLAN1) This read/write register contains the VLAN tag field to identify VLAN1 frames.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 284 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.3.10 Host MAC VLAN2 T ag Register (HMAC_VLAN2) This read/write register contains the VLAN tag field to identify VLAN2 frames.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 285 Revision 1.4 (08-19-08) DA T ASHEET 14.3.1 1 Host MAC W a ke-up Frame Filter Register (HMAC_WUFF) This write-only registe r is used to configure th e wake-up frame filter .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 286 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.3.12 Host MAC W ake-up Control a nd St atus Register (HMAC_WUCSR) This read/write regi ster contains data and control settings pertaining to the Host MAC’s remote wake- up status and capabilities.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 287 Revision 1.4 (08-19-08) DA T ASHEET 14.4 Ethernet PHY Cont rol and S t atus Registers This section de tails the vari ous LAN931 1/LAN931 1i Ethernet PHY control and st atus registers.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 288 SMSC LAN931 1/LAN931 1i DA T ASHEET 17 PHY_MODE_CONTROL_ST A TUS_x Port x PHY Mo de Control/St at us Register , Section 14.4. 2.8 18 PHY_SPECIAL_MODES_x Port x PHY S pecial Modes Register , Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 289 Revision 1.4 (08-19-08) DA T ASHEET 14.4.2.1 Port x PHY Basic Contro l Register (PHY_BASIC_CONTROL_x) This read/write register is used to configure th e Port x PHY .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 290 SMSC LAN931 1/LAN931 1i DA T ASHEET Note 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 291 Revision 1.4 (08-19-08) DA T ASHEET 14.4.2.2 Port x PHY Basic St atus Register (PHY_BASIC_ST A TUS_x) This register is used to monitor the status of the Port x PHY .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 292 SMSC LAN931 1/LAN931 1i DA T ASHEET Note 14.52 The PHY supports 100BASE-TX (half and full duplex) and 10BASE-T (half and full duplex) only .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 293 Revision 1.4 (08-19-08) DA T ASHEET 14.4.2.3 Port x PHY Identi ficati on M SB Register ( PHY_ID_MSB_x) This read/write register con t a ins the MSB of the Organizationally Uniq ue Identifier (OUI) for the Port x PHY .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 294 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.4.2.4 Port x PHY Identi ficati on LSB Register (PHY_ID_LSB_x) This read/wri te register co ntains the LSB of the Or ganizatio nally Unique Ident ifier (OUI) for the Port x PHY .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 295 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 296 SMSC LAN931 1/LAN931 1i DA T ASHEET Note 14.53 The Pause and Asymmetric Pause bits are loaded into th e PHY registers by the EEPROM Loader .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 297 Revision 1.4 (08-19-08) DA T ASHEET 11 1 T able 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 298 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 299 Revision 1.4 (08-19-08) DA T ASHEET Note 14.57 The Port 1 & 2 PHY’s support only IEEE 802.3. 6 10BASE-T Full Duplex This bit indicate s the link partner PHY 10BASE-T full duplex capability .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 300 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.4.2.7 Port x PHY Auto-Ne gotiation Exp ansion Register (PHY_AN_EXP_x) This read/write register is used in the Auto-Negot iation process between the link partner and the Port x PHY .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 301 Revision 1.4 (08-19-08) DA T ASHEET 14.4.2.8 Port x PHY Mode Control/ St atus Register (PHY_MODE_CONTROL_ST A TUS_x) This read/write regist er is used to control an d monitor various Port x PHY configurati on options.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 302 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.4.2.9 Port x PHY Special Mode s Register (PHY_SPECIAL_MODES_x) This read/write regist er is used to control t he special modes of the Port x PHY .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 303 Revision 1.4 (08-19-08) DA T ASHEET 01 1 100BASE-TX Full Dupl ex. Auto-negotiation disabled. CRS is active during Receive. 1001 N/A 100 100BASE-TX Half Duplex is adverti sed.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 304 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.4.2.10 Port x PHY Special Control/S tatus In dication Register (PHY_ SPECIAL_CONTROL_ST A T_IND_x) This read/write regist er is used to control vario us options of the Port x PH Y .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 305 Revision 1.4 (08-19-08) DA T ASHEET T able 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 306 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.4.2.1 1 Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_ x) This read-only register is used to det ermine to so urce of various Po rt x PHY interrupts.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 307 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 308 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.4.2.13 Port x PHY S p ecial Control/St atus Register (PHY_SPEC IAL_CONTROL_ST A TUS_x) This read/write regist er is used to control an d monitor various option s of the Port x PHY .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 309 Revision 1.4 (08-19-08) DA T ASHEET 14.5 Switch Fabric Cont rol and S t atus Registers This section details the variou s LAN931 1/LAN931 1i switch control and status registers th at reside within the switch fabric.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 310 SMSC LAN931 1/LAN931 1i DA T ASHEET 0414h MAC_RX_256_ TO_51 1_CNT_MII Port 0 MAC Receive 256 to 51 1 Byte Count Register, Section 14.5. 2.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 31 1 Revision 1.4 (08-19-08) DA T ASHEET 0455h MAC_TX_65_TO_127_ CNT_MII Port 0 MAC Tr ansmit 65 to 127 Byt e Count Register, Section 14.5. 2.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 312 SMSC LAN931 1/LAN931 1i DA T ASHEET 0812h MAC_RX_65_TO_127_CNT_1 Port 1 MAC Receive 65 to 127 Byt e Count Register, Section 14.5. 2.5 0813h MAC_RX_128_TO_255_CNT_1 Port 1 MAC Receive 128 to 255 Byte Count Register , Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 313 Revision 1.4 (08-19-08) DA T ASHEET 0852h MAC_TX_P AUSE_CNT_1 Port 1 MAC Transmit Pause Count Register , Secti on 14.5.2.26 0853h MAC_TX_PKTOK_CNT_1 Port 1 MAC Tr ansmit OK Count Register , Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 314 SMSC LAN931 1/LAN931 1i DA T ASHEET 0C10h MAC _RX_UNDSZE_CNT_2 Port 2 MAC Receive Undersize Co unt Register , Section 14.5. 2.3 0C1 1h MAC_RX_64_CNT_2 Po rt 2 MAC Receive 64 Byt e Count Register, Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 315 Revision 1.4 (08-19-08) DA T ASHEET 0C42h-0C50h RESERVED Rese rved for Future Use 0C51h MAC_TX_DEFER_CNT_2 Port 2 MAC Transmit Deferred Count Register , Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 316 SMSC LAN931 1/LAN931 1i DA T ASHEET Switch Engine CSRs 1800h SWE_ ALR_CMD Switch Engine ALR Command Register , Section 14.5.3.1 1801h SWE_ALR_WR_DA T_ 0 Switch Engin e ALR Write Data 0 Register , Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 317 Revision 1.4 (08-19-08) DA T ASHEET 1847h SWE_INGRESS _PORT_TYP Switch Engine Ingress Port T ype Register , Sectio n 14.5.3.22 1848h SWE_BCST_THROT Switch Engine Broadcast Throttling Register, Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 318 SMSC LAN931 1/LAN931 1i DA T ASHEET 1C02h BM_FC_P AUSE_L VL Buffe r Manager Flow C ontrol Pause Le vel Register , Section 14.5. 4.3 1C03h BM_FC_RESUME_L VL Buffer Manager Flow Co ntrol Resume Lev el Register , Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 319 Revision 1.4 (08-19-08) DA T ASHEET 1C20h BM_IMR Buffer Manager Interrupt Mask Register, Se ction 14.5.4.26 1C21h BM_IP R Buf fer Manager Interru pt Pending Register , Section 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 320 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.1 General Switch CSRs This section details the gen eral switch fabric CSRs. These registers control the main reset and interrupt fu nctions of th e switch fabric.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 321 Revision 1.4 (08-19-08) DA T ASHEET 14.5.1.2 Switch Reset Register (SW_RESET) This register contains the switch fabri c global reset. Refer to Section 4.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 322 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.1.3 Switch Global Interr upt Mask Register (SW_IMR) This read/write register co ntains the global interr upt mask for the switch fabric interrupt s.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 323 Revision 1.4 (08-19-08) DA T ASHEET 14.5.1.4 Switch Global Interr upt Pe nding Register (SW_IPR) This read-only register con tains the pending global interrup ts for the switch fabric.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 324 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2 Switch Port 0, Port 1, and Port 2 CSRs This section details the switch Port 0(Host MAC) , Port 1, and Port 2 CSRs.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 325 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.2 Port x MAC Receive Configuration Regis ter (MAC_RX_CFG_x) This read/write register con figures the packet type passing parameters of the port.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 326 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.3 Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x) This register provides a counter of undersize d packets received by the port.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 327 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.4 Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_ x) This register provides a count er of 64 byte packets received by the port.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 328 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.5 Port x MAC Receive 65 to 127 Byte Count Regis ter (MAC_RX_65_TO_127_ CNT_x) This register provides a counter of received packets between the size of 65 to 127 bytes.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 329 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.6 Port x MAC Receive 128 to 255 Byte Count Registe r (MAC_RX_128_T O_255_CNT_x) This register provides a counte r of received packets between the size of 128 to 255 bytes.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 330 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.7 Port x MAC Receive 256 to 51 1 Byte Count Register (MAC_RX_256_TO _51 1_CNT_x) This register provides a counter of received packets between the size of 25 6 to 51 1 bytes.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 331 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.8 Port x MAC Receive 512 to 1023 Byte Count Register (MAC _RX_512_T O_1023_CNT_x) This register pro vides a counter of recei ved packets between the size of 512 to 1023 bytes.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 332 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 333 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.10 Port x MAC Receive Oversize Count Register (M AC_RX_OVRSZ E_CNT_x) This register provides a counter of received packet s with a size greater than the maximum by te size.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 334 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.1 1 Port x MAC Receive OK Co unt Register (MAC_ RX_PKTOK_CNT_x) This register provides a counter of rece ived packets that are or proper length and are free of e rrors.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 335 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.12 Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x) This register provides a counter of received packets that with CRC erro rs.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 336 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.13 Port x MAC Receive Multicast Count Register (M AC_RX_MULCST_CNT_x) This register provides a counter of vali d received packets with a multicast destinatio n address.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 337 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.14 Port x MAC Receive Broadcast Count Register (M AC_RX_BRDCST_CNT_x) This register provides a counter of valid received packets with a broadcast destination address.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 338 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.15 Port x MAC Receive Pause Fram e Count Register (MAC_RX_P AUSE_CNT_x) This register provides a counter of vali d received pause frame packets.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 339 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.16 Port x MAC Receive Fragment Er ror Count Register (MAC_RX_FRAG _CNT_x) This register provides a cou nter of received packets of less than 64 bytes a nd a FCS error .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 340 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 341 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.18 Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x) This register provides a counter of received packets with 64 bytes to the maximum allowable , and a FCS error .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 342 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.19 Port x MAC Receive Packet Lengt h Count Register (M AC_RX_PKTLEN_CNT_x) This register provides a cou nter of total bytes received.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 343 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.20 Port x MAC Receive Good Packet Leng th Count Register (MAC _RX_GOODPKTLEN_CNT_x) This register p rovides a counter o f total bytes received in good p ackets.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 344 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.21 Port x MAC Receive Symbol Erro r Count Register (MAC_RX_SYMBOL_ CNT_x) This register prov ides a counter of received packe ts with a symbol error .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 345 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.22 Port x MAC Receive Control Fram e Count Register (MAC_RX_ CTLFRM_CNT_x) This register provides a co unter of good packets with a type fiel d of 8808h.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 346 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.23 Port x MAC T ransmit Conf iguration Register (MAC_TX_CFG_x) This read/write regist er configures the transmit packet parameters of the port.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 347 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.24 Port x MAC T ransmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x) This read/write regist er configures the flow con trol settings of the port .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 348 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.25 Port x MAC T ransmit Deferred Count Register (MAC_TX_ DEFER_CNT_x) This register provide s a counter deferred packets.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 349 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.26 Port x MAC T ransmit Pause Count Register (MAC_TX_P AUSE_CNT_x) This register provides a counter of transmit ted pause packets.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 350 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.27 Port x MAC T ransmit OK C ount Register (MAC_TX_PKT OK_CNT_x) This register provides a counter of successful transmissio ns.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 351 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.28 Port x MAC T ransmit 64 Byte Count Register (MAC_TX_64_CNT_x) This register provides a cou nter of 64 byte packe ts transmitted by t he port.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 352 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.29 Port x MAC T ransmit 65 to 127 By te Count Register (MAC_TX_65 _TO_127_ CNT_x) This register provide s a counter of transmitt ed packets between the size of 65 to 127 bytes.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 353 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.30 Port x MAC T ransmit 128 to 255 Byte Count Register (MAC_TX_128_T O_255_CNT_x) This register prov ides a counter of tra nsmitted packets between the size of 128 to 255 byte s.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 354 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.31 Port x MAC T ransmit 256 to 51 1 Byte Count Register (MAC_TX_256_T O_51 1_CNT_x) This register provides a counter of transmitted p a ckets bet ween the size of 256 to 5 1 1 bytes.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 355 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.32 Port x MAC T ransmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x) This register provides a counter of transmitted packets between the size of 512 to 1 023 bytes.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 356 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 357 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.34 Port x MAC T ransmit Undersiz e Count Regist er (MAC_TX_UNDSZE_CNT_x) This register provides a counter of u ndersized packe ts transmitted by the port.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 358 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.35 Port x MAC T ransmit Packet Leng th Count Register (MAC_TX_PKTLEN_CNT_x) This register provides a counter of total bytes transmitted.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 359 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.36 Port x MAC T ransmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x) This register provides a counter of transmit ted broadcast packets.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 360 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.37 Port x MAC T ransmit Multicast Count Register (MAC_T X_MULCST_CNT_x) This register provides a cou nter of transmitted mu lticast packets.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 361 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.38 P ort x MAC T r ansmit Late Collision Count Regi ster (MAC_ TX_LA TECOL_CNT_x ) This register provides a counter of transmitted pa ckets which experien ced a late collision.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 362 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.39 Port x MAC T ransmit Excessive Coll ision Co unt Regi ster (MAC_TX_EX CCOL_CNT_x) This register provides a counter of transmitted packets which experienced 16 co llisions.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 363 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.40 Port x MAC T ransmit Single Collisi on Count Register (MAC_TX_SNGLECOL_CNT_x) This register provides a counter of transmitted packets which ex perienced exactly 1 collision.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 364 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.4 1 Port x MAC T ransmit Multiple Colli sion Count Regis ter (MAC_TX_MUL TICOL_CNT_x) This register provides a counter of tran smitted pa ckets which experienced between 2 a nd 15 collision s.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 365 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.42 Port x MAC T ransmit T ot al Collis ion Count Register (MAC_TX_TOT ALCOL_CNT_x) This register provides a counter of total collisions including late collisi ons.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 366 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.2.43 Port x MAC Interrupt Mask Register (MAC_IMR_x) This register contains the Port x interru pt mask.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 367 Revision 1.4 (08-19-08) DA T ASHEET 14.5.2.44 Port x MAC Interrupt Pending Register (MAC_IPR_x) This read-only registe r cont ains the pendi ng Port x interrupts.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 368 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 369 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 370 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 371 Revision 1.4 (08-19-08) DA T ASHEET 18:16 Port These bits indicate the p ort(s) associated with this MAC address. When bit 18 is cleared, a single port i s selected.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 372 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.4 Switch Engine ALR Read Da t a 0 Register (SWE_ALR_RD_DA T_0) This register is used i n conjunction with the Switch Engine ALR Read Data 1 Reg ister (SWE_ALR_RD_DA T_1) to read the ALR table.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 373 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.5 Switch Engine ALR Read Da t a 1 Register (SWE_ALR_RD_DA T_1) This register is used i n conjunction with the Switch Engine ALR Read Data 0 Reg ister (SWE_ALR_RD_DA T_0) to read the ALR table.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 374 SMSC LAN931 1/LAN931 1i DA T ASHEET 18:16 Port These bits indicate the p ort(s) associated with this MAC address. When bit 18 is cleared, a single port i s selected.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 375 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.6 Switch Engine ALR Command S ta tus Register (SWE_ALR_CMD_STS) This register indica tes the current ALR command status.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 376 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.7 Switch Engine ALR Config uration Register (SWE_ALR_CFG) This register contro ls the ALR aging timer durat ion.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 377 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.8 Switch Engine VLAN Command Register (SWE_VLAN_CMD) This register is used to read and writ e the VLAN or Port VID tables.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 378 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.9 Switch Engine VLAN W rite Data Register (SWE_VLAN_WR_DA T A) This register is used writ e the VLAN or Port VID tables.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 379 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.10 Switch Engine VLAN Read Dat a Register (SWE_VLAN_RD_DA T A ) This register is used to read the VLAN or Port VID tables.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 380 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.1 1 Switch Engine VLAN Command St atus Register (SWE_VLAN_CMD_STS) This register indica tes the current VLAN command status.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 381 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.12 Switch Engine DIFFSERV T able Command Register (SWE_DIFFSERV_T BL_CFG) This register is used t o read and write the DIFFSERV table.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 382 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.13 Switch Engine DIFFSERV T able Writ e Dat a Register (SWE_DIFFSERV_TBL_WR_DA T A) This register is used to write th e DIFFSERV table.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 383 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.14 Switch Engine DIFFSERV T able Read Dat a Register (SWE_DIFFSERV_TBL_RD_DA T A) This register is used to read the DIFF SERV t able.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 384 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.15 Switch Engine DIFFSER V T able Command St atus Register (SWE_DIFFSER V_TBL_CMD_STS) This register indi cates the current D IFFSERV command status.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 385 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.16 Switch Engine Global Ingress Conf iguration Register (SWE_GLOBAL_ INGRSS_CFG) This register is used to configure the globa l ingress rules.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 386 SMSC LAN931 1/LAN931 1i DA T ASHEET 1 VL Higher Priority When this bit is set and VLANs are enabled, the priority fr om the VLAN tag has higher priority than the IP TOS/SC fie ld.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 387 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.17 Switch Engine Port Ingress Conf iguration Register (SWE_PORT_INGRSS_CFG ) This register is used to configure the per po rt ingress rules.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 388 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.18 Switch Engine Admit Only VLAN Register (SWE_ADMT_ONL Y_VLAN) This register is used to configure the per po rt ingress rule for all owing only VLAN tagged packets.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 389 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.19 Switch Engine Port St ate Register (SWE_PORT_ST A TE) This register is used to configure the p er port spanning tree state.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 390 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.2 0 Switch Engine Pr iority to Queue Register (SWE_PRI_TO_QU E) This register specifies the T raffic Class table that maps the packet priority into the egress queues.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 391 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.21 Switch Engine Port Mi rroring Register (SWE_PORT_MIRROR) This register is used to configure port mirroring.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 392 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 393 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.23 Switch Engine Broadcast Thr ottling Regi ster (SWE_B CST_THROT ) This register configure s the broadcast input rat e throttling.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 394 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.24 Switch Engine Admit Non Member Register (SWE_ADMT_N_MEMBER) This register is used to allow access to a VLAN even if t he ingress port is not a member .
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 395 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 396 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.26 Switch Engine Ingress Rate Co m mand Register (SWE_INGRSS_RA TE_C MD) This register is used to indirectly read and write t he ingress rate metering/color table registe rs.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 397 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 398 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.27 Switch Engine Ingres s Rate Command St atus Register (SWE_INGRSS_RA TE_CMD_STS) This register indica tes the current ingress rat e command status.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 399 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.28 Switch Engine Ingress Rate Write Dat a Register (SWE_INGRSS _RA TE_WR_DA T A) This register is used to write the ingress rate table registers.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 400 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.29 Switch Engine Ingress Rate Re ad Dat a Register (SWE_INGRSS_RA TE_RD_DA T A) This register is used to read the ingress rate table regi sters.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 401 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.30 Switch Engine Port 0 Ingress Filt ered Count Register (SWE_FIL TERED_CNT_MII) This register counts the number of packets filtered at ingress on Port 0(Host MAC).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 402 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.3.31 Switch Engine Port 1 Ingress Filt ered Count Register (SWE_FIL TERED_CNT_1) This register counts the number of packets filtered at ingress on Port 1.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 403 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.32 Switch Engine Port 2 Ingress Filt ered Count Register (SWE_FIL TERED_CNT_2) This register counts the number of packets filtered at ingress on Port 2.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 404 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 405 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 406 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 407 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 408 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 409 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 410 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 41 1 Revision 1.4 (08-19-08) DA T ASHEET 14.5.3.40 Switch Engine Interr upt Pending Register (SWE_ IPR) This register contains the Switch Engine int errupt status.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 412 SMSC LAN931 1/LAN931 1i DA T ASHEET 10:9 Source Port B When bit 8 is set, these bits indicate the source po rt on which the packet was dropped.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 413 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4 Buffer Manager CSRs This section details the Buffer Manager (BM) regi sters. These registers allow conf iguration and monitoring of the switch buffe r levels and usage.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 414 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.4.2 Buff er Manager Drop Level Register ( BM_DROP_L VL) This register configure s the overall buffer usage limits.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 415 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.3 Buffer Manager Flow Control Pause Leve l Register (BM_FC_P AUSE_L VL) This register configure s the buffer usage level when a Pause f rame or backpressure is sent.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 416 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.4.4 Buffer Manager Flow Control Re s ume Level Register (BM_FC_RESUME_L VL) This register configure s the buffer usage level when a Pa use frame with a pause value of 1 is sent.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 417 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.5 Buffer Manager Broadcast Bu ffer Level Register (BM_BCST_L VL) This register configure s the buffer usage limits for broadcasts, multicasts, and unknown unicasts.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 418 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.4.6 Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_MII) This register counts the number of packets dropped by the Buffer Manager that were received on Port 0(Host MAC).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 419 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.7 Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1) This register counts the number of packets dropped by the Buffer Manager that were received on Port 1.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 420 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.4.8 Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2) This register counts the number of packets dropped by the Buffer Manager that were received on Port 2.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 421 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.9 Buffer Manager Reset S ta tus Register (BM_RST_STS) This register indica tes when the Buffer Manager has be en initialized by the reset process.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 422 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.4.10 Buffer Manager Random Discard T abl e Command Register (BM_RNDM_DSCRD_TBL_CMD) This register is used to read and write the Random Discard Weight table.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 423 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.1 1 Buffer Manager Random Discard T able Write Data Register (BM_RNDM_DSCRD_TBL_WDA T A) This register is used to write the Random Discard Weight table.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 424 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.4.12 Buffer Manager Random Discard T able Re ad Data Register (BM_RNDM_DSCRD_TBL_RDA T A) This register is used to read the Random Di scard Weight table.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 425 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.1 3 Buffer Manager Egress Port T ype Register (BM_EGRSS_PORT_TYPE ) This register is used to configur e the egress VLAN tagging rules.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 426 SMSC LAN931 1/LAN931 1i DA T ASHEET 17:16 Egress Port T ype Port 2 These bits set the egress po rt type which det ermines the tagging/un-tagging rules.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 427 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 428 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 429 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 430 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 431 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 432 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 433 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.20 Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_M II) This register is used to specify the default VLAN ID and priority of Port 0(Ho st MAC).
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 434 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.4.21 Buffer Manager Port 1 Default VLAN ID and Priority Registe r (BM_VLAN_1) This register is used to specify the default VLAN ID and priority of Port 1.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 435 Revision 1.4 (08-19-08) DA T ASHEET 14.5.4.22 Buffer Manager Port 2 Default VLAN ID and Priority Registe r (BM_VLAN_2) This register is used to specify the default VLAN ID and priority of Port 2.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 436 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 437 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 438 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 439 Revision 1.4 (08-19-08) DA T ASHEET 14.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 440 SMSC LAN931 1/LAN931 1i DA T ASHEET 14.5.4.2 7 Buffer Manager Int err upt Pending Register (BM_IPR) This register contains the Buffer Manager interrupt status.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 441 Revision 1.4 (08-19-08) DA T ASHEET 6:3 Drop Reason A When bit 0 is set, th ese bits indicate the reaso n a packet was dropped. See the Drop Reason B description above for definit ions of each value of th is field.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 442 SMSC LAN931 1/LAN931 1i DA T ASHEET Chapter 15 Operational Characteristics 15.1 Absolute Maximum Ratings* Supply V oltage (VDD33A1 , VDD33A2, VDD33BIAS, VDD33IO) ( Note 15.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 443 Revision 1.4 (08-19-08) DA T ASHEET 15.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 444 SMSC LAN931 1/LAN931 1i DA T ASHEET 15.4 DC Specifications Note 15.6 This specification applies to all IS type inputs and tri-stated bi-direct ional pins.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 445 Revision 1.4 (08-19-08) DA T ASHEET Note 15.8 Measured at line side of transfo rmer , li ne replaced by 100 Ω (+/- 1%) resistor . Note 15.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 446 SMSC LAN931 1/LAN931 1i DA T ASHEET 15.5.2 Reset and Configuration Strap T iming This diagram illustrates the nRST pin timing req uirements and its relation to the configuration strap pins and output d rive.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 447 Revision 1.4 (08-19-08) DA T ASHEET 15.5.3 Power-On Configurat ion Strap V alid Timing This diagram ill ustrates the configura tion strap valid timing requirements in relation to powe r-on.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 448 SMSC LAN931 1/LAN931 1i DA T ASHEET 15.5.4 PIO Read Cycle Timing Please refer to Section 8.5.4, "PIO Reads, " on page 1 07 for a functiona l description o f this mode.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 449 Revision 1.4 (08-19-08) DA T ASHEET 15.5.5 PIO Burst Re ad Cycle Timing Please refer to Section 8.5.5, "PIO Burst Reads, " on page 108 for a functional description of this mode.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 450 SMSC LAN931 1/LAN931 1i DA T ASHEET 15.5.6 RX Data FIFO Direct PIO Read Cycle T iming Please refer to Section 8.5.6, "RX Da ta FIFO Direct PIO Reads," on page 1 09 for a functional description of this mode.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 451 Revision 1.4 (08-19-08) DA T ASHEET 15.5.7 RX Dat a FIFO Direct PIO Burst Read Cycle Timing Please refer to Section 8.5.7, "RX Data FIFO Direct PIO Burst Reads," on page 1 10 for a funct ional description of this mode.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 452 SMSC LAN931 1/LAN931 1i DA T ASHEET 15.5.8 PIO Write Cycle T iming Please refer to Section 8.5.8, "PIO Writes," on page 1 1 1 for a functional description o f this mode.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 453 Revision 1.4 (08-19-08) DA T ASHEET 15.5.9 TX Dat a FIFO Direct PIO Write Cycle T iming Please refer to Section 8.5.9, "TX Data FIFO Direct PIO Writes," on page 1 12 for a functional description of this mode.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 454 SMSC LAN931 1/LAN931 1i DA T ASHEET 15.5.10 Microwire T iming This section specifies the Microwire EEPROM in terface timing requirements. Please refer to Se ctio n 10.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 455 Revision 1.4 (08-19-08) DA T ASHEET 15.6 Clock Circuit The LAN931 1/LAN931 1i can accept eit her a 25MHz cryst al (preferred) or a 25MHz sin gle-ended clock oscillator (+/- 50ppm) input.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 456 SMSC LAN931 1/LAN931 1i DA T ASHEET Chapter 16 Package Outlines 16.1 128-VTQFP Package Outline Figure 16.1 LAN931 1 128-VTQFP Packag e Definition T able 16.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 457 Revision 1.4 (08-19-08) DA T ASHEET Notes: 1. All dimensions are in milli meters unless otherwise noted. 2. Dimensions b & c apply to the flat section of the l ead foot between 0.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 458 SMSC LAN931 1/LAN931 1i DA T ASHEET 16.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN931 1/LAN931 1i 459 Revision 1.4 (08-19-08) DA T ASHEET Notes: 1. All dimensions are in milli meters unless otherwise noted. 2. Dimensions b & c apply to the flat section of the l ead foot between 0.
T wo Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.4 (08-19-08) 460 SMSC LAN931 1/LAN931 1i DA T ASHEET Chapter 17 Revision History T able 17.1 Customer Revision History REVISION LEVEL & DATE SECTI ON/FIGURE/ENTRY CORRECTION Rev .
Ein wichtiger Punkt beim Kauf des Geräts SMSC LAN9311i (oder sogar vor seinem Kauf) ist das durchlesen seiner Bedienungsanleitung. Dies sollten wir wegen ein paar einfacher Gründe machen:
Wenn Sie SMSC LAN9311i noch nicht gekauft haben, ist jetzt ein guter Moment, um sich mit den grundliegenden Daten des Produkts bekannt zu machen. Schauen Sie zuerst die ersten Seiten der Anleitung durch, die Sie oben finden. Dort finden Sie die wichtigsten technischen Daten für SMSC LAN9311i - auf diese Weise prüfen Sie, ob das Gerät Ihren Wünschen entspricht. Wenn Sie tiefer in die Benutzeranleitung von SMSC LAN9311i reinschauen, lernen Sie alle zugänglichen Produktfunktionen kennen, sowie erhalten Informationen über die Nutzung. Die Informationen, die Sie über SMSC LAN9311i erhalten, werden Ihnen bestimmt bei der Kaufentscheidung helfen.
Wenn Sie aber schon SMSC LAN9311i besitzen, und noch keine Gelegenheit dazu hatten, die Bedienungsanleitung zu lesen, sollten Sie es aufgrund der oben beschriebenen Gründe machen. Sie erfahren dann, ob Sie die zugänglichen Funktionen richtig genutzt haben, aber auch, ob Sie keine Fehler begangen haben, die den Nutzungszeitraum von SMSC LAN9311i verkürzen könnten.
Jedoch ist die eine der wichtigsten Rollen, die eine Bedienungsanleitung für den Nutzer spielt, die Hilfe bei der Lösung von Problemen mit SMSC LAN9311i. Sie finden dort fast immer Troubleshooting, also die am häufigsten auftauchenden Störungen und Mängel bei SMSC LAN9311i gemeinsam mit Hinweisen bezüglich der Arten ihrer Lösung. Sogar wenn es Ihnen nicht gelingen sollte das Problem alleine zu bewältigen, die Anleitung zeigt Ihnen die weitere Vorgehensweise – den Kontakt zur Kundenberatung oder dem naheliegenden Service.
