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SMSC LAN91C1 1 1 REV C DA T ASHEET Revision 1.91 ( 08-18-08) Datasheet PRODUCT FEA TURES LAN91C1 1 1 10/100 Non-PCI Ethernet Single Chip MAC + PHY Single Chip Ethernet C ontroller Dual S pe ed.
ORDER NUMBERS: LAN91C1 1 1-NC, LAN91C1 1 1i-NC (INDUSTRIAL T EMPERATURE) FOR 128-PIN QFP PACKAGES L A N 91 C 111 - N S , L A N 9 1 C 111 i - N S (INDUSTRIAL T EMPERATURE) FOR 128-PIN QFP LEAD-FREE ROHS COMPLIANT PACKAGES LAN91C1 1 1-NE (1.0MM HEIGHT); LAN91C 1 1 1i-N E (INDUSTRIAL T EMPERATU RE) FOR 128-PIN TQFP PACKAGES LAN91C1 1 1-NU (1.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 3 Revision 1.91 (0 8-18-08) DA T A SHEET T able of Content s Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 4 SMSC LAN91C1 1 1 REV C DA T A SHEET 8.4 Bank Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 5 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Chapter 16 Revision History .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 6 SMSC LAN91C1 1 1 REV C DA T A SHEET List of Figures Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 7 Revision 1.91 (0 8-18-08) DA T A SHEET List of T ables Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP an d 1.0mm TQFP package) . . . . . . . . . . . . . . 14 Table 7.1 4B/5B Sy mbol Mapping .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 8 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 1 General Description The SMSC LAN91C1 1 1 is design ed to facilitate the imple mentation of a third generation of Fast Ethernet connectivity solutions for embedded appl ic ations.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 9 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 2 Pin Configurations Figure 2.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 10 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 2.2 Pin Configuration - LAN91 C1 1 1-FEAST 128 PIN QFP 1 2 3 4 5 6 7 8 9 .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 1 1 Revision 1.91 (08-18-08) DA T A SHEET Chapter 3 Block Diagrams The diagram sho wn in Figure 3.1, "Basic Functional Bl ock Diagram", describe s the device basic functional blocks.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 12 SMSC LAN91C1 1 1 REV C DA T A SHEET The diagram shown in Figure 3.2 describes the su pported Host i nterfaces, which i nclude ISA or Generic Embedded.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 13 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 3.3 LAN91C1 1 1 Physica l Layer to Internal M AC Block Diagram C O L L I.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 14 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 4 Signal Descriptions Table 4.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 15 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 5 Description of Pin Functions PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION TQFP QFP 81-92 83-94 Address A4-A15 I** Input. Decoded by LAN91C1 1 1 to determine access to its registers.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 16 SMSC LAN91C1 1 1 REV C DA T A SHEET 42 44 Local Bus Clock LCLK I** Input. Used to interface synchro nous buses. Maximum frequency is 50 MHz. Limited to 8.33 MHz for EISA DMA burst mode.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 17 Revision 1.91 (0 8-18-08) DA T A SHEET 9 1 1 EEPROM Clock EESK O4 Output. 4 μ sec clock used to shift data in and out of the serial EEPROM. 10 12 EEPROM Select EECS O4 Output.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 18 SMSC LAN91C1 1 1 REV C DA T A SHEET Note 5.1 If the EEPROM is enabled. 125 127 Rec eive Data Va l i d RX_DV I with pulldown Input from MII PHY . Envelope of data valid reception.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 19 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 6 Signal Description Parameters This section provides a detailed description of each SMSC LAN91C1 1 1 signal. The si gnals are arranged in functional groups according to their associated function.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 20 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 7 Functional Description 7.1 Clock Generator Block 1. The XT AL 1 and XT AL 2 pins are to be connected to a 25 MHz crystal.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 21 Revision 1.91 (0 8-18-08) DA T A SHEET 7.4 BIU Block The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are used for each one.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 22 SMSC LAN91C1 1 1 REV C DA T A SHEET The MAC and external PHY communicate via MDIO a nd MDC of the MII Management serial interface. MDIO:Management Data input/output. Bi-directi onal between MAC and PHY that carries management data.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 23 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 7.1 MI Serial Port Frame Timing Diagram M D I O M D C 0 2 1 3 4 7 6 5 8 .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 24 SMSC LAN91C1 1 1 REV C DA T A SHEET 7.5.4 MII Packet Data Communi cation with External PHY The MIl is a nibble wide packet data interface defin ed in IEEE 80 2.3. The LAN91C1 1 1 meets all the MIl requirements outlined in IEEE 802.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 25 Revision 1.91 (0 8-18-08) DA T A SHEET edges. RXD0 carries the l east signifi cant bit an d RX D3 the most significant bit of the nibble. RX_DV goes inactive when the la st valid nibble of the packet (CRC) is presente d at RXD0-RXD3.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 26 SMSC LAN91C1 1 1 REV C DA T A SHEET On the transmit side for 100 Mbps TX operation, data is received on the controll er and then se nt to the 4B5B encoder for formatting .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 27 Revision 1.91 (0 8-18-08) DA T A SHEET 10Mbps operation is similar to the 100Mbp s TX operation except , (1) there is .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 28 SMSC LAN91C1 1 1 REV C DA T A SHEET * These 5B cod es are not used. For decod er , these 5B codes are decode d to 4B 0000. For encod er , 4B 0000 is encoded to 5B 1 1 1 10, as shown in symbol D ata 0.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 29 Revision 1.91 (0 8-18-08) DA T A SHEET 7.7.4 Clock and Data Recovery Clock Reco very - 100 Mbp s Clock recovery is done wi th a PL L. If there i s no vali d data present on the T P inputs, the PLL is locked to the 25 MHz TX25.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 30 SMSC LAN91C1 1 1 REV C DA T A SHEET If 25 consecutive descrambled idle pattern 1's are not detected within th e 1ms interval, the descrambler goes out of synchronization and restarts the synchronization process.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 31 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 7.4 TP Output V oltage T emplate - 10 MBPS REFERENCE TIME (NS) INTERNAL MAU VOL T AGE (V) A0 0 B1 5 1 . 0 C1 5 0 . 4 D2 5 0 .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 32 SMSC LAN91C1 1 1 REV C DA T A SHEET T ransmit Leve l Adjust The transmit output current level is de rived from an internal referen ce voltage and the external resistor on RBIAS pin.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 33 Revision 1.91 (0 8-18-08) DA T A SHEET STP (150 Ohm) Cable Mode The transmitter can be configured to drive 150 Ohm sh ielded twisted pair cable.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 34 SMSC LAN91C1 1 1 REV C DA T A SHEET TP Squelch - 100 Mbps The squelch block determines if the TP input contai ns valid data. The 100 Mbps TP squelch is one of the criteria used to determine l ink integri ty .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 35 Revision 1.91 (0 8-18-08) DA T A SHEET Equalizer Disable The adaptive equalizer can be disabl ed b y setting the equal izer disable bit in th e PHY Ml serial port Configuration 1 re gister .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 36 SMSC LAN91C1 1 1 REV C DA T A SHEET SSD) is signaled to the control ler interface. W hen False Carrier i s detect ed, the MAC is notified of false carrier and invalid received, and the bad SSD bit is set in the PHY Ml serial port S tatus Output register .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 37 Revision 1.91 (0 8-18-08) DA T A SHEET 7.7.12 Link Integrity & AutoNegotiation General The LAN91C1 1 1 can be configu red to implement ei th er the standard lin k integrity algori thms or the AutoNegotia tion algori thm.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 38 SMSC LAN91C1 1 1 REV C DA T A SHEET 100BASE-TX Link Integr ity Algorithm -100Mb p s Since 100BASE-TX is defined to have an active idle signal, then there is no need to have separate link pulses like those define d for 10BASE-T .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 39 Revision 1.91 (0 8-18-08) DA T A SHEET The AutoNegotiation algorithm is initiated by any of these events: (1 ) AutoNegotiation enabled, (2) a device enters the Link Fail S tate, (3) AutoNegotiatio n Reset.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 40 SMSC LAN91C1 1 1 REV C DA T A SHEET device halts all transmissi ons including link pul ses fo r 1200-1500 ms, en ters the Link F ail S tate, and restarts the negotiation process.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 41 Revision 1.91 (0 8-18-08) DA T A SHEET Autopolarity Disable The autopolarity feature can be disabl ed by setting the autopolari ty disable bit in the PHY MI serial port Configuration 2 register .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 42 SMSC LAN91C1 1 1 REV C DA T A SHEET R/L T bits are also interrupt bits if they are not masked out with the Mask register bits. Interrupt bits automatically latch themselves into their register location s and assert the interrupt indication when they change state.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 43 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 8 MAC Dat a Structures and Registers 8.1 Frame Format In Buffer Memory The frame format in memory is similar for the T ransmi t and Receive areas.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 44 SMSC LAN91C1 1 1 REV C DA T A SHEET The receive byte coun t always appears as even ; the ODDFRM bit of the recei ve status word indicates if the low byte of the last word is relevant.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 45 Revision 1.91 (0 8-18-08) DA T A SHEET BROADCAST - Receive frame was br oadcast. When a broad cast packet is received, the MUL TCAST bit may be also set on the status word in addition to the BRODCAST bit.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 46 SMSC LAN91C1 1 1 REV C DA T A SHEET Regardless of the functional descriptio n, all register s can be accessed as dou blewords, words or bytes. The default bit values u pon hard reset are hi ghlighted below ea ch register .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 47 Revision 1.91 (0 8-18-08) DA T A SHEET Bank 7 is a new register Bank to the SMSC LAN9 1C1 1 1 device. Thi s bank has extended registers that allow the extended feature se t of the SMSC LAN91C1 1 1.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 48 SMSC LAN91C1 1 1 REV C DA T A SHEET FORCOL - When set, the FORCOL bit will force a collisio n by not deferring delib erately . This bit is set and cleared only by the CPU.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 49 Revision 1.91 (0 8-18-08) DA T A SHEET SQET - Signal Quality Error T est. This bit is set und er the following conditions: 1. LAN91C1 1 1 is set to operate in Hal f Duplex mode (SWFDUP=0); 2.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 50 SMSC LAN91C1 1 1 REV C DA T A SHEET ABORT_ENB - Enables abort of recei ve when collisi on occurs. Defaults low . Wh en set, the LAN91C1 1 1 wil l automatically abort a packet being recei ved when the appropri ate collision input is activated.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 51 Revision 1.91 (0 8-18-08) DA T A SHEET 8.9 Bank 0 - Memory Information Register FREE MEMORY A V AILABLE - This register can be rea d at any time to determine the amount of free memory .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 52 SMSC LAN91C1 1 1 REV C DA T A SHEET Register) and de termine the duple x mode. When this bit is set (1), the Internal PHY w ill operate at full duplex mode. When this bit is clea red (0), the Intern al PHY will operate at half Dup lex mode.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 53 Revision 1.91 (0 8-18-08) DA T A SHEET LS2A, LS1A, LS0A – LED select Signal Enable. Thes e bits define what LED control signal s are routed to the LEDA output pin on the LAN91C1 1 1 Etherne t Controller .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 54 SMSC LAN91C1 1 1 REV C DA T A SHEET Reserved – Must be 0. 8.1 1 Bank 1 - Configuration Register The Configuration Register holds b its that define the adapter c onfiguration and are not expected to change during run-time.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 55 Revision 1.91 (0 8-18-08) DA T A SHEET 8.12 Bank 1 - Base Address Register This register holds the I/O address decode option chosen for th e LAN91 C1 1 1 . It is part of the EEPROM saved setup and is not usua lly modified during run-time.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 56 SMSC LAN91C1 1 1 REV C DA T A SHEET 8.14 Bank 1 - Genera l Purpose Register This register can be used as a way of storing a nd retrieving non-vo latile informat ion in the EEPROM to be used by the software driver .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 57 Revision 1.91 (0 8-18-08) DA T A SHEET 8.15 Bank 1 - Control Register RCV_BAD - When set, bad CRC packet s are re ceived. When clear bad CRC packets do not generate interrupts and their me mory is released.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 58 SMSC LAN91C1 1 1 REV C DA T A SHEET 8.16 Bank 2 - MMU Command Register This register is used by the CPU to control the memory allocation, de-a llocation, TX FIFO and RX FIFO control.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 59 Revision 1.91 (0 8-18-08) DA T A SHEET Note: When using the RESET TX FIFOS command, the CP U is responsible for releasi ng the memory associated with outstanding packets, or re-enqueuing them.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 60 SMSC LAN91C1 1 1 REV C DA T A SHEET This register is updated u pon an ALLOCA TE MEMORY MMU command. F AILED - A zero indicates a successful allocation completion. If the allocatio n fails the bit is set and only cleared when the pending allocation is satisfied.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 61 Revision 1.91 (0 8-18-08) DA T A SHEET TEMPTY - No transmit p ackets in completion queu e. For polling purposes, uses the TX_INT bit in the Interrupt S tatus Register . TX FIFO P ACKET NUMBER - Packet number presently at the output of the TX FIFO.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 62 SMSC LAN91C1 1 1 REV C DA T A SHEET 8.20 Bank 2 - Dat a Register DA T A REGISTER - Used to read or write the data bu ffer byte/word presently addressed by the pointer register .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 63 Revision 1.91 (0 8-18-08) DA T A SHEET This register can be read and written as a word o r as two individual bytes. The Interrupt Mask Register bits enable the appropri ate b its when high and disable them when lo w .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 64 SMSC LAN91C1 1 1 REV C DA T A SHEET LA TC OL - Late Collision 16COL - 16 collisions Any of the above interrupt so urces can be masked by the appropria te ENABLE bits in the Control Register .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 65 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 8.2 Interrupt St r ucture TX FI FO EMPT Y DQ S nQ IntAck1 DQ S nQ IntAck.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 66 SMSC LAN91C1 1 1 REV C DA T A SHEET 8.22 Bank 3 - Multicast T able Registers The 64 bit multicast table is used for group address filtering. The ha sh value is defined as the six most significant bits of the CRC of the destination addresses.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 67 Revision 1.91 (0 8-18-08) DA T A SHEET 8.23 Bank 3 - Management Interface MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode (SWFDUP=0). MDO - MII Management output.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 68 SMSC LAN91C1 1 1 REV C DA T A SHEET 8.25 Bank 3 - RCV Register RCV DISCRD - Set to discard a packet being received. Wi ll discard packets only in the process of being received.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 69 Revision 1.91 (0 8-18-08) DA T A SHEET CYCLE NCSOUT LAN91C1 1 1 DA T A BUS AEN=0 A3=0 A4-15 matches I/O BASE BANK SEL ECT = 7 Driven low . Transp arently latched on nADS rising edge.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 70 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 9 PHY MII Registers Multiple Register Acces s Multiple registers can be accessed on a single PHY Ml serial port access cycle with the multiple register access features.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 71 Revision 1.91 (0 8-18-08) DA T A SHEET PHY Register Description D[15:0] ↓ Register 0 Control Register 1 S tatus Regi.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 72 SMSC LAN91C1 1 1 REV C DA T A SHEET REGAD[4:0] Register Address If REGAD[4:0] = 00000-1 1 1 1 0, thes e bi ts determine the specific register from which D[15:0] is read/writte n.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 73 Revision 1.91 (0 8-18-08) DA T A SHEET T able 9.2 MII Serial Port Register MAP R/LT R/LT R R R/LT R/LT R R 0 1 R/LT R/LT R/LT R/LT R R/LT R/LT R/LT 0 0 00 00 0 00 00 0 0 x.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 74 SMSC LAN91C1 1 1 REV C DA T A SHEET 9.1 Register 0. Control Register RST - Reset A ‘1’ written to this bit will initiate a reset of the PHY . The bit is self-clearing, and the PHY wil l return a ‘1’ on reads to this bit until the reset is completed.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 75 Revision 1.91 (0 8-18-08) DA T A SHEET DPLX - Duplex mode When Auto Negotiation is disab led this bit can be used to manually select the link duplex state. Writing a ‘1’ to this bit selects full duplex while a ‘0’ selects half duplex.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 76 SMSC LAN91C1 1 1 REV C DA T A SHEET REM_FL T - Remote Fault Detect ‘1’ indicate s a Remote Fault. Latches the ‘1’ cond ition and is cl eared by reading this register or resetting the PHY .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 77 Revision 1.91 (0 8-18-08) DA T A SHEET NP - Next Page A ‘1’ indicates the PHY wishes to exchang e Next Page informati on.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 78 SMSC LAN91C1 1 1 REV C DA T A SHEET 9.6 Register 16. Config uration 1 - S tructur e and Bit Definition LNKDIS X MTDI.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 79 Revision 1.91 (0 8-18-08) DA T A SHEET 9.7 Register 17. Config uration 2 - Structure and Bit Definition Select 0 = Rec.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 80 SMSC LAN91C1 1 1 REV C DA T A SHEET 9.8 Register 18. S tatu s Output - S tructur e and Bit Definition 0 = No Multipl.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 81 Revision 1.91 (0 8-18-08) DA T A SHEET 9.9 Register 19. Mask - St ructure and Bit Definition SSD: S tart Of S tream Er.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 82 SMSC LAN91C1 1 1 REV C DA T A SHEET 9.10 Register 20. Reserved - Structure and Bit Definition MLNKF AIL: Interrupt M.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 83 Revision 1.91 (0 8-18-08) DA T A SHEET Reserv ed: Reserved for Factory Use Reserved Reserved Reserved Reserved Re serv.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 84 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 10 Sof tware Driver and Hardware Sequence Flow 10.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 85 Revision 1.91 (0 8-18-08) DA T A SHEET 10.2 T ypical Flow of Event s fo r T ransmit (Auto Release = 0) T able 10.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 86 SMSC LAN91C1 1 1 REV C DA T A SHEET 10.3 T ypical Flow of Event s fo r T ransmit (Auto Release = 1) 6 Upon transmit completion the first word in memory is written with the status word.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 87 Revision 1.91 (0 8-18-08) DA T A SHEET 10.4 T ypical Flow of Event For Receive 7 The MAC generates a TXEMPTY interrupt upon a completion of a sequence of e nqueued packets.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 88 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 10.1 Interrupt Service Routine ISR Save Bank Select & A ddress Ptr Re.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 89 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 10.2 RX INTR RX INTR W rite Ad.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 90 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 10.3 TX INTR TX Interrupt With AUTO_RELEASE = FALSE 1. S ave the P acket Num ber Regi ster Saved _PNR = R ead By te (Bank 2, Offset 2) 2.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 91 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 10.4 TXEMPTY INTR (Assumes Auto Re lease Optio n Selected) TXEM PTY INT R Write Ac knowledge Reg.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 92 SMSC LAN91C1 1 1 REV C DA T A SHEET MEMOR Y P ARTITIONING Unlike other controllers, the LAN91C1 1 1 does not r equire a fixed memory partitioning betwee n transmit and receive resources.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 93 Revision 1.91 (0 8-18-08) DA T A SHEET multicast packet s that might not be for the node, and that ar e not subject to upper la yer software flow control.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 94 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 10.6 Interrupt Generation for T ransmit, Receive, MMU T X F I F O T X C O.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 95 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 1 1 Board Setup Information The following parameter s ar e obtained fro.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 96 SMSC LAN91C1 1 1 REV C DA T A SHEET STORE and RELOAD bits of CTR will readback as both bits high. No o ther bits of the L AN91C111 can be read or written until the EEPROM operatio n complete s and both bits are clear.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 97 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 1 1.1 64 X 16 Serial EEPROM Map CONFI G UR A TION REG. BASE REG. CONFI G UR A TION REG. BASE REG. CONFI G UR A TION REG. BASE REG.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 98 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 12 Application Considerations The LAN91C1 1 1 is envisioned to fit a few differ ent bus types.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 99 Revision 1.91 (0 8-18-08) DA T A SHEET D0-D31 D0-D31 32 bit data bus. The bus byte(s) used to access the device are a function of nBE0-nBE3: Not used = tri-state on reads, ignored on writes.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 100 SMSC LAN91C1 1 1 REV C DA T A SHEET HIGH-END ISA OR NON- BURST EISA MACHINES On ISA machines, the LAN91C1 1 1 is accessed as a 16 bit perip heral. T he sign al connection s a re listed in the following table: Figure 12.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 101 Revision 1.91 (0 8-18-08) DA T A SHEET nIOWR nWR I/O Write strobe - asynchronous write access. Address is valid before leading edge. D ata is latched on traili ng edge.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 102 SMSC LAN91C1 1 1 REV C DA T A SHEET EISA 32 BIT SLA VE On EISA the LAN91C1 1 1 is accessed as a 32 bit I/O slave, along with a Slave DMA type "C" data path option.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 103 Revision 1.91 (0 8-18-08) DA T A SHEET Latched W-R combined with nCMD nRD I/O Read strobe - asynchronous re ad accesses. Address is valid before its leading edge. Must not be active during DMA bursts if DMA is supported.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 104 SMSC LAN91C1 1 1 REV C DA T A SHEET GND A1 Figure 12.3 LAN91C1 11 on EISA BUS T able 12.3 EISA 32 Bit Slave Signal Connection s (continued) EISA BUS SIGNAL LAN91C1 1 1 SIGNAL NOTES A2-A15 RESET AEN INT R0 nRD nW R LCLK nADS nLDEV LA N91C111 LA2- LA15 RESET O.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 105 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 13 Operational Description 13.1 Maximum Guar anteed Ratings* *S tresse s above those listed above co uld cause permanent d amage to the device.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 106 SMSC LAN91C1 1 1 REV C DA T A SHEET Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Inp.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 107 Revision 1.91 (0 8-18-08) DA T A SHEET CAP ACIT ANCE T A = 25 ° C; fc = 1MHz; V CC = 3.3V CAP ACITIVE LOAD ON OUTPUTS I/O24 T ype Buffer Low Output Level High Output Level Output Leakage V OL V OH I OL 2.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 108 SMSC LAN91C1 1 1 REV C DA T A SHEET 13.3 T wisted Pair Char acteristics, T ransmit V DD = 3.3v +/- 5% RBIAS = 1 1K +/- 1 %, no load SYM P ARAMETER LIMI T UNIT CONDITIONS MIN TYP MAX T ov TP Differential Output Vo l t a g e 0.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 109 Revision 1.91 (0 8-18-08) DA T A SHEET 13.4 T wisted Pair Char acteristics, Receive Unless otherwise noted, a ll test conditions are as fol lows: Vcc = 3.3V +/-5% RBIAS = 1 1 K +/- 1 %, no load 62.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 1 10 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 14 T iming Diagrams Figure 14.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 1 1 1 Revision 1.91 (08-18-08) DA T A SHEET Figure 14.2 Asynchronous Cycl e - Using nADS P ARAMETER MIN TYP MAX UNITS t1 .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 1 12 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 14.3 Asynchronous Cycle - nADS=0 P ARAMETER MIN TYP MAX UNITS t1A nDA T.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 1 13 Revision 1.91 (0 8-18-08) DA T A SHEET P ARAMETER MIN TYP MAX UNITS t26 ARDY Low Pulse Width 100 1 50 ns t26A Con trol Active to ARDY Lo w 10 ns t13 V alid Data to ARDY High 10 ns Figure 14.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 1 14 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 14.6 Burst Read Cycles - nVLBUS=1 P ARAMETER MIN TYP MAX UNITS t12 nDA .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 1 15 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 14.7 Address Latching for All Modes P ARAMETER MIN TYP MAX UNITS t8 A1-A15, AEN, nBE[3:0 ] Setup to nADS Rising 8 ns t9 A1-A15, AEN, nBE[3:0 ] Hold After nADS Rising 5 ns t25 A4-A15, AEN to nLDEV Delay 30 ns Figure 14.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 1 16 SMSC LAN91C1 1 1 REV C DA T A SHEET P ARAMETER MIN TYP MAX UNITS t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 n.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 1 17 Revision 1.91 (0 8-18-08) DA T A SHEET P ARAMETER MIN TYP MAX UNITS t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 1 18 SMSC LAN91C1 1 1 REV C DA T A SHEET AC TEST TIMING CONDITI ONS Unless otherwise noted, a ll test conditions are as fol lows: 1. V DD = 3.3V +/-5% 2. RBIAS = 1 1 K +/- 1%, no load 3.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 1 19 Revision 1.91 (0 8-18-08) DA T A SHEET T ab le 14.2 Receive Timing Characteristics SYM P ARAMETER LIMIT UNIT CONDITIONS MIN TYP MAX t36 Receive Input Jitte r ±3.0 nS p k-pk 100Mbps ±13.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 120 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 14.13 Collision Timing, Receive t 34 LEDn t 35 t 34 t 35 LEDn TPI± I TP.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 121 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 14.14 Collision Timing, T ransmit t 34 t 35 t 34 t 35 LEDn LEDn TPO± I.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 122 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 14.15 Jam Timing t 41 t 40 MII 100 Mbps MII 10 Mbps TPI± TPO± II DATA .
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 123 Revision 1.91 (0 8-18-08) DA T A SHEET T able 14.4 Link Pulse Ti ming Characteristics SYM P ARAMETER LIMIT UNIT CONDITIONS MIN TYP MAX t42 N LP T ransmit Li nk Pulse Width See F igure 7.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 124 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 14.16 Link Pulse T iming TPO± t 42 a.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 125 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 14.17 FLP Link Pulse Timing TPO± t 48 a.) Transmit FLP and Transmit FLP Burst t 49 TPI± t 52 b.) Receive FLP t 54 TPI± CLK DATA CLK DATA DATA CLK CLK t 51 CLK DATA DATA CLK t 53 31.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 126 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 15 Package Outlines Notes: 1. Controlling Unit: millime ter 2. T oler ance on the position of the leads is ± 0.035 mm maximum 3.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 127 Revision 1.91 (0 8-18-08) DA T A SHEET Notes: 1. Controlling Unit: millime ter 2. T oler ance on the position of the leads is + 0.04 mm maximum. 3. Package body dimensions D1 and E1 do not inclu de the mold protrusion.
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 128 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 16 Revision History T able 16.1 Customer Revision History REVISION LEVEL & DATE SECTI ON/FIGURE/ENTRY CORRECTION Rev .
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Wenn Sie SMSC LAN91C111 noch nicht gekauft haben, ist jetzt ein guter Moment, um sich mit den grundliegenden Daten des Produkts bekannt zu machen. Schauen Sie zuerst die ersten Seiten der Anleitung durch, die Sie oben finden. Dort finden Sie die wichtigsten technischen Daten für SMSC LAN91C111 - auf diese Weise prüfen Sie, ob das Gerät Ihren Wünschen entspricht. Wenn Sie tiefer in die Benutzeranleitung von SMSC LAN91C111 reinschauen, lernen Sie alle zugänglichen Produktfunktionen kennen, sowie erhalten Informationen über die Nutzung. Die Informationen, die Sie über SMSC LAN91C111 erhalten, werden Ihnen bestimmt bei der Kaufentscheidung helfen.
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Jedoch ist die eine der wichtigsten Rollen, die eine Bedienungsanleitung für den Nutzer spielt, die Hilfe bei der Lösung von Problemen mit SMSC LAN91C111. Sie finden dort fast immer Troubleshooting, also die am häufigsten auftauchenden Störungen und Mängel bei SMSC LAN91C111 gemeinsam mit Hinweisen bezüglich der Arten ihrer Lösung. Sogar wenn es Ihnen nicht gelingen sollte das Problem alleine zu bewältigen, die Anleitung zeigt Ihnen die weitere Vorgehensweise – den Kontakt zur Kundenberatung oder dem naheliegenden Service.
