Benutzeranleitung / Produktwartung LAN1198 des Produzenten SMSC
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SMSC AN 12.12 APPLICA TION NOTE Revision 1.0 (12-14-09) AN 12.12 LAN91 18 Family Programmer Reference Guide 1 Introduction This application no te describes how to successfully develop a network device dr iver for LAN91 18 Family products.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 2 SMSC AN 12.12 APPLICA TION NOTE An octet or byte is a group of 8 bits, treated as a single unit, with a value of 0-255 unsigned, or - 127 to +127 signed. A byte is genera lly the smallest unit of data that can be individually ad dressed.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 3 Revision 1.0 (12-14-09) APPLICA TION NOTE 2.1.2 System Level Block Diagram Figure 2.2 LAN91 18 Family Devi ce System-Level Blo ck-Diagram 2.2 Common Product Family Features Single chip Ethernet contro ller Fully compliant with I EEE 802.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 4 SMSC AN 12.12 APPLICA TION NOTE High-Performance ho st bus interface Simple SRAM-like interface Large, 16Kbyte FIFO memory with.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 5 Revision 1.0 (12-14-09) APPLICA TION NOTE 3 Register Description Refer to the LAN91 18 Family datasheets for complete descriptions of the Con.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 6 SMSC AN 12.12 APPLICA TION NOTE 3.1 Directly Addressable Registers These registers are also referre d to as “Slave Registers”.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 7 Revision 1.0 (12-14-09) APPLICA TION NOTE 3.2 MAC Control and St atus Registers The registers listed below are accessed indire ctly thro ugh the MAC_CSR_CMD and MAC_CSR_DA T A Registers. These registers are used in Section 5.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 8 SMSC AN 12.12 APPLICA TION NOTE 3.4 Restrictions on Read -Follow-W rite CSR Accesses There are timing restrictions on successive operat ions to some CSRs.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 9 Revision 1.0 (12-14-09) APPLICA TION NOTE 3.5 Restrictions on Re ad-Follow-Read CSR Accesses There are also restrictions on certain CSR read operations following other read operations. These restrictions arise when a read oper ation has a side-effect that affect s another read operation.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 10 SMSC AN 12.12 APPLICA TION NOTE 4 Programming Recommendations The fundamental operations of the driver are initialization, transmit packet processing, receive packet processing, and inte rrupt processing.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 1 1 Revision 1.0 (12-14-09) APPLICA TION NOTE 4.4 Register Functionality in the LAN91 18 Family Devices T able 4.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 12 SMSC AN 12.12 APPLICA TION NOTE 4.5 An Example of Concurrency The need of maintaining the ind ependence of th e transmit an d receive packet processing functions has already b een mentioned.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 13 Revision 1.0 (12-14-09) APPLICA TION NOTE The first example works because of th e assumption th at only one thre ad will ever write to the flag and signal the SwInt. The SwInt handl er can use the flag to interpret th e requested operation.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 14 SMSC AN 12.12 APPLICA TION NOTE TX_FIFO_INF Read Only . Used in TX thread, in Tx_GetTxS tatusCount, Tx_SendSkb, and Tx_CompleteTx .
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 15 Revision 1.0 (12-14-09) APPLICA TION NOTE 5 Initialization 5.1 MAC Initialization The ID_REV register is a good starting point from which to.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 16 SMSC AN 12.12 APPLICA TION NOTE Besides the MAC address, no other values are automatically loaded to the controller from EEPROM in a reload cycle.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 17 Revision 1.0 (12-14-09) APPLICA TION NOTE has the bits corresponding with the inte rrupts to be ena bled set to “1”. T o disable specific inte rrupts, AND the contents with a bit-mask which has the bits correspond ing to the interru pts to be disabled set to “0”.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 18 SMSC AN 12.12 APPLICA TION NOTE 5.5 Configuring Addr ess Filtering Options T able 5.2, "Address Filtering Modes" shows the relations betwee n the control flags which affect the address filter mode.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 19 Revision 1.0 (12-14-09) APPLICA TION NOTE 5.6 PHY Detection and Initialization Applications commonly delegate link set-u p to the physical media device (PHY).
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 20 SMSC AN 12.12 APPLICA TION NOTE has completed, or else spurious o per ations could result. Setti ng of the CSR Address , R/nW and CSR busy bits can all be do ne with a single write command to the MAC_C SR_CMD Register .
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 21 Revision 1.0 (12-14-09) APPLICA TION NOTE Figure 5.1 PHY Access Command and Data Pathways The driver can verify the existence of the internal PHY by reading the PHY R egisters 2 and 3 at PHY Address 1 and ensuring the contents are 0x0007 and 0xc0 c1 respecti vely .
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 22 SMSC AN 12.12 APPLICA TION NOTE Basic Control Register (index 0) and comple tes when the Auto-negotiate Complete bit (5) is set in the Ba sic St atus Reg ister (index 1). Auto-negotiate Complete status should be available within 1.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 23 Revision 1.0 (12-14-09) APPLICA TION NOTE Figure 5.2 The MII Switching Pr ocedure 1. Both the internal PHY and the exte rnal PHY must be placed in a stable state. The TX_CLK and RX_CLKs of both devices must be stable and glit ch-free before the switch can be made.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 24 SMSC AN 12.12 APPLICA TION NOTE 4. The PHY_CLK_SE L field must be set to 10b. This action will disable the MII clocks from the internal and external PHYs to the controller ’s internal logic.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 25 Revision 1.0 (12-14-09) APPLICA TION NOTE Step Three: Keep reading the MAC_CSR_CMD Regi ster until the CSR Busy Bit =0. Load the MII write command word (MII W/nR == 1) th at is to be written to the MII ACC register into the MAC_CSR_Data register .
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 26 SMSC AN 12.12 APPLICA TION NOTE Step s Thre e - Seven: 3. Read the MAC_CSR_CMD Register until the CSR Busy Bit = 0. 4. Write the MAC_CSR_CMD as follows: Busy Bit = 1, R/nW = 1, CSR Addre ss = 0x06.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 27 Revision 1.0 (12-14-09) APPLICA TION NOTE 6 T ransmit Packet Processing T ransmitti ng packets i s a straightforward process comp ared with receiving packets; in that the host can efficiently synchronize the entire transmit process wit h the application .
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 28 SMSC AN 12.12 APPLICA TION NOTE Last Segment i s also a 1-bit field, marking the data transfer as the end of a sing le packet. T o better understand the use of these last two fields, let’s discuss two popular operating systems that utilize different packet allocation schem es.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 29 Revision 1.0 (12-14-09) APPLICA TION NOTE 6.4 Packet T ransfer Completion: Manageme nt St atistics Once a data packet has been transferred i.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 30 SMSC AN 12.12 APPLICA TION NOTE 6.5 T ransmit Packet Examples Let’s take a look at T able 6.2, "T ransmit Packet Example" , which shows a 78-byte (0x4e) transmit packet used in the example, which begins at location 0xb4002013 in physical memory .
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 31 Revision 1.0 (12-14-09) APPLICA TION NOTE Keep in mind that this example is running in a Little Endian environment. T o begin the transfer sequence, write the two command word s as DWORDs, followed by th e packet data.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 32 SMSC AN 12.12 APPLICA TION NOTE Figure 6.1 Multiple (3) Buffer Data Single Packet T ransfer Sequence 78-byte Pay load Data Data Tr.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 33 Revision 1.0 (12-14-09) APPLICA TION NOTE 6.5.1 T ransmit Command Words for Figure 6.1, "Multiple (3) Buffer Dat a Single Packet T rans.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 34 SMSC AN 12.12 APPLICA TION NOTE 6.6 The Overall Pack et T ransmit Process Now that we’ve established a background for transmi tting packets with the device, let’ s look at the diagram in Figure 6.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 35 Revision 1.0 (12-14-09) APPLICA TION NOTE Figure 6.2 Packet T ransmission Once the device is initiali zed, the application can co ntinue sen.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 36 SMSC AN 12.12 APPLICA TION NOTE 7 Receive Packet Processing A receive process must signal the host that there ar e incoming packet.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 37 Revision 1.0 (12-14-09) APPLICA TION NOTE Figure 7.1 Packet Reception In the F igure 7.1 above we only begin reading packets whenever the RX St atus FIFO cont a ins any entries (see RX_FIFO_INF:RSXUSED ).
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 38 SMSC AN 12.12 APPLICA TION NOTE 7.1 Receive Dat a T ransfer Given that the device makes al l data transfers in DW ORD pieces, the driver can easily align the receiving data memory address to a D WORD boundary .
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 39 Revision 1.0 (12-14-09) APPLICA TION NOTE : Enabling a receive transfer requires setting up the RX_CFG register , shown in T able 7.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 40 SMSC AN 12.12 APPLICA TION NOTE RX_DA T A_FIFO must be read a n appropriate n umber of DWORDS to purge the miniscule p acket. This should only happe n if the MAC_CR is configur ed to P ASSBAD packets ( == ‘1’).
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 41 Revision 1.0 (12-14-09) APPLICA TION NOTE 8 Instrument ation and Debug This chapter is base d upon the experience gained from the development of the simple Linu x Driver for the LAN91 18 family .
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 42 SMSC AN 12.12 APPLICA TION NOTE 8.1.3 SMSC_ASSERT(condition) SMSC_ASSERT points are enabled wh en USE_ASSER T is defined during co mpile time. It has no run time dependency on debug mode.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 43 Revision 1.0 (12-14-09) APPLICA TION NOTE Figure 8.1 Oscilloscope/Logic Analyzer Dis play GPIOs can also be used with a scope for instrumentat ion. Most scopes provid e a way to measure the time between events.
LAN91 18 Family Programmer Reference Guide Revision 1.0 (12-14-09) 44 SMSC AN 12.12 APPLICA TION NOTE Some other useful error interrupts to be aware of include: TXSO TDFO TSFF – TX st atus FIFO full RSFF – RX status FIFO full 8.
LAN91 18 Family Programmer Reference Guide SMSC AN 12.12 45 Revision 1.0 (12-14-09) APPLICA TION NOTE 80 ARKA Y DRIVE, HAU PP AUGE, NY 1 1788 (631) 43 5-6000, FA X (631) 273-3123 Copyright © 200 9 SMSC or its sub sidiaries.
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