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Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Pr imeCell ® AHB SRAM/NOR Memor y Controller (PL241) Revisi on: r0p1 T echnical Ref erence Man ual.
ii Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B PrimeCell AHB SRAM/NOR Me mory Controller (PL241) T echnical Reference Manual Copyright © 2006 A RM Limited. All rights reserv ed. Release Information The following changes ha ve been made to this book.
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. iii Contents PrimeCell AHB SRAM/NOR Memory Controller (PL241) T ec hnical Reference Man ual Preface About this manual ............... ...................................................
Contents iv Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Chapter 4 Programmer’s Model for Test 4.1 SMC integration test regist ers .............. .............. .............. .............. ............ 4-2 Chapter 5 Device Driver Requirements 5.
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. v List of T ab les PrimeCell AHB SRAM/NOR Memory Controller (PL241) T ec hnical Reference Man ual Change History ............. ........................................................ .
List of Tables vi Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Table 2-21 Synchronous read and asynchronous write opmode chip register settings ............ 2-37 Table 3-1 Register summary ...................... .............. ...
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. vii List of Figures PrimeCell AHB SRAM/NOR Memory Controller (PL241) T ec hnical Reference Man ual Key to timing diagram conventions ................. .. ......... .............. ......
List of Figures viii Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Figure 2-20 Synchrono us burst read in multiplexed-mo de ............... .............. .............. ............. 2-34 Figure 2-21 Synchronous burst write ......
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. ix Preface This preface introduces the PrimeCell AHB SRAM/NOR Memory Contro ller (MC) (PL241) T echnical Reference Manual . It contains the following sections: • About this manual on pag e x • F eedback on page xiv.
Preface x Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B About this manual This is the T ec hnical Refer ence Manual (TRM) for the PrimeCell AHB SRAM/NOR Memory Contr oller .
Preface ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. xi App en dix A Signal Descriptions Read this appendix for a description of the AHB MC input and outp ut signals. Glossary Read the Glossary for def initions of terms u sed in this manual.
Preface xii Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Note Angle brackets can also enclose a permitted range of v alues. The example, <0-3>, sho ws that in name e xtensions, only one of the values 0, 1, 2, or 3 is valid.
Preface ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. xiii Pref ix B Denotes AXI write response channel signals. Pref ix C Denotes AXI low-po wer interface signals. Pref ix H Denotes Advanced High-performance Bus (AHB) signals. Pref ix P Denotes Advanced P eripher al Bus ( APB) signals.
Preface xiv Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Feedback ARM Limited welcomes feedback on the AHB MC and its documentation . Feedbac k on this pr oduct If you hav e any comments or suggestions about this product, contact your supplier giving: • the product name • a concise explanati on of your comments.
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 1-1 Chapter 1 Intr oduction This chapter introduces the AHB MC. It contains the following sections: • About the AHB MC on page 1-2 • Supported devices on page 1-5 .
Introduction 1-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 1.1 About the AHB MC The AHB MC is an Advanced Micr ocontr oller Bus Ar chitectur e (AMBA) compliant System-on-Chip (SoC) peripheral. It is dev eloped, tested, and licensed by ARM Limited.
Introduction ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 1-3 1.1.1 AHB interface The interface con verts the inco ming AHB transfers to the protocol used internally by the AHB MC.
Introduction 1-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 1.1.3 SMC The SMC is a high-performance, area- optimized SRAM mem ory controller . The SMC is pre-configured and v a lidated for: • the SRAM memory type • the number of SRAM memory devices • the maxi mum SRAM memory widt h.
Introduction ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 1-5 1.2 Suppor ted de vices The SMC supports SRAM/NOR, see SMC on page 1-4.
Introduction 1-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B.
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-1 Chapter 2 Functional Overview This chapter describes the major components of the AHB MC and ho w they operate. It contains the follo wing sections: • Functional descriptio n on page 2-2 • SMC on page 2-4 • Functional operation on page 2-7.
Functional Overview 2-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 2.1 Functional description Figure 2-1 shows an AHB MC (PL241) conf iguration.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-3 2.1.3 Clock doma ins The memory controller has two clock domains: AHB clock doma in This is clocked by hclk , smc_aclk and reset b y hresetn . Static memory clock domain This is clocked by smc_mclk0 , smc_mclk0n and reset by smc_mreset0n .
Functional Overview 2-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 2.2 SMC Figure 2-3 shows a block diagram of the SMC. Figure 2-3 S MC bloc k diagram The main blocks of the SMC.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-5 2.2.1 SMC inte rface The SMC interface processes the incoming AHB transfers and sends them to the command format block. 2.2.2 APB sla ve inte rface The SMC has 4KB of memory allocated to it.
Functional Overview 2-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 2.2.6 P ad interface The pad interface module provides a re gist ered I/O interface for data a nd control signals. It also con tains interrupt generation lo gic.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-7 2.3 Functional operation This section is divided into: • AHB interface operation • AHB to APB bridge oper ation on page 2-10 • Clock domain operation on page 2-11 • Low-power interface operation on page 2-12 • SMC functiona l oper ation on page 2-15.
Functional Overview 2-8 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Undefined length INCR b ursts All undefined length INCR b ursts are con verted to INCR b ursts of length four . Many AHB masters rely on using undef ined length INCR bursts to access data.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-9 If transfers are described as non-buf ferable then the bridge must wait for the write response to indicate that th e transfer has been completed to memory .
Functional Overview 2-10 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Registered HWDA T A The interconnect used within the AH B MC co ntains combinatorial paths for the write data. T o impro ve the synthesis timing, HWD A T A is registered and mak es these paths internal to the desi gn.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-11 Figure 2-6 AHBC memor y map The other fourteen 4KB regions are read as zero. The lo wer 16 bits of the AHB address decode the memory controller that is being used.
Functional Overview 2-12 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Static memory c loc king options T able 2-1 lists the static memory clocking option s. 2.3.4 Low-po wer interfac e operation The memory controller has two lo w-power interfaces.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-13 an active output <domain>_cactive Where: <domain> is ahb or smc. Figure 2-7 explains the protocol for the interface b y sho wing a request to enter lo w-power mode .
Functional Overview 2-14 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B The AHB domain accepts or denies requests ba sed on whether it is busy performing any transfers.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-15 2.4 SMC functio nal operation This section describes: • Operat ing states • Clocking and r esets on page .
Functional Overview 2-16 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B The state transitions are: Ready to Reset When reset is asserted to the smc _aclk domain, it enters the Reset state. Reset to Ready When reset is deasserted to the smc_aclk domain, it enters the Ready state.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-17 These clocks can be grouped into two clock domains: AHB domain smc_aclk is in this dom ain. Y ou can onl y stop the smc_aclk domain signals when the SMC is in lo w-power mode.
Functional Overview 2-18 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Y ou can change both reset signals asynchronously to th eir respecti ve clock domain. Internally to the SMC the deassert ion of the hr esetn signal is synchronized to smc_aclk .
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-19 smc_msync0 When HIGH, indicates smc_mclk0 is synchronous to smc_aclk . Otherwise they are as yn chronous. Ensure that smc_msync0 is tied to the same v alue as smc_async0 .
Functional Overview 2-20 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B The SMC ensures the ordering of read transfers from a single port is m aintained RAR, and additionally that the ordering of write transfer s from a single master is maintained WA W.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-21 memory b ursts, terminat ing a memory transfer at the b urst boundary . Also ens ure the page size is an integer multiple of the burst length, to avoid a memory b urst crossing a page boundary .
Functional Overview 2-22 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 2.4.6 Memor y ma nager operation The memory manager module is responsi ble for controlling the state of the SMC and the updating of chip configuration registers.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-23 The APB registers smc_set_cy cles and smc_set_opmode act as holding registers, the configuration registers wi.
Functional Overview 2-24 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Direct comman ds The SMC enables code to be ex ecuted from the memory wh ile simultan eously , from the software perspecti ve, moving the same chip to a dif ferent operating mode.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-25 Figure 2-12 Device pin mechanism :ULWHWLPLQJSDUDPHWHUV DQGRSHUDWLQJPRGHWR WKHPHPRU.
Functional Overview 2-26 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Figure 2-13 Software mechanism :ULWHWLPLQJSDUDPHWHUV DQGRSHUDWLQJPRGHWR WKHPHPRUFR.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-27 2.4.7 Interrupts oper ation The next read to an y chip select on th e appropriate memory interfa ce clears the interrupt. The interrupt outputs are generated through a combinati onal path from the rele vant input pin.
Functional Overview 2-28 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Read data output by the memory device is also registered on the rising edge of smc_mcl k0n , equi v alent to the falling edge of smc_mclk0 , for asynchronous reads.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-29 Figure 2-14 Asynchronous read Asynchr onous read in m ultiple xed-mode T able 2-4 and T ab le 2-5 list the smc_opmode0_<0-3> and SRAM Register settings.
Functional Overview 2-30 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Note In multiplexed-mode, both address an d data are output by the SMC on the smc_data_out_0[31:0] output bus. Read data is accepted on the smc_data_in_0[31:0] bus .
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-31 Asynchronous writ e in multiplexed-mode T able 2-8 and T ab le 2-9 list the smc_opmode0_<0-3> and SRAM Register settings. Figure 2-17 shows an asynchronous w rite in multiplex ed-mode.
Functional Overview 2-32 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Figure 2-18 shows a page read access, with an initial access time , t RC , of three c ycles, an output enable assertion delay , t CEOE , of two cycles a nd a page access time, t PC , of one cycle.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-33 Figure 2-19 shows a b urst read with the smc_wait_0 output of the memory used to delay the transfer .
Functional Overview 2-34 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Synchr onous b urs t read in m ultiple xed-mode T able 2-14 and T able 2-15 list the smc_opmode0_<0-3> and SRAM Register settings. Figure 2-20 shows the same synchronous re a d burst transfer as Figure 2-19 on page 2-33, but in multiplex ed-mode.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-35 Synchronous burst write T able 2-16 and T able 2-17 list the sm c_opmo de0_<0- 3> and SRAM Re gister settings. Figure 2-21 sho ws a synchronous burst write transfer that is delayed by the smc_wait_0 signal.
Functional Overview 2-36 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B Synchr onous b urs t write in m ultiple xed-mo de T able 2-18 and T able 2-19 list the smc_opmode0_<0-3> and SRAM Register settings. Figure 2-22 shows the same synchronous burst write as Figure 2-21 on page 2-35, b ut in multiplexed-mode.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-37 Synchronous read and asy nchr onous write T able 2-20 and T able 2-21 list the sm c_opmo de0_<0- 3> and SRAM Re gister settings. Figure 2-23 on pag e 2-38 sho ws the turnaround ti me t TR , enforced between synchronous read and asynchronous write.
Functional Overview 2-38 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B Figure 2-23 Synchronous read and asynchr onous write Programmi ng t RC and t WC when the controller oper ate.
Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-39 For t WC : • when using mem ory de vi ces that are not wait-enabled, you must program t WC to be the number.
Functional Overview 2-40 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B.
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-1 Chapter 3 Pr ogrammer’ s Model This chapter describes the registers of the SMC and provides information for programming th e de v ice.
Programmer’s Model 3-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 3.1 About the programmer’ s model The SMC has 4KB of memory allocated to it from a base address of 0x1000 to a maximum address of 0x1FFF .
Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-3 3.2 Register summar y Figure 3-2 shows the SMC configuration re gister map.
Programmer’s Model 3-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Note Figure 3-3 on page 3-3 shows the maximum number of supported chips. If you intend to use fe wer , then the highest chip configura tion blocks of the correct type are read back as zero.
Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-5 smc_set_cycles 0x1014 WO N /A See SMC Set Cycles Re gister at 0x1014 on page 3-11. smc_set_opmode 0x1018 WO N /A See SMC Set Opmode Re gister at 0x1018 on page 3-12.
Programmer’s Model 3-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 3.3 Register descriptions This section describes the SMC registers. 3.3.1 SMC Memory Controll er Status Regist er at 0x1000 The read-only smc_memc_st atus Re gister provides information on the configuration of the SMC and also the current state of the SMC.
Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-7 3.3.2 SMC Memory Interface Co nfiguration Regis ter at 0x1004 The read-only smc_memif_cfg Register provides information on the configuration of the memory interface.
Programmer’s Model 3-8 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 3.3.3 SMC Set Configuration Register at 0x1008 The write-only smc_memc_cf g_set Register enables the memory controller to be changed to Lo w-power state, and interrupts en abled.
Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-9 T able 3-4 lists the register bit assignments. 3.3.4 SMC Clear Configuration Regi ster at 0x100C The write-only smc_memc_cfg_clr Register enables the memory controller to be mov ed out of the Low-po wer state, and the in terrupts disabled.
Programmer’s Model 3-10 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B 3.3.5 SMC Direct Command Registe r at 0x1010 The write-only smc_direct_cmd Register passes commands to the external memory , and controls the updating of the chip configuration registers with values held in the set_opmode and set_cycles re gisters.
Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-11 3.3.6 SMC Set Cycles Registe r at 0x1014 This is the holding register for th e smc_set_cycles0_<n>.
Programmer’s Model 3-12 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B 3.3.7 SMC Set Opmode Register at 0x1018 This register is the holding register for the smc_opmode0_<n> working registers. The write-only smc_set_opmode Register cannot be written to in eith er the Reset or Low-po wer state.
Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-13 T able 3-8 lists the register bit assignments. T able 3-8 smc_set_opmode Register bit assignments Bits Name Function [31:16] - Reserved, undef i ned, write as zero.
Programmer’s Model 3-14 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B [9:7] set_wr_bl Holding register for value to be wr itten to the specific SRAM ch ip smc_opmode Register bls fie ld .
Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-15 3.3.8 SMC Refresh P eriod 0 Register at 0x1 020 The read/write smc_refresh_period_0 Register enables the AHB MC to perform refresh cycles for PSRAM de vices that you connect to memory interface 0.
Programmer’s Model 3-16 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B T able 3-10 lists the register bit assignments. 3.3.10 SMC Opmode Register s <0-3> at 0x1104, 0x1124, 0x 1144, 0x1164 There is an instance of the smc_opmode Regi ster for each chip supported.
Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-17 T able 3-11 lists the register bit assignments. T able 3-11 smc_opmode Register bit assignments Bits Name Function [31:24] address_match Returns the value of this ti e-off.
Programmer’s Model 3-18 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B 3.3.11 SMC User Status Regi ster at 0x1200 The smc_user_status Register is a general purpose read-only register that returns the state on the smc_user_status[7:0] primary inputs.
Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-19 3.3.12 SMC User Configuration Regist er at 0x1204 The smc_user_config Register is a general purp ose write-only register . This re gister s ets the v alue of the smc_user_config[7:0] primary outputs.
Programmer’s Model 3-20 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B Figure 3-18 shows the correspondence between bits of the smc_ periph_id re gisters and the conceptual 32-bit Peripheral ID Register .
Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-21 SMC P eriph eral Identifi cation Register 1 The smc_periph_id_1 Register is hard-coded and the fields within the re gister indicate the v alue. T able 3 -16 lists th e re gister bit assignments.
Programmer’s Model 3-22 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B 3.3.14 SMC PrimeCell Identifi cation Register s <0-3> at 0x1FF0- 0x1FFC The smc_pcell_id Regist ers are four 8-bit wide register s , that span address locations 0xFF0-0FFC .
Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-23 The following sections describe the smc_pcell_id Re gisters: • SMC PrimeCell Identification Re gister 0 .
Programmer’s Model 3-24 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B SMC PrimeCell Identi fication Register 2 The smc_pcell_id_2 Register is hard-coded an d the fields within the re gister indicate the value. T able 3-22 lists the register bit assignments.
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 4-1 Chapter 4 Pr ogrammer’ s Model for T est This chapter describes the additional log ic for functional verif ication and production testing. It contains the following section: • SMC inte grati on test r e gister s on page 4-2.
Programmer’s Model for Test 4-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 4.1 SMC integration test registers T est registers are provided for integration testing . Figure 4-1 shows the SMC integration test register map. Figure 4-1 SMC integration test regi ster map T able 4-1 lists the SMC integration test registers.
Programmer’s Model for Test ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 4-3 T able 4-2 lists the register bit assignments. 4.1.2 Integration Inputs Register at 0x1E04 The read-only smc_int_ inputs Re gister enables an e xtern al master to access the inputs of the SMC using the APB interf ace.
Programmer’s Model for Test 4-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 4.1.3 Integration Outpu ts Register a t 0x1E08 The write-only smc_ int_output s Re gister enables an external master to access the outputs of the SMC using the APB interface.
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 5-1 Chapter 5 De vice Driver Requirements This chapter contains v arious flo w diagrams to aid in the de velopment of a software dri ver for the SMC. It cont ains the following section: • Memory initiali zation on page 5-2.
Device Driver Requirements 5-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B 5.1 Memor y initialization Figure 5 -1 on page 5-3 and Figure 5-3 on page 5-5 shows the sequence of e v.
Device Driver Requirements ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 5-3 Figure 5-1 SMC and memory initia lization sheet 1 of 3 6WDUW 3VHXGR&RGHIRU.
Device Driver Requirements 5-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B Figure 5-2 SMC and memory initialization sheet 2 of 3 6KHHW ,V PHPRUGHYLFH 0RGH5HJDFFHVVHG.
Device Driver Requirements ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 5-5 Figure 5-3 SMC and memory initia lization sheet 3 of 3 Where: x = denotes the appropriate chip select.
Device Driver Requirements 5-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B.
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-1 Appendix A Signal Descriptions This appendix lists and describes the processor signal s.
Signal Descriptions A-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B A.1 About the signals list This appendix lists the PL241 signals.
Signal Descriptions ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-3 A.2 Clocks and resets T able A-1 lists the clock and reset signals.
Signal Descriptions A-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B A.3 AHB signals T able A-2 lists the AHB signals. where: <x> = 0 or C, where C = Configuration.
Signal Descriptions ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-5 A.4 SMC memor y interface signals T able A-3 lists the SMC memory interface signals.
Signal Descriptions A-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B A.5 SMC miscellaneous signals T able A-4 lists the SMC miscellaneous signals.
Signal Descriptions ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-7 A.6 Low-power interface T able A-5 lists the lo w-power interf ace signals.
Signal Descriptions A-8 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B A.7 Configuration signal T able A-6 lists the co nf iguration signal.
Signal Descriptions ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-9 A.8 Scan chains T able A-7 lists the scan chain signals. T able A-7 Scan c hain signals Name T ype Source/ des.
Signal Descriptions A-10 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B.
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. Glossary-1 Glossary This glossary describes some of the terms used in technical documents from ARM Limited. Adv anced High-per formance Bus (AHB) A bus protocol with a f ixed pipeline between address/control and data phases.
Glossary Glossary-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B Adv anced Pe ripheral B us (APB) A simpler bus protocol than AHB. It is designed for use with ancillary or general-purpose peripherals such as timers, in t errupt controllers, U AR Ts, and I/O ports.
Glossary ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. Glossary-3 Boundary scan chain A boundary scan chain is made up of serially -connected de vices that implement boundary scan technology using a standard JT A G T AP interface.
Glossary Glossary-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B SBO See Should Be One. SBZ See Should Be Ze ro. SBZP See Should Be Ze ro or Preserved. Scan chain A scan chain is made up of serially-connected de vices that implement boundary scan technology using a standard JT A G T AP interface.
Glossary ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. Glossary-5 Remapping Changing the address of physical memory or de vices after the ap plication has started ex ecuting. This is t ypically done to perm it RAM to replace R OM when the initialization has been completed.
Glossary Glossary-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0 389B.
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