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S3F80JB 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1.1.
Important Notice The information in this publication has b een carefully checked and is believed to be entirely accu rate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any co nsequences resulting from the use of the information contained here in.
S3F80JB MICROCONTROLLER iii Preface The S3F80JB Microcontroller User's Manual is designed for application designers and programmers who are usin g S3F80JB mi croc ontro ller for ap pli cat ion dev elo pment .
S3F80JB MICROCONTROLLER v Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8/S3F8-Ser ies Microcontrol lers ....... .................. ................... .................. .................. ..... ......... ............. 1-1 S3F80JB Mi crocontrolle r .
vi S3F80JB MICROCONTROLLER Table of Contents (Continued) Chapter 5 Interrupt Structure Overview ......................... ....................... .................. .................. ....................... ................................ ......... 5-1 Interrupt Types .
S3F80JB MICROCONTROLLER vii Table of Contents (Continued) Chapter 8 RESET Overview ......................... ................... ....................... .................. .................. ................ .................... ......... 8-1 Reset Sou rces .
viii S3F80JB MICROCONTROLLER Table of Contents (Continued) Chapter 10 Basic T imer and Timer 0 Overview ......................... ....................... .................. .................. ....................... ............ .................... .
S3F80JB MICROCONTROLLER ix Table of Contents (Continued) Chapter 15 Embedd ed Flash Memory Interface Overview ......................... ................... ....................... .................. .................. ................ ................
x S3F80JB MICROCONTRO LLER List of Figures Figure Title Page Number Number 1-1 Block Diagram (32 -pin) ........... .... ................... .................. .................. ................... .... 1-3 1-2 Block Diagram (44 -pin) ........... ....
S3F80JB MICROCONTROLLER xi List of Figures (Continued) Figure Title Page Number Number 5-1 S3C8/S3F8-Serie s Interrupt Type s............ .................. .................. ................... ........ 5-2 5-2 S3F80JB Interrupt Structure ..........
xii S3F80JB MICROCONTROLLER List of Figures (Continued) Figure Title Page Number Number 12-1 Coun ter A Block Diagra m ..................... .................. .................. .................. .............. 12-2 12-2 Counter A Co ntrol Register (CACON ) .
S3F80JB MICROCONTROLLER xiii List of Figures (Continued) Figure Title Page Number Number 18-1 Typical Low-Side Driver (Sink) Ch aracteristics ( P3.1 only ) ················· ···· ·············· ···· 18-5 18-2 Typical Low-Side Driver (Sink) Chara cteristics (P3.
S3F80JB MICROCONTROLLER xv List of Tables Table Title Page Number Number 1-1 Pin Descrip tions of 32-SOP ..... .................. .................. ..... .................. .................. .... 1-7 1-2 Pin Descrip tions of 44-QFP .................
xvi S3F80JB MICROCONTROLLER List of Tables (Continued) Table Title Page Number Number 15-1 Descriptio ns of Pins Used to Read/Wri te the Fla sh in Tool Program Mod e .............. 15-2 15-2 ISP Secto r Size ........................... .... ..........
S3F80JB MICROCONTROLLER xvii List of Programming Tips Description Page Number Chapt er 2 Addr ess S pace s Setting the Re gister Pointers .............. .... ................... .................. .................. .................. ....... ........
S3F80JB MICROCONTROLLER xix List of Register Descriptio ns Register Full Register Name Page Iden tifi er Number BTCON Basic Timer Control Register................ ................... .................. .................. ............. 4-5 CACON Counter A Control Register .
S3F80JB MICROCONTROLLER xxi List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADC Add with carry ...... ....................... .................. ................... ....................... ................. 6-1 4 ADD Add.
xxii S3F80JB MICROCONTRO LLER List of Instruction Descriptions (Continued) Instruction Full Register Name Page Mnemonic Number NEXT N ext ................. ....................... .................. ....................... .................. .........
S3F80JB PRODUCT OVERVIEW 1-1 1 PRODUCT OVERVIEW S3C8/S3F8-SE RIES MICROCONTROLLERS Samsung's S3C8/S 3F8-series of 8-bit sing le- chip CMOS microcont roll ers offers a fast and eff icient CPU, a wide range of integra te d pe rip he rals, and various flash me mory ROM sizes.
PRODUCT OVERVIEW S3F80JB 1-2 FEATURES CPU • SAM8 RC CPU core Memory • Program memory: - 64-Kbyte Internal Flash Memory - Sector size: 12 8Bytes - 10years data rete ntion - Fast Programming Time : .
S3F80JB PRODUCT OVERVIEW 1-3 BLOCK DIAGRAM (32-PIN PA CKAGE) 8-Bit Tim er 0 /Counter P0.0-0.3 (INT0-INT 3 ) P2.0-2.3 (INT5- INT8) P2.4-2.7 (INT9) (CIN0-CIN 3) P3.
PRODUCT OVERVIEW S3F80JB 1-4 BLOCK DIAGRAM (44-PIN PACKAGE) 8-Bit Tim er0 /Counter P0.0-0.3 (INT0-INT3) P2.0-2.3 (INT5-INT8) P2.4-2.7 (INT9) (CIN0-CIN3) P3.
S3F80JB PRODUCT OVERVIEW 1-5 PIN ASSI GNMENTS S3F80JB (Top View) 32-SO P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD P3.1/REM/T0CK/SCLK P3.0/T0PW M/T0CAP/T 1CAP/T2CAP/SDAT P2.4/INT9/CIN0 P2.3/INT8 P2.2/INT7 P2.1/INT6 P2.0/INT5 P0.7/INT4 P0.6/INT4 P0.5/INT4 P0.
PRODUCT OVERVIEW S3F80JB 1-6 PIN ASSIGNMENTS (Continued) S3F80JB (Top View) (44-QFP) 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 P0.4/INT4 P0.5/INT4 P0.6/INT4 P0.7/INT4 P4.3 P4.2 P4.1 P4.0 P2.0/INT5 P2.1/INT6 P2.2/INT7 P2.3/INT 8 P2.
S3F80JB PRODUCT OVERVIEW 1-7 Table 1-1. Pin Descr iptions of 32-SOP Pin Names Pin Type Pin Descrip tion Circuit Type 32 Pin No. Shared Functions P0.0–P0.7 I/O I/O port with bit-prog rammable pins . Configur able to input or push-pull ou t put mode. Pull-up resistors are assignable by sof tware.
PRODUCT OVERVIEW S3F80JB 1-8 Table 1-2. Pin Desc ri ptions of 44-QFP Pin Names Pin Type Pin Description Circuit Type 44 Pin No. Shared Functions P0.0–P0. 7 I /O I/O port with bi t-programmable p i ns. Configura ble to input or push- pull output mode.
S3F80JB PRODUCT OVERVIEW 1-9 Table 1-2. Pin De scriptions of 44-QFP (Continued) Pin Names Pin Type Pin Description Circuit Type 44 Pin No. Shared Functions P3.1 I/O I/O port with bit-program mable pin. Configurable to input mod e, push-pull ou tput mode, or n- channel open-drain outp ut mode.
PRODUCT OVERVIEW S3F80JB 1-10 PIN CIRCUITS V DD Pull-up Enable V DD INP UT/O UTPUT Pull-Up Resistor (55k Ω - typ) Data V SS External Interrupt Output Disable Noise Filter MUX P2CONx.x CMPS EL.0-.3 P2.4-P 2. 7 Only + - REF External REF (P2.7 only) Compar ator Stop Stop Release Figure 1-5.
S3F80JB PRODUCT OVERVIEW 1-11 PIN CIRCUITS (Continued) V DD Pull-up Resistor (55k Ω -Typ) V DD V SS Noise Filter INP U T/ OUTP U T Pull-up Enable Data Output Disable Normal Input Open-Drain Figure 1-6. Pin Circuit Type 2 (P ort 1, Port 4, P3.4 and P 3.
PRODUCT OVERVIEW S3F80JB 1-12 PIN CIRCUITS (Continued) V DD Pull-up Enable P3.0/T0PW M T0CAP/ (T1CAP/T2CAP) Pull-up Resist or (55k Ω -Typ) Open-Drain Port 3.0 Data V SS P3.0 Input M U X P3CON.2 Data Output Disable T0CAP/(T1CAP/T2CAP) T0_ PW M Noise filter M U X P3CON.
S3F80JB PRODUCT OVERVIEW 1-13 PIN CIRCUITS (Continued) V DD Pull-up Enable V DD P3.1/REM /(T0CK) Pull-up Resistor (55k Ω -Typ) Open-Drain Port 3.1 D a ta V SS P3.1 I nput M U X P3CON.5 Data Outpu t Disable T0CK Carrier On/Off (P3.7) CACON.2 Noise filter M U X P3CON.
PRODUCT OVERVIEW S3F80JB 1-14 PIN CIRCUITS (Continued) V DD Pull-up Resistor (500k Ω -Ty p) nRESET Figure 1-10. Pin Circui t Type 6 (nRES ET).
S3F80JB A DDRESS SPACE 2-1 2 ADDRESS SPACE OVERVIEW The S3F80JB microcontroller has two types of ad dress spa ce: — Internal p rogram memory (Flas h memory) — Internal reg ister file A 16-bit add ress bus supports program memo ry operations . A separate 8 -bit regis ter bus ca rries addr esses a nd data between the CPU and the register file.
S3F80JB ADD RESS SPACES 2-2 PROGRAM MEMORY Program memory (Flash memory) stores prog ra m cod e or table data. The S 3F80JB has 64-Kby t e of in te rnal programmable Flash memory. The prog ram memory addre ss range is theref ore 0000H–FFFFH of Flash memory (See Figure 2-1 ).
S3F80JB A DDRESS SPA CES 2-3 SMART OPTION Smart option is the progr am memory option for starting condition of the chip. The program memory addresse s used by smart o pt i on ar e fr om 003CH to 003FH. The S3F80JB only use 00 3E H and 003FH. User can wr it e an y value in the no t used addr esses ( 003CH an d 003DH).
S3F80JB ADD RESS SPACES 2-4 NOTES 1. By setting I SP Reset Vector Change Selection Bit (3E H. 7) to ‘0’, user can have t h e av a ila ble ISP area. If ISP Rese t Vector Chang e Se le cti on Bit (3EH.7) i s ‘1’, 3E H.6 and 3EH.5 are meaningless.
S3F80JB A DDRESS SPA CES 2-5 REGISTER ARCHI TECTURE In the S3F80JB impleme ntation, the u pper 64-byte a rea of reg ister files is expanded tw o 64-byte a reas, called s et 1 and set 2.
S3F80JB ADD RESS SPACES 2-6 Bank1 D0H CFH E0H DFH C0H Bank 0 System and Peripheral Control Register (Register Addressing Mode) System Register (Register Addressing Mode) Working Register (Working Regi.
S3F80JB A DDRESS SPA CES 2-7 REGISTER PAGE POIN TER (PP) The S3C8/S3 F 8-se rie s architecture suppo rt s the logical exp ansion of the phy sical 333-byt e internal regist e r files (using an 8-bit da ta bus) into as man y as 16 separately ad dre ssab l e reg i ste r pa ge s.
S3F80JB ADD RESS SPACES 2-8 REGISTER SET 1 The term set 1 refers to the up per 64 bytes of the r egister file, locatio ns C0H–FFH . The upper 32 -byte are a of this 64- byte spac e (E0H–FFH) is divided into two 32-byte register banks, b ank 0 and bank 1.
S3F80JB A DDRESS SPA CES 2-9 PRIME REGI ST ER SPACE The lower 192 byt es of the 256-by te physical inte rn al register file (0 0H –BFH) are called th e prime register space or, more si mply, the pr ime area. Yo u can ac cess r egisters in this ad dress using any ad dress ing mode.
S3F80JB ADD RESS SPACES 2-10 WORKING REGI S TERS Instructio ns can access spe cif ic 8-bit register s or 16 -b it register pairs using eit her 4-bit or 8-bit address fields.
S3F80JB A DDRESS SPA CES 2-11 USING THE REGIST ER POINTERS Register p ointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, ar e used to select two mova ble 8-byte work ing registe r slices in the registe r file.
S3F80JB ADD RESS SPACES 2-12 16-byte non-contiguous working register block Register File Contains 32 8-Byte Slices 8-Byte Slice 00H (R0) 07H (R15) F0H (R0) F7H (R7) RP1 RP0 1 1 1 1 0 X X X 0 0 0 0 0 X X X 8-Byte Slice Figure 2-8.
S3F80JB A DDRESS SPA CES 2-13 REGISTER ADDRESSING The S3C8-ser ies regist er architectur e provides a n efficient method of wo rking regis ter address ing that take s full advantag e o f shorter instru ction formats t o reduce execut ion time.
S3F80JB ADD RESS SPACES 2-14 FFH D0H FFH C0H Set 2 CFH RP1 RP0 Register Pointers C0H BFH 00H Special-Pu rpose Re gisters General-Pu rp o s e Reg isters All Addressing Mod e s Page 0 Indirect Register,.
S3F80JB A DDRESS SPA CES 2-15 COMMON WORKING REGI STER AREA (C0H–CFH) After a rese t, register pointers R P0 and RP1 automa tically select two 8-byte re gister slic es in set 1, loca tions C0H–CFH, as the a ctiv e 16-byte wo rking register blo ck: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte addr ess range is c alled common area .
S3F80JB ADD RESS SPACES 2-16 PROGRAMMING TIP — Addressing th e Common Working Register Area As the follow ing examples show, yo u should ac cess w orking r egisters in the common ar ea, loc ations C0H– CFH, using workin g register addressin g mode only.
S3F80JB A DDRESS SPA CES 2-17 Toget her they cre ate an 8-bit re gister address Register poin ter provides fi ve high-orde r bits Address O PCODE Selects RP0 or RP 1 RP1 RP0 4-bit address procides thre e low-or der bits Figure 2-12.
S3F80JB ADD RESS SPACES 2-18 8-BIT WORKING REGISTER ADDRE S SING You can also use 8 -bi t wo rking register addre ssing to access registers in a sele ct ed working register area . To initiate 8-b i t working register a dd re ssing , the upper fo ur bit s of the instruct ion ad dr ess must contain th e v a lue 1100B.
S3F80JB A DDRESS SPA CES 2-19 Specifies w orking register add ressing RP0 Selec ts RP1 RP1 0 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 Register a ddress (0ABH) 0 11 0 1 1 1 0 8-bit address from instructio n 'LD R11, R2 ' R11 Figure 2-15.
S3F80JB ADD RESS SPACES 2-20 SYSTEM AND USER STACKS S3C8-series microcontrollers u se the syst em stack f or subroutine calls and r eturns and t o store da ta. The P USH and POP instructio ns are used to control syst e m sta ck opera ti ons. The S3F80JB arch ite ct ure sup po rt s sta ck operations in the interna l register file.
S3F80JB A DDRESS SPA CES 2-21 PROGRAMMING TIP — Standa rd Sta ck Operations Using PUSH and POP The following ex amp le shows you how to pe rf orm stack operations in the internal regi ster file .
S3F80JB AD DRESSING MODES 3-1 3 ADDRESSING MODES OVERVIEW The program c ounter is used to fetch instruct ions that are stored in program me mory for exe cution. Instruc tions indicate the o peration to be perfor med and th e data to be oper ated on. Add ressing mo de is the meth od used to determine t he l oca tio n o f t he da ta operand.
A DDRESSING MODES S3F80JB 3-2 REGISTER ADDRESS ING MODE (R) In Registe r addressing mo de, the operand is the content of a specified reg ister or regi ster pair (see Figure 3-1 ).
S3F80JB ADDRESSING MODES 3-3 INDIRECT REGISTE R ADDRESSING MODE (I R) In Indirect Register ( IR) addres sing mode , the content of th e spec ified regist er or regis ter pair is the addre ss of the operand.
A DDRESSING MODES S3F80JB 3-4 INDIRECT RE GI STER ADDRESSI NG MODE (Co ntinued) dst OPCODE Points to Register Pair Example Instru ction References Program Mem or y Sample Instructions : CALL @RR2 JP @RR2 Program Memory Register File Value used in instruction OPERAND Register Pair Program Memory 16-Bi t Address Points to Program Mem or y Figure 3-4.
S3F80JB ADDRESSING MODES 3-5 INDIRECT REGISTE R ADDRESSING MODE (Continue d) dst OPCODE ADDRESS 4-bit Working Register Address Point to the Woking Register (1 of 8) Sample Instruction: OR R3, @R6 Prog.
A DDRESSING MODES S3F80JB 3-6 INDIRECT RE GI STER ADDRESSI NG MODE (Co ntinued) dst OPCODE 4-bit W ork ing Register Address Sample Instructions: LCD R5 ,@RR6 ; Prog ram memor y access LDE R3,@RR14 ; E.
S3F80JB ADDRESSING MODES 3-7 INDEXED ADDR ES SING MODE (X) Indexed (X ) addressing mode ad ds an offset va lu e to a base addre ss duri ng instruction e xecution in ord er to calculate t he ef fective operand address (see Fig ur e 3– 7) .
A DDRESSING MODES S3F80JB 3-8 INDEXED ADDRES SING MODE (Continued) Register File OPER AND Prog r am Memor y or Data M emory Point to W orking Register Pair (1 of 4) LSB Selects 16-Bit address added to.
S3F80JB ADDRESSING MODES 3-9 INDEXED ADDRES SING MODE (Continued) Register File OPER AND Pro gr am Memor y or Data Memory Point to W orking Register Pair LSB Selects 16-Bit address added to offset RP0.
A DDRESSING MODES S3F80JB 3-10 DIRECT ADDRESS MODE (DA) In Direct Addr ess (DA) mode, the in struction pr ovides the oper and's 16- bit memory add ress. Jump (JP) and Ca ll (CALL) ins tructions use this ad dressing mode to specify the 16-bit de stination add ress that is lo aded into the PC whenever a JP or C ALL instr uction is executed.
S3F80JB ADDRESSING MODES 3-11 DIRECT ADDRES S MODE (Continued) OPCODE Program M emory Lower Address By te Program Mem or y Address Used Upper Addr ess Byte Sample Instructions: JP C,JOB1 ; W here JOB 1 is a 16-bit immediate addr ess CALL DISPLAY ; W here DISPLAY is a 16-bit immediate address Nex t OPCODE Figure 3-11.
A DDRESSING MODES S3F80JB 3-12 INDIRECT ADDRE S S MODE (IA) In Indirect A d dre ss (IA) mode, th e instruction spe cifi e s an address locate d in th e lowest 256 byt e s of the program memory. The selected pair of me mor y l oca ti ons contains t he actu al address of the ne x t in struction to be ex e cuted.
S3F80JB ADDRESSING MODES 3-13 RELATIVE ADDRE S S MODE (RA) In Relative Addres s (RA) mo de, a two's -complement s igned displa cement betwee n – 128 and + 127 is specified in the instruction . The displaceme nt value is then add ed to the cur rent PC value.
A DDRESSING MODES S3F80JB 3-14 IMMEDI ATE MODE (IM) In Immediate ( IM) mode, the op erand valu e used in th e instruct ion is th e value supp lied in the operand field itself. The operand may be one byte or one wor d in length, de pe nd ing on the instruct ion used.
S3F80JB CONTROL REGISTERS 4- 1 4 CONTROL REGISTERS OVERVIEW In this sect ion, detailed de s criptions of the S3F80JB co ntrol register s are pre sented in an easy-to-r ead format. You can use this section as a quick-re ference source when writ ing application programs.
CONTROL REGISTERS S3F 80JB 4-2 Table 4-1. Mapped Regi sters (Bank0, Set1) Register Name Mnemonic D ecimal Hex R/W Timer 0 Counter T0CNT 208 D0H R (NOTE) Timer 0 Data Regist er T0DATA 209 D1H R/W Timer.
S3F80JB CONTROL REGISTERS 4-3 Table 4-1. Mapped Re gisters (Continued) Register N ame Mnemonic De cimal Hex R /W Counter A Cont ro l Reg i st er CACON 2 43 F3H R/W Counter A Data Reg ister (High Byt e.
CONTROL REGISTERS S3F 80JB 4-4 FLA GS - System Flags Register Bit I d e ntifier Reset Value Read/Write R = Read-only W = Wr i te - o n ly R/W = Read /write ' - ' = N ot u sed Bit number: MSB.
S3F80JB CONTROL REGISTERS 4-5 BTCON — Basic T imer Control Register D3H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .7 – .
CONTROL REGISTERS S3F 80JB 4-6 CACON — Counter A Control Register F3H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Registe r ad dr essin g mode only .7 and .
S3F80JB CONTROL REGISTERS 4-7 CLKCON — System Clo ck Control Register D4H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .7 – .
CONTROL REGISTERS S3F 80JB 4-8 CMOD — Comparator Mode Re gis ter E9H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Registe r ad dr essin g mode only .7 Comparat or Enable Bit 0 Comparator operatio n di sable 1 Comparator operation en able .
S3F80JB CONTROL REGISTERS 4-9 CMPSEL — Comparator Input Selection Regi ster EBH Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3F 80JB 4-10 EMT — External Memory Timing Register (NOTE) FEH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 0 1 1 1 1 1 0 – Read/Write R/W R/W R/W R/W R/W R/W R/W – Addressing Mode Registe r ad dr essin g mode only .
S3F80JB CONTROL REGISTERS 4-11 FLAGS — System Flags Register D5H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e x x x x x x 0 0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3F 80JB 4-12 FMCON — Flash Memory Contro l Register EFH Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 0 0 0 0 – – – 0 Read/Write R/W R/W R/W R/W – – – R/W Addressing Mode Registe r ad dr essin g mode only .
S3F80JB CONTROL REGISTERS 4-13 FMSECH — Flash Memory Sector Address Register(High By te) ECH Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3F 80JB 4-14 IMR — Interrupt Mask Register DDH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Registe r ad dr essin g mode only .7 Interrupt Le vel 7 (IRQ7) Ena ble Bit; External Int errupts P0.
S3F80JB CONTROL REGISTERS 4-15 IPH — Instruction Pointer (High B yte) DAH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 . 2 .1 .0 Reset Valu e x x x x x x x x Read/Write R/W R/W R/W R/W R/ W R/W R/W R/W Addressing Mode Regis te r addressin g mode only .7 – .
CONTROL REGISTERS S3F 80JB 4-16 IPR — Interrupt Priority Register FFH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode onl y .7, .4, and .
S3F80JB CONTROL REGISTERS 4-17 IRQ — Interrupt Request Register DCH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Addressing Mode Register addressing mode only .7 Level 7 (IRQ7) Request Pending Bit; External Int errupts P0.
CONTROL REGISTERS S3F 80JB 4-18 LVDCON — LVD Control Register E0H Set1 Bank1 Bit Ident ifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue – – – – – – – 0 Read/Write – – – – – – – R/W Addressing Mode Re gi ster addressing mode onl y .
S3F80JB CONTROL REGISTERS 4-19 P0CONH — Port 0 Control Register (High By te) E8H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3F 80JB 4-20 P0CONL — Port 0 Control Register (Low Byte) E9H Set1 Bank0 Bit Ident ifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Registe r ad dr essin g mode only .
S3F80JB CONTROL REGISTERS 4-21 P0INT — Port 0 External Interrupt En ab le Register F1H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3F 80JB 4-22 P0PND — Port 0 Extern al Interrupt Pend ing Register F2H Set1 Bank0 Bit Ident ifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Registe r ad dr essin g mode only .
S3F80JB CONTROL REGISTERS 4-23 P0PUR — Port 0 Pull-up Resistor Enable Re gister E7H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3F 80JB 4-24 P1CONH — Port 1 Control Register (High By te) EAH Set1 Bank0 Bit Ident ifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Registe r ad dr essin g mode only .
S3F80JB CONTROL REGISTERS 4-25 P1CONL — Port 1 Control Regis ter (Low Byte) EBH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3F 80JB 4-26 P2CONH — Port 2 Control R egister (High Byte ) ECH Set1 Bank0 Bit Ident ifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Re gi ster addressing mode onl y .
S3F80JB CONTROL REGISTERS 4-27 P2CONL — Port 2 Control Register (Low Byte) EDH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3F 80JB 4-28 P2INT — Port 2 External Interrupt Enable Regi ster E5H Set1 Bank0 Bit Ident ifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Registe r ad dr essin g mode only .
S3F80JB CONTROL REGISTERS 4-29 P2PND — Port 2 External Interrupt Pendi ng Register E6H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3F 80JB 4-30 P2PUR — Port 2 P ull-up Resi stor Enab le Register EEH Set1 Bank0 Bit Ident ifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Registe r ad dr essin g mode only .
S3F80JB CONTROL REGISTERS 4-31 P3CON — Port 3 Control Register EFH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .7 and .6 Package Selection a nd Alternative Function Select Bits 0 0 32 pin packa ge P3.
CONTROL REGISTERS S3F 80JB 4-32 NOTES : 1. The port 3 data register, P3, at location E3H, set 1, bank0, contains seven bit value s which correspond to the following Port 3 pin functions ( bit 6 is not used for the S3F80J B: a. Port3, bit 7: carrier signal on (“1”) or off (“0”).
S3F80JB CONTROL REGISTERS 4-33 P345CON — Port3[4:5] Contr ol Re gis t er E1H Set1 Bank1 Bit Ide ntifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 1 0 1 – – – 0 Read/Write R/W R/W R/W R/W – – – R/W Addressing Mode Registe r ad dr essin g mo de only .
CONTROL REGISTERS S3F 80JB 4-34 P4CON — Port 4 Control Register F0H Set1 Bank0 Bit Ident ifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Registe r ad dr essin g mode only .7 P4.7 Mode Selection Bit 0 Open-drain output mode 1 Push-pull output mode .
S3F80JB CONTROL REGISTERS 4-35 P4CONH — Port 4 Control Register (Hi gh By te) E2H Set1 Bank1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3F 80JB 4-36 P4CONL — Port 4 Control Reg ister (Low Byte) E3H Set1 Bank1 Bit Ident ifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Registe r ad dr essin g mode only .
S3F80JB CONTROL REGISTERS 4-37 PP — Register Page Pointer DFH Set1 Bank0 Bit Identifier . 7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .7 – .4 Destinat ion Register P age Select ion Bits 0 0 0 0 Destinatio n: page 0 (See N ote) .
CONTROL REGISTERS S3F 80JB 4-38 RP0 — Register Pointer 0 D6H Set1 Bank0 Bit Ident ifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 1 1 0 0 0 – – – Read/Write R/W R/W R/W R /W R/W – – – Addressing Mode Registe r ad dr essin g mode only .7 – .
S3F80JB CONTROL REGISTERS 4-39 SPL — Stack Pointer (Low Byte) D9H Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Val u e x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only. .7 – .0 Stack Poin ter Addres s ( Low Byte) The SP value is un de f ined following a rese t.
CONTROL REGISTERS S3F 80JB 4-40 SYM — System Mode Register DEH Set1 Bank0 Bit Ident ifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 0 – – x x x 0 0 Read/Write R/W – – R/W R/W R/W R/W R/W Addressing Mode Registe r ad dr essin g mode only .
S3F80JB CONTROL REGISTERS 4-41 T0CON — Timer 0 Control Re gister D 2H Set 1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Val u e 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R /W R/W Addressing Mode Register addressing mode only .7 – .
CONTROL REGISTERS S3F 80JB 4-42 T1CON — Timer 1 Control Register FAH Set1 Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va lue 0 0 0 0 0 0 0 0 Read/Write R/W R/W R /W R/W R/W R/W R/W R/ W Addressing Mode Registe r addressin g mode only .7 and .
S3F80JB CONTROL REGISTERS 4-43 T2CON — Timer 2 Con t r ol Regis ter E8H Set1 Ban k1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu e 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/ W R/W R/W R/W R/W Addressing Mode Register ad dressin g mode o nly .7 and .
S3F80JB INTERRUPT STRUCTURE 5-1 5 INTERRUPT STRUCTURE OVERVIEW The S3C8/S3F8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors.
INTERRUPT STRUCTURE S3F80JB 5-2 INTERRUPT TYPES The three components of the S3C8/S3F8-series interrupt structure described above — levels, vectors, and sources — are combined to determine the interrupt struct ure of an individual device and to make full use of its available interrupt logic.
S3F80JB INTERRUPT STRUCTURE 5-3 The S3F80JB microcontroller supports tw enty-four interrupt sources. Sixt een of the interrupt sources have a corresponding interrupt vector address; the remaining eight interrupt sources share by two vector address.
INTERRUPT STRUCTURE S3F80JB 5-4 Vectors(18) Sources (24) Levels(8 ) IRQ0 Timer 0 match/captur e 0 1 Reset/Cl ear RESET 100H Basic t imer overflow FCH IRQ2 ECH Counter A S/W H/W H/W F4H IRQ1 F6H 0 1 Timer 0 ov er flow FAH Timer 1 match/capture Timer 1 ov er flow S/W H/W H/W F0H IRQ3 F2H 0 1 Timer 2 match/capture Timer 2 ov er flow S/W H/W D6H P2.
S3F80JB INTERRUPT STRUCTURE 5-5 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3F80JB interrupt structure are stored in the vector address area of the internal program memory ROM, 00H–FFH (See Figure 5-3). You can allocate unused locations in the vector address area as normal program memory.
INTERRUPT STRUCTURE S3F80JB 5-6 Table 5-1. S3F80JB Interrupt Vectors Vector Address Interrupt Source Request Reset/Clear Decimal Value Hex Value Interrupt Level Priority in Level H/W S/W 256 100H Basi.
S3F80JB INTERRUPT STRUCTURE 5-7 ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) Executing the Enable Interrupts (EI) in struction globally enables the interrupt structure. All interrupts are then serviced as they occur, and accordi ng to the established priorities.
INTERRUPT STRUCTURE S3F80JB 5-8 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways : globally or by a specific interrupt level and source.
S3F80JB INTERRUPT STRUCTURE 5-9 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more correspondi ng peripheral control register s that let you control the interrupt generated by that peripheral (See Table 5-3). Table 5-3.
INTERRUPT STRUCTURE S3F80JB 5-10 SYSTEM MODE REGISTER (SYM) The system mode register, SYM (DEH, Set 1, Bank0), is used to globally enable and disable interrupt processing and to control fast interrupt processing (See Figure 5-5). A reset clears SYM.7, SYM.
S3F80JB INTERRUPT STRUCTURE 5-11 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (DDH, Set 1, Bank0) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit va lues are undetermined and must therefore be written to their required settings by the initialization routine.
INTERRUPT STRUCTURE S3F80JB 5-12 INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (FFH, Set 1, Bank 0), is used to set the relati ve priorities of the interrupt levels used in the microcontroller’s interrupt structure.
S3F80JB INTERRUPT STRUCTURE 5-13 Interrupt Priority Register (IPR) FEH, Set 1, Bank 0 , R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB L S B Group A 0 = IRQ0 > IRQ1 1 = IRQ0 < IRQ1 Subgroup B (see note) 0 = IR.
INTERRUPT STRUCTURE S3F80JB 5-14 INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register , IRQ (DCH, Set 1, Bank0), to monitor interrupt request status for all levels in the microcontroller’s interrupt stru cture.
S3F80JB INTERRUPT STRUCTURE 5-15 INTERRUPT PENDING FUNCTION TYPES Overvi ew There are two types of interrupt pending bits: One type is automatically cleared by hardware after the interrupt service routine is acknowledged and exec uted; the other type must be cleared by the interrupt service routine.
INTERRUPT STRUCTURE S3F80JB 5-16 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifie s a pending condition for that source.
S3F80JB INTERRUPT STRUCTURE 5-17 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (except smart option ROM Cell- 003CH, 003DH, 003EH and 003FH) contains the addresses of interrupt service routines t hat correspond to each level in the interrupt structure.
INTERRUPT STRUCTURE S3F80JB 5-18 FAST INTERRUPT PROCESSING (Continued) Two other system registers suppor t fast interrupt processing: — The instruction pointer (IP) contai ns the starting address of.
S3F80JB INSTRUCTION SET 6-1 6 INSTRUCTION SET OVERVIEW The SAM8 instruct ion set is speci fically designed t o supp or t t he large register fi les th at are ty pical of most SAM8 microcontrollers.
INSTRUCTION SET S3F80JB 6-2 Table 6-1. In struc ti o n Gr oup S u mmary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst, src Load LDB dst, src Load bit LDE dst, src Load externa l.
S3F80JB INSTRUCTION SET 6-3 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Ins tructions ADC dst,src Add with carry ADD dst,src Add CP dst,src Compare DA dst.
INSTRUCTION SET S3F80JB 6-4 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and jump r elative on fals e BTJRT dst,sr.
S3F80JB INSTRUCTION SET 6-5 Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions RL dst Rota te left RLC dst Rotate left thr ough c arry RR dst .
INSTRUCTION SET S3F80JB 6-6 FLAGS REGISTER (FLAGS) The flags regist er FLA G S contains eig ht bits that describ e th e curr en t status of CPU op era t i ons. Four of these bits, FLAGS. 7–FLAGS.4, can be test ed and used wit h conditional jump instruction s; two othe rs FLAGS.
S3F80JB INSTRUCTION SET 6-7 FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result fr om an arit hmetic operation gen er at es a carry-out from or a borrow to the bit 7 position (MS B). After rotate and shift ope rat io ns, it contains the last v alue shifted out of the specified register.
INSTRUCTION SET S3F80JB 6-8 INSTRUCTION SET NOTATI ON Table 6-2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag D Decimal-adjust flag H Half-carry flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared accor din g to operation – Value is unaffected x Value is undefined Table 6-3.
S3F80JB INSTRUCTION SET 6-9 Table 6-4. Instruc ti on Notation Conventions Notation Description Ac tual Operand Range cc Condition code See list of condition codes in Tabl e 6-6. r Working regis ter only Rn (n = 0– 15) rb Bit (b) of working regist er Rn.
INSTRUCTION SET S3F80JB 6-10 Table 6-5. Opcode Quick R eference OPCODE MAP LOWER NIBBLE (HEX) – 0 1 2 3 4 5 6 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM BOR r0–Rb P 1 RLC R1 RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM BCP r1.
S3F80JB INSTRUCTION SET 6-11 Table 6-5. Opcode Quic k Refer ence (Continued) OPCODE MAP LOWER NIBBLE (HEX ) – 8 9 A B C D E F U 0 LD r1,R2 LD r2,R1 DJNZ r1,RA JR cc,RA LD r1,IM JP cc,DA INC r1 NEXT .
INSTRUCTION SET S3F80JB 6-12 CONDITION CODES The op-c ode of a con ditional jump alwa ys contains a 4-bit field called the cond it ion code (cc). This specifies under which condition s it is to e xecute the ju mp.
S3F80JB INSTRUCTION SET 6-13 INSTRUCTION DESCRI PTI ONS This section contain s det ail ed information and programming exa mples for each instruct ion in the SAM8 instruction set . I nf ormation is arrange d in a consistent forma t f or im pro ve d readability a nd for fast refer encin g.
INSTRUCTION SET S3F80JB 6-14 ADC — Add with carry ADC ds t,src Operation: dst ← dst + src + c The source ope ran d, along with the sett in g of the carry fl ag , is added to the destin at ion operand and the sum is store d in t he destination. The cont ents of the source are una ffected.
S3F80JB INSTRUCTION SET 6-15 ADD — Add ADD dst,src Operation: dst ← dst + s rc The source operand is add ed t o the destinatio n operand and the sum is stor ed in the destinat ion . The conten ts of the s ource a re unaffec ted. Two's-c omplement ad dition is pe rformed.
INSTRUCTION SET S3F80JB 6-16 AND — Logical AND AND ds t,src Operation: dst ← dst AND src The source ope ran d is log ically ANDed with the dest ina ti on operand.
S3F80JB INSTRUCTION SET 6-17 BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) ← dst( 0) AND src (b) or dst(b) ← ds t(b) AN D sr c(0) The specified bit of th e sourc e (or the destination ) is logically ANDed w ith the zer o bit (LSB) o f the destination (or source ).
INSTRUCTION SET S3F80JB 6-18 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit o f the sou rce is comp ared to ( subtrac ted from) bit ze ro (LSB) of th e destinatio n. The zero flag is set if t he bits are the same; otherwise it is cleared.
S3F80JB INSTRUCTION SET 6-19 BITC — Bit Complem en t BITC dst .b Operation: dst(b) ← NOT dst(b) This instruction comp leme nt s the specified bit wit hin the destinat i on with ou t affecting any ot her bits in the destinat io n. Flags: C: Unaffecte d.
INSTRUCTION SET S3F80JB 6-20 BITR — Bit Rese t BITR dst.b Operation: dst(b) ← 0 The BITR ins truction clears th e specifie d bit within th e destinatio n without a ffecting an y other bits in the destin ation.
S3F80JB INSTRUCTION SET 6-21 BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction sets the s pecified bit within the destin ation without a ffecting any othe r bits in the destination .
INSTRUCTION SET S3F80JB 6-22 BOR — Bit OR BOR d st,src .b BOR d st.b,sr c Operation: dst(0) ← ds t(0) O R src (b) or dst(b) ← dst(b) OR sr c(0) The specified bi t of the sou rce (or the des tination) is logically OR ed with b it zero (L SB) of the destination (or the sour ce).
S3F80JB INSTRUCTION SET 6-23 BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC ← PC + dst The specif ied bit within th e sou rce op er and i s test ed .
INSTRUCTION SET S3F80JB 6-24 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src .b Operation: If sr c(b) is a "1", th en PC ← PC + ds t The specified bit within the source ope ran d is te ste d.
S3F80JB INSTRUCTION SET 6-25 BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst( 0) XOR src( b) or dst(b) ← ds t(b) XO R src (0) The spec if ied bit of the source (or t he destinatio n) is log i cal ly exclusive- ORe d wit h bit zero (LSB) of the destin at i on (or sou rce).
INSTRUCTION SET S3F80JB 6-26 CALL — Call Procedu re CALL dst Operation: SP ← SP – 1 @SP ← PCL SP ← SP –1 @SP ← PCH PC ← dst The current conten ts of the program count er are p ushe d on to th e top of the stack. The pro gram counter value u sed is th e ad dre ss of the first inst ru ctio n f ollowing the CALL inst ru ctio n.
S3F80JB INSTRUCTION SET 6-27 CCF — Complement C arry Flag CCF Operation: C ← NOT C The carr y flag (C ) is comple mented. If C = "1", th e value of th e carr y flag is ch anged to log ic zero; if C = "0", the value of the carry flag is changed to logic one.
INSTRUCTION SET S3F80JB 6-28 CLR — Clear CLR dst Operation: dst ← "0" The destination loc a tion is clear ed to "0". Flags: No flags are affected.
S3F80JB INSTRUCTION SET 6-29 COM — Compleme nt COM dst Operation: dst ← NOT dst The cont e nt s of the destination l ocat i o n are compl emented (one's complement); all "1s" a re changed to "0s" , an d v i ce- ve rsa. Flags: C: Unaffecte d.
INSTRUCTION SET S3F80JB 6-30 CP — Compare CP dst,src Operation: dst – src The source ope ran d is comp are d to (subtracted f rom) th e dest ination operand, and the appropriate flags are set accordingly. The content s of both operands are u naffected b y the comparison.
S3F80JB INSTRUCTION SET 6-31 CPIJE — Compare, Increment, and Jum p on Equal CPIJE dst,src,RA Operation: If ds t – src = "0" , PC ← PC + RA Ir ← Ir + 1 The source op erand is compared to (subt racted from) the dest ination operan d.
INSTRUCTION SET S3F80JB 6-32 CPIJNE — Compare, Increment, and Jum p on Non-Eq ua l CPIJNE d st,src ,RA Operation: If ds t – src "0", P C ← PC + RA Ir ← Ir + 1 The source ope ran d is comp are d to (subtracted f rom ) the destinat ion ope rand.
S3F80JB INSTRUCTION SET 6-33 DA — Decimal Adjust DA dst Operation: dst ← DA d st The destinat io n op era nd is adju st e d to fo rm two 4-bit BCD digits fo llo wing an ad dit ion or subtraction opera t ion. For addition (A DD, ADC) or subtraction (SUB, SBC) , t he following table indicates the opera tion performed .
INSTRUCTION SET S3F80JB 6-34 DA — Decimal Adjust DA (Continu ed) Example: Given: Wor king regis ter R0 co ntains the va lue 15 (BCD ), working register R1 contains 27 (BCD) , an d ad dre ss 27H cont.
S3F80JB INSTRUCTION SET 6-35 DEC — Decrement DEC dst Operation: dst ← dst – 1 The conten ts of the d estination operand a re decre mented by one. Flags: C: Unaffecte d. Z: Set if the result is "0"; cleared ot he rwise. S: Set if re sult is negati ve; cleared otherwise.
INSTRUCTION SET S3F80JB 6-36 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The cont en ts of the destinat io n loca ti on (which must be an even address) and the ope ran d following that l ocat io n are treated as a single 16 -bit v a lue that is decremen t ed by one.
S3F80JB INSTRUCTION SET 6-37 DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system mod e control register, SY M.0, is cleared to "0", globally disabli ng all interrupt processing.
INSTRUCTION SET S3F80JB 6-38 DIV — Divide (Unsigned) DIV dst,s rc Operation: dst ÷ src dst (UPPER) ← REMA INDER dst (LOWER) ← QUOTI ENT The dest ina t ion operand (16 bit s) is di v i de d by the source operand (8 bi ts). The quotient (8 bits) is stored in the lower half of the destination.
S3F80JB INSTRUCTION SET 6-39 DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation: r ← r – 1 If r ≠ 0, PC ← PC + dst The work ing regi ster being used as a cou nt er is decre mented.
INSTRUCTION SET S3F80JB 6-40 EI — Enable Interrupts EI Operation: SYM (0) ← 1 An EI instruct ion sets bi t zero of the system mode regi ste r, SYM. 0 to "1". This allows interrupts to be serviced as they occur (a ssumin g they have hig he st priority).
S3F80JB INSTRUCTION SET 6-41 ENTER — Enter ENTER Operation: SP ← SP – 2 @SP ← IP IP ← PC PC ← @IP IP ← IP + 2 This inst ru ctio n is useful when imple m ent in g t hreaded-code languages. The conten ts of the instruction point er are pushed to the sta ck.
INSTRUCTION SET S3F80JB 6-42 EXIT — Exit EXIT Operation: IP ← @SP SP ← SP + 2 PC ← @IP IP ← IP + 2 This instructi on is useful when implementing thread ed -cod e lan guages. The stack value is popped and load ed in to th e inst ruction pointer.
S3F80JB INSTRUCTION SET 6-43 IDLE — Idle Operation IDLE Operation: The IDLE instruction stop s the CPU cloc k while allowing system clock oscillation to continue. Idle mode can be released by an in terrupt reque st (I RQ) or an ex ternal reset oper ation.
INSTRUCTION SET S3F80JB 6-44 INC — Increm ent INC dst Operation: dst ← dst + 1 The contents of th e de stination op era nd are in creme nt ed by one. Flags: C: Unaffec ted. Z: Set if th e result is "0"; cleared otherwis e. S: Set if the result is ne gat iv e; cleared otherwise.
S3F80JB INSTRUCTION SET 6-45 INCW — Increment W o rd INCW dst Operation: dst ← dst + 1 The cont e nt s of the destination (which must b e an eve n address) and the by t e following that location are treat ed as a single 16-bit v alu e t hat is incremente d by on e.
INSTRUCTION SET S3F80JB 6-46 IRET — Interrupt Return IRET IRET (Norma l) IRET (F ast) Operation: FLAG S ← @SP PC ↔ IP SP ← SP + 1 FLAG S ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instructi on is used at the end of an interrupt serv ice routine.
S3F80JB INSTRUCTION SET 6-47 JP — Jump JP cc,dst (Conditional) JP dst (Uncon ditional) Operation: If c c is true, PC ← dst The condit ional JUMP instruct io n tr ansfers program control to the des.
INSTRUCTION SET S3F80JB 6-48 JR — Jump Re la tive JR cc,dst Operation: If cc is true , PC ← PC + dst If t he con dition specifi ed by th e condition code (cc) is tru e, the relativ e add re ss is .
S3F80JB INSTRUCTION SET 6-49 LD — Load LD dst,src Operation: dst ← src The contents of the source are load ed i nt o th e de stination. The sou rce's cont ents are unaff ected.
INSTRUCTION SET S3F80JB 6-50 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, regist e r 01H = 20 H, register 02H = 02H, LOO P = 30H, an d register 3AH = 0FFH: LD R0.
S3F80JB INSTRUCTION SET 6-51 LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) ← src(b) or dst(b) ← src(0) The spec if ied bit of the source is loade d int o bit zero (LSB) of the destin at ion, or bit zero of the source is loaded into the spe cifi ed bit of the destination.
INSTRUCTION SET S3F80JB 6-52 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ← src This instruc tion loads a byte from p rogram or data memory in to a work ing regis ter or vice -versa. The sourc e values ar e unaffected. L DC refers to program memor y and LDE to data memory.
S3F80JB INSTRUCTION SET 6-53 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locat ion s 0103H = 4FH, 0104H = 1A , 01 05 H = 6DH, and 1 104 H = 88H.
INSTRUCTION SET S3F80JB 6-54 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ← src rr ← rr – 1 These inst ru ct io ns are used f o r user st acks or bl ock transfers of da ta fro m pro gra m or d ata memory to the reg i st er f ile.
S3F80JB INSTRUCTION SET 6-55 LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ← src rr ← rr + 1 These instru ctions are used fo r user s tacks or block transfer s of data from pro gram or d ata memory to the regist er file.
INSTRUCTION SET S3F80JB 6-56 LDCPD/LD EPD — Load Memor y w it h Pre-Decrem ent LDCPD/ LDEPD ds t,src Operation: rr ← rr – 1 dst ← src These inst ru ctio ns are used for block tran sfe rs of data from prog ram or data memory from the register file.
S3F80JB INSTRUCTION SET 6-57 LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src Operation: rr ← rr + 1 dst ← src These inst ructions are used for block transfers of da t a fr om pr ogram or data memory fr om the register file.
INSTRUCTION SET S3F80JB 6-58 LDW — Load Wo rd LDW dst,src Operation: dst ← src The contents of th e sou rce (a word ) are load ed int o the destinatio n.
S3F80JB INSTRUCTION SET 6-59 MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← dst × src The 8-bit destination operand (even re gist er of the regist e r pai r) is multiplied by the source operand (8 bits) a nd the pr oduct (16 b its) is s tored in the register pair spec ified by the destination address.
INSTRUCTION SET S3F80JB 6-60 NEXT — Next NEXT Operation: PC ← @ IP IP ← IP + 2 The NEXT in stru cti on is useful when implemen ting threaded -cod e lan gu ag es. The program memory word that is poin te d t o by the instructio n po int er is loaded into th e pro gr am cou nt er.
S3F80JB INSTRUCTION SET 6-61 NOP — No Operati o n NOP Operation: No action is performed whe n th e CPU executes this ins truction. Typically, on e or more NOPs ar e executed in s equence in order to effect a timing d elay of variable duration. Flags: No flags are aff ect ed.
INSTRUCTION SET S3F80JB 6-62 OR — Logical OR OR dst,s rc Operation: dst ← dst O R src The source ope ran d is log i cally O Red wit h the destinat ion oper an d an d th e re sult is stored in the destination. The contents of the sou rce are unaffected.
S3F80JB INSTRUCTION SET 6-63 POP — Pop From Stack POP dst Operation: dst ← @SP SP ← SP + 1 The cont e nt s of the location ad dre ssed b y t h e stack pointer are lo ad ed in to the destination . Th e stack p ointer is th en incremen ted by on e.
INSTRUCTION SET S3F80JB 6-64 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src IR ← IR – 1 This instructi on is used for user-defined stacks in the registe r f ile. The contents of the register file location addr essed by th e user stack point e r are loaded into th e destination .
S3F80JB INSTRUCTION SET 6-65 POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst ← src IR ← IR + 1 The POPUI instru ction is used for user-d ef ined stacks in the registe r f ile. The content s of t h e register file locati on addressed by the user stack pointer are load ed into the destin at ion .
INSTRUCTION SET S3F80JB 6-66 PUSH — Push To Stack PUSH src Operation: SP ← SP – 1 @SP ← src A PUSH inst ru ctio n decrements the sta ck poin te r v alu e an d loads the content s of the sour ce (src) into the locat i o n ad dre ssed by the decrem en te d sta ck pointer.
S3F80JB INSTRUCTION SET 6-67 PUSHUD — Push User Stack (D ecrementing) PUSHUD dst,src Operation: IR ← IR – 1 dst ← src This inst ru ctio n is used to address user-defi ned stacks in the register fi le.
INSTRUCTION SET S3F80JB 6-68 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← IR + 1 dst ← src This instructi on is used for user-defined stacks in the registe r f ile.
S3F80JB INSTRUCTION SET 6-69 RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is cleared to lo gic zero , re ga rdless of its prev iou s val ue.
INSTRUCTION SET S3F80JB 6-70 RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction is normally used to return to the previously executing pr ocedure at the end of a procedure ente red by a CA LL inst ruction. The conte nts of the locat io n addressed by the st ack pointer are popped into the program cou nt er.
S3F80JB INSTRUCTION SET 6-71 RL — Rotate Le ft RL dst Operation: C ← ds t (7) dst (0) ← dst ( 7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destina tion opera nd are r otated left one bit pos ition. The in itial value of bit 7 is moved to th e bit zer o (LSB) pos ition and a lso repla ces the carry flag .
INSTRUCTION SET S3F80JB 6-72 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ← C C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The cont en ts of th e destination op era nd with the carry f l ag are ro ta te d le ft one bit posit io n.
S3F80JB INSTRUCTION SET 6-73 RR — Rotate Right RR dst Operation: C ← ds t (0) dst (7) ← dst (0) dst (n ) ← dst (n + 1), n = 0–6 The contents of the destina tion opera nd are r otated ri ght one bit position. The initial value o f bit zero (LSB) is mov ed to bit 7 (MSB) and also re places the carry fl a g (C).
INSTRUCTION SET S3F80JB 6-74 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ← C C ← dst (0) dst (n) ← d st (n + 1), n = 0–6 The cont en ts of the destinat io n op era nd and the carry f l ag are ro ta ted right one bit position.
S3F80JB INSTRUCTION SET 6-75 SB0 — Selec t Bank 0 SB0 Operation: BANK ← 0 The SB 0 in str uct ion clears the bank address fl a g in t he FLAG S re gist er (FLAGS.0) to logic zer o, selecting bank 0 regist er addressing in the set 1 area of the re gist er f ile.
INSTRUCTION SET S3F80JB 6-76 SB1 — Select B ank 1 SB1 Operation: BANK ← 1 The SB1 instruc tion sets th e bank ad dress fla g in the FLAGS r egister (FL AGS.0) to logic one, selecting bank 1 regist er addressing in the set 1 ar ea of t he regi ster file.
S3F80JB INSTRUCTION SET 6-77 SBC — Subtract With Carry SBC dst,src Operation: dst ← dst – src – c The sou rce op er and , along with the cur ren t v alu e of the carry fl a g, is subtracted fro m th e destination ope ran d an d the result is stored in the destination .
INSTRUCTION SET S3F80JB 6-78 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag ( C) is set to logic one, regar dless of its previous value. Flags: C: Set to "1 ". No oth er f lags are affect ed . Format: Bytes Cycles Opcode (Hex) opc 1 4 DF Example: The state ment SCF set s the carry flag to lo gic one.
S3F80JB INSTRUCTION SET 6-79 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ← ds t (7) C ← d st (0) dst (n) ← dst (n + 1), n = 0–6 An arithme tic shift-right of one bit position is performed on the dest ina tion operand. B it zero (the LSB) repl aces the carry fla g.
INSTRUCTION SET S3F80JB 6-80 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 1.
S3F80JB INSTRUCTION SET 6-81 STOP — Stop Operation STOP Operation: The STOP instruct ion stops the both the CPU clock and system clock and causes the microcontroller to ent e r Stop mode. Durin g St op mode, the cont ents of on-chip CPU reg isters, peripheral reg isters, and I /O port control and dat a registers a re retained.
INSTRUCTION SET S3F80JB 6-82 SUB — Subtract SUB ds t,src Operation: dst ← dst – src The source ope ran d is subt racted from the dest ina tion operand and the result is stored in t he destination. The con t e nt s of the source are unaffect ed .
S3F80JB INSTRUCTION SET 6-83 SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) The con te nt s of the lower fo ur bi ts and upper four bi ts of the destinat ion operand are swapped. 70 4 3 Flags: C: Undefined. Z: Set if the result is "0"; cleared ot he rwise.
INSTRUCTION SET S3F80JB 6-84 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src This instructi on tests selected bits in the destinat ion ope rand for a logic one v alu e. The b its to be tested are specifi ed by setting a "1" bit in the correspond ing posit ion of the source operand (mask).
S3F80JB INSTRUCTION SET 6-85 TM — Test Under Mask TM dst,src Operation: dst AND s rc This instruction test s selected bits in the de stination oper and for a lo gic zero valu e.
INSTRUCTION SET S3F80JB 6-86 WFI — Wait For Interrupt WFI Operation: The CP U is effectively halted until an interrupt occurs , except that DMA tr ansfers can still take place during this wait sta te . The WFI status can be rel eased by an intern al in te rru pt, including a fast interr u pt .
S3F80JB INSTRUCTION SET 6-87 XOR — Logical Exclusive OR XOR dst,src Operation: dst ← ds t XOR s rc The source op er and is logically exclusive -O Red wit h the destinati on operand and the result is stored in the destinat io n.
S3F80JB CLOCK CIRCUITS 7-1 7 CLOCK CIRCUITS OVERVIEW The clock frequency fo r the S3F80JB can be gen era ted by an ext ernal crystal or suppli ed by an external clock source. The clock fr equency for t he S3F80JB ca n range from 1 MHz to 8 MHz. The maximum CP U clock frequency , as determine d by CLKCON r egister, is 8 MHz .
CLOCK CIRCUITS S3F80JB 7-2 CLOCK STATUS DURING POWE R-DOWN MODES The two power-down modes, Stop mode and Id le mod e, affect the syst em clock as follows: — In Stop mode, the main oscillator is halted. When stop mode is released, the oscilla tor starts by a reset operation or b y an ex ternal interru pt .
S3F80JB CLOCK CIRCUITS 7-3 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system c lock con trol regist er , CLKCON , is located in ad dress D4H, Set1, Bank 0. It is rea d/write add r essab le and has the followin g fu nctions: — Osc illator freq uency di vide-by value The CLKCON.
S3F80JB RESET 8-1 8 RESET OVERVIEW Resettin g th e MCU i s th e f u nction to star t p roce ssing by generati ng reset signal usin g sev e ra l reset schemes. During res et, most co ntrol and status a re forced to initial valu es and the program c ounter is loa ded from the reset vector.
RESET S3F 80JB 8-2 nRESET Watchdog Timer (smart opt ion bit [7] @03FH) IPOR / LVD Contorl B it ' 1' STOP (EI)external in terrupt enable P 0&P2 (INT0-INT9) STOP IPOR / LVD C onto rl Bit &.
S3F80JB RESET 8-3 P0&P2 (INT0~INT9) Nois e Filter External I nterrup t Control Block P0& P2 STOP STOPCON IPOR / LVD Control Bit '1' smart option bi t[7 ] @03FH Enabled INT0 ~INT9 SED&R Circuit P0& P2.
RESET S3F 80JB 8-4 RESET MECHANISM The interloc king work of reset pin and LVD c ircuit supplie s two oper ating modes: bac k-up mode input, and s ystem reset input. B ack-u p mo de inp ut automati call y creates a chip stop state when th e re set pin is set to low level or the voltage at V DD is lower than V LVD .
S3F80JB RESET 8-5 NOTES 1. IPOR / LVD Control Bit is one of smart option bits assigned addr ess 03FH. User can enable / disa ble LVD in the stop mode by manipula ti ng this bit. Whe n t he va lue is ‘1’, LVD alway s op er ate in the normal and stop mode.
RESET S3F 80JB 8-6 Voltage [V] Tim e Reset pulse Va Reset Pulse W idth V DD V IH = 0.85 V DD V IL = 0.4 V DD T VDD = 1ms (V DD Rising Time) V DD Figure 8-5. Timi ng Diagram for Internal Powe r-On Reset Circui t NOTE The system reset operation de pe nds on the inte rlo cki ng work o f t he reset pin, LVD circu it and Int ern al POR.
S3F80JB RESET 8-7 V LVD V DD 0.4V DD a. System reset is not occurred. b. System reset is occurred by internal POR circuit. If "Vreset > VIH", the operating status is in STO P mode and IPOR / LVD control bit of smart option is '0', LVD circuit is disabled in the S3F80J B.
RESET S3F 80JB 8-8 STOP ERROR DETECTION & RECOVE RY When IPOR /LVD Con trol Bit (smar t option bit [7] @ 03FH) is set to ‘0’and ch ip is in stop or abnor mal state, th e falling edge input of P0 and P2.4 -P2.7 generates the reset signal. Refer to follo wing ta ble an d f igure for more information.
S3F80JB RESET 8-9 POWER-DOWN MODES The power down mode of S3F80JB are described following that: — Idle mode — Back- up mode — Stop mode IDLE MODE Idle mode is inv oke d b y t h e instruction IDL E (o p- cod e 6FH ). In Idle mode, CP U op er ations are halt ed while some peripheral s remain ac tive.
RESET S3F 80JB 8-10 BACK-UP MODE For reducing current consumpt ion, S3F80JB goes into Back- up mode. If external reset pi n is low state or a falling level of V DD is detected by LV D circuit on the point of V LVD , chip go es in to the back-up mode .
S3F80JB RESET 8-11 STOP MODE STOP mode i s inv oke d b y executing t he inst ruction ‘STOP’, after set ting the stop control regist er (STO P C ON). In STOP mode, the operation of the CP U an d all peripherals is halt ed. That is, the on-chip main oscillator stops and the current consu m pt ion can be reduced.
RESET S3F 80JB 8-12 SOURCES TO RELEASE ST OP MODE Stop mode is relea sed whe n f ollowing sources go act i v e: — System Res et by extern al reset pin (nRESET) — System Re set by I nterna l Power .
S3F80JB RESET 8-13 SED&R (Stop Error Detect and Recovery) The Stop Error Detect & Recover y circuit is used to re lease stop mode and p revent abno rmal - stop mod e that can be oc curred by battery bo uncing. It e xecutes tw o functions in related to the inte rnal logic o f P0 and P2.
RESET S3F 80JB 8-14 SYSTEM RESET OPERATION System reset starts the oscilla tion circuit, synchronize ch ip operation with CPU clock, and initialize the internal CPU and pe ripheral mod ules. This pr ocedure b rings the S3F8 0JB into a kno wn operatin g status.
S3F80JB RESET 8-15 HARDWARE RESET V ALUE S Tables 8-3 list th e re set values for CP U an d sy stem registe rs, pe rip heral control reg i st ers, and periph er al d at a registers fo llowing a re set operation .
RESET S3F 80JB 8-16 Table 8-3. Se t 1, Bank 0 Register Values After Re set (Continued) Address Bit Values Afte r Re se t Register Name Mnemonic Dec Hex 7 6 5 4 3 2 1 0 Port 1 Control Register (High By.
S3F80JB RESET 8-17 Table 8-4. Se t 1, Bank 1 Register Val ues After Reset Address Bit Va lue s After Re se t Register Name Mnemonic Dec Hex 7 6 5 4 3 2 1 0 LVD Control Register LVDCON 224 E0H – – .
RESET S3F 80JB 8-18 Table 8-5. Reset Generation Accordi ng to the Condition of Smart Option Smart option7th bit @3FH Mode Reset Source 1 0 Reset Pin O Reset O Reset Watch Dog Time r Enable O Reset O R.
S3F80JB RESET 8-19 RECOMMENDATION FOR UNUSUED PINS To reduce overall power consumptio n, please configure unused pins according to the guideline descript ion Table 8-6.
RESET S3F 80JB 8-20 SUMMARY TABLE OF BACK-UP MODE, S TOP MODE, AND RE SE T STATUS For more un derstanding, pl ease see th e below des cription Ta ble 8-7.
S3F80JB I/O PORTS 9-1 9 I/O PORTS OVERVIEW The S3F80JB m i cro con tr olle r has two kinds of pa ckag e an d d ifferent I / O num b er relating to th e p ackage type: 44-QFP package ha s f iv e bit-programma ble I/ O ports, P0–P3 and P4. Four p or ts, P0–P2 and P4, are 8-bit port s and P3 is a 6- bit port.
I/O PORTS S3F 80JB 9-2 Table 9-1. S3F80JB P ort Conf iguration Overview (44-QFP) Port Configuration Options Port 0 8-bit gen era l-p urpose I/O po rt ; Input or push-p ul l output; ex te rnal interrup.
S3F80JB I/O PORTS 9-3 Table 9-3. S3F80JB Port Conf iguration Overview (32-SOP) Port Configuration Options Port 0 8-bit gene ra l-p ur po se I /O port; Input or push-pull out put; exte rn al in terrupt.
I/O PORTS S3F 80JB 9-4 PORT DATA REGI S TERS Table 9-4 gi v es y ou an overvie w of the register lo cat i o ns of all four S3F80JB I/O port dat a registers. Dat a registers f or port s 0 ,1 ,2 and 4 have th e general forma t shown in Fig ure 9-1. NOTE The data regist e r for port 3, P3 , co ntains 6-bits fo r P3.
S3F80JB I/O PORTS 9-5 PULL-UP RESISTOR E NABLE REGI STE RS You can as sign pull-up resistor s to the p in circu its of individual pins in port0 and p ort2. To do this , you make th e appropriat e settings to t he correspondin g pu ll-u p resistor enabl e re gist ers; P0PUR and P2PUR.
S3F80JB BA S IC TIMER and TIMER 0 10-1 10 BASIC TIMER and TIMER 0 OVERVIEW The S3F80JB has two default time rs: the 8-bit bas ic timer and the 8 -bit gener al-purpo se timer/c ounter.
BASIC TIMER and T IMER 0 S3F 80JB 10-2 BASIC TIMER CONTROL REGI STER (BTCON) The basic timer con trol re gi ster, BTCON, is used to sele ct t he inp ut clock frequency , t o cle ar t he ba sic timer counter an d freque ncy dividers, an d to enab le or disable the watch- dog timer fu nction.
S3F80JB BA S IC TIMER and TIMER 0 10-3 BASIC TIMER FUNCTION DE SCR IP TION Watch-dog Timer Function You can pr ogram the basic timer o verflow sig nal (BTOVF) to ge nerate a reset by se tting BTCON.7– BTCON.4 to any val ue other th an '1010B'.
BASIC TIMER and T IMER 0 S3F 80JB 10-4 TIMER 0 CONTROL REGISTER (T0 CON) You use the t imer 0 control regi ster, T0CON, to — Select the timer 0 operating mode (i nterval time r, capture mode, or PWM.
S3F80JB BA S IC TIMER and TIMER 0 10-5 Ti mer 0 Cont rol Registe r (T 0CO N ) D2H, Set 1, Bank0 , R/W .7 .6 .5 .4 .3 .2 .1 .0 MS B LS B Timer 0 Inter rupt Pending Bit: 0 = No interrupt pending 0 = Cle.
BASIC TIMER and T IMER 0 S3F 80JB 10-6 TIMER 0 FUNCTION DE SCR IP TION Timer 0 Interru pts (IRQ0, Vectors FAH and FCH) The timer 0 modu le can generat e tw o in terrupts: th e t imer 0 overflow interrupt (T0OVF), and th e t imer 0 match/ capture inter rupt (T0INT) .
S3F80JB BA S IC TIMER and TIMER 0 10-7 Pulse Width Modulation Mode Pulse width mo dulation (PWM) mode lets yo u program th e width (duration) of t h e pulse that is o utput at t he T0PWM pin. As in in te rv a l timer mode, a mat ch signal is generate d wh en t h e cou nt e r value is identica l to th e value written to the timer 0 data re gister.
BASIC TIMER and T IMER 0 S3F 80JB 10-8 Capture Mode In capture mode, a sig nal edge th at is detected a t the T0CAP pin opens a gate and lo ads the c urrent co unter value into the T0 data reg ister. You can selec t rising or falling e dges to tr igger this operation.
S3F80JB BA S IC TIMER and TIMER 0 10-9 MUX MUX DIV R 8-Bit Up-Counter (T0CNT) 8-Bit Compatator Timer 0 Buffer Register Bits 5, 4 Bit 0 Bit 1 IRQ0 Clear Data Bus Bit 0 IRQ0 OVF 8-Bit Up Counte r (BTCNT , Read-Only) DIV R X IN X IN OVF RESET Data Bus Clear W hen BTCNT.
BASIC TIMER and T IMER 0 S3F 80JB 10-10 PROGRAMMING TIP — Confi guring the Basic Timer This exampl e sho ws ho w to con figure the basi c time r to sample specifi cations: ORG 0100H RESET DI ; D.
S3F80JB BA S IC TIMER and TIMER 0 10-11 PROGRAMMING TIP — Programming Timer 0 This sample pr ogram sets timer 0 to inter val timer mode, s ets the fr equency o f the oscilla tor clock , and determines t he ex ecution sequen ce wh ich follows a time r 0 interrupt.
BASIC TIMER and T IMER 0 S3F 80JB 10-12 PROGRAMM ING TIP — Program ming Timer 0 (Continued) CP R0,#32H ; 50 × 4 = 200 ms JR ULT,NO_200MS_SET B I T S R 1 .
S3F80JB TIMER 1 11-1 11 TIMER 1 OVERVIEW The S3F80JB microcont ro lle r has a 16-bit timer/co un te r calle d Timer 1 (T1). For universal remot e con tr olle r applications, Ti mer 1 can be u sed t o ge nerate the env elo pe pattern for th e remo t e controller signal.
TIMER 1 S3F80JB 11-2 TIMER 1 OVERFLOW INTERRUPT Timer 1 can be programmed to gen era te an ov erflow interru pt (IRQ1, F4H) whenev er an ov er flow occurs in the 16-bit up coun te r.
S3F80JB TIMER 1 11-3 TIMER 1 MATCH INTERRUPT Timer 1 can also be used to gen era t e a match interrupt (IRQ1, vector F6H) when ever the 16-bit coun ter value matches the value th at is written to the Time r 1 refer ence data r egisters , T1DATAH an d T1DATAL.
TIMER 1 S3F80JB 11-4 MUX 16-Bit Up-Counter (Read-Only) 16-Bit Compatator Timer 1 High/L ow Buffer Regist er MUX IRQ1 Clear IRQ1 Mat c h (note) NOTE: Match signal is occurrd only in int erval mode. T1CON. 7-.6 T1CON.2 T1CON.3 Match Signa l T1OVF Data Bus Time r 1 Data High/Low Register CAOF (T-F/F) f OSC /16 f OSC /8 f OSC /4 R OVF T1CON.
S3F80JB TIMER 1 11-5 TIMER 1 CONTROL REGISTER (T1 CON) The Timer 1 control reg ist er, T1CON, is located in Set 1, FAH, Bank0 and is read/write add re ssable .
TIMER 1 S3F80JB 11-6 Timer1 C ounter High-by te Register (T1C NTH) F6H, Set 1, Bank 0 , R .7 .6 .5 . 4 .3 .2 .1 .0 MSB LS B Reset Val ue: 00H Timer 1 Cou nter Low -byte Regist er (T1C NTL) F7H, Set 1, Bank 0 , R .7 .6 .5 . 4 .3 .2 .1 .0 MS B L SB Reset Value: 00H Timer 1 Data Hig h-b yte Re gi s te r (T1DATAH) F8H, Set 1 , Bank 0, R /W .
S3F80JB COUNTER A 12-1 12 COUNTER A OVERVIEW The S3F80JB microcont roller has one 8-bit coun te r calle d cou nter A. Count er A, which can be used to generat e the carrier freque ncy , has the follow.
COUNTER A S3F80JB 12-2 MUX 16-Bit Down Counter MUX Counter A Data Low Byte Register IRQ2 (CAINT) NOTE: The value of the CADAT AL register is loaded i nto the 8-bit counter when the operation of the counter A stars. If a borrow occurs, the value of the CADATAH register is loaded into the 8-bit counter.
S3F80JB COUNTER A 12-3 COUNTER A CONTROL RE GISTER (CACON) The counter A cont ro l register, CACON, is loca ted in F3H, Set 1, Ba nk 0, and is read/write ad dre ssable.
COUNTER A S3F80JB 12-4 COUNTER A PULSE WIDTH CALCULATIONS t LOW t HIGH t LOW To generate the abo ve rep ea ted waveform consist e d of low period time , t LOW , an d hi gh period time, t HIGH. Wh en CAOF = 0, t LOW = (C ADATAL + 2) × 1/Fx. 0H < CA DATA L < 100H, where Fx = the selected clock.
S3F80JB COUNTER A 12-5 High High Counter A Clock 0H CAOF = '0' CADATAL = 01-FFH CADATAH = 00H CAOF = '0' CADATAL = 00H CADATAH = 01-FFH CAOF = '0' CADATAL = 00H CADATAH =.
COUNTER A S3F80JB 12-6 PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P3.1 This example sets Counter A to the re peat mode, sets the osc illation frequency as the Counter A clock source, and CADATAH and CA DATA L to make a 38 kHz, 1/3 Du ty carr ier f requency.
S3F80JB COUNTER A 12-7 PROGRAMMING TIP — To generate a one-pulse signal through P3.1 This example set s Cou nt er A to the one shot mode , set s the oscillation frequency as the Co un te r A clock source, and CADATAH and CADA TAL to ma ke a 40 µ s width pulse.
S3F80JB TIMER 2 13-1 13 TIMER 2 OVERVIEW The S3F80JB microcont ro ller has a 16 -b it t imer/counter calle d Timer 2 (T2). For u niv ersal remote controlle r applications, ti me r 2 can be use d to genera t e the envelope p at te rn f or t he remote controller signa l.
TIMER 2 S3F80JB 13-2 TIMER 2 OVERFLOW INTERRUPT Timer 2 can be programmed to gen era te an ov erflow interru pt (IRQ3, F0H) whenev er an ov er flow occurs in the 16-bit up coun te r.
S3F80JB TIMER 2 13-3 TIMER 2 MATCH INTERRUPT Timer 2 can also be used to gen era t e a match interrupt (IRQ3, vector F2H) when ever the 16-bit coun ter value matches the value that is writte n to the timer 2 refer e nce data reg isters, T2DA TA H and T2DATAL.
TIMER 2 S3F80JB 13-4 MUX 16-Bit Up-Counter (Read-Only) 16-Bit Compatator Timer 2 High/Low Buff er Register MUX IRQ3 Clear IRQ3 Mat c h (note) NOTE: Match signal is occurrd only in interval mode. T2CON. 7-.6 T2CON.2 T1CON.3 Match Signal T2OV F Data Bus Tim er 2 Da ta High/Low Register CAOF (T-F/F) f OSC /16 f OSC /8 f OSC /4 R OVF T2C ON .
S3F80JB TIMER 2 13-5 TIMER 2 CONTROL REGISTER (T2 CON) The timer 2 control reg iste r, T2CON, is located in addre ss E8H, Bank1, Set 1 and is rea d/ wri te addressable.
TIMER 2 S3F80JB 13-6 Timer2 Counter High-Byte Register (T2CNTH) E4H , Set 1, Bank 1, Read-only .7 .6 .5 .4 . 3 .2 .1 .0 MS B LS B Reset Value: 00H Timer 2 Counter Low-Byte Register (T2CN TL) E5H , Set 1, Bank 1, Read-only .7 .6 .5 .4 . 3 .2 .1 .0 MSB L S B Reset Value: 00H Timer 2 Data High-Byte Register (T2D ATAH) E6H , Set 1, Bank 1, R/W .
S3F80JB CO M P AR AT O R 14-1 14 COMPARATOR OVERVIEW P2.4, P2.5, P2.6 and P2. 7 can b e used as ana log input pins for a comp ar at or. The reference voltage for the 4- channel comparator can be supp lied either i nternally o r externally at P2.7. When an inter nal reference v oltage is used, four channe ls (P2.
CO M P AR AT O R S3F80JB 14-2 MUX V DD Comparison Result Register (CMP REG) MUX MUX MUX CMPSEL_3 Ref (Internal ) SCAN signal Ref (External) R R + - 1/ 2R Internal BUS NOTES: 1. INT occurs only for digital input selecting. If an analog input, any INT doesn't occur.
S3F80JB CO M P AR AT O R 14-3 COMPARATOR OPERATION The comparator comp ar es inp ut analog voltage at CIN0–CIN3 with an ex ternal or interna l ref e rence voltage (V REF ) that is selected by the CMOD re gist er. The result is writt en t o the comparison result re gister CMPREG at address EAH, Set 1, Ba nk1.
CO M P AR AT O R S3F80JB 14-4 LSB MSB Comparator Mode Register (CMOD) E9H, Set1, Bank 1, R/ W Referenc e Vol tage Selection Bits Selected V ref=Vdd x ( N + 0.5) /16, n=0 t o 15 Comparator Enale/Disable Bit 0:Comparator operation di sable 1:Comparator operation enab le Not used for S3 F80JB.
S3F80JB CO M P AR AT O R 14-5 Comparator Result Register (CM PREG) EBH, Set1, Bank 1, R .7 .6 .5 .4 .3 .2 .1 .0 MS B L SB Comparator Result Data Not used for S3F80JB Figure 14-5.
S3F80JB EMBEDDED FLASH MEMORY INTERFA CE 15-1 15 EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F80JB has an on-chip fl a sh memo ry int ernally instead of masked RO M. Th e fla sh mem ory is accessed by instruction ‘LDC’ . This is a sect or erasa ble and a by te progra mmab le flash.
EMBEDDED FLASH MEMORY INTERFA CE S3F80JB 15-2 User Program Mode This mode suppor ts sector er as e, byte programmin g, by te read and one pr otec tion mode (Hard Loc k Protection). The S3F80JB has the inter na l pumping ci rcuit to gen era t e hig h v olt ag e.
S3F80JB EMBEDDED FLASH MEMORY INTERFA CE 15-3 ISP TM (ON-BOARD PROGRAMMING) SECTOR ISP TM sectors located i n pro gra m memo ry area can store On Boa rd Pr og ram S oftware (Boot program code for upgrading applica tio n cod e by interfacing with I/ O port pin).
EMBEDDED FLASH MEMORY INTERFA CE S3F80JB 15-4 SMART OPTION Smart option is th e pro gr am memo ry option for start ing condition of the chip. Th e pr ogram memory addre sses used by smart optio n ar e fr om 00 3CH t o 003FH. The S3F80JB on ly use 00 3EH a nd 0 03FH.
S3F80JB EMBEDDED FLASH MEMORY INTERFA CE 15-5 NOTES 1. By sett ing ISP R eset Vec tor Cha nge Selec tion Bit (3E H.7) to ‘0’, user c an have the availab le ISP a rea. If ISP R eset Vector Change Sele ction Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 ar e meaningles s.
EMBEDDED FLASH MEMORY INTERFA CE S3F80JB 15-6 FLASH MEMORY CONTROL REGISTERS (USER PR OGRA M MODE) FLASH MEMORY CONTROL REGISTER (FMCON) FMCON register is available only in user pr ogr am mo de t o sele ct t he flash memory operat ion mode; sector erase, byte programmi ng, and to make the fl a sh memo ry into a hard lock protect ion.
S3F80JB EMBEDDED FLASH MEMORY INTERFA CE 15-7 FLASH MEMORY SECTOR ADDRESS REGI STE RS There are two sector add re ss registers for the erase or pr og rammi ng flash memory.
EMBEDDED FLASH MEMORY INTERFA CE S3F80JB 15-8 SECTOR ERASE User can erase a flash memor y pa rt ially by using secto r era se fu nct ion only in user program mod e. The only unit of flash memory t o be e rased in the user program mod e is a sect or. The program memory of S 3F80JB, 64Kbyt es fl ash memory, is divi de d int o 512 sectors.
S3F80JB EMBEDDED FLASH MEMORY INTERFA CE 15-9 The Sector Erase Procedure in User Program Mode 1. Set Flash Memory User P rog ramm ing Enable Register (FM USR) t o “1 010 0101B”. 2. Set Flash Memory Secto r Add ress Regist er (FMSECH and FMSECL ). 3.
EMBEDDED FLASH MEMORY INTERFA CE S3F80JB 15-10 PROGRAMMING TIP — Sector Erase Case1. Erase one se ctor • • ERASE_ONESECTOR: SB1 LD FMUSR, #0A5H ; User program mode enabl e LD FMSECH,# 40H ; .
S3F80JB EMBEDDED FLASH MEMORY INTERFA CE 15-11 SECTOR_ERASE: LD R12 ,SecN umH LD R 14,SecN umL MULT RR12,#80H ; Calculation t he ba se address of a target sect or MULT RR14,#80H ; The size of one sec tor is 12 8-bytes ADD R13 ,R14 ; B T J R F F L A G S .
EMBEDDED FLASH MEMORY INTERFA CE S3F80JB 15-12 PROGRAMMING A flash memory is progr amme d in o ne- by te unit after secto r erase. The write operation of programming starts by ‘LDC’ instruction. The program procedure in user program mode 1. Must era se target sec tors befor e programmin g.
S3F80JB EMBEDDED FLASH MEMORY INTERFA CE 15-13 SB1 Start ; Select Bank1 ; User Program Mode Enable ; Set Secotr Base A ddress ; Write data at flash ; User Program Mode Disable FM SECH High Address of .
EMBEDDED FLASH MEMORY INTERFA CE S3F80JB 15-14 SB1 Start ; Sel e c t Ban k 1 ; User Program Mode Enable ; Set Secotr Base Address ; Write data at flash ; User Pro gram Mode Disable FMSECH High Address.
S3F80JB EMBEDDED FLASH MEMORY INTERFA CE 15-15 PROGRAMMING TIP — Programming Case1. 1-By te Programming • • WR_BYTE: ; Write data “AAH ” to des tination a ddres s 4010H SB1 LD FMUSR,#0A5.
EMBEDDED FLASH MEMORY INTERFA CE S3F80JB 15-16 Case3. Programming to the flash memo ry space located in other sectors • • WR_IN SECTOR2: LD R0 ,#40H LD R1,#40 H SB1 LD FMUSR,#0 A5H ; User progr am.
S3F80JB EMBEDDED FLASH MEMORY INTERFA CE 15-17 READING The read operation s tarts by ‘LD C’ instru ction. The program procedure in user pr ogram mode 1. Lo ad a flash memory upper a ddress into upper reg ister of pa ir workin g register. 2. Load a flash memory lower address int o lower register of pa ir wor king regi ster.
EMBEDDED FLASH MEMORY INTERFA CE S3F80JB 15-18 HARD LOCK PROTEC TION User can set Hard Lock Protec tion by writing ‘0110B’ in FMCON 7-4. This func tion prevents the changes of data in a flash memo ry area. If this func tion is enab led, the user cannot write or erase the dat a in a fla sh memory area.
S3F80J B LOW VOLTA GE DETECTOR 16-1 16 LOW VOLTAGE DETECTOR OVERVIEW The S3F80JB micro-con tr olle r ha s a built -in Low Voltag e Det e ctor (LVD) circuit, which a llows LV D and LVD_FLAG detect ion of po wer vo lta ge.
LOW VOLT AGE DETECTOR S3F80JB 16-2 NOTES 1. When smart option bi t is set “1” , o per at ing frequency is selecte d 8MHz and LVD voltage level is 2.3V. On the other hand, when smart op ti on bit is set “0”, operating freq ue ncy is selected 4MHz and LVD vo ltage lev el is 2.
S3F80J B LOW VOLTA GE DETECTOR 16-3 LOW VOLTAGE DETECTOR CONTROL REGISTER (LVDCON) LVDCON .0 is use d flag bit to indicate low batter y in IR ap plication or others. W hen LVD circui t detects LVD_FLAG, LV DCON. 0 f lag bit is set auto mat i ca lly . The reset value of LV DCON is #00H.
S3F80J B ELECTR ICA L DATA (4MHz) 17 -1 17 ELECTRICAL DATA – 4MHz OVERVIEW In this secti on , S 3F80JB electrical characteristics are presen te d in tables and grap hs. The informat ion is arranged in the followin g order : — Absolute Maximum Ratings — D.
ELECTRICAL DA TA (4MHz) S3F80JB 17-2 Table 17-1. Absolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Rating Unit Supply Vo ltage V DD – – 0.3 to + 3.8 V Input Volta ge V IN – – 0.3 to V DD + 0.3 V Output Voltage V O All output pins – 0.
S3F80J B ELECTR ICA L DATA (4MHz) 17 -3 Table 17-2. D.C. Electrical Charact eristics (Continued) (T A = – 25 ° C to + 85 ° C, V DD = 1.7 V to 3.6 V) Parameter Symbol Conditi ons Min Typ Max Unit Output Low Voltage V OL1 V DD = 2.1 V, I OL = 12mA Port 3.
ELECTRICAL DA TA (4MHz) S3F80JB 17-4 Table 17-2. D. C. Electrical Characteristics (Cont inue d) (T A = – 25 ° C to + 85 ° C, V DD = 1.7 V to 3.6 V) Parameter Symbol Conditi ons Min Typ Max Unit Supply Current (note) I DD1 Operatin g Mode V DD = 3.
S3F80J B ELECTR ICA L DATA (4MHz) 17 -5 TYPICAL VOL vs IOL(VDD=3.3V) 0.00 0.20 0.40 0.60 0.80 1.00 0 1 0 2 0 3 0 4 05 06 0 7 0 8 0 IOL(mA ) VOL(V) TYPICAL VOL VS VDD(IO L=12mA) 0 50 100 150 200 250 300 1.800V 2. 400V 3.000 V 3.600V VDD(V) VOL(mV) 85 °C 25° C − 25 °C 85° C 25° C − 25 °C Figure 17-1.
ELECTRICAL DA TA (4MHz) S3F80JB 17-6 TYPICAL VOL v s IOL(VDD=3.3V) 0.00 0.20 0.40 0.60 0.80 1.00 05 1 0 1 5 IOL(mA ) VOL(V) TYPICAL VOL VS VDD(IOL=2mA ) 0 20 40 60 80 100 120 140 160 1.800V 2.400V 3. 000V 3.600V VDD( V) VOL(mV) 85° C 25°C − 25 ° C 85 °C 25 °C − 25 °C Figure 17-3.
S3F80J B ELECTR ICA L DATA (4MHz) 17 -7 TYPICAL VDD-VOH(VDD=3.3V) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 0246 8 1 0 1 2 IOH(mA ) VDD-VOH(V) TYPICAL VDD-VOH VS VDD(IOH= − 2.2mA) 0 0.1 0.2 0.3 0.4 0.5 0.6 1.8V 2.3 2.8 3.3 3.8 VDD(V) VDD-VOH(V) 85 °C 25 °C − 25 °C 85 °C 25 ° C − 25 °C Figure 17-5.
ELECTRICAL DA TA (4MHz) S3F80JB 17-8 Execution of STOP Instr ction ~ ~ V DDDR ~ ~ Stop M ode Idle Mode (Basic Timer Active) Data Retention Mode t WAI T EXT INT V DD Normal Operating Mode 0.
S3F80J B ELECTR ICA L DATA (4MHz) 17 -9 Normal Operating M ode Stop Mode Oscillation Stabilization Time Reset Occu r Execution of STOP Instr ction V DD NOTE: t WA I T is the same as 4096 x 16 x 1/f OSC . V LVD ~ ~ Data Retention T im e V DDDR Back-up Mode t WA I T ~ ~ Figure 17-9.
ELECTRICAL DA TA (4MHz) S3F80JB 17-10 t INTH t INT L 0.8 V DD 0.2 V DD 0.2 V DD 0.8 V DD NOTE: The u ni t t CPU means on e CPU clock pe riod. Figure 17-10. Input Timing for Exte rnal Interrupts (Port 0 and Port 2) Normal Oper atin g Mode Oscillation Stabilization Time Reset Occu r V DD NOTE: t WAI T is the same as 4096 x 16 x 1/f OSC .
S3F80J B ELECTR ICA L DATA (4MHz) 17-11 Table 17-7. Osc il lation Characteristics (T A = – 25 ° C to + 85 ° C) Oscillator Clock Circuit Conditions Min Typ Max Unit Crystal X IN C1 C2 X OUT CPU clo.
ELECTRICAL DA TA (4MHz) S3F80JB 17-12 Table 17-8. Oscillati on Stabilization Time (T A = – 25 ° C to + 85 ° C, V DD = 3.6 V) Oscillator Test Condi tion Min Ty p Max Unit Main crystal f OSC > 400 kH z – – 20 ms Main ceramic Oscillation stabilizat ion occurs when V DD is equal to the min imu m oscil lator voltage range.
S3F80J B ELECTR ICA L DATA (4MHz) 17-13 Minimun Instruction Cloc k 1kHz f OSC (Main Oscillator Frequency) 123 45 Supply Voltage (V) Minimun Instruction C lock = 1/4n x oscillator frequency (n = 1, 2, 8, or 16) A: 1.7 V, 4 MHz 250 kHz 1MHz 1.5MHz 2 MHz 8 MHz 6 MHz 4 MHz 400 kHz 67 500 kHz A 1 MH z 2 MH z Figure 17-12.
S3F80J B ELECTRIC AL DA TA (8MHz) 18 -1 18 ELECTRICAL DATA – 8MHZ OVERVIEW In thi s section, S 3F80JB electrical characteristics are presen ted in table s and grap hs. The inf ormation is arranged in the followin g order : — Absolute Maximum Ratings — D.
ELECTRICAL DA TA (8MHz) S3F80JB 18-2 Table 18-1. Absolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Rating Unit Supply Vo ltage V DD – – 0.3 to + 3.8 V Input Volta ge V IN – – 0.3 to V DD + 0.3 V Output Voltage V O All output pins – 0.
S3F80J B ELECTRIC AL DA TA (8MHz) 18 -3 Table 18-2. D.C. Electrical Characteristic s (Continued) (T A = – 25 ° C to + 85 ° C, V DD = 1.95 V to 3.6 V) Parameter Symb ol Conditi ons Min Typ Max Unit Output L ow Voltage V OL1 V DD = 2.35 V, I OL = 12mA Port 3.
ELECTRICAL DA TA (8MHz) S3F80JB 18-4 Table 18-2. D. C. Electrical Characteristics (Continue d) (T A = – 25 ° C to + 85 ° C, V DD = 1.95 V to 3.6 V) Parameter Symbol Conditi ons Min Typ Max Unit Supply Current (note) I DD1 Operatin g Mode V DD = 3.
S3F80J B ELECTRIC AL DA TA (8MHz) 18 -5 TYPICAL VOL v s IOL(VDD=3.3V) 0.00 0.20 0.40 0.60 0.80 1.00 0 1 02 03 04 0 5 0 6 07 08 0 IOL(mA) VOL( V) TYPICA L VOL VS VDD(IO L= 12mA ) 0 50 100 150 200 250 300 1.800V 2.400V 3.000V 3.600V VDD(V) VOL( mV) 85° C 25°C − 25 °C 85° C 25°C − 25 °C Figure 18-1.
ELECTRICAL DA TA (8MHz) S3F80JB 18-6 TYPICAL VOL vs IO L(VDD=3.3 V) 0.00 0.20 0.40 0.60 0.80 1.00 0 1 02 03 04 0 5 0 6 0 7 08 0 IOL(mA) VOL(V ) TYPICA L VOL VS VDD(IOL=12mA ) 0 50 100 150 200 250 300 1.800V 2.400V 3. 000V 3.600V VDD(V) VOL(mV) 85 °C 25 °C − 25 °C 85° C 25° C − 25 °C Figure 18-3.
S3F80J B ELECTRIC AL DA TA (8MHz) 18 -7 25 °C -25 °C TY PICAL VDD-VOH(VDD=3.3V) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 0246 8 1 0 1 2 IOH(mA) VDD-VOH (V) TYPICAL VDD- VOH VS VDD(IOH= − 2. 2mA) 0 0.1 0.2 0.3 0.4 0.5 0.6 1.8V 2. 3 2.8 3.3 3.8 VDD(V) VDD-VOH(V) 85°C 25° C − 25 °C 85°C 25° C − 25 °C Figure 18-5.
ELECTRICAL DA TA (8MHz) S3F80JB 18-8 Execution of STOP Instr ction ~ ~ V DDDR ~ ~ Stop M ode Idle Mode (Basic Timer Active) Data Retention Mode t WAI T EXT INT V DD Normal Operating Mode 0.
S3F80J B ELECTRIC AL DA TA (8MHz) 18 -9 Normal Operating M ode Stop Mode Oscillation Stabilization Time Reset Occu r Execution of STOP Instr ction V DD NOTE: t WA I T is the same as 4096 x 16 x 1/f OSC . V LVD ~ ~ Data Retention T im e V DDDR Back-up Mode t WA I T ~ ~ Figure 18-9.
ELECTRICAL DA TA (8MHz) S3F80JB 18-10 t INTH t INT L 0.8 V DD 0.2 V DD 0.2 V DD 0.8 V DD NOTE: The u ni t t CPU means on e CPU clock pe riod. Figure 18-10. Input Timing for Exte rnal Interrupts (Port 0 and Port 2) Normal Oper atin g Mode Oscillation Stabilization Time Reset Occu r V DD NOTE: t WAI T is the same as 4096 x 16 x 1/f OSC .
S3F80J B ELECTRIC AL DA TA (8MHz) 18-11 Table 18-7. Compa rator Electric al Charact eristics (T A = –2 5 ° C to + 85 ° C, V DD = 1.95 V to 3.6 V, V SS = 0 V) Parameter Symbol Condi tion Min Ty p M.
ELECTRICAL DA TA (8MHz) S3F80JB 18-12 Table 18-9. Oscillati on Stabilization Time (T A = –25 ° C to + 85 ° C, V DD = 3.6 V) Oscillator Test Condi tion Min Ty p Max Unit Main crystal f OSC > 400 kH z – – 20 ms Main ceramic Oscillation stabilizat ion occurs when V DD is equal to the min imu m oscil lator voltage range.
S3F80J B ELECTRIC AL DA TA (8MHz) 18-13 Min i m un I n s tr u ct i on Clock 1kHz f OSC (Main Oscillator Frequency) 123 4 5 Supply Voltage (V) Minimun Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, or 16) A: 1.95 V, 8 M Hz 250 kHz 1MHz 1.
ELECTRICAL DA TA (8MHz) S3F80JB 18-14 NOTES.
S3F80JB MECHA NICAL DA TA 19-1 19 MECHANICAL DATA OVERVIEW The S3F80JB microcont ro ller is curren t ly available in a 32 -pin SO P an d 44 -pin QFP package. 32-SOP-45 0A 20.30 M AX 19.90 ± 0.20 #17 #16 0-8 0.25 + 0.10 - 0.05 11.43 8.34 ± 0.20 0.90 ± 0.
MECHANICA L DATA S3F80JB 19-2 44-QFP -1010B #44 NOTE : Dimensions are in millimeters. 10.00 ± 0.20 13.20 ± 0.30 10.00 ± 0.20 13.20 ± 0.30 #1 0.35 + 0.10 - 0.05 0.80 0.10 MA X 0.80 ± 0.20 0.05 MI N 2.05 ± 0.10 2.30 MA X 0.15 + 0.10 - 0.05 0-8 0.15 M AX (1.
S3F80JB DEVELOPMENT TOOLS DATA 20-1 20 DEVELOPMENT TOOLS DATA OVERVIEW Samsung provi des a po wer f u l and easy-to-use dev elopment supp or t system on a tur nkey ba sis. The development sup po rt system is composed of a host syst em, debugging tools, an d supp or tin g sof tware.
DEVELOPMENT TOOLS DATA S3F80JB 20-2 TB80JB TARGET BOARD The TB80JB target boa rd is used fo r th e S3F80JB microcontro ller s. I t is supported by OP ENice-i500 (In-Circu it Emulator).
S3F80JB DEVELOPMENT TOOLS DATA 20-3 Table 20-1. Components Consisti ng of S3F80JB Target Board Block Symbols OPEN-i500 Conne cto r J1A Co nn ect ion debugging sign als be twe en em ula to r an d 80 JB EVA t arget boar d. TEST Board Conne cto r J2 Connection bet wee n t arget board and remocon applicati on board.
DEVELOPMENT TOOLS DATA S3F80JB 20-4 Table 20-2. Defaul t Se tti ng of the Jumper in S3F80JB Target Board JP# Description 1-2 connect ion 2-3 connection Setting S1 Target board power so urce Open-ice p.
S3F80JB DEVELOPMENT TOOLS DATA 20-5 NOTE: N.C means No Connectio n. N.C N.C N.C P1.5 J2 (for 44-QF P) P2.3/I NT8 P2.4/INT9 /CIN0 P3.0/T0PW M/T 0CAP/SDAT P3.1/REM/SCLK TEST P2.5/INT9/CI N1 P3.4 P3.5 P2.7/INT9 /CIN3 P1.0 P3.2/T0CK P3.3/T1CAP/T 2CAP P1.2 P1.
DEVELOPMENT TOOLS DATA S3F80JB 20-6 SAMSUNG provide s a comple t e line of developm ent tools for SA MS UNG's microcontroller. Wi th long experien ce in developing MCU syst ems, our third parties are leading comp an ies in the tool's tech nology.
S3F80JB DEVELOPMENT TOOLS DATA 20-7 OTP/MTP PROGRAMM ER (WRITER) SPW2+ Single PROM OTP/ FLASH MTO Programmer • Download/Upload a nd data edit fun ctio n • PC-bas ed operation with RS23 2C port • Full function regardin g OTP progr ammer (Read, Program, Ve rif y, Blank, Pr ot ect ion.
(For duplicate cop i e s of this form, an d f or a dd itional orderin g in f o rmation, ple ase contact your local Samsung sales re pr ese nt ative. Sam sung sales offi ces ar e list ed on the back cove r of this book.
(For duplicate cop i e s of this form, an d f or a dditional orde rin g in f o rmation, ple ase contact your local Samsung sales re pr ese nt ative. Sam sung sales offi ces ar e list ed on the back cove r of this book.
FLASH APPLICATION NOTES S3F80JB Programming By Tool.
S3F80JB 1 TOOL PROGRAMMIN G OF S3F80J B To read/write/e rase by OTP/MTP writer, the following six pins are used . Table 1. Descripti ons of Pins Used to Re ad/Write/Erase the Flash in Tool Program Mode During Programming Normal Chip Pin Name Pin Name Pin No.
S3F80JB 2 This is only an example fo r set t ing Vdd. This is SPW2+ which is one of OPT/MTP Write r s..
Import ant Note Subject : Toggling phenomenon when serial writin g programming on the S3F80JB..
Important Note S3F80JB 1 1. ANALYSIS RESULT When s e rial writ ing pr ogr amm ing on S 3F8 0J B, o nly p or t1. 4,1. 5,1. 6, 1. 7 are aff ected by S D AT sig nal. T his phenom eno n is only po rt1. 4,1 .5, 1.6, 1 .7 i ssue s and i n norm al o p era ting mode it nev er b e occu rre d.
S3F80JB Important Note 2 2.2 FOR NORMAL OPERATING MODE The S3F80JB/9 is needed to nRESET pin = “1(VDD)” & TEST pin = “0(GND)” P1.4~1.7 When nRESET pin = “1(VDD )” & TEST pin = “0(GND)” In the Figure 2, beca use TEST signal is low(Logic level 0) , “outdis” and “data” signal is same to MUX “0” signal.
Important Note S3F80JB 3 3. DIFFERENCE S3F80JB AND S3F80J9 3.1 WHEN TEST PIN = “1 (VDD)” This is Fabrication Test mode (For Design team & PE ) : Design team & PE team tested S3F80JB by using ADVAN equipment When testing S3F80JB, port1.0~1.
S3F80JB Important Note 4 ¾ When S3F80J9 On S3F80J9 , address & d ata por t is different from S3F8 0JB. Because the 28-SOP type doesn’t have port1.4~1.7, port1.0~1.3 and port2.4~2.7 are used to addre ss & data port. (S3F80J9 is supported to 32-SOP and 28-SOP type.
Ein wichtiger Punkt beim Kauf des Geräts Samsung S3F80JB (oder sogar vor seinem Kauf) ist das durchlesen seiner Bedienungsanleitung. Dies sollten wir wegen ein paar einfacher Gründe machen:
Wenn Sie Samsung S3F80JB noch nicht gekauft haben, ist jetzt ein guter Moment, um sich mit den grundliegenden Daten des Produkts bekannt zu machen. Schauen Sie zuerst die ersten Seiten der Anleitung durch, die Sie oben finden. Dort finden Sie die wichtigsten technischen Daten für Samsung S3F80JB - auf diese Weise prüfen Sie, ob das Gerät Ihren Wünschen entspricht. Wenn Sie tiefer in die Benutzeranleitung von Samsung S3F80JB reinschauen, lernen Sie alle zugänglichen Produktfunktionen kennen, sowie erhalten Informationen über die Nutzung. Die Informationen, die Sie über Samsung S3F80JB erhalten, werden Ihnen bestimmt bei der Kaufentscheidung helfen.
Wenn Sie aber schon Samsung S3F80JB besitzen, und noch keine Gelegenheit dazu hatten, die Bedienungsanleitung zu lesen, sollten Sie es aufgrund der oben beschriebenen Gründe machen. Sie erfahren dann, ob Sie die zugänglichen Funktionen richtig genutzt haben, aber auch, ob Sie keine Fehler begangen haben, die den Nutzungszeitraum von Samsung S3F80JB verkürzen könnten.
Jedoch ist die eine der wichtigsten Rollen, die eine Bedienungsanleitung für den Nutzer spielt, die Hilfe bei der Lösung von Problemen mit Samsung S3F80JB. Sie finden dort fast immer Troubleshooting, also die am häufigsten auftauchenden Störungen und Mängel bei Samsung S3F80JB gemeinsam mit Hinweisen bezüglich der Arten ihrer Lösung. Sogar wenn es Ihnen nicht gelingen sollte das Problem alleine zu bewältigen, die Anleitung zeigt Ihnen die weitere Vorgehensweise – den Kontakt zur Kundenberatung oder dem naheliegenden Service.
