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MuxOneNAND2G(KFM2G16Q2A-DEBx) - 1 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) KFM2G16Q2A KFN4G16Q2A 2Gb MuxOneNAND A-die INFORMA TION IN THIS DOCUMENT IS PROVID ED IN RELA TION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 2 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Revision History Document Title MuxOneNAND Revision History Revision No. History Draft Date Remark 0.0 0.1 0.2 1.0 1.1 1.1 1 1.2 1. Initial issue. 1. Corrected errata. 2. Chapter 3.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 3 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Revision No. Histo ry Draf t Dat e Remark 1.3 1. Corrected errata. 2. Chapter 2.8.18 Command Register F220h (R /W) revised. 3. Chapter 3.4.3 NAND Array Write Protection states revised.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 4 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 1.0 INTRODUCTION This specification contains information about the Samsung Electronics Company MuxOneNAND ‚ Flash memory product family . Section 1.0 includes a general overview , revision history , and product ordering information.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 5 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 1.2 Ordering Information 1.3 Architectural Benefit s MuxOneNAND is a highly integrated non-volatile memory solution based around a NAND Flash memory arr ay .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 6 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 1.4 Product Features Device Architecture Design T echnology: Supply V oltage: Host.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 7 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 1.5 General Overview MuxOneNAND ‚ is a monolithic integrated circui t with a NAND Flash array using a NOR Flash inte rface. T his device in cludes control logic, a NAND Flash array , and 5KB of internal BufferRAM.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 8 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.0 DEVICE DESCRIPTION 2.1 Det ailed Product Description The MuxOneNAND is an advanced generation, high-performance NAND- based Flash memory .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 9 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.3 Pin Configuration 2.3.1 2Gb Product (KFM2 G16Q2A) (TOP VIEW , Balls Fac ing Down) 63ball FBGA MuxOneNAND Chip 63ball, 10mm x 13mm x max 1.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 10 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.3.2 4Gb Product (KFN4G16Q2A) (TOP VIEW , Balls Fac ing Down) 63ball FBGA MuxOneNAND Chip 63ball, 10mm x 13mm x max 1.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 11 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.4 Pin Description NOTE : Do not leave power supply(Vcc-Core/Vcc-IO, V SS ) disco nnected.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 12 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.5 Block Diagram 2.6 Memory Array Organization The MuxOneNAND architecture integrates several memory areas on a single chip.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 13 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Internal Memory Array Information Internal Memory Array Organization Area Block Page Sector Main 128KB 2KB 512B S pare 4.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 14 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.6.2 External (Buff erRAM) Memory Organization The on-chip external memory is comprised o f 3 buf fers used for Boot Code storage and data buffering.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 15 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) External Memory Array Organization BootRAM 0 BootRAM 1 BootRAM DataRAM 1_0 DataRAM 1_1 DataRAM 1_2 DataRAM 1_3 DataR AM1.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 16 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7 Memory Map The following tables are the memory maps for the MuxOneNAND. 2.7.1 Internal (NAND Array) Memo ry Organization The following tables show the Internal Memory address map in word order.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 17 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page a nd Sector Address Size Block Block Addre ss Page and Sect or Address Size Block64 0040h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 18 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block128 0080h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 19 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block192 00C0h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 20 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block256 0100h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 21 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block320 0140h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 22 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block384 0180h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 23 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block448 01C0h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 24 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block512 0200h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 25 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block576 0240h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 26 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block640 0280h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 27 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block704 02C0h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 28 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block768 0300h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 29 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block832 0340h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 30 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block896 0380h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 31 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block960 03C0h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 32 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1024 0400h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 33 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1088 0440h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 34 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1 152 0480h 000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 35 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1216 04C0h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 36 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1280 0500h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 37 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1344 0540h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 38 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1408 0580h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 39 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1472 05C0h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 40 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1536 0600h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 41 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1600 0640h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 42 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1664 0680h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 43 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1728 06C0h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 44 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1792 0700h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 45 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1856 0740h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 46 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sec tor Address Size Block Block Address Page and Sector Address Size Block1920 0780h 0000h.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 47 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1984 07C0h 0000.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 48 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7.2 lnternal Memor y Sp are Area Assignment The figure below shows the assignment of the sp are area in the Internal Memory NAND Arr ay .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 49 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7.3 External Memory (Buffe rRAM) Address Map The following table shows the External Me mory address map in Word and Byte Order. Note that the data output is unknown while host reads a register bit of reserved area.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 50 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7.4 External Memory Map Detail Information The tables below show Word Order Address Map inform ation for the BootRAM and DataRAM main and spare areas.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 51 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7.5 External M emory Sp are Area Assig nment Buf. Wor d Address Byte Address F E D C B A 9 8 7 6 5 4 3 2 1 0 BootS 0 8.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 52 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Buf. Word Address Byte Address F E D C B A 9 8 7 6 5 4 3 2 1 DataS 0_2 8020h 10040h BI 8021h 10042h Managed by Internal .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 53 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) NOTE : - BI: Bad block Information >Host can use complete spare area except BI and ECC code area. For example, Host can write data to Spare area buffer except for the area controlled by ECC logic at program operation.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 54 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8 Registers Section 2.8 of this specification provides information about the MuxOneNAND registers. 2.8.1 Register Addre ss Map This map describes the register addresses, register name, register description, and host accessibility .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 55 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.2 Manufact urer ID Register F000h (R) This Read register describes the manufacturer's identification. Samsung Electronics Company manufacturer's ID is 00ECh.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 56 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.3 Devic e ID Regi ster F001h ( R) This Read register describes the device. F001h, see table for default. Device Identification Device ID Default 15 14 13 12 11 10 98 76543210 DeviceID Device Identification Description DeviceID [1:0] Vcc 00 = 1.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 57 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.4 V ersion ID Register F002h This Register is reserved for internal use.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 58 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.6 Boot Buffer Size Register F004h (R) This Read register describes the size of the Boot Buffer . F004h, default = 0200h 2.8.7 Numb er of Buffers Register F005h (R) This Read register describes the number of each Buffer .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 59 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.9 S t art Address1 Register F100h (R/W) This Read/Write register describes the NAND Flash bl ock addr ess which will be loaded, programmed, or erased. F100h, default = 0000h NOTE : 1) Bit 0 should be fixed ‘low’ at 2X Program an d 2X Cache Program .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 60 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.1 1 St art Addres s3 Register F102h (R/W) This Read/Write register describes the NA ND Flash destination block address which will be copy back programmed. Also, this regi ster indi- cates the block address for the first page to be read in Cache Read Operation.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 61 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.13 S t art Address5 Registe r F104h (R/W) This Read/Write register describes the num ber of page in Synchronous Burst Block Read.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 62 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.17 S t art Buffer Register F200h (R/W) This Read/Write register describes the BufferRAM Se ctor Count (BSC) and BufferRAM Sector Address (BSA).
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 63 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.18 Comman d Register F220h (R/W ) Command can be issued by two following methods, and use r ma y select one way or the other to issue appropriate command; 1. Write command into Command Register when INT is at ready stat e.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 64 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.18.1 T wo Methods to Clear Interrupt Register in Command Input T o clear Interrupt Register in command input, user may select one from either following me thods. First method is to turn INT low by manually wr iting 0000h to INT bit of Interrupt Register.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 65 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.19 System Configu ration 1 Register F221h (R, R/W) This Read/Write register descri bes the system configuration. F221h, default = 40C0h Read Mode (RM) Read Mode Information[15] Burst Read Write Latency (BRWL) * Default value of BRWL and HF value is BRWL=4, HF=0.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 66 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Burst Length (BL) Hosts must follow burst length set by BL when reading data in synchronous burst read. NOTE : 1) For normal synchronous burst read, setti ng BL=000 (continuous) will read 1K words, depending on th e number of clocks.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 67 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) I/O Buffer Enable (IOBE) IOBE is the I/O Buffer Enable for the INT and RDY signals. At startup, INT and RDY outputs are High-Z. Bits 6 and 7 become vali d after IOBE is set to "1".
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 68 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Write Mode (WM) Write Mode Information[1] MRS(Mode register Setting) Description NOTE : 1) Operation not guara nteed for cases not defined in above table.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 69 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.20 System Configuration 2 Regist er F222h This register is reserved for future use. 2.8.21 Controller S t atus Register F240h (R) This Read register shows the overall internal status o f the MuxOneNAND and the controller.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 70 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Progra m This bit shows the Program Operation status. In 2X Cache Program Operation, ‘Prog’ bit shows the overall stat us of 2X Cache Program process. Program Information[12] Erase This bit shows the Erase Operation status.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 71 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Reset / Busy (RSTB) This bit shows the Reset Operation status. RSTB Information[7] OTP Lock Status (OTP L ) This bit shows whether the OTP block is lo cked or unlocked.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 72 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Plane1 Current This bit shows the current program status of Plane1 at Final 2X Cache Program, 2X Prog ram, and 2X Interleave Cache Program.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 73 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Controller Status Register Output Modes NOTE : 1) ERm and/or ERs bits in ECC status register at Load Fail case is 10. (2bits error - uncorrectable) 2) ERm and ERs bits in ECC status register at Load Reset case are 00.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 74 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Controller Status Register Output Modes (Continued) NOTE : 1) "1" for OTP Block Lock, "0" for OTP Block Unlock. 2) "1" for 1st Block OTP Lock, "0" for 1st Block O TP Unlock.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 75 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.22 Interrupt S t atus Register F241h (R/W) This Read/Write register shows st atus of the MuxOneNAND interrupts. In DDP, INT register will not be written if DBS, DFS is not set.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 76 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Write Interrupt (WI) This is the Write interrupt bit. WI Interrupt [6] Erase Interrupt (EI) This is the Erase interrupt bit. EI Interrupt [ 5] Reset Interrupt (RSTI) This is the Reset interrupt bit.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 77 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.23 St art Block Address Register F24Ch (R/W) This Read/Write register shows the NAND Fl ash block address in the Write Protection m ode.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 78 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.26 ECC St atus Register F F00h (R) This Read register shows the Error Correction Status. The MuxOneN AND can detect 1- or 2-bit errors and correct 1-bit errors. 3-bit or more error detection and correction is not supported.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 79 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.27 ECC Result of 1 st Selected Sector , Main Area Data Register FF01h (R) This Read register shows the Error Correctio n result for the 1st selected sector of the main are a data.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 80 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.31 ECC R esult of 3 rd Selected Sector , Main Area Data Register FF05h (R) This Read register shows the Er ror Correction result for the 3rd selected sector of the main area data.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 81 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) ECC Log Sector ECClogSector0~ECClogSector3 i ndicates the error position in the 2nd word and LSB of 3rd word in the spare area.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 82 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.0 DEVICE OPERA TION This section of the datasheet discusses the operati on of the MuxOneNAND device. It is followed by AC/DC Characteristics and Timing Diagrams which may be consulted for further information.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 83 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.1.1 Reset MuxOneNAND Command The Reset command is given by writing 00F0h to the boot partiti on address. R eset will return all default values into the device . 3.1.2 Load MuxOneNAND Command Load Data into Buffer command is a two-cycle command.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 84 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.2 Device Bus Operation The device bus operations are shown in the table belo w. NOTE : L=VIL (Low), H=VIH (High), X=Don’t Care. Operation CE OE WE ADQ0~15 RP CL K AV D S tandby H X X High-Z H X X W arm Reset X X X High -Z L X X Asynchronous Write L H L Add.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 85 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.3 Reset Mode Operation The One NAND has 4 reset modes: Cold/Warm/Hot Reset, and NAND Fl ash Array Reset.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 86 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.3.1 Cold Reset Mode Operation See Timing Diagram 6.17 At system power-up, the voltage detector in the device detects th e rising edge of Vcc and releases an internal pow er-up reset s ignal.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 87 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.4 Write Protecti on Operation The MuxOneNAND can be write-protected to pr ev ent re-programming or erasu re of data. The areas of write-protection are the BootRAM, and the NAND Flash Array .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 88 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.4.3.1 Un locked NA ND Array Write Protecti on St ate An Unlocked block can be programmed or erased. The status of an unlocked block can be cha nged to locked or locked-tight using t he appro- priate software command.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 89 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.4.3.3 Locked-tight NAND A rray Write Protection St ate A block that is in a locked-tight state can only be changed to lock ed state after a Cold or Warm Reset. Unlock and Lock command sequences will not affect its state.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 90 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Data Protection Operation Flow Diagram * Samsung strongly recommen ds to follow the above flow chart NOTE : 1) ‘Write 0 to interru pt register’ step may be ignored when using INT auto mode.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 91 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) All Block Unlock Flow Di agram * Samsung strongly recommen ds to follow the above flow chart * * If any blocks are changed to locked -tight st ate, the all block unlock command will fail.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 92 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.5 Dat a Protection Duri ng Power Down Operation See Timing Diagram 6.21 The device is designed to offer protection from any involuntary program/erase during power-transitions.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 93 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.7 Read Operation See Timing Diagrams 6.1, 6.2, 6.5, and 6.6 The device has two read modes; Asynchronous Read an d Synchronous Burst Read.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 94 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.7.2.1 Continuous Linear Burst Read Opera tion See Timing Diagram 6.2 First Clock Cycle The initial word is output at tIAA after the rising edge of the first CLK cycle. The RDY output indicates the initial word is r eady to the system by pulsing high.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 95 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.7.2.3 Programmable Burst Read Latency Operation See Timing Diagrams 6.1 and 6.2 Upon power up, the number of initial clock cycles from V alid Address (A VD ) to initial data defaults to four clocks.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 96 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.8 Cache Read Operation (RM=X, WM=X) A Normal Load Operation(0000h) consists of sequential operation of ‘sensing from NAND Flash Array to Page Buffer’ and ‘transfer ring from Page Buffer to DataRAM’.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 97 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Cache Read Flow Chart NOTE : 1) In case of first cycle cache re ad, BSA must be set to 1000 or 1 100, and from second cycle cache read, BSA will aut omatical ly be switched between DataRAM0 and DataRAM1.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 98 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Cache Read Diagram INT A/DQ0: A/DQ15 1st Address Host reads 1st data from Dat aRAM Setting 2nd Address Setting Comma.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 99 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.9 Synchronous Burst Block Read Operation(RM=1, WM=X) See Timing Diagram 6.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 100 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.9.1 Burst Address Sequence During Synchronous Burst Block Re ad Mode In a Synchronous Burst Block Read, data is output with respect to a clock input.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 101 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Synchronous Burst Block Read Boundary Read Sequence for Single Plane Device :note that only main area data is read.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 102 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.9.3 4-, 8-, 16-, 32-, 1K- W ord Linear Burst Read Operation During Synchron ous Burst Block Read Mode Same as normal linear burst read, synchr onous bur st block read enables a fixed number of words to be read from consecutive addr ess.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 103 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.9.5 Handshaking Operation During Synchr onous Burst Block Re ad Mode The handshaking feature allows the host system to simply monitor t he RDY signal from the device to determine whe n the initial w ord of burst data is ready to be read.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 104 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.10 Synchronous Wr ite(RM=1, WM=1) See Timing Diagram 6.8, 6.9 and 6.10. Burst mode operations enable high-speed synchronous read and write operations. Burst operations consist of a multi-clock sequen ce that must be performed in an ordered fashion.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 105 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.1 1 Program Operation See Timing Diagram 6.12 The Program operation is used to program data from the on-chip BufferRAMs into the NAND FLASH memory array . The device has two 2KB data buffers, each 1 Page (2KB + 64B) in si ze.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 106 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Program Operation Fl ow Diagram NOTE : 1) DBS must be set before data input. 2) Data input could be done anywhere between "S tart" and "Write Program Command".
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 107 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.1 1.1 2X Program Operation See Timing Diagram 6.13 The 2X Program is an extension of Program Operation. Since the device is equipped with two DataRAMs, and two-plane NAND Flash m em- ory array , these two component ena bles simultaneous program of 4KB.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 108 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2X Program Operation Flow Diagram NOTE : 1) DBS must be set before data input. 2) Data input could be done anywhere between "S tart" and "Write Program Command" 3) FBA must be an even block.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 109 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.1 1.2 2X Cache Program Operation See Timing Diagram 6.14 The 2X Cache Program Operation is invented to accomplish continuous 2X Program Operat ion efficiently by hi ding transferring tim e from Dat- aRAM to page buffer .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 110 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2X Cache Program Operation Flow Diagram NOTE : 1) DBS must be set before data input. 2) FBA must be an even block. 3) These registers must be set as BSA=1000, BSC=00 and FSA=00.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 111 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.1 1.3 2X Interleave Cache Program Operation See Timing Diagram 6.15 The 2X Interleave Cache Progr am is available only on DDP . Host can write data on a chip while programming another chip with th is operation.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 112 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2X Interleave Cache Program Operatio n Flow Diagram NOTE : 1) DBS must be set before data input. 2) FBA must be an even block. 3) These registers must be set as BSA=1 000, BSC=00 and FSA=00.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 113 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.12 Copy-Back Program Operation The Copy-Back program is configured to quickly rewrite data stor ed in one page without utilizing memory other than OneNAND.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 114 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) The Copy-Back steps shown in the flow chart are : Data is read from the NAND Array using Flash Bl ock Addre ss (FBA), Flash Page Address (FP A) and Flash Sector Address (FSA).
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 115 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.12.1 Copy-Back Program Operat ion with Random Dat a Input The Copy-Back Program Operation with Random Data Input in MuxOne NAND consists of 2 phase, Load data into Dat aRAM, Modify data a nd program into designated page.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 116 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.13 Erase Operation There are multiple methods for erasing data in th e device including Block Erase and Multi- Block Erase. 3.13.1 Block Erase Op eration See Timing Diagram 6.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 117 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) In order to perform the Internal Erase Rout ine, the following comm and sequence is necessary . The Host selects Flash Core of DDP chip. The Host sets the block address of the memory location.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 118 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.13.3 Multi-Block Erase V erify Read Operation After a Multi-Block Erase Operation, verify Erase Operation result of each block with Multi-Block Erase V erify Command combined with address of each block.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 119 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.13.4 Erase Suspend / Erase Resume Operation The Erase Suspend/Erase Resume Commands interrupt and restart a Blo ck Er.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 120 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Erase Resume When the Erase Resume command is executed, the Block Erase will restart. The Erase Re sume operation does not actually resume th e erase, but starts it again from the beginning.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 121 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) OTP Block Area Structure 1st Block OTP Area Structure Page:2KB+64B Sector(main area) :512B Sector(spare area):16B One B.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 122 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.1 OTP Block Load Operation An OTP Block Load Operation accesses the OTP area and transfers i dentified content from the OTP to the DataRAM on-chip buffer , thus making the OTP contents available to the Host.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 123 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.2 OTP Block Program Operation An OTP Block Program Operation accesses the OT P area and program s content from th e DataRAM on-chip buffer to the designated pag e(s) of the OTP .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 124 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) OTP Block Program Operatio n Flow Chart NOTE : 1) FBA(NAND Flash Block Address) could be omitted or any address. 2) Data input could be done anywhere between "S tart" and "Write Program Command".
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 125 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.3 OTP Block Lock Op eration Even though the OTP area can only be programmed once withou t eras e capability , it can be locked when the device starts up to pr event any changes from being made.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 126 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) OTP Block Lock Operation Flow Chart NOTE : 1) FBA(NAND Flash Block Address) could be omitted or any address. 2) Data input could be done anywhere between "S tart" and "W rite Program Command".
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 127 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.4 1st Block OTP Lock Operation 1st Block could be used as OTP , for secured booting operation.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 128 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 1st Block OTP Lock Operation Flow Ch art NOTE : 1) FBA(NAND Flash Block Address) could be omitted or any address. 2) Data input could be done anywhere between "S tart" and "W rite Program Command".
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 129 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.5 OTP and 1st Block OTP Lock Operation OTP and 1st Block can be locked simultaneously , for lo cking bit lies in the same word of OTP area.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 130 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) OTP and 1st Block OTP Lock Operation Flow Chart NOTE : 1) FBA(NAND Flash Block Address) could be omitted or any address. 2) Data input could be done anywhere between "S tart" and "W rite Program Command".
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 131 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.15 Dual Operations The device has independent dual data buffers on-chip (except duri ng the Boot Load period) that enables higher performance read and pro- gram operation.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 132 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Read While Load Diagram Page B ADQ WE OE INT 0~15 2) 2) Page A Int_reg : Interrupt Register Address Add_reg : Address R.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 133 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Write While Program Diagram Page B ADQ WE OE INT 0~15 3) 2) Page A Add_reg : Address Register Address DBn_add : DataRAM.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 134 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.16 DQ6 T oggle Bit The MuxOneNAND device has DQ6 T oggle bit. T oggle bit is anoth er option to detect whether an interna l load operation is in progr ess or com- pleted.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 135 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.17 ECC Operation The MuxOneNAND device has on-chip ECC with t he capability of detecting 2 bit errors and correcting 1-bit errors in the NAND Fla sh Arr ay memory main and spare areas.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 136 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.18 Invalid Block Operation Invalid blocks are defined as blocks in the device's N AND Flash Array memory that contai n one or more invalid bits whose re liab ility is not guaranteed by Samsung.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 137 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Invalid Block T ab le Creation Flow Chart 3.18.2 Invalid Block Replacement Operation Within its life time, additional invalid blo cks may develop with NAND Flash Array memo ry .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 138 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Referring to the diagram for further illustration, when an erro r happens in the nth page of block 'A' during program operation, copy the data in the 1st ~ (n-1)th page to the same location of block 'B' via data buffer0.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 139 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 4.0 DC CHARACTERISTICS 4.1 Absolute Maximum Ratings NOTE : 1) Minimum DC voltage is -0.5V on In put/ Output pins. During transitions, this level should not fall to POR level(typ.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 140 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 4.3 DC Characteristics NOTE : 1) CE should be VIH for RDY . IOBE should be ‘0’ for INT .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 141 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.0 AC CHARACTERISTICS 5.1 AC T est Conditions 5.2 Device Cap acit ance CAP ACIT ANCE (T A = 25 C, V CC = 1.8V , f = 1.0MHz) NOTE : Capacitance is perio dically sampled and not 100% tested.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 142 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.4 AC Characteristics for Sy nchronous Burst Read See Timing Diagrams 6.1, 6.2, 6.3, 6.4 and 6.24 NOTE : 1) If OE is disabled at th e same time or before CE is disabled, the output will go to hig h-z by t OEZ .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 143 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.5 AC Characteristics for Asynchronous Read See Timing Diagrams 6.5, 6.6, 6.22 and 6.23. NOTE : 1) If OE is disabled at th e same time or before CE is disabled, the output will go to hig h-z by t OEZ .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 144 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.7 AC Characteristics for Asynchronous Write See Timing Diagrams 6.7 5.8 AC Characteristics fo r Burst Write Operation See Timing Diagrams 6.8, 6.9 and 6.10 NOTE : 1) T arget Clock frequency is 83Mhz.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 145 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.9 AC Characteristics for Loa d/Program/Erase Performance See Timing Diagrams 6.1 1, 6.12, and 6.16 NOTE : 1) These parameters are tested based on INT bit of interrupt regi ster .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 146 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.0 TIMING DIAGRAMS 6.1 8-Word Linear Burst Read Mode with W rap Around See AC Characteristics T able 5.4 6.2 Continuous Line ar Burst Read Mode with W rap Around See AC Characteristics T able 5.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 147 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.3 Synchronous Burst Bloc k Read Operation Timing See AC Characteristics table 5.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 148 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.4 Synchronous Burs t Block Read Timing See AC Characteristics table 5.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 149 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Case 2 : BL=8 word synchrono us burst block read 1st burst dat a Nth burst data S tart Page Address Setting Number of P.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 150 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.5 Asynchronous Read (V A T ransition Before A VD Low) See AC Characteristics T able 5.5 NOTE : V A=V alid Read Address, RD=Read Data. See timing diagram 6.22, 6.23 for t ASO 6.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 151 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.7 Asynchronous Write See AC Characteristics T able 5.7 NOTE : V A=V alid Read Address, WD=W rite Dat a.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 152 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.8 8-Word Linear Burst W rit e Mode See AC Characteristics T able 5.8 6.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 153 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.10 S t art Initial Burst W rite Operation See AC Characteristics T able 5.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 154 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.1 1 Load Operation Timing See AC Characteristics T ables 5.5, 5.7 and 5.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 155 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.12 Program Operation Timing See AC Characteristics T ab les 5.5, 5.7 and 5.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 156 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.13 2X Program Operation Timing A1 : Address of DataRAM to be written.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 157 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.14 2X Cache Program Operation Timing 1st data input 2nd dat a input 2X cache program Command ADQ0~ A1, A2, A3 : Addre.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 158 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.15 2X Interleave Cache Program Operation Timing 1st data input 2nd data input Address Setting 2X cache program Command ADQ0~ A1, A2, A3 : Address of Dat aRAM to be written.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 159 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.16 Block Erase Operation Timing See AC Characteristics T ables 5.5, 5.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 160 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.17 Cold Reset Timing NOTE : 1) Bootcode copy operation start s 400us later than POR activation. The system power should reach Vcc after POR triggerin g level(typ. 1.5V) within 400us for valid boot code data.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 161 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.18 W arm Reset Timing See AC Characteristics T ab les 5.6. NOTE : 1) The status which can accept any registe r ba sed operation(Load, Prog ram, Erase command, etc.). 2) The status wher e reset is ongoing.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 162 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.19 Hot Reset Timing See AC Characteristics T ab les 5.6. NOTE : 1) Internal reset operation means tha t the device initializes in ternal registers and makes output signals go to default status a nd bufferRAM dat a are kept unchanged after W arm/Hot reset opera tions.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 163 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.20 NAND Flash Core Reset Timing 6.21 Dat a Protection Timing During Power Down The device is designed to offer protection from any in vo luntary program/erase during power-transitions.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 164 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.22 T oggle Bit Timing in Asynchronous Read (V A T ransition Before A VD Low) See AC Characteristics T able 5.5 NOTE : 1) V A=V alid Read Address, RD=Read Da ta. 2) Before IOBE is set to 1, RDY and INT pin are High-Z stat e.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 165 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.24 INT auto mode See AC Characteristics T ab les 5.10. NOTE : INT pin polarity is based on ‘IOBE=1 and IN T pol=1 (.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 166 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.0 TECHNICAL AND APPLICA TION NOTES From time-to-time supplemental technical information and application notes pertaining to the design a nd operation of the device in a system are included in this section.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 167 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.1.1 The INT Pin to a Host General Purpose I/O INT can be tied to a Host GPIO to detect the rising edge of INT , signaling the end of a command operation. This can be configured to operate eith er synchro nously or asynchronously as shown in the diagrams below .
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 168 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.1.2 Polling the Interrupt Register S t atus Bit An alternate method of determining the end of an operation is to c ontinuously monitor the Interrupt St atus Register Bit instead of using the INT pin.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 169 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.1.3 Determining R p V alue (DDP , QDP only) For general operation, INT operates as normal output pin, so that tF is equivalent to tR (below 10ns).
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 170 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) NOTE : 1) Refer to chapter 2.8.10 St art Address Register F101h DDP Block Diagram ~50k ohm INT 1) Vcc or Vccq Rp INT pol = ‘Low’ Busy S tate Ready VOH tf tr VOL Vss Vcc tr ,t f Ibusy [mA] Rp( oh m) Ibusy tf [ us ] KFN4G16Q2A @ Vcc = 1.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 171 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.2 Boot Sequence One of the best features MuxOneNAND has is that it can be a booting device itself si nce it contains an internally built-in boot loade r despite the fact that its core architecture is based on NAND Flash.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 172 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Partition of NAND Flash array NOTE : Step 2 and Step 3 can be copied into DRAM through two DataRAMs using dual bufferin.
MuxOneNAND2G(KFM2G16Q2A-DEBx) - 173 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 8.0 P ACKAGE DIMENSIONS 2G product (KFM2G16Q2A) 4G product (KFN4G16Q2A) 0.10 MAX 0.45 ± 0.05 0.32 ± 0.0 5 0.9 ± 0.10 BOTTOM VIEW TOP VIEW A C E B D F 0.80x9=7.20 A 0.80x1 1=8.
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