Benutzeranleitung / Produktwartung SH7781 des Produzenten Renesas
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Revision Date: Jan. 10 , 2008 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC Engine Family SH7780 Series Rev.1.00 REJ09B0261-0100 SH7785.
Rev.1.00 Jan. 10, 2008 Page ii of xxx REJ09B0261-0100 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use.
Rev.1.00 Jan. 10, 2008 Page iii of xxx REJ09B0261-0100 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MP U/ MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manua l.
Rev.1.00 Jan. 10, 2008 Page iv of xxx REJ09B0261-0100.
Rev.1.00 Jan. 10, 2008 Page v of xxx REJ09B0261-0100 Preface This LSI is a RISC (Reduced Instruction Set Co mput er) microcomp uter which includes a Renesas Technology- original RISC CPU (SH- 4A) and va rious pe ripheral fu nctions requi red to con figure a system.
Rev.1.00 Jan. 10, 2008 Page vi of xxx REJ09B0261-0100 Abbreviations ALU Arithmetic Logic Unit ASID Address Space Identifier BGA Ball Grid Array CMT Timer/Counter (Compare Mat ch Timer) CPG Clock Pulse.
Rev.1.00 Jan. 10, 2008 Page vii of xxx REJ09B0261-0100 MSB Most Significan t Bit PC Program Count er PCI Peripheral Compone nt Interconnect PCIC PCI (local bus) Controller PFC Pin Functi on Cont rolle.
Rev.1.00 Jan. 10, 2008 Page viii of xxx REJ09B0261-0100 All trademarks and registered tradema rks ar e the property of th eir respective owners..
Rev.1.00 Jan. 10, 2008 Page ix of xxx REJ09B0261-0100 Contents Section 1 Overview .................................................................................................................. 1 1.1 Features of t he SH 7785 .......................
Rev.1.00 Jan. 10, 2008 Page x of xxx REJ09B0261-0100 5.2.2 Exce ption Event Regi ster (EXPEVT )................................................................... 91 5.2.3 Inter rupt Event Register (I NTEVT) ...........................................
Rev.1.00 Jan. 10, 2008 Page xi of xxx REJ09B0261-0100 7.1.1 Address Space s ................................................................................................... 146 7.2 Register Desc riptions ............................................
Rev.1.00 Jan. 10, 2008 Page xii of xxx REJ09B0261-0100 7.8.1 Ove rview of 32-Bit Addr es s Extended Mode ..................................................... 199 7.8.2 Transition t o 32-Bit Addr ess Extended Mode .....................................
Rev.1.00 Jan. 10, 2008 Page xiii of xxx REJ09B0261-0100 8.7 Store Que ues ................................................................................................................... ... 238 8.7.1 SQ C onfiguration .............................
Rev.1.00 Jan. 10, 2008 Page xiv of xxx REJ09B0261-0100 10.4 Interrupt Sourc es .............................................................................................................. .. 324 10.4.1 NMI Interrupts ................................
Rev.1.00 Jan. 10, 2008 Page xv of xxx REJ09B0261-0100 11.5.9 Bus Arbitration ................................................................................................... 448 11.5.10 Master Mo de .................................................
Rev.1.00 Jan. 10, 2008 Page xvi of xxx REJ09B0261-0100 12.5.11 Method for Se curing Time Re quired for Initialization, Self-Refresh Cancellation, etc. ................................................................................................ 549 12.
Rev.1.00 Jan. 10, 2008 Page xvii of xxx REJ09B0261-0100 14.4.2 Channel Prio rity .................................................................................................. 706 14.4.3 DMA Transfer Types .........................................
Rev.1.00 Jan. 10, 2008 Page xviii of xxx REJ09B0261-0100 16.4.1 Reset Reque st ..................................................................................................... 769 16.4.2 Using Watchdog Ti mer Mode ................................
Rev.1.00 Jan. 10, 2008 Page xix of xxx REJ09B0261-0100 18.3.4 Timer Control Registers (T CRn) ( n = 0 to 5) ..................................................... 807 18.3.5 Input Capture Regist er 2 (TCPR2) ............................................
Rev.1.00 Jan. 10, 2008 Page xx of xxx REJ09B0261-0100 19.3.26 Color Palette 4 Transparent Co lor Register ( CP4TR) ........................................ 887 19.3.27 Display Off M ode Output Re gister (DOOR) .........................................
Rev.1.00 Jan. 10, 2008 Page xxi of xxx REJ09B0261-0100 19.4.12 Scroll Disp lay ..................................................................................................... 950 19.4.13 Wraparound Di splay ......................................
Rev.1.00 Jan. 10, 2008 Page xxii of xxx REJ09B0261-0100 20.3.21 MC Command FIFO (MCCF) .......................................................................... 1000 20.3.22 MC Status Regist er (MCS R) ................................................
Rev.1.00 Jan. 10, 2008 Page xxiii of xxx REJ09B0261-0100 21.3.12 Serial Port Regist er n (SCS PTR) ...................................................................... 1066 21.3.13 Line Status Regist er n (SCLS R) ...................................
Rev.1.00 Jan. 10, 2008 Page xxiv of xxx REJ09B0261-0100 23.2 Input/Output P ins ............................................................................................................. 1 153 23.3 Register Desc riptions ...........................
Rev.1.00 Jan. 10, 2008 Page xxv of xxx REJ09B0261-0100 24.4.1 Operations in MMC Mode ................................................................................ 1209 24.5 MMCIF Interrupt Sources ...................................................
Rev.1.00 Jan. 10, 2008 Page xxvi of xxx REJ09B0261-0100 26.4 Operation ...................................................................................................................... ... 1314 26.4.1 Bus Form at .................................
Rev.1.00 Jan. 10, 2008 Page xxvii of xxx REJ09B0261-0100 Section 28 General Purpose I/O Ports (GPIO) ........................................................... 1377 28.1 Features .......................................................................
Rev.1.00 Jan. 10, 2008 Page xxviii of xxx REJ09B0261-0100 28.2.37 Port L Pull-Up Control Register (P LPUPR ) ..................................................... 1438 28.2.38 Port M Pull-Up Control Register (P MPUPR) .................................
Rev.1.00 Jan. 10, 2008 Page xxix of xxx REJ09B0261-0100 30.3.2 Interrupt Source Regi ster (S DINT) ................................................................... 1492 30.3.3 Bypass Register (SDB PR) ...............................................
Rev.1.00 Jan. 10, 2008 Page xxx of xxx REJ09B0261-0100 Appendix ............................................................................................................................ 162 7 A. Package Dime nsions .................................
1. Overview Rev.1.00 Jan. 10, 2008 Page 1 of 1658 REJ09B0261-0100 Section 1 Overview The SH7785 incorporates a DDR2 -SDRAM interface, a PCI controll er, a DMA controller, timers, serial interfaces, au.
1. Overview Rev.1.00 Jan. 10, 2008 Page 2 of 1658 REJ09B0261-0100 Item Features CPU • Renesas Technology original architecture • 32-bit internal data bus • General-register files: ⎯ Sixteen 32.
1. Overview Rev.1.00 Jan. 10, 2008 Page 3 of 1658 REJ09B0261-0100 Item Features FPU • On-chip floating-point coprocessor • Supports single (32-bit) and double (64- bit) precisions • Supports IEE.
1. Overview Rev.1.00 Jan. 10, 2008 Page 4 of 1658 REJ09B0261-0100 Item Features Memory management unit (MMU) • 4-Gbyte address space, 256 addr ess s pace identifiers (8-bit ASID) • Supports single.
1. Overview Rev.1.00 Jan. 10, 2008 Page 5 of 1658 REJ09B0261-0100 Item Features URAM • 128-Kbyte large-capacity memory • Three independent read/write ports • 8-/16-/32-bit access by the CPU or t.
1. Overview Rev.1.00 Jan. 10, 2008 Page 6 of 1658 REJ09B0261-0100 Item Features Local bus state controller (LBSC) • A dedicated Local-bus interfac e ⎯ Controls the external memory space divid ed into seven 64-Mbyte (max.) areas ⎯ The interface type, bus width, and wa it-cycle insertio n can be set for each area.
1. Overview Rev.1.00 Jan. 10, 2008 Page 7 of 1658 REJ09B0261-0100 Item Features DDR2-SDRAM bus controller (DBSC) • A dedicated DDR2-SDRAM bus interface ⎯ Multi-bank support: Supports mult i-bank (.
1. Overview Rev.1.00 Jan. 10, 2008 Page 8 of 1658 REJ09B0261-0100 Item Features PCI bus controller (PCIC) • PCI bus controller (supports a subset of revision 2.
1. Overview Rev.1.00 Jan. 10, 2008 Page 9 of 1658 REJ09B0261-0100 Item Features Watchdog timer (WDT) • Number of channels: One • Single-channel watchdog time r (operation in watchdog-timer or inte.
1. Overview Rev.1.00 Jan. 10, 2008 Page 1 0 of 1658 REJ09B0261-0100 Item Features Display unit (DU) • Display plane ⎯ 6 planes (a maximum number at 480 dots x 234 dots) ⎯ 4 planes (a maximum num.
1. Overview Rev.1.00 Jan. 10, 2008 Page 1 1 of 1658 REJ09B0261-0100 Item Features Synchronized serial I/O with FIFO (SIOF) • Number of channels: One (max.
1. Overview Rev.1.00 Jan. 10, 2008 Page 1 2 of 1658 REJ09B0261-0100 Item Features Serial sound interface (SSI) • Number of channels: Two (max.) • Supports transfer of compressed and non-co mpressed data • Selectable frame size NAND flash memory controller (FLCTL) • Number of channels: One (max.
1. Overview Rev.1.00 Jan. 10, 2008 Page 1 3 of 1658 REJ09B0261-0100 1.2 Block Diagram A block diagram of t he SH7785 is give n as figure 1.1. ROM NOR Flash PC Card/ATA3 DDR2-SDRAM DDR2-400/600 1 GB ma.
1. Overview Rev.1.00 Jan. 10, 2008 Page 1 4 of 1658 REJ09B0261-0100 1.3 Pin Arrangement Table Table 1.2 Pin Function No. Pin Name I/O Function No. Pin Name I/O Function 1 MDQ0 IO DDR data 0 28 MDQ27 I.
1. Overview Rev.1.00 Jan. 10, 2008 Page 1 5 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 55 MA10 O DDR address 10 87 D12 IO Local bus data 12 56 MA11 O DDR address 11 88.
1. Overview Rev.1.00 Jan. 10, 2008 Page 1 6 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 119 A12 O Local bus a ddress 12 140 RD / FRAME O/O Read strobe/MPX IF FRAME 120 .
1. Overview Rev.1.00 Jan. 10, 2008 Page 1 7 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 155 D37/AD5/DR5 IO/IO/O Loc al bus data 37/PCI address data 5/Digital red 5 168 .
1. Overview Rev.1.00 Jan. 10, 2008 Page 1 8 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 181 D63/AD31 IO/IO Local bus d ata 63/PCI address data 31 199 REQ2 I Bus request.
1. Overview Rev.1.00 Jan. 10, 2008 Page 1 9 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 217 BREQ / BSACK I Bus request (Master mode)/ Bus acknowledgement (Slave mode) 2.
1. Overview Rev.1.00 Jan. 10, 2008 Page 2 0 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 249 SIOF_SCK/ HAC0_BITCLK/ SSI0_CLK IO/I/IO SIOF serial clock/HAC0 bit clock/SSI.
1. Overview Rev.1.00 Jan. 10, 2008 Page 2 1 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 269 MODE11/ SCIF4_SCK/ FD3 I/IO/IO Mode control 11/SCIF4 serial clock/NAND flash.
1. Overview Rev.1.00 Jan. 10, 2008 Page 2 2 of 1658 REJ09B0261-0100 1.4 Pin Arrangement Package: 436-p in FC-BGA, 19 mm x 19 mm, ball pitch: 0.8 mm A B C D E F G H J K L M N P R T U V W Y AA A B C D E.
1. Overview Rev.1.00 Jan. 10, 2008 Page 2 3 of 1658 REJ09B0261-0100 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 VSS A25 .
1. Overview Rev.1.00 Jan. 10, 2008 Page 2 4 of 1658 REJ09B0261-0100 1.5 Physical Memory Address Map The SH7785 supports 32-bit virtual address space, and suppor ts both 29-bit and 32-bit physical address spaces. For details of ma ppings from the virtual addre ss space to the physical address spaces, see section 7, Memory Ma nagement Unit (MMU).
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 2 5 of 1658 REJ09B0261-0100 Section 2 Programming Model The programm ing model of this LSI i s explained in t his section. T h is LSI h as registers an d data formats as shown bel ow. 2.1 Data Formats The data forma ts supported i n this LSI are shown i n figure 2 .
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 2 6 of 1658 REJ09B0261-0100 2.2 Register Descriptions 2.2.1 Privileged Mode and Banks (1) Processing Modes This LSI has two processing modes, user m ode and pri vileged mode .
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 2 7 of 1658 REJ09B0261-0100 (DBR), whic h can only be accessed in privil eged mode. Some bits of the status register (s uch as the RB bit) can only be acce ssed in privileged mode.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 2 8 of 1658 REJ09B0261-0100 Table 2.1 Initial Register Va lues Type Registers Initial Value * General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BA.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 2 9 of 1658 REJ09B0261-0100 31 0 R0 _ BANK0 * 1, * 2 R1 _ BANK0 * 2 R2 _ BANK0 * 2 R3 _ BANK0 * 2 R4 _ BANK0 * 2 R5 _ BANK0 * 2 R6 _ BANK0 * 2 R7 _ BAN.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 0 of 1658 REJ09B0261-0100 2.2.2 General Re gisters Figure 2.3 s hows the relat ionship bet ween the processi ng modes an d general regi sters. This L SI has twenty-fo ur 32-bit general registers (R 0_BANK0 t o R7_BANK 0, R0_BAN K1 to R7_BANK1, and R8 to R15).
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 1 of 1658 REJ09B0261-0100 Note on Pr ogrammin g: As the user's R 0 to R7 are a ssigned to R0_BAN K0 to R7_ BANK0, an d after an except ion or in.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 2 of 1658 REJ09B0261-0100 7. Single -precision float ing-poin t extended regi ster matrix, XMTRX: XMT RX comprises all 16 XF registers.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 3 of 1658 REJ09B0261-0100 2.2.4 Contr ol Registers (1) Status Register (S R) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BIt: 0111000000000000 MD.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 4 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 27 to 16 — All 0 R Reserved For details on reading/writing this bit, see Ge neral Precautions on Handling of Product.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 5 of 1658 REJ09B0261-0100 (2) Saved Status Register (SSR) (32 bi ts, Privileged Mode, Initial Value = Undefined) The contents of SR are sa ved to SSR in the event of an excep tion or interrupt.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 6 of 1658 REJ09B0261-0100 (4) Floating-P oint Status/Contr ol Register (FPSCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000100 RRRRR.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 7 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 17 to 12 Cause 000000 R/W 11 to 7 Enable (EN) 00000 R/W 6 to 2 Flag 00000 R/W FP.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 8 of 1658 REJ09B0261-0100 <Bi g endian> DR (2i) FR (2i) FR (2i+1) 8n+4 8n+7 8n 8n+3 63 0 63 32 31 0 Floatin g -point re g ister Memory area 63 .
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 9 of 1658 REJ09B0261-0100 2.3 Memory-Mapped Registers Some control r egisters are ma pped to the following mem ory areas. Each of the mapped registers has two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are use d as follows.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 4 0 of 1658 REJ09B0261-0100 2.4 Data Formats in Registers Register opera nds are always longwords (32 bi ts). When a memory ope rand is only a by te (8 bits) or a word (16 bits), it is sign-extended into a longw ord when loaded into a register.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 4 1 of 1658 REJ09B0261-0100 Address A A 70 7 0 70 7 0 31 15 0 15 0 31 0 15 0 31 0 23 15 7 0 A + 1 A + 2 A + 3 Byte 0 Word 0 Lon g word Word 1 Byte 1 By.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 4 2 of 1658 REJ09B0261-0100 From any state when reset/manual reset input Reset state Instruction execution state Sleep instruction execution Power-down state Interrupt occurence Reset/manual reset clearance Reset/manual reset input Reset/manual reset input Figure 2.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 4 3 of 1658 REJ09B0261-0100 2.7 Usage Notes 2.7.1 Notes on Self-Modifying Code To accelerate the processing speed , the instruction prefetching cap ability of this LSI has been significantl y enhanced from that of t h e SH-4.
2. Programming Model Rev.1.00 Jan. 10, 2008 Page 4 4 of 1658 REJ09B0261-0100.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 4 5 of 1658 REJ09B0261-0100 Section 3 Instruction Set This LSI's instruction set is imp lemented with 16-bit fixe d-length instructi ons. This L SI can use byte (8-bit), w ord (16-bit ), longword (3 2-bit), an d quadwor d (64-bit) data sizes for memory access.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 4 6 of 1658 REJ09B0261-0100 Table 3.1 Execution Order of Delayed Branch Instructions Instructions Execution Order BRA TARGET (Delayed branc h instruction.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 4 7 of 1658 REJ09B0261-0100 3.2 Addressing Modes Addressing modes and effective address calculation methods are shown in tabl e 3.2. When a location in virtual memory space is accessed (A T in MMUCR = 1), t he effective address is translated into a physical memory addre ss.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 4 8 of 1658 REJ09B0261-0100 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula Register indirect with pre- decre.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 4 9 of 1658 REJ09B0261-0100 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula GBR indirect with displace- ment @(disp:8, GBR) Effective address is register GBR contents with 8-bit displacement disp added .
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 0 of 1658 REJ09B0261-0100 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula PC-relative disp:8 Effective address is PC + 4 with 8-bit displacement disp added after being sign-e xtended and multiplied by 2.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 1 of 1658 REJ09B0261-0100 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula Immediate #imm:8 8-bit immediate dat a imm of TST, AND, OR, or XOR instruction is zero-extended.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 2 of 1658 REJ09B0261-0100 3.3 Instruction Set Table 3.3 sho ws the notat ion used i n the SH i nstruction li sts shown i n tables 3.4 to 3.13. Table 3.3 Notation Used in Instruction List Item Format Description Instruction mnemonic OP.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 3 of 1658 REJ09B0261-0100 Item Format Description Privileged mode "Privileged" means the instruction ca n only be executed in privileged mode.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 4 of 1658 REJ09B0261-0100 Instruction Operation Instruction C ode Privileged T Bit New MOV.B @(disp * ,Rm),R0 (disp + Rm) → sign extension → R0 10000100mmmmdddd — — — MOV.W @(disp * ,Rm),R0 (disp × 2 + Rm) → sign extension → R0 10000101mmmmdddd — — — MOV.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 5 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New MOVT Rn T → Rn 0000nnnn00101001 — — — SWAP.B Rm,Rn Rm → swap lower 2 bytes → Rn 0110nnnnmmmm1000 — — — SWAP.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 6 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New CMP/STR Rm,Rn When any bytes are equal, 1 → T Otherwise, 0 →.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 7 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New MULU.W Rm,Rn Unsigned, Rn × Rm → MACL 16 × 16 → 32 bits 00.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 8 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New XOR #imm,R0 R0 ∧ imm → R0 11001010iiiiiiii — — — XOR.B #imm, @(R0,GBR) (R0 + GBR) ∧ imm → (R0 + GBR) 11001110iiiiiiii — — — Table 3.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 9 of 1658 REJ09B0261-0100 Table 3.8 Branch Instructions Instruction Operation Instruction C ode Privileged T Bit New BF label When T = 0, disp × 2 + P.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 6 0 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New LDC Rm,SSR Rm → SSR 0100mmmm00111110 Privileged — — LDC Rm.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 6 1 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New SETS 1 → S 0000000001011000 — — — SETT 1 → T 000000000.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 6 2 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New SYNCO Data acce sses invoked by the following instructions are not executed until execution of data accesses which precede this instruction has been completed.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 6 3 of 1658 REJ09B0261-0100 Instruction Operation Instruction Cod e Privileged T Bit New FADD FRm,FRn FRn + FRm → FRn 1111nnnnmmmm0000 — — — FCMP.
3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 6 4 of 1658 REJ09B0261-0100 Table 3.12 Floating-Point Contr ol Instructions Instruction Operation Instructio n Code Privileged T Bit New LDS Rm,FPSCR Rm → FPS CR 0100mmmm01101010 — — — LDS Rm,FPUL Rm → FPUL 0100mmmm01011010 — — — LDS.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 6 5 of 1658 REJ09B0261-0100 Section 4 Pipelining This LSI is a 2-ILP (instruction-level-paralle lism) supe rscalar pi pelining mi croprocessor. Instruction e x ecution i s pipelined, a n d two i nstructions can be executed i n parallel .
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 6 6 of 1658 REJ09B0261-0100 Figure 4.2 s hows the inst ruction execution p atterns. Repre sentations in figure 4.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 6 7 of 1658 REJ09B0261-0100 I1 I2 I3 (I1) (ID) ID E1/S1 E2/s2 E3/s3 WB I3 I3 I3 (I2) (I3) I1 I2 ID E1/S1 E2/S2 E3/S3 WB I1 I2 ID E1/S1 E2/S2 E3/S3 WB I1 I2 ID.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 6 8 of 1658 REJ09B0261-0100 I3 I3 I3 I1 I2 ID s1 s2 s3 WB I1 I2 ID WB I1 I2 ID E1/S1 E2/s2 E3/s3 E1/s1 E2/s2 E3/S3 WB I1 I2 I3 ID E1 E2 E3 WB (2-1) 1-step ope.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 6 9 of 1658 REJ09B0261-0100 I1 I2 I3 ID S1 S2 S3 WB I3 I3 I3 I3 I1 I2 ID S1 S2 S3 WB I1 I2 ID S1 S2 S3 WB E2S2 E3S3 WB E1S1 I1 I2 ID S1 S2 S3 WB E2S2 E3S3 WB .
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 0 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3 WB I3 I3 I3 I3 I3 I3 I3 I1 I2 ID s1 s2 s3 WB I1 I2 ID s1 s2 s3 WB I1 I2 ID S1 S2 S3 WB I1 I2 ID E1s1 E2s2 E3s.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 1 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3 WB I3 I3 I3 I3 I3 I3 I3 I1 I2 ID WB I1 I2 ID S1 S2 S3 E1s1 E2s2 E3s3 WB I1 I2 ID WB I1 I2 ID S1 S2 S3 E1S1 E2.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 2 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3 WB MS I3 I3 I3 I3 I3 I3 I3 I3 I1 I2 ID E1 M2 M3 E1 M2 M3 MS E1 M2 M3 MS M2 M3 MS I1 I2 ID I1 I2 ID S1 S2 S3 W.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 3 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3 s1 s2 s3 WB s1 s2 s3 WB FS1 FS2 FS3 FS4 FS1 FS2 FS3 FS4 FS FS1 FS2 FS3 FS4 FS1 FS2 FS3 FS4 FS1 FS2 FS3 FS4 FS.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 4 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3 FS1 FS2 FS3 FS4 FS I1 I2 I3 ID I1 I2 I3 ID s1 s2 s3 FS1 FS2 FS3 FS4 FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 I3 ID FE.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 5 of 1658 REJ09B0261-0100 I1 I2 I3 ID FE1 FE2 FE3 FEPL FEPL FE4 FE5 FE6 FS I1 I2 I3 ID FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 I3 ID FE1 FE2 FE1 FE2 FE3 FE4 FE5 FE.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 6 of 1658 REJ09B0261-0100 4.2 Parallel-Executability Instructions are categorized into six groups according to the inte rnal function bl ocks used, as shown in tabl e 4.2. Table 4.3 shows t he paral lel-executabili ty of pairs o f instructions i n terms of groups.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 7 of 1658 REJ09B0261-0100 Instruction Group Instruction FE FADD FSUB FCMP (S/D) FCNVDS FCNVSD FDIV FIPR FLOAT FMAC FMUL FRCHG FSCHG FSQRT FTRC FTRV FSCA FSRRA FPCHG CO AND.B #imm,@(R0,GBR) ICBI LDC Rm,DBR LDC Rm, SGR LDC Rm,SR LDC.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 8 of 1658 REJ09B0261-0100 Table 4.3 Combination of Precedin g and Following Instructions Preceding Instruction (addr) EX MT BR LS FE CO EX No Yes Yes Yes Ye.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 9 of 1658 REJ09B0261-0100 4.3 Issue Rates and Execution Cycles Instruction execution cycles a re summarized in table 4.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 0 of 1658 REJ09B0261-0100 Table 4.4 Issue Rates and Execution Cycles Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 1 EXTS.B Rm,Rn EX 1 1 2-1 2 EXTS.W Rm,Rn EX 1 1 2-1 3 EXTU.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 1 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 30 MOV.L Rm,@-Rn LS 1 1 3-1 31 MOV.B R0,@(disp,Rn) LS 1 1 3-1 32 MOV.W R0,@(disp,Rn ) LS 1 1 3-1 33 MOV.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 2 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 60 CMP/GT Rm,Rn EX 1 1 2-1 61 .
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 3 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 90 TST Rm,Rn EX 1 1 2-1 91 TST #imm,R0 EX 1 1 2-1 92 TST.B #imm,@(R0,GBR) CO 3 3 3-2 93 XOR Rm,Rn EX 1 1 2-1 94 XOR #imm,R0 EX 1 1 2-1 Logical instructions 95 XOR.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 4 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 120 JMP @Rn BR 1+3 1 1-2 121 J.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 5 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 150 LDC.L @Rm+,SPC LS 1 1 4-5 151 LDC.L @Rm+,VBR LS 1 1 4-5 152 LDS Rm,MACH LS 1 1 5-1 153 LDS Rm,MACL LS 1 1 5-1 154 LDS Rm,PR LS 1 1 4-13 155 LDS.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 6 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 180 FLDI0 FRn LS 1 1 6-13 181 FLDI1 FRn LS 1 1 6-13 182 FMOV FRm,FRn LS 1 1 6-9 183 FMOV.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 7 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 210 FABS DRn LS 1 1 6-12 211 F.
4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 8 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 241 FRCHG FE 1 1 6-14 242 FSCH.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 8 9 of 1658 REJ09B0261-0100 Section 5 Exception Handling 5.1 Summary of Exception Handling Exception ha ndling processi ng is handle d by a special routine whic h is executed by a reset, general exception handling, or in terrupt.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 0 of 1658 REJ09B0261-0100 Table 5.2 States of Regist er in Each Operating Mode Register Name Abbr. Power-on Reset Manual Reset Sleep Standby TRAPA e.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 1 of 1658 REJ09B0261-0100 5.2.2 Excepti on Event Register (E XPEVT) The exception event register (EXP EVT) consists of a 12-bit exce ption code. The exception code set in EXPEVT is that for a reset or general exception event.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 2 of 1658 REJ09B0261-0100 5.2.3 Interrupt Event Re gister (INTEVT) The interrupt event register (INTEVT) consi sts of a 14-bit exception code. T h e exception code is set automatically by hardware when an exce p tion occurs.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 3 of 1658 REJ09B0261-0100 5.2.4 Non-Sup port Detection Exce ption Registe r (EXPMASK) The non-support de tection exception register (EXPMASK) is u sed to enable or disable the generation of exceptions i n response to the use of a n y of funct ions 1 to 3 l isted below.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 4 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 5 ⎯ All 0 R Reserved For details on reading/writing these b its, see General Precautions on Handling of Product. 4 MMCAW 1 R/W Memory-Mapped Cac he Associative Write 0: Memory-mapped cache associative wr ite is disabled.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 5 of 1658 REJ09B0261-0100 5.3 Exception Handling Functions 5.3.1 Excepti on Handling Flow In exceptio n handlin g, the content s of the p rogram cou.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 6 of 1658 REJ09B0261-0100 5.4 Exception Types and Priorities Table 5.3 sho ws the types o f exceptions, with th eir relative priorities, vector addresses, a nd exception/interrup t codes.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 7 of 1658 REJ09B0261-0100 Exception T ransition Direction * 3 Exception Category Execution Mode Exception Priority Level * 2 Priority Order * 2 Vect.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 8 of 1658 REJ09B0261-0100 5.5 Exception Flow 5.5.1 Excepti on Flow Figure 5.1 s hows an out line flowchart of the basic operations in i nstruction e xecution and exception ha ndling.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 9 of 1658 REJ09B0261-0100 Execute next instruction Is hi g hest- priority exception re-exception type? Cancel instruction execution result Yes Yes Yes No No No No Yes SSR ← SR SPC ← PC SGR ← R15 EXPEVT/INTEVT ← exception code SR.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 00 of 1658 REJ09B0261-0100 5.5.2 Excepti on Source Acceptance A priority ranking is provided for all except ions fo r use in dete rmining w hich of tw o or more simultaneously ge nerated exceptions should be accepted.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 01 of 1658 REJ09B0261-0100 5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, genera l exceptions and interrupts are accepted.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 02 of 1658 REJ09B0261-0100 5.6 Description of Exceptions The various e xception ha ndling operati ons explaine d here are exception sources , transition address on the occurrence of excep tion, and proces sor operation when a transition is made.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 03 of 1658 REJ09B0261-0100 (4) Instruction TLB Mult iple Hit Exception • Source: Multiple ITLB address matches • Transition a ddress: H'A0 .
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 04 of 1658 REJ09B0261-0100 5.6.2 General E xceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB addre ss comparison • Transi.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 05 of 1658 REJ09B0261-0100 (2) Instruction TLB Miss E xception • Source: Address mismatch in ITLB address comparison • Transition ad dress: VBR .
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 06 of 1658 REJ09B0261-0100 (3) Initial Page Write Exception • Source: TLB is hit in a store access, but di rty bit D = 0 • Transition ad dress: .
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 07 of 1658 REJ09B0261-0100 (4) Data TLB Protection Violation Exception • Source: The access does not acco rd with the UTLB protection information (PR bits or EPR bits) sh own in t able 5.4 an d table 5.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 08 of 1658 REJ09B0261-0100 The PC and SR contents for the instru ction at which this excep ti on occurred are save d in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0A0 (for a read access) or H' 0C0 (for a write access) is set in E XPEVT.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 09 of 1658 REJ09B0261-0100 (5) Instruction TLB Protec tion Violation Exception • Source: The access does not accord with the ITLB pr otection inf ormation (PR bits or EPR bits) shown in ta ble 5.6 and table5.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 10 of 1658 REJ09B0261-0100 ITLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 00A0; SR.MD = 1; SR.RB = 1; SR.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 11 of 1658 REJ09B0261-0100 • Transition operations: The virtual a ddress (32 bi ts) at which t his exception occurre d is set in TE A, and the correspondi ng virtual pa ge number (22 bit s) is set in PTEH [31:10] .
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 12 of 1658 REJ09B0261-0100 (7) Instruction Address Error • Sources: ⎯ Instructio n fetch from othe r than a word bounda ry (2n +1) ⎯ Instruction fetch from area H'80000000 to H'FFFFFFFF in user mode Area H'E5000000 t o H'E5FFFFFF can be a ccessed in user mode.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 13 of 1658 REJ09B0261-0100 (8) Uncondi tional Trap • Source: Execut ion of TRAP A instructio n • Transition ad dress: VBR + H' 00000100 •.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 14 of 1658 REJ09B0261-0100 (9) General Illegal Instruction Exception • Sources: ⎯ Decoding of a n undefined instruct ion not i n a delay sl ot D.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 15 of 1658 REJ09B0261-0100 (10) Slot Illegal Instruc tion Exception • Sources: ⎯ Decoding of a n undefined instruct ion in a d elay slot Delayed.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 16 of 1658 REJ09B0261-0100 (11) General FPU Disable Exception • Source: Decodi ng of an FPU instructi on* not in a delay slot with SR.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 17 of 1658 REJ09B0261-0100 (12) Slot FP U Disa ble Exception • Source: Decod ing of an F PU instructi on in a del ay slot wi th SR.FD = 1 • Transition ad dress: VBR + H' 00000100 • Transition operations: The PC contents for the preceding delayed bran ch instru ction ar e saved in SP C.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 18 of 1658 REJ09B0261-0100 (13) Pre-Execution User Break/Post-Execution User Bre ak • Source: Fulfilling of a break conditio n set in the user bre.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 19 of 1658 REJ09B0261-0100 (14) FPU Exception • Source: Except ion due to exec ution of a floating-p oint opera tion • Transition ad dress: VBR + H' 00000100 • Transition operation s: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR .
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 20 of 1658 REJ09B0261-0100 5.6.3 Interrupts (1) NMI (N onmaskable Interr upt) • Source: NMI p in edge detecti on • Transition ad dress: VBR + H&.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 21 of 1658 REJ09B0261-0100 The code corresponding t o the each interrupt source is set in INTEVT . The BL, MD, and RB bits are set to 1 in SR, and a branch is made to VBR + H'0600. When the INTMU bit in CPUOPM is 1, IMASK bit in SR is changed to accepted interrupt level.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 22 of 1658 REJ09B0261-0100 8. In itial page write exception in second data transfer (2) Indivisible Delayed Branch Instru ction an d Delay Slot Instruction As a delayed branch instruction and its associated del ay slot inst ruction are i ndivisible, t hey are treated as a single instruction .
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 23 of 1658 REJ09B0261-0100 5.7 Usage Notes (1) Return from Exception Handling A. Check the BL bit in SR with software. If SPC and S SR have been saved to memory, set the BL bit in SR to 1 before restor ing them.
5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 24 of 1658 REJ09B0261-0100 other exceptio ns is determine d depending on the processing mode by SR after restoring or the BL bit. The comple tion type exception is accepted before branching to the destination of RTE instruc tion.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 25 of 1658 REJ09B0261-0100 Section 6 Floating-Point Unit (FPU) 6.1 Features The FPU has the following features.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 26 of 1658 REJ09B0261-0100 6.2 Data Formats 6.2.1 Fl oating-Poin t Format A floatin g-point n umber con sists of t he followi ng three fie ld.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 27 of 1658 REJ09B0261-0100 Table 6.1 Floating-Poin t Number Formats and Parameters Parameter Single-Preci sion Double-Precision Total bit wid.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 28 of 1658 REJ09B0261-0100 Table 6.2 Floating-Poi nt Ranges Type Single-Precision Double-Precision Signaling non- number H'7FFF FFFF to .
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 29 of 1658 REJ09B0261-0100 6.2.2 No n-Numbers (Na N) Figure 6.3 shows the bit p attern of a non-number (NaN).
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 30 of 1658 REJ09B0261-0100 See section 10, Instruction De scriptions of the SH-4A Extended Functions Softw are Manual for details of floating- point operat ions when a non-n umber (Na N) is input .
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 31 of 1658 REJ09B0261-0100 6.3 Register Descriptions 6.3.1 Fl oating-Poin t Registers Figure 6.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 32 of 1658 REJ09B0261-0100 7. Single-precision float ing-poin t extended regi ster matrix, XMTRX: XMT RX comprises all 16 XF registers.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 33 of 1658 REJ09B0261-0100 6.3.2 Floa ting-Point Status/ Control Register (FPSCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: 000000.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 34 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 17 to 12 Cause All 0 R/W 11 to 7 Enable All 0 R/W 6 to 2 Flag All 0 R/W.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 35 of 1658 REJ09B0261-0100 <Bi g endian> DR (2i) FR (2i) FR (2i+1) 8n+4 8n+7 8n 8n+3 63 0 63 32 31 0 Floatin g -point re g ister Memory.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 36 of 1658 REJ09B0261-0100 Table 6.3 Bit Allocation for FPU E xception Handling Field Name FPU Error (E) Invalid Operation (V) Division by Ze.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 37 of 1658 REJ09B0261-0100 6.4 Rounding In a floating-point instr uction, rounding is performed when g enerating the final operation r esult from the intermediate result.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 38 of 1658 REJ09B0261-0100 6.5 Floating-Point Exceptions 6.5.1 General FPU Disable Exceptions a nd Slot FPU Disable Exceptions FPU-related exceptions are occurred when an FPU instruction is executed with SR.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 39 of 1658 REJ09B0261-0100 6.5.3 FPU E xception Handling FPU exception handling is initiated in the following cases: • FPU error (E): FPSCR.DN = 0 and a denormalized numb er is input • Invalid operation (V): FPSCR.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 40 of 1658 REJ09B0261-0100 6.6 Graphics Support Functions This LSI supports two kinds of graphics functio ns: new instr uctions for geometric op erations, and pair single -precision t ransfer instructions that enable high-speed data transfer.
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 41 of 1658 REJ09B0261-0100 (2) FTRV XMTRX, FVn (n: 0, 4, 8, 12) This instruction is basically used for the following purposes: • Matrix (4 .
6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 42 of 1658 REJ09B0261-0100 This instruction chang es the value of the SZ bit in FPSCR, enabling fast switching between use and non-use of pair single-p recision data transfer.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 43 of 1658 REJ09B0261-0100 Section 7 Memory Management Unit (MMU) This LSI supports an 8-b it address space identifier, a 32-bit virt ual addres s space, and a 29-bit or 32-bit physical address space.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 44 of 1658 REJ09B0261-0100 7.1 Overview of MMU The MMU was conceived as a means of making ef ficient use of physical memory.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 45 of 1658 REJ09B0261-0100 There are tw o methods by which the MM U can perform mappi ng from vi rtual memo ry to physical memory: the paging method, using fixed- length address translation, an d the segment method, using variable-len gth address translation.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 46 of 1658 REJ09B0261-0100 7.1.1 Addre ss Spaces (1) Virtual Address Space This LSI supports a 32-bit virtua l address space, and can access a 4-Gbyte address space. The virtual address space is divi ded into a number of areas, as shown in figures 7.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 47 of 1658 REJ09B0261-0100 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 Physical address space 256 256 U0 area Cacheable Addres.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 48 of 1658 REJ09B0261-0100 (b) P1 Area The P1 area does not allow address tra nslation using t he TLB but can be accessed using t he cache. Regardless of whether the M MU is enabled or disa bled, clearing t he upper 3 bi ts of an ad dress to 0 gives the corr esponding phys ical address.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 49 of 1658 REJ09B0261-0100 The area from H'E000 0000 to H'E3FF FFFF comp rises addresses for accessing the store queue s (SQs). In user mode, t he access right is specified by the SQMD bit in MM UCR.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 50 of 1658 REJ09B0261-0100 (2) Physical Address Sp ace This LSI supports a 29-bit physical address space. The physical addr ess space is divided into eight areas as shown in figure 7.5. Area 7 is a reserv ed area.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 51 of 1658 REJ09B0261-0100 the return from the exception handling routine, the instruction which caused the TLB miss exception is re-execu ted.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 52 of 1658 REJ09B0261-0100 7.2 Register Descriptions The following registers are related to MMU processing.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 53 of 1658 REJ09B0261-0100 Register Name Abbreviation Power-on Reset Manual Reset Sleep Standby Instruction re-fetch inhibit control register IRMCR H'0000 0000 H'0000 0000 Retained Retained 7.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 54 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 10 VPN Undefined R/W Virtual Page Number 9, 8 ⎯ All 0 R Reserve d For details on reading from or writing to these bits, see description in General Precautions on Hand ling of Product.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 55 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 V Undefi ned R/W 7 SZ1 Undefined R/W 6 PR1 Undefi ned R/W 5 PR0 Un.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 56 of 1658 REJ09B0261-0100 7.2.4 TLB Excepti on Address Register (TEA) After an MMU exception or addr ess error exception occurs, the virtual address at which the exception occ urred is st ored.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 57 of 1658 REJ09B0261-0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit: 0000000000000000 Initial value: R/W R/W R/W R/W R/W R/W R .
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 58 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 25, 24 ⎯ All 0 R Reserved For details on reading from or writing to these bits, see description in General Precautions on Hand ling of Product.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 59 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 ME 0 R/W TLB Extended Mode Switching 0: TLB compatible mode 1: TLB extended mode For modifying the ME bit value, always set the TI bit to 1 to invalidate the contents of ITLB and UTLB.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 60 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 14 ⎯ All 0 R Reserve d For details on reading/writing these b its, see General Precautions on Handling of Product.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 61 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 8 ⎯ All 0 R Reserve d For details on reading from or writing to these bits, see description in General Precautions on Hand ling of Product.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 62 of 1658 REJ09B0261-0100 7.2.8 Instr uction Re-Fetch Inhibit Control Register (IRMCR) When the specific resource is change d, IRMCR controls whether the instruction fet ch is performed agai n for the next instr uction.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 63 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 R1 0 R/W Re-Fetch Inhi bit 1 after Register Change When a register allocated in a ddresses H'FF200000 to H'FF2FFFFF is changed, this bit controls whether re- fetch is performed for the next instruction.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 64 of 1658 REJ09B0261-0100 7.3 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0) 7.3.1 Unified TLB (UTLB) Configuration The UTLB is used for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 65 of 1658 REJ09B0261-0100 • SH: Share status bit When 0, pa ges are not sha red by processes.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 66 of 1658 REJ09B0261-0100 1: Cacheable When the cont rol register area is ma pped, thi s bit must be cleared to 0. • D: Dirty bit Indicates whet her a write ha s been perfo rmed to a page .
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 67 of 1658 REJ09B0261-0100 7.3.2 Instruction T LB (ITLB) Configuration The ITLB is used to translate a virtual addre ss to a physical ad dress in an instruction access. Information in the address translation table located in the UTLB is cache d into the ITLB.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 68 of 1658 REJ09B0261-0100 SR.MD? R/W? R/W? Yes Yes No No No Yes Yes Yes No PR? PR? D? R/W? W W W R R R R W R/W? WT? 1 1 0 0 00 or 01 10 11 01 or 11 00 or 10 Yes No Internal resource access 1 0 CCR.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 69 of 1658 REJ09B0261-0100 Figure 7.10 shows a flowchart of a me mory access using the ITLB.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 70 of 1658 REJ09B0261-0100 7.4 TLB Functions (TLB Extended Mode; MMUCR.ME = 1) 7.4.1 Unified TLB (UTLB) Configuration Figure 7.11 s hows the co nfiguration of the UTLB in TLB extended m ode.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 71 of 1658 REJ09B0261-0100 0001: 4-Kb yte page 0010: 8-Kb yte page 0100: 64-K byte page 0101: 256- Kbyte page 0111: 1-Mb yte pa ge 1000: 4-Mb yte pa ge 1100: 64-M byte page Note: When a value othe r than those listed ab ov e is reco rded, opera tion is not guar anteed.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 72 of 1658 REJ09B0261-0100 EPR[1]: Writing in user mode EPR[0]: Exec ution in u ser mode (inst ruction fet ch) • C: Cacheability bit Indicates whether a page is c acheable. 0: Not cacheable 1: Cacheable When the cont rol register area is ma pped, thi s bit must be cleared to 0.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 73 of 1658 REJ09B0261-0100 Virtual address Physical address 31 1-Kbyte pa g e 10 9 0 VPN Offset 28 10 9 0 PPN Offset 31 4-Kbyte pa g e 12 .
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 74 of 1658 REJ09B0261-0100 7.4.3 Addre ss Translation Method Figure 7.14 is a flowchart of memory access using the UTLB in TLB extended mode.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 75 of 1658 REJ09B0261-0100 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match, ASIDs match, and V = 1 Only one entry matches SR.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 76 of 1658 REJ09B0261-0100 Figure 7.15 is a flowchart of memory acces s using the ITLB in TLB extended mode. SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match, ASIDs match, and V = 1 Only one entry matches SR.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 77 of 1658 REJ09B0261-0100 7.5 MMU Functions 7.5.1 MM U Hardware Managem ent This LSI supports the following MMU functions.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 78 of 1658 REJ09B0261-0100 7.5.3 MMU Instruction (LDTLB) A TLB load instruction (LDTLB) is provide d for recording UTLB entries.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 79 of 1658 REJ09B0261-0100 The operation of the LDTLB instructio n is show n in figure s 7.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 80 of 1658 REJ09B0261-0100 PPN[28:10] PPN[28:10] PPN[28:10] ESZ [ 3:0 ] ESZ [ 3:0 ] ESZ [ 3:0 ] SH SH SH C C C EPR [ 5:0 ] EPR [ 5:0 ] EPR.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 81 of 1658 REJ09B0261-0100 7.5.5 Avoiding Synony m Problems When information on 1- or 4-Kbyte pages is written as TLB entries, a synonym problem may arise.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 82 of 1658 REJ09B0261-0100 7.6 MMU Exceptions There are seven M MU except ions: instr uction TLB m ultiple hit exce ption, inst ruction TL.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 83 of 1658 REJ09B0261-0100 7.6.2 Instr uction TLB Miss Exception An instruction TLB miss exceptio n occurs when address translation information for the virtual address to which an instruction access is made is not found in th e UTLB entries by the hardware ITLB miss handling routine.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 84 of 1658 REJ09B0261-0100 3. In TLB co mpatible mode, execute th e LDTLB instruction and write the con tents of PTEH and PTEL to the TLB. In TLB extend ed mode, exec ute the LDTL B inst ruction and write the contents of PTE H, PTEL, PTEA to the UTLB.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 85 of 1658 REJ09B0261-0100 (2) Software Processing (Instruction TLB Protection Vi olation Exception Handling Routine) Resolve the ins truc.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 86 of 1658 REJ09B0261-0100 3. Sets exception code H'040 in the case of a re ad, or H'060 in the case of a write in EXPEVT (OCBP, OCBWB: read; OCBI, MOVC A.L: write). 4. Sets th e PC value indicating the address of th e instruction at which th e exception occurred in SPC.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 87 of 1658 REJ09B0261-0100 7.6.6 Data TLB Protection Violati on Exception A data TLB pr otection viol ation excepti on occurs whe n , even.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 88 of 1658 REJ09B0261-0100 7.6.7 Initial Page Write Exception An initial page write excep tion occurs when the D bit is 0 even though a UTLB entry contains address translation information matching the virtual addre ss to which a dat a access (write) is made, and the access is permi tted.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 89 of 1658 REJ09B0261-0100 5. In TLB co mpatible mode , execute th e LDTLB instru ction and write th e contents o f PTEH and PTEL to the TLB. In TLB extended mode, execu te the LDTLB instruction and write the con tents of PTEH, PTEL, PTEA to the UTLB.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 90 of 1658 REJ09B0261-0100 7.7 Memory-Mapped TLB Configuration To enable the ITLB and UTL B to be mana ged by s oftware, their contents are allowed to be read from and written to by a program in the P1/P2 area with a MOV instru ction in privileged mode.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 91 of 1658 REJ09B0261-0100 7.7.1 ITLB Address Array The ITLB address array is allocated to a ddresses H'F200 0000 to H'F2FF FFFF in t he P4 area.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 92 of 1658 REJ09B0261-0100 7.7.2 ITLB Data Array (TLB Compatible Mode) The ITLB data array is allocated to addresses H'F3 00 0000 to H' F37F FFFF in the P4 area.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 93 of 1658 REJ09B0261-0100 7.7.3 ITLB Data Array (TLB E xtended Mode) In TLB exten ded mode t he names of t he data arrays have be en changed from ITLB data array t o ITLB data array 1, ITLB data array 2 is added, and the EPR and ESZ bits a re accessible.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 94 of 1658 REJ09B0261-0100 (2) ITLB Data Array 2 The ITLB data arra y is allocated to addresses H' F380 0000 to H'F3 FF FFFF in th e P4 area.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 95 of 1658 REJ09B0261-0100 7.7.4 UTLB Address Array The UTLB address arra y is allocated to addresses H'F600 0000 to H'F60F FFFF in the P4 area.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 96 of 1658 REJ09B0261-0100 Address field Data field VPN: V: E: D: * : Virtual pa g e number Validity bit Entry Dirty bit Don't care A.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 97 of 1658 REJ09B0261-0100 Address field Data field PPN: V: E: SZ: D: * : Physical pa g e number Validity bit Entry Pa g e size bits Dirty.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 98 of 1658 REJ09B0261-0100 (2) UTLB Data Array 2 The UTLB data arra y is allocated to ad dresses H' F780 0000 to H'F78F F FFF in the P4 area.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 99 of 1658 REJ09B0261-0100 7.8 32-Bit Address Extended Mode Setting the SE bit in PASCR to 1 c hanges mode from 29 -bit address m ode which handles t he 29- bit physical address space to 32-b it address extended mode whic h handles the 32-bit physical address space.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 00 of 1658 REJ09B0261-0100 7.8.2 Transiti on to 32-Bit Address Extended Mode This LSI enters 29-bit address mo de after a power-on reset. Transition is made to 32-bit address extended mode by setting the SE bit in PASCR to 1.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 01 of 1658 REJ09B0261-0100 Legend: • VPN: Virtual page number For 16-Mbyte page: Upper 8 bit s of virtual add ress For 64-Mbyte page: Up.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 02 of 1658 REJ09B0261-0100 • WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-throug h mode • UB: Buffered write b it Specifies whether a buffered write is performed.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 03 of 1658 REJ09B0261-0100 7.8.5 Mem ory-Mapped PMB Configurati on To enable the PMB to be manage d by software, its cont ents are allowe d to be read from and written to by a P1 or P2 area program with a MOV instruction in privileged mode.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 04 of 1658 REJ09B0261-0100 Address field Data field VPN: V: E: Physical pa g e number Validity bit Entry : Reserved bits (write value should be 0 and read value is undefined ) 31 0 V 8 8 7 VPN 31 19 20 0 11110 000 11 01 0 0 E 23 24 12 11 00000 00000 00 0 0 Figure 7.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 05 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 30 to 8 ⎯ All 0 R Reserve d For details on reading from or writing to these bits, see description in General Precautions on Hand ling of Product.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 06 of 1658 REJ09B0261-0100 (5) CCR.CB The CB bit in CCR is invalid. Whether a cacheab le write for the P1 area is performed in copy- back mode or write-though mode is determined by the WT bit in the PMB.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 07 of 1658 REJ09B0261-0100 7.9 32-Bit Boot Function The address m ode of this LS I after a p ower-on reset o r manual reset ca n be switche d between 2 9- bit address m ode and 32 -bit address extended m ode by s pecifying e xternal pins.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 08 of 1658 REJ09B0261-0100 C. If the MT bit in IRMCR is set to 0 (initia l value) before accessin g the memory-mapped PMB, no specific sequence is require d . However, c orrect operati on with met hod C may no lon ger be guara nteed in future S uperH- family products.
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 09 of 1658 REJ09B0261-0100 7.10 Usage Notes 7.10.1 Note on Using LDTLB Instruction When using an LDTLB instruction instead of soft ware to a value t o the MMUCR. URC, execute 1 or 2 below .
7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 10 of 1658 REJ09B0261-0100 Notes: 1. An exception handling routine is an entir e set of instructions that are executed from the address (VBR + offset) upon occurrence of an exception to the RTE for retu rning to the original pr ogram or t o the RTE del ay slot.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 11 of 1658 REJ09B0261-0100 Section 8 Caches This LSI has an on-chi p 32-Kbyte i nstruction cache (IC) fo r instructions a nd an on-chip 32-Kbyte operand cache (OC) for data. 8.1 Features The features of the cache are given in t able 8.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 12 of 1658 REJ09B0261-0100 This LSI has an IC way prediction scheme to reduce power con sumption. In addition, memory- mapped associative writing , which is detectable as an e xception, can be enabled by using the non- support detection exception regist er (EXPMASK) .
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 13 of 1658 REJ09B0261-0100 31 54 2 LW0 32 bits LW1 32 bits LW2 32 bits LW3 32 bits LW4 32 bits LW5 32 bits LW6 32 bits LW7 32 bits MMU [12:5] 255 19 bits 1 bit .
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 14 of 1658 REJ09B0261-0100 • Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU In a 4-way set-associative method, up to 4 items of data can be registered i n the cache at each entry address.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 15 of 1658 REJ09B0261-0100 8.2 Register Descriptions The following registers are related to cach e. Table 8.3 Register Configuration Register Name Abbreviation .
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 16 of 1658 REJ09B0261-0100 8.2.1 Cac he Control Regis ter (CCR) CCR controls the cache ope rating mode, the cach e write mode, a nd invalidation of all cache entries. CCR modifications must only be mad e by a progra m in the non-cacheable P2 area or IL memory.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 17 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 10, 9 ⎯ All 0 R Reserve d For details on reading from or writing to these bits, see description in General Precautions on Hand ling of Product.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 18 of 1658 REJ09B0261-0100 8.2.2 Queue Address Contro l Register 0 (QACR0) QACR0 specifies the area onto whi ch store q ueue 0 (SQ 0) is mappe d when the MMU is disabled.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 19 of 1658 REJ09B0261-0100 8.2.3 Queue Address Contro l Register 1 (QACR1) QACR1 specifies the area onto whi ch store q ueue 1 (SQ 1) is mappe d when the MMU is disabled.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 20 of 1658 REJ09B0261-0100 8.2.4 On-Chip Memory Control R egister (RAMCR) RAMCR controls the nu mber of ways in the IC and OC a nd prediction of t he IC way. RAMCR modi fications must only be ma de by a progra m in the no n-cacheable P2 a rea.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 21 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 RP 0 R/W On-Chip Mem ory Protection Enable Bit For details, see section 9.4, On-Chip Memory Protective Functions. 7 IC2W 0 R/W IC Two-Way Mode bit 0: IC is a four-way operation 1: IC is a two-way operation For details, see section 8.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 22 of 1658 REJ09B0261-0100 8.3 Operand Cache Operation 8.3.1 Read Operati on When the Oper and Cache (OC) is enable d (OCE = 1 in C CR) and data is read fr om a cacheable area, the cache operates a s follows: 1.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 23 of 1658 REJ09B0261-0100 write-back buffer is then wr itten back to external memory. 8.3.2 Prefetc h Operation When the Oper and Cache (OC) is enabled (OCE = 1 in CCR) and data i s prefetched from a cacheable area, the cache operates as follows: 1.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 24 of 1658 REJ09B0261-0100 8.3.3 Write Operation When the Oper and Cache (OC) is enable d (OCE = 1 i n CCR) and dat a is writ ten to a cacheabl e area, the cache operates a s follows: 1. The tag, V bit, U bit, and LRU bits on each way are read fr om the cache li ne indexed by virtual address bits [12:5].
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 25 of 1658 REJ09B0261-0100 6. Cache miss (copy- back, with write-back) The tag and data field of t he cache line on the wa y which is selected to replace are saved in the write-back buffer.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 26 of 1658 REJ09B0261-0100 8.3.6 OC Tw o-Way Mode When the OC2W bit in RAMCR is set to 1, OC two-wa y mode which only uses way 0 and way 1 in the OC is e ntered. Thus, power co nsumption can be red uced. In this mode, only way 0 and wa y 1 are used even if a memory-mapped OC access is made.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 27 of 1658 REJ09B0261-0100 8.4 Instruction Cache Operation 8.4.1 Read Operati on When the IC is enabled (ICE = 1 in CCR) and in struction fetches are performed from a cach eable area, the instruction cache operates as follows: 1.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 28 of 1658 REJ09B0261-0100 3. Cache hit The LRU bits is updated to indicate the way is the latest one. 4. Cache miss Data is read into the cache line on a way whi ch selected using the LRU bits to replace from the physical address space correspondin g to the virtual a ddress.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 29 of 1658 REJ09B0261-0100 8.5 Cache Operation Instruction 8.5.1 Coherenc y between Cache and External Memory (1) Cache Operation Instruction Coherency bet ween cache and external memory should be assured by software.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 30 of 1658 REJ09B0261-0100 • FLUSH transaction When the operand cache is enabled, the FLUSH transaction checks t he operand cache and if the hit line is dirty, then th e data is written back to the external memory.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 31 of 1658 REJ09B0261-0100 the dirty bit to 0. This o peration is onl y execut able in privileged mode , and an address error exception occurs in user mode .
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 32 of 1658 REJ09B0261-0100 8.6 Memory-Mapped Cache Configuration The IC and OC can be managed by softwa re. The content s of IC data array can be read from or written to by a program in the P2 area by means of a MOV instru ction in privileged mode.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 33 of 1658 REJ09B0261-0100 In the data field, the tag is indicated by bits [ 31:10], an d the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [ 31:29] are not used in the case of a writ e in whic h association is not performed.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 34 of 1658 REJ09B0261-0100 8.6.2 IC Data Array The IC data array is allocated to addresses H'F1 00 0000 to H'F1FF FFFF i n the P4 area. A data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 35 of 1658 REJ09B0261-0100 32-bit data field specification. Th e wa y and entry to be accessed are specified in the address field, and the write tag , U bit, and V bit are specified in the data field.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 36 of 1658 REJ09B0261-0100 Address field 3 1 2 3 543210 1 1 1 1 0 1 0 0 Entry A Data field 31 10 9 1 0 V Ta g 24 13 12 14 15 2 U V U A : Validity bit : Dirty bit : Association bit : Reserved bits (write value should be 0 and read value is undefined ) : Don't care Way 0 00 0 ******** * * Figure 8.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 37 of 1658 REJ09B0261-0100 Address field 3 1 2 3 543210 11110101 E n t r y Data field 31 0 Lon g word data 24 13 12 14 15 L * : Lon g word specification bits : Don't care Way 0 L0 ******** * Figure 8.8 Memory-Mappe d OC Data Array (Cache siz e = 32 Kbytes) 8.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 38 of 1658 REJ09B0261-0100 8.7 Store Queues This LSI supports two 32-byte stor e queues (SQs) to perform high- speed writes to external memory. 8.7.1 SQ Confi g uration There are tw o 32-byte st ore queues, SQ0 and S Q1, as shown in figure 8.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 39 of 1658 REJ09B0261-0100 8.7.3 Transfer to E xternal Memory Transfer from the SQs to external memory can be perf ormed with a prefet ch instruction (PREF). Issuing a PRE F instruction for addresses H'E000 0000 to H'E 3FF FFFC in the P4 area starts a transfer from the SQ s to external memory.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 40 of 1658 REJ09B0261-0100 Physical address bits [4:0] are always fixed at 0 since burst t ransfer starts at a 32-byte boundar y.
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 41 of 1658 REJ09B0261-0100 8.8 Notes on Using 32-Bit Address Extended Mode In 32-bit ad dress extende d mode, the items descri bed in this section are extended as follows. 1. Th e tag bits [28:10] (19 bits) in th e IC and OC are extended to bits [31:10] (22 b its).
8. Caches Rev.1.00 Jan. 10, 2008 Page 2 42 of 1658 REJ09B0261-0100.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 43 of 1658 REJ09B0261-0100 Section 9 On-Chip Memor y This LSI includes three type s of memory modu les for storage of instructions and d ata: OL memory, IL memory, and U memory. The OL memory is suitable for data sto rage while the IL memory is suit able for instruc tion stora ge.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 44 of 1658 REJ09B0261-0100 (2) IL Memory • Capacity The IL memory in this LSI is 8 Kbytes. • Page The IL memory is divided into two pages (pages 0 a nd 1). • Memory map The IL memory is allocated to t he addresses sho wn in table 9.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 45 of 1658 REJ09B0261-0100 The CPU can access the P4 area in th e virtual address space ( when SR.MD = 1) or on-chi p memory area (when SR.MD = 0 an d RAMCR.RMD = 1). Access operatio ns involving these addresses are alwa ys non-cacheable.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 46 of 1658 REJ09B0261-0100 9.2 Register Descriptions The following registers are related to th e on-chip memory.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 47 of 1658 REJ09B0261-0100 9.2.1 On-Chip Memory Control R egister (RAMCR) RAMCR contr ols the protect ive functions i n the on-chi p memory. When updatin g RAMCR, please follow li mitation descri bed at section 8.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 48 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 OC2W 0 R/W OC Two-Way Mode For further details, refer to section 8.3.6, OC Two-Way Mode. 5 ICWP D 0 R/W IC Way Prediction Disable For further details, refer to section 8.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 49 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 to 0 L0SSZ Undefine d R/W OL memory Page 0 Block Transfer Source A ddress Select When MMUCR.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 50 of 1658 REJ09B0261-0100 9.2.3 OL memory Transfer Source Address Register 1 (LSA1) When MMUCR.AT = 0 or RAMCR.RP = 0, the LS A1 specifies the tran sfer source physical address for bl ock transfer to page 1A or 1B i n the OL memory.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 51 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 to 0 L1SSZ Undefined R/W OL memory Pa ge 1 Block Transfer Source Address Select When MMUCR.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 52 of 1658 REJ09B0261-0100 9.2.4 OL mem ory Transfer Dest ination Addre ss Register 0 (LDA0) When MMUCR.AT = 0 or RAMCR.RP = 0, LDA0 specifi es the transfer destination physical address for bl ock transfer to pa ge 0A or 0B of the OL memory.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 53 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 to 0 L0DSZ Undefined R/W OL memory Pa ge 0 Block Transfer Destinati on Address Select When MMUCR.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 54 of 1658 REJ09B0261-0100 9.2.5 OL mem ory Transfer Dest ination Addre ss Register 1 (LDA1) When MMUCR.AT = 0 or RAMCR.RP = 0, LDA1 specifi es the transfer destination physical address for bl ock transfer to page 1A or 1B i n the OL memory.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 55 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 to 0 L1DSZ Undefi ned R/W OL memory Pa ge 1 Block Transfer Destinati on Address Select When MMUCR.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 56 of 1658 REJ09B0261-0100 9.3 Operation 9.3.1 Instr uction Fetch Access from the CPU (1) OL Memory Instruction fetch access from the CPU is perfor med via the cache/RAM inte rnal bus. This access takes more than one cycle.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 57 of 1658 REJ09B0261-0100 (3) U Memory Operand access from the CPU and read access from the FPU are performed via the read buffer.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 58 of 1658 REJ09B0261-0100 (1) When MMU is Enabled (MMUCR.AT = 1) and RAMCR.RP = 1 An address of the OL memory area is specifi ed to the UTLB VPN field,.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 59 of 1658 REJ09B0261-0100 When the PREF instruction is issu ed to the OL me mory area, the physical address bits [28:10] a re generated in accordance with the LSA0 or LSA1 specificat ion. The physical address bits [9:5] a re generated fro m the virtual address.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 60 of 1658 REJ09B0261-0100 9.4 On-Chip Memory Protective Functions This LSI im plements t he following protective f unctions t o the on-c hip memory by .
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 61 of 1658 REJ09B0261-0100 9.5 Usage Notes 9.5.1 Page Conflict In the event o f simultane ous access to t he same page from different buses, page c onflict occurs. Although each access is completed co rrectly, this kind of conflict tends to lower OL memory accessibility.
9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 62 of 1658 REJ09B0261-0100 (2) IL Memory In order to allocate instructions in the IL memory , write an instruction to the IL me mory, execute the following seq uence, then bran ch to the rewritten instructio n.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 63 of 1658 REJ09B0261-0100 Section 10 Interrupt Controller (INTC) The interrupt controller (INTC) determines the prio rity of interrupt so urces and controls the flow of interrupt requests to the CPU (SH-4A).
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 64 of 1658 REJ09B0261-0100 Figure 10.1 show s a block diagra m of the INTC. Input control Priority determination for e xter nal interrupts.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 65 of 1658 REJ09B0261-0100 The details of the input control circu it of figure 10.1 are shown in figure 10.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 66 of 1658 REJ09B0261-0100 10.1.1 Interrupt Method The basic flo w of exceptio n handlin g for inte rrupts is as follows.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 67 of 1658 REJ09B0261-0100 10.1.2 Interrupt Sources Table 10.1 shows an examp le of the interrupt ty pes. The INTC supports both ex ternal interrupts and on-chip peripheral module interrupts.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 68 of 1658 REJ09B0261-0100 Source Number of Sources (Max.) Priority INTEVT Remarks H'320 IRL[3:0] pin = HLLH (H'9) H'C20 IR.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 69 of 1658 REJ09B0261-0100 Source Number of Sources (Max.) Priority INTEVT Remarks DMAC(0) 7 H'680 DMINT3 * H'6A0 DMINT4 * On-ch.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 70 of 1658 REJ09B0261-0100 Source Number of Sources (Max.) Priority INTEVT Remarks SIOF 1 H'CE0 SIOFI MMCIF 4 H'D00 FSTAT Values.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 71 of 1658 REJ09B0261-0100 BRI0, BRI1, BRI2, BRI3, BRI4, BRI5: SCIF channels 0 to 5 break interrupt TXI0, TXI1, TXI2, TXI3, TXI4, TXI5: SC.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 72 of 1658 REJ09B0261-0100 10.2 Input/Output Pins Table 10.2 sho ws the pin co nfiguration.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 73 of 1658 REJ09B0261-0100 10.3 Register Descriptions Table 10.3 shows the INTC register configur ation. Table 10.4 shows the register states in each operating mode. Table 10.3 INTC Register C onfigurati on Name Abbreviatio n R/W P4 Addres s Area 7 Address Access Size Sync.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 74 of 1658 REJ09B0261-0100 Name Abbreviatio n R/W P4 Addres s Area 7 Address Access Size Sync.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 75 of 1658 REJ09B0261-0100 Table 10.4 Register States in Eac h Operating Mode Name Abbreviation Power-on Reset by PRESET Pin/WDT/H-UDI Man.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 76 of 1658 REJ09B0261-0100 Name Abbreviation Power-on Reset by PRESET Pin/WDT/H-UDI Manual Reset by WDT/Multiple Exception Sleep by SLEEP .
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 77 of 1658 REJ09B0261-0100 10.3.1 External Interrupt Re quest Registers (1) Interrupt Control Register 0 (ICR0) ICR0 is a 32-bit readable .
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 78 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 25 NMIB 0 R/W NMI Block Mode Selects whether an NMI interrupt is held until the BL bit in SR is cleared to 0 or detected immediate ly when the BL bit in SR of the CPU is set to 1.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 79 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 21 LVLMODE 0 R/W Level-sense IRQ/ IRL with holding function Selects whether or not to use the holding func tion for level-sense IRQ and IRL interrupts.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 80 of 1658 REJ09B0261-0100 (2) Interrupt Control Register 1 (ICR1) ICR1 is a 32-bit readable/writ able register that specifies the individual input signal detection modes for the respective external interrupt inpu t pins IRQ/ IRL7 to IRQ/ IR L0 .
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 81 of 1658 REJ09B0261-0100 IRQ and IRL Interrupt Requests). 2. When the IRQnS setting is changed from edge sens e (IRQnS is 00 or 01) to level sense (IRQnS is 10 or 11), the IRQ interr upt source that has been edge sensed is cleared.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 82 of 1658 REJ09B0261-0100 (3) Interrupt Priority Register (INTPRI) INTPRI is a 32-bit readable/writable reg ister used to set the priori ties of IRQ[ 7:0] (as leve ls from 15 to 0).
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 83 of 1658 REJ09B0261-0100 (4) Interrupt Source Re gister (INTREQ) INTREQ is a 32-bit readable and cond itionally writable register that indicates which of the IRQ [n] (n = 0 to 7) interrupts is currently asserting a request for the INTC.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 84 of 1658 REJ09B0261-0100 (5) Interrupt Mask Register 0 (INTMSK0) INTMSK0 is a 32-bit readable and co nditionally writable register that sets masking for each of the interrupt requests IRQn (n = 0 to 7).
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 85 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 26 IM05 1 R/W Sets masking of individual pin interrupt source on IRQ5. 25 IM06 1 R/W Sets masking of individual pin interrupt source on IRQ6.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 86 of 1658 REJ09B0261-0100 (6) Interrupt Mask Register 1 (INTMSK1) INTMSK1 is a 32-bit readable and co nditionally writable register that sets masking for IRL interrupt requests. To clear the mask setting for the interrupt, write 1 to th e corresponding bit in INTMSKCLR 1.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 87 of 1658 REJ09B0261-0100 (7) Interrupt Mask Register 2 (INTMSK2) INTMSK2 is a 32-bit readable and co nditionally writable register that sets masking for IRL interrupt requests for input lev el pattern on the IRL pins.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 88 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 26 IM010 0 R/W Masks the interr upt source of IRL3 to IRL0 = LHLH (H'5). 25 IM009 0 R/W Masks the interr upt source of IRL3 to IRL0 = LHHL (H'6).
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 89 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 15 IM115 0 R/W Masks the interr upt source of IRL7 to IRL4 = LLLL (H'0). 14 IM114 0 R/W Masks the interr upt source of IRL7 to IRL4 = LLLH (H'1).
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 90 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 2 IM102 0 R/W Masks the interrupt source of IRL7 to IRL4 = HHLH (H'D). 1 IM101 0 R/W Masks the interrupt source of IRL7 to IRL4 = HHHL (H'E).
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 91 of 1658 REJ09B0261-0100 (8) Interrupt Mask Clear Re gister 0 (INTMSKCLR0) INTMSKCLR0 is a 32-bit write-only register that clears the mask settings fo r each of the interrupt requests IRQn (n = 0 to 7 ).
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 92 of 1658 REJ09B0261-0100 (9) Interrupt Mask Clear Re gister 1 (INTMSKCLR1) INTMSKCLR1 is a 32-bit write-only register th at clears the mask settings for the IRL interrupt requests. Unde fined values are read from t his register.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 93 of 1658 REJ09B0261-0100 (10) Interrupt Mask Clear Re gister 2 (INTMSKCLR2) INTMSKCLR2 is a 32-bit write-only register th at clears the mask settings for the IRL interrupt requests for each input level pattern on the IRL pins.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 94 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 23 IC007 0 R/W Clears masking of the interrupt source of IRL3 to IRL0 = HLLL (H'8). 22 IC006 0 R/W Clears masking of the interrupt source of IRL3 to IRL0 = HLLH (H'9).
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 95 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 11 IC111 0 R/W Clears masking of the interrupt source of IRL7 to IRL4 = LHLL (H'4). 10 IC110 0 R/W Clears masking of the interrupt source of IRL7 to IRL4 = LHLH (H'5).
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 96 of 1658 REJ09B0261-0100 (11) NMI Flag Control Re gister (NMIFC R) NMIFCR is a 32-bit readable and co nditionally writa ble reg ister that has an NMI flag (N MIFL bit). The NMIFL bit is automatically set to 1 when an NMI interrupt is detected by the INTC.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 97 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 16 NMIFL 0 R/(W) NMI Flag (NMI Interrupt Request Detection) Indicates whether an NMI interrupt req uest signal has been detected.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 98 of 1658 REJ09B0261-0100 10.3.2 User Mode Interrupt Disable Function (1) User Interrupt Mask Le vel Se tting Register (USERIMASK) USERIMASK is a 32-bit readable and c onditionally writable register that sets the acceptable interrupt level.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 99 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 31 to 24 (Code for writing) H'00 R/W Code for writing (H'A5) These bits are always read as 0.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 00 of 1658 REJ09B0261-0100 3. Branch to the device driver. 4. In the device driver operat ing in user mode, set the UIM ASK bits to mask the B-type interrupts. 5. Process more urgent i nterrupts i n the device driver.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 01 of 1658 REJ09B0261-0100 Table 10.5 Interrupt Request Sou rces and INT2PRI0 to INT2PRI9 Bits Register 28 to 24 20 to 16 12 to 8 4 to 0 I.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 02 of 1658 REJ09B0261-0100 (2) Interrupt Source Register (Not affect ed by Mask Setting) (INT2A0) INT2A0 is a 32-bit read-o nly register t hat indicat es the interrupt sources of on-chip peri pheral modules.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 03 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 21 Undefined R HSPI HSPI interrupt source indication 20 Undef.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 04 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 5 Undefined R SCIF channel 3 SCIF channel 3 interrupt source .
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 05 of 1658 REJ09B0261-0100 Table 10.7 Reflection time for INT2A0 an d INT2A1 when Interrupt Source Bit in Peripheral Module Is Set/Cleared.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 06 of 1658 REJ09B0261-0100 Module Relation between Setting/Clear ing Interrupt Source of Module and Indication by IN T2A0 and INT2A1 DMAC Interrupt sources DMAE0, DMAE1 When the DMAE0 or DMAE1 interrupt source bit (i.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 07 of 1658 REJ09B0261-0100 (3) Interrupt Source Register (Affecte d by Mask States) (INT2A1) INT2A1 is a 32-bit read-o nly register t hat indicat es the interrupt sources of on-chip peri pheral modules.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 08 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 20 0 R SIOF SIOF interrupt source indication 19 0 R PCIC (5) .
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 09 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 3 0 R SCIF channel 1 SCIF channel 1 interrupt source indicati.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 10 of 1658 REJ09B0261-0100 (4) Interrupt Mask Regi ster (INT2MSKR) INT2MSKR is a 32-bit read able/writable register th at can mask interrupts for sources indicated in the interrupt source reg ister.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 11 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 18 1 R/W PCIC (4) Masks the PCIINTD interrupt 17 1 R/W PCIC (.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 12 of 1658 REJ09B0261-0100 (5) Interrupt Mask Clear Register (INT2MSKCR) INT2MSKCR is a 32-bit write-only reg ister that clears the masking set in the interrupt mask register. When the corresponding bit in this register is set to 1, the interrupt source masking is cleared.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 13 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 18 0 R/W PCIC (4) Clears the PCIINTD interrupt masking 17 0 R.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 14 of 1658 REJ09B0261-0100 10.3.4 Individual On-Chip Modul e Interrupt Source Re gist ers (INT2B0 to INT2B 7) INT2B0 to INT2B7 are registe.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 15 of 1658 REJ09B0261-0100 (2) INT2B1: Detailed Interrupt Sources for the SCIF Module Bit Name Detailed Source Description SCIF 31 to 24 ⎯ Reserved These bits are read as 0 and cannot be modified.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 16 of 1658 REJ09B0261-0100 Module Bit Name Detailed Source Description SCIF 11 TXI2 SCIF channel 2 transmit FIFO data empty interrupt 10 B.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 17 of 1658 REJ09B0261-0100 (3) INT2B2: Detailed Interrupt Sources for the DMAC Module Bit Name Detailed Source Description DMAC 31 to 14 ⎯ Reserved These bits are read as 0 and cannot be modified.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 18 of 1658 REJ09B0261-0100 (4) INT2B3: Detailed Interrupt Sources for the PCIC Module Bit Name Detailed Source Description PCIC 31 to 10 ⎯ Reserved These bits are read as 0 and cannot be modified.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 19 of 1658 REJ09B0261-0100 (5) INT2B4: Detailed Interrupt Sources for the MMCIF Module Bit Name Detailed Source Description MMCIF 31 to 4 ⎯ Reserved These bits are read as 0 and cannot be modified.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 20 of 1658 REJ09B0261-0100 (7) INT2B6: Detailed Interrupt Sources for the GPIO Module Bit Name Detailed Source Description GPIO 31 to 26 ⎯ Reserved These bits are read as 0 and cannot be modified.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 21 of 1658 REJ09B0261-0100 (8) INT2B7: Detailed Interrupt Sources for the GDTA Module Bit Name Detailed Source Description GDTA 31 to 3 ⎯ Reserved These bits are read as 0 and cannot be modified.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 22 of 1658 REJ09B0261-0100 10.3.5 GPIO Interrupt Set Re gister (INT2GPIC) INT2GPIC enables inte rrupt r equests in put from the pins 0 to 5 of port E, pi ns 1 to 4 of port H, pins 6 and 7 of port L , as GPIO interrupt s.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 23 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Function Description 18 PORTH3E 0 R/W Enables interrupt request from pin 3 of port H. 17 PORTH2E 0 R/W Enables interrupt request from pin 2 of port H.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 24 of 1658 REJ09B0261-0100 10.4 Interrupt Sources There are four types of interrup t sources, NMI, IRQ, IRL, and on -chip mo dule inter rupts. Each interrupt has a priority level (16 to 0).
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 25 of 1658 REJ09B0261-0100 (2) Dependence o n ICR0.LVL MODE Setting For the IRQ i nterrupt at l evel detect ion, ther e are the followin g features a ccording to the setting of ICR0.LVLMODE.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 26 of 1658 REJ09B0261-0100 Priority encoder Interrupt requests SH7785 IRQ/ I R L3 to IRQ/ I R L 0 IRQ/ I R L 7 to IRQ/ I R L4 I R L 7 to I R L4 I R L3 to I R L 0 Interrupt requests Priority encoder Figure 10.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 27 of 1658 REJ09B0261-0100 The priority of IRL interrupts should be retained from when an i n terr upt is accepted to when interrupt handling starts. The l evel can be ch anged to a hi gher level .
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 28 of 1658 REJ09B0261-0100 An on-chi p peripheral module interrupt source fl ag or an int errupt enable fl ag should be update d when the BL bit in SR i s set to 1 or when th e correspondi ng interrupt is not ge nerated b y the setting of interrupt masking occurs.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 29 of 1658 REJ09B0261-0100 An interrupt request is masked if priority level H'01 is set. INTC distin g uishes between priority levels H'1A and H'1B, althou g h both become the same level after truncatin g the least si g nificant bit for the CPU.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 30 of 1658 REJ09B0261-0100 Table 10.13 Interrupt Except ion Handling and Priority Interrupt Source INTEVT Code Interrupt Priority Mask/Cle.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 31 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clear Register & Bit Interrupt Source Register Detail .
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 32 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clear Register & Bit Interrupt Source Register Detail .
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 33 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clear Register & Bit Interrupt Source Register Detail .
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 34 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clear Register & Bit Interrupt Source Register Detail .
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 35 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clear Register & Bit Interrupt Source Register Detail .
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 36 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clear Register & Bit Interrupt Source Register Detail .
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 37 of 1658 REJ09B0261-0100 10.5 Operation 10.5.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 10.4 shows a fl owchart of the operations. 1. Interrupt request sources send i nterrupt req uest signals t o the INTC.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 38 of 1658 REJ09B0261-0100 Pro g ram execution state Interrupt g enerated? ICR0.MAI = 1? SR.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 39 of 1658 REJ09B0261-0100 10.5.2 Multiple Interrupts To handle multiple i nterrupts, the procedure for the inte rrupt handl ing routi ne should be as follows.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 40 of 1658 REJ09B0261-0100 10.6 Interrupt Response Time Table 10.14 s hows response t ime.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 41 of 1658 REJ09B0261-0100 Table 10.15 s hows response t ime. The response tim e is from the interrupt exception handling to the start of fetching th e first instruction in exception h andling routine.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 42 of 1658 REJ09B0261-0100 Table 10.16 s hows response t ime. The response tim e is the time until when the interrupt request signal from the INTC to the CPU is n egated.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 43 of 1658 REJ09B0261-0100 10.7 Usage Notes 10.7.1 Example of Handing Routine of IRL Interrupts and Level Detection IRQ Interrupts when ICR0.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 44 of 1658 REJ09B0261-0100 10.7.2 Notes on Setti ng IRQ/ IR L[7 :0] Pin F unction When the IRQ/ IRL[7:0] pin f unctions are switched, the INTC may ret ain an incorrect ly detected interrupt re quest.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 45 of 1658 REJ09B0261-0100 10.7.3 Clearing IR Q and IRL Interru pt Requests To clear the interrupt request retained in the INTC, follow th e procedure bel ow. (1) Clearing Inter rupt Request Indepe ndent from ICR0.
10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 46 of 1658 REJ09B0261-0100.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 47 of 1658 REJ09B0261-0100 Section 11 Local Bus State Controller (LBSC) The local bus state controller (LBSC) di vides the external memory sp ace and outputs control signals according to t he specification of each memor y and bus interface .
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 48 of 1658 REJ09B0261-0100 • MPX interface ⎯ Address/data multiplex ing Connectable area: 0 to 6 Settable bus widt h: 64 and 32 .
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 49 of 1658 REJ09B0261-0100 Figure 11.1 show s a block diagra m of the LBSC. Bus interface CSnWCR CSnBCR BCR CSnPCR Memory controller.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 50 of 1658 REJ09B0261-0100 11.2 Input/Output Pins Table 11.1 sho ws the LBSC pi n configuratio n.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 51 of 1658 REJ09B0261-0100 Pin Name Function I/O Description WE0 / REG Data Enable 0 O Write strobe signal for D7 to D0 in SRAM inte.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 52 of 1658 REJ09B0261-0100 Pin Name Function I/O Description BACK Bus Request Acknowledge O Bus request acknowl edge signal Multiplexed with Port M0 (GPIO input/output).
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 53 of 1658 REJ09B0261-0100 Pin Name Function I/O Description MODE11, MODE12 Bus Mode Switching I Signals for switching buses: lo cal.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 54 of 1658 REJ09B0261-0100 11.3 Overview of Areas 11.3.1 Space Divisions The LSI has a 32-bit virtual addres s space as the architecture. The vi rtual address space is divided into five areas according t o the upper address valu e.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 55 of 1658 REJ09B0261-0100 Table 11.2 LBSC Extern al Memory Space Map Area External addresses Size Connectable Memory Specifiable Bu.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 56 of 1658 REJ09B0261-0100 Area External addresses Size Connectable Memory Specifiable Bus Width (bits) Access Size * 7 SRAM 8, 16, .
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 57 of 1658 REJ09B0261-0100 11.3.2 Memory Bus Width The memory b us width of the LBSC ca n be set independen tly for each a rea. In area 0, a bus width of 8, 16, 32, or 64 bits is selec ted according to th e external pin settings at a powe r-on reset by the PRESET pin.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 58 of 1658 REJ09B0261-0100 11.3.3 PCMCIA Support This LSI supports the PCMCIA interface specificati ons for areas 5 and 6 in the external memory space. The IC memory card interfac e and I/O card inte rface specified in JEIDA sp ecifications version 4.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 59 of 1658 REJ09B0261-0100 Table 11.4 PCMCIA Support Interface IC Memory Card Interface I/O Card Interface Pin Signal Name I/O Funct.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 60 of 1658 REJ09B0261-0100 IC Memory Card Interface I/O Card Interface Pin Signal Name I/O Function Signal Name I/O Function Corresp.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 61 of 1658 REJ09B0261-0100 IC Memory Card Interface I/O Card Interface Pin Signal Name I/O Function Signal Name I/O Function Corresp.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 62 of 1658 REJ09B0261-0100 11.4 Register Descriptions Table 11.5 shows registers for the LBSC. These registers contro l the interface with each memory, wait state, etc. Table 11.5 Register Configuration (1) Register Name Abbrev.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 63 of 1658 REJ09B0261-0100 Table 11.5 Register Configuration (2) Register Name Abbrev.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 64 of 1658 REJ09B0261-0100 11.4.1 Memory Address Map Select Register (MMSELR) MMSELR is a 32-bit register that selects memory address maps for areas 2 to 5. This register should be accessed at t h e address H'FC 40 0020 in longword.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 65 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 AREASEL 000 R/W DDR2-S DRAM/PCI Memory Space Select 000.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 66 of 1658 REJ09B0261-0100 Example: ----------------------------------------------------------------------- MOV.L #H'FC400020, R0 ; MOV.L #MMSELR_DATA, R1 ; MMSELR_DATA=Writing value of MMSELR SYNCO ; (upper word=H'A5A5) MOV.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 67 of 1658 REJ09B0261-0100 11.4.2 Bus Control Re gister (BCR) BCR is a 32-bit readable/writable register that sp ecifies the function, bus cycle state, etc for each area.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 68 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 26 DPUP 0 R/W Data Pin Pu ll-Up Resistor Control Specifies the pull-up resistor state of the data pins (D63 to D0).
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 69 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19, 18 ⎯ All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. 17 BREQEN 0 R/W BREQ Enable Specifies whether an external request can be accepted or not.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 70 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 to 0 ASYNC[6:0] All 0 R/W Asynchronous Input These bits enable asynchronous inp uts of the corresponding pins.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 71 of 1658 REJ09B0261-0100 11.4.3 CSn Bus Control Reg ister (CSnBCR) CSnBCR are 32-bit readable/writable registers that specify the bus width for area n (n = 0 to 6), idle mode between cycles, burst ROM setting and memory typ es.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 72 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 30 to 28 IWW 111 R/W Idle Cycles between Write-Read/Wr ite-Write These bits specify the number of idle cycles to be inserted after the access of the memory connected to the space.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 73 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 23 ⎯ 0 R Reserved This bit is always read as 0.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 74 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 ⎯ 0 R Reserved This bit is always read as 0.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 75 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 9, 8 SZ 11 R/W * Bus Width In CS0BCR, the external pins (MODE5 and MODE6) to specify the bus size are sampled at a power- on reset.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 76 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 to 4 BW 111 R/W Burst Pitch When the burst ROM interfac e is used, these bits specify the number of wait cycles to be insert ed after the second data access in a burst transfer.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 77 of 1658 REJ09B0261-0100 11.4.4 CSn Wait Control Register (CSnWCR ) CSnWCR (n = 0 to 6) are 32-bit readable/writable re gisters th.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 78 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 27 ⎯ 0 R Reserved This bit is always read as 0.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 79 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19 ⎯ 0 R Reserved This bit is always read as 0.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 80 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 ⎯ 0 R Reserved This bit is always read as 0.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 81 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 to 0 IW[3:0] 1111 R/W Insert Wait Cycle These bits specify the num ber of wait cycles to be inserted.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 82 of 1658 REJ09B0261-0100 11.4.5 CSn PCMCIA Co ntrol Register ( CSnPCR) CSnPCR is a 32-bit readab le/writable register that specifi.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 83 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 27 ⎯ 0 R Reserved This bit is always read as 0.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 84 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19 to 16 PCIW 0000 R/W PCMCIA Insert Wait Cycle B These bits specify the num ber of wait cycles to be inserted. The bit settings are selected when the access area of PCMCIA interface is the second half.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 85 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 14 to 12 TEDA 000 R/W OE / WE Assert Delay A These bits set the delay time from address output to OE / WE assertion when the first half area is accessed with the connected PCMCIA interface.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 86 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 to 4 TEHA 000 R/W OE / WE Negation-Address Delay A These bits set the delay time from OE / WE negation to address hold when the first half area is acces sed with the connected PCMCIA interface.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 87 of 1658 REJ09B0261-0100 11.5 Operation 11.5.1 Endian/Access Size and Data Alignme nt This LSI supports both big and little end ian modes.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 88 of 1658 REJ09B0261-0100 Table 11.6 64-Bit Extern al Device/Big Endi an Access and Data Alignment (1) Operation Data Bus Access Size Address No.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 89 of 1658 REJ09B0261-0100 Table 11.7 64-Bit Extern al Device/Big Endi an Access and Data Alignment (2) Operation Strobe Signal Access Size Address No.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 90 of 1658 REJ09B0261-0100 Table 11.8 32-Bit Extern al Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 91 of 1658 REJ09B0261-0100 Table 11.9 16-Bit Extern al Device/Big-E ndian Access and Data Alignment Operation Data B us Strobe Signals Access Size Address No.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 92 of 1658 REJ09B0261-0100 Table 11.10 8-Bit External Device/Big-E ndian Access and Data Ali gnment Operation Data Bus Strobe Si gnals Access Size Address No.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 93 of 1658 REJ09B0261-0100 Table 11.11 64-Bit Exter nal Device/ Littl e Endian Access and Data Alignment (1) Operation Data Bus Access Size Address No.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 94 of 1658 REJ09B0261-0100 Table 11.12 64-Bit Exter nal Device/ Littl e Endian Access and Data Alignment (2) Operation Strobe Signal Access Size Address No.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 95 of 1658 REJ09B0261-0100 Table 11.13 32-Bit Exter nal Device/ Li ttle-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 96 of 1658 REJ09B0261-0100 Table 11.14 16-Bit Exter nal Device/ Li ttle-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 97 of 1658 REJ09B0261-0100 Table 11.15 8-Bit External Device/Little-E ndian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 98 of 1658 REJ09B0261-0100 11.5.2 Areas (1) Area 0 Area 0 is an area where bits 28 to 26 in the local bu s address are 000. The interface that can be set for this a r ea is the SRAM, burst ROM or MPX interface.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 99 of 1658 REJ09B0261-0100 For the nu mber of bu s cycles, 0 to 25 wait cy cles to be inserted can be selected by C S1WCR. When the burst ROM interface is used, th e number of a burst pitch is selectable in the range from 0 to 7 with the BW bits in CS1BCR.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 00 of 1658 REJ09B0261-0100 (4) Area 3 Area 3 is an area where bits 28 to 26 in the local bu s address are 011. The interface that can be set for this area is the SRAM, MPX, or burst ROM interface.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 01 of 1658 REJ09B0261-0100 For the nu mber of bu s cycles, 0 to 25 wait cy cles inserted can be selected by CS4WCR. When the burst ROM interface is used, th e number of a burst pitch is selectable in the range from 0 to 7 with the BW bits in CS4BCR.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 02 of 1658 REJ09B0261-0100 CS5PCR. In a ddition, t he number of wait cyc les can be specified in the range from 0 to 50 cycles by the PCWA/ B bit.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 03 of 1658 REJ09B0261-0100 11.5.3 SRAM interface (1) Basic Timing The strobe signals for the SR AM interface in th is LSI are output primar ily based on the SRAM connection. Figure 11.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 04 of 1658 REJ09B0261-0100 T1 CLKOUT A25 to A0 CS n R/ W RD D31 to D0 (In readin g ) W En D31 to D0 (In writin g ) BS T2 RDY DACKn In this example, DACKn is hi g h-active.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 05 of 1658 REJ09B0261-0100 Figures 11. 6 to 11.8 sh ow examples of connec tions to SR AM with 3 2-, 16- and 8-bit data width, respectively.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 06 of 1658 REJ09B0261-0100 A16 A0 CS O E I/O7 I/O0 W E A17 A1 CS n RD D15 D8 W E1 D7 D0 W E 0 SH7785 128K × 8 bits SRAM A16 A0 CS O.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 07 of 1658 REJ09B0261-0100 A16 A0 CS n RD D7 D0 W E 0 SH7785 128K × 8 bits SRAM A16 A0 CS O E I/O7 I/O0 W E •••• •••• •••• •••• •••• •••• •••• •••• Figure 11.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 08 of 1658 REJ09B0261-0100 T1 CLKOUT A25 to A0 CS n R/ W RD D31 to D0 (In readin g ) WE n D31 to D0 (In writin g ) BS Tw T2 RDY DACKn In this example, DACKn is active-hi g h. (The circle indicates the samplin g timin g .
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 09 of 1658 REJ09B0261-0100 When software wait insertion is specified by CSnWCR, the extern al wait input signal, RDY , is also sampled. The RDY signal sampling ti ming is shown in figu re 11.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 10 of 1658 REJ09B0261-0100 (3) Read-Strobe/ Write-Strobe Timing When the SRAM interface is used, the strobe sign al negati on timing i n reading ca n be specified with the RDSPL bit in CSnBCR.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 11 of 1658 REJ09B0261-0100 TAS1 CLKOUT A25-A0 CS n R/ W RD D31-D0 T1 TS1 Tw Tw Tw T2 Tw TH1 TH2 TAH1 * 1 * 2 TS1: CS n assertion - R.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 12 of 1658 REJ09B0261-0100 11.5.4 Burst ROM Interface When the TYPE bit in CSnBCR is set to 010 , a bur st ROM can be connected to areas 0 to 6. The burst ROM interface provides hi gh-spee d access to ROM that ha s a burst access function.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 13 of 1658 REJ09B0261-0100 T1 TB1 TB2 TB1 TB2 TB1 TB2 T2 CLKOUT A25 to A5 A4 to A0 CS n R/ W RD D31 to D0 (In readin g ) BS RDY Figure 11.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 14 of 1658 REJ09B0261-0100 T1 Twe TB2 TB1 Tw TB2 Tw Tw TB1 TB2 Tw T2 TB1 CLKOUT A25 to A5 A4 to A0 CS n R/ W RD D31 to D0 (In readin g ) BS RDY Figure 11.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 15 of 1658 REJ09B0261-0100 * 2 TAS1 TS1 TB2 TB1 TB2 TB1 TB1 T1 TB2 T2 TAH1 TH1 CLKOUT A25 to A5 A4 to A0 CS n R/ W RD D31 to D0 (In readin g ) BS RDY DACKn * 1 Notes: 1. In this example, DACKn is active-hi g h.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 16 of 1658 REJ09B0261-0100 11.5.5 PCMCIA Interface By setting the TYPE bits in CS 5BCR a nd CS6BCR, the bus interface for the external space areas 5 and 6 can be set to the IC memory card interface or I/O c ard interface, which is stipulated in JEIDA specification v ersion 4.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 17 of 1658 REJ09B0261-0100 complement mode. To access the De vice Control Re gister and Alternate Status Register, use a CPU byte access (do not use a DMA transfer), and to access the Data Register, use the CPU word access (do not use a DM A transfer).
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 18 of 1658 REJ09B0261-0100 Table 11.16 Relationship between Addre ss and CE when Usin g PC MCIA Interface Bus (Bits) Read/ Write Acc.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 19 of 1658 REJ09B0261-0100 Bus (Bits) Read/ Write Access (bits) * 1 Odd/ Even IOIS16 Access CE2 CE1 A0 D15 to D8 D7 to D0 Write 8 Ev.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 20 of 1658 REJ09B0261-0100 G A25 to A0 D15 to D0 PC card (memory I/O) CD1, CD2 C E1 G C E 2 O E W E / P G M ( I ORD ) ( I OWR ) ( I .
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 21 of 1658 REJ09B0261-0100 (1) Memory Card Interface Basic Timing Figure 11.17 shows the basic timing for the PCMCIA memory card interface, and figure 11.18 shows the wait timing for the PC MCIA memory card interface.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 22 of 1658 REJ09B0261-0100 CLKOUT Tpcm0 A25 to A0 R/ W C Exx R E G RD (In readin g ) D15 to D0 (In readin g ) D15 to D0 (In writin g ) W E1 (In writin g ) BS RDY Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w DACKn In this example, DACKn is active-hi g h.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 23 of 1658 REJ09B0261-0100 (2) I/O Card Inte rface Timing Figures 11.19 and 11.20 s how the timing for the PCMC IA I/O card interface. When a PCMCIA card is acce ssed as the I/O card in terface, dynamic sizing with the I/O bus width can be performed using t he IOIS16 pin.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 24 of 1658 REJ09B0261-0100 CLKOUT Tpci1 Tpci2 A25 to A0 R/ W C Exx I C I ORD (In readin g ) D15 to D0 (In readin g ) I C I OWR (In writin g ) D15 to D0 (In writin g ) BS R E G DACKn In this example, DACKn is active-hi g h.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 25 of 1658 REJ09B0261-0100 CLKOUT A25 to A0 R/ W C Exx I C I ORD (In readin g ) I C I OWR (In writin g ) D15 to D0 (In readin g ) D15 to D0 (In writin g ) BS RDY I O I S 1 6 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w R E G DACKn In this example, DACKn is active-hi g h.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 26 of 1658 REJ09B0261-0100 Tpci Tpci0 Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci2 Tpci1w Tpci2w CLKOUT A25 to A1 A0 R/ W I ORD ( W E 2 ) (I.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 27 of 1658 REJ09B0261-0100 11.5.6 MPX Interface When both the MODE 7 pin is set to 0 at a pow er-on reset by the PRESET pin, the MPX interface is selected for area 0. The MPX interface is sel ected for areas 1 to 6 by the MPX bit in CS1BCR, CS2BCR, and CS4BCR to CS6BCR.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 28 of 1658 REJ09B0261-0100 CLKOUT CS n BS RD R/ W D31 to D0 RDY SH7785 MPX device CLK CS BS F R AME W E I/O31 to I/O0 RDY Figure 11.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 29 of 1658 REJ09B0261-0100 Tm1 Tm1 CLKOUT RD / F R AME CS n R/ W D63 to D0 BS Tmd1w Tmd1 RDY D A C K A D0 A Figure 11.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 30 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D63 to D0 BS Tmd1w Tmd1w Tmd1 RDY DACKn D0 In this example, DACKn is active-hi g h. The circles indicate the samplin g timin g .
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 31 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D63 to D0 BS Tmd1 RDY DACKn D0 In this example, DACKn is active-hi g h. The circle indicates the samplin g timin g . Figure 11.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 32 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D63 to D0 BS Tmd1w Tmd1w Tmd1 RDY DACKn D0 In this example, DACKn is active-hi g h.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 33 of 1658 REJ09B0261-0100 Tm1 CLKOUT RD / F R AME CS n R/ W D63 to D0 BS Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 RDY DACKn D1 D2 D3 D0 A In this example, DACKn is active-hi g h.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 34 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D63 to D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 RDY DACKn D3 D1 D2 D0 In this example, DACKn is active-hi g h. Figure 11.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 35 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D63 to D0 BS Tmd1 Tmd2 Tmd3 Tmd4 RDY DACKn D0 D1 D2 D3 In this example, DACKn is active-hi g h.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 36 of 1658 REJ09B0261-0100 D2 D1 Tm1 CLKOUT A RD / F R AME CS n R/ W D63 to D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 RDY DACKn D0 D3 In this example, DACKn is active-hi g h. Figure 11.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 37 of 1658 REJ09B0261-0100 Tm1 CLKOUT RD / F R AME CS n R/ W D31 to D0 BS Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 RDY DACKn A In this example, DACKn is active-hi g h. D2 D3 D1 D4 D6 D7 D8 D5 Figure 11.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 38 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D31 to D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 RDY DACKn D7 D8 D2 D3 D1 In this example, DACKn is active-hi g h.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 39 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D31 to D0 BS Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 RDY DACKn D1 D2 D3 D4 D5 D6 D7 D8 In this example, DACKn is active-hi g h.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 40 of 1658 REJ09B0261-0100 D3 D2 Tm1 CLKOUT A RD / F R AME CS n R/ W D31 to D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 RDY DACKn D1 D7 D8 In this example, DACKn is active-hi g h.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 41 of 1658 REJ09B0261-0100 11.5.7 Byte Control SR AM Interface The byte control SRAM interface is a memory interface that outputs a byte -select strobe ( WEn ) in both read and write bus cycles.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 42 of 1658 REJ09B0261-0100 A18 to A3 CS n RD R/ W SH7785 64K × 16 bits SRAM D47 to D32 W E5 W E4 D31 to D16 W E3 W E 2 D15 to D0 W .
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 43 of 1658 REJ09B0261-0100 T1 T2 CLKOUT A25 to A0 CS n R/ W RD D31 to D0 (In readin g ) BS DACKn RDY W En In this example, DACKn is active-hi g h.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 44 of 1658 REJ09B0261-0100 TAS1 CLKOUT A25-A0 CS n R/ W W En (In readin g ) (In writin g ) D63-D0 T1 TS1 Tw Tw Tw T2 Tw TH1 TH2 TAH1.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 45 of 1658 REJ09B0261-0100 T1 Tw Twe T2 CLKOUT A25 to A0 CS n R/ W RD D31 to D0 (In readin g ) BS DACKn RDY W En In this example, DACKn is active-hi g h.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 46 of 1658 REJ09B0261-0100 11.5.8 Wait Cycles betw een Access Cycles When the ext ernal memory bus operatin g frequenc y is high, the turn-of f of the data b uffer performed o n completion of reading fr om a low-speed de vice may not be made in time.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 47 of 1658 REJ09B0261-0100 T1 CLKOUT CSm CS n A25 to A0 BS R/ W RD D31 to D0 T2 Twait T1 T2 Twait T1 T2 Reading area m space CSnBCR.IWRRD=001 CSnBCR.IWRWS=001 Reading area n space Writing area n space Figure 11.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 48 of 1658 REJ09B0261-0100 11.5.9 Bus Arbitrati o n This LSI is provided with a bus arb itration functio n that gi ves the bus to an external de vice when a request is issued from the devi ce.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 49 of 1658 REJ09B0261-0100 Asserted for 2 cycles or more Master-mode device access CLKOUT BR EQ B A C K A25 to A0 CS n R/ W RD W En .
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 50 of 1658 REJ09B0261-0100 11.5.10 Master Mode The processor in master mo de holds the bus itself until it receives a bus request.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 51 of 1658 REJ09B0261-0100 11.5.11 Slave Mode In slave mode, usually, the bus is released. Unless the bus control i s hold by performing bus arbitration, the external device cannot be accessed.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 52 of 1658 REJ09B0261-0100 11.5.14 Mode Pin Settings and Ge neral Input Output Port Settings about Data Bus Width Table 11.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 53 of 1658 REJ09B0261-0100 Table 11.19 Register Settings for Divided-Up DACKn Out put in DMA1 Transfer Usin g the SRAM/Burst ROM/Byt.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 54 of 1658 REJ09B0261-0100 Table 11.20 Register Settings for Divided-Up DACKn Output in DMA1 Transfer Using the PCMCIA Interface Not.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 55 of 1658 REJ09B0261-0100 Table 11.21 Register Settings for Divided-Up DACKn Output in DM A1 Transfer in Re ad Access Using the MPX.
11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 56 of 1658 REJ09B0261-0100 Table 11.22 Register Settings for Divided-Up DACKn Out put in DMA1 Transfer in Write Access Using the MPX.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 57 of 1658 REJ09B0261-0100 Section 12 DDR2-SDRAM Interface (DBSC2) The DDR2-SDRAM interface (DBS C2) c ontrols the DDR 2-SDRAM.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 58 of 1658 REJ09B0261-0100 ⎯ DDR2-SDR AM data bus width: 16 bits • One 256 Mbits (16 M × 16 bits) connected in parallel (total capac.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 59 of 1658 REJ09B0261-0100 Figure 12.1 show s a block diagra m of the DBSC2. BUS IF Request queue Control unit Re g isters DDRPAD DLL IO .
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 60 of 1658 REJ09B0261-0100 12.2 Input/Output Pins Table 12.1 sho ws the pin co nfiguration o f the DBSC2.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 61 of 1658 REJ09B0261-0100 The frequency of the SDRAM operation cl ocks MCK0, MCK0 , MCK1, and MCK1 is the same as the frequency of the DDR clock.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 62 of 1658 REJ09B0261-0100 Table 12.2 An Exa mple of DDR2-SDRAM Co nnection (When Four 2- Gb DDR2-SDRAM U nits (256 M × 8 Bits) Are Used.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 63 of 1658 REJ09B0261-0100 3. SDRAM pins should be connected as sho wn below. Memory #1 Pins SH7785 Pins DQS MDQS3 DQS MDQS3 DM MDM3 DQ7 MDQ31 DQ6 MDQ30 DQ5 MDQ29 DQ4 MDQ28 DQ3 MDQ27 DQ2 MDQ26 DQ1 MDQ25 DQ0 MDQ24 4.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 64 of 1658 REJ09B0261-0100 5. SDRAM pins should be conn ected as shown below. Memory #3 Pins SH7785 Pins DQS MDQS1 DQS MDQS1 DM MDM1 DQ7 MDQ15 DQ6 MDQ14 DQ5 MDQ13 DQ4 MDQ12 DQ3 MDQ11 DQ2 MDQ10 DQ1 MDQ9 DQ0 MDQ8 6.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 65 of 1658 REJ09B0261-0100 12.3 Data Alignment The DBSC2 ac cesses DDR2-SDR AM with a fixed burst length of 4 (figur e 12.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 66 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] Invalid 32-bit width: MDQS[3:0] 1.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 67 of 1658 REJ09B0261-0100 Table 12.3 Positions of Valid Data for Access with Burst Length of 4, when the External Data Bus Width I s Set.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 68 of 1658 REJ09B0261-0100 Table 12.4 Positions of Valid Data for Access with Burst Length of 4, when the External Data Bus Width I s Set.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 69 of 1658 REJ09B0261-0100 (2) Big Endian First Access Sec ond Access Third Access Fourth Access Byte access (address 8n + 0,1) Valid Inv.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 70 of 1658 REJ09B0261-0100 Table 12.5 Data Alignment for Access in Little Endia n when External Da ta Bus Width I s Set to 32 Bits Access.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 71 of 1658 REJ09B0261-0100 Access Size Address MDQ31 to MDQ24 MDQ23 to MDQ16 MDQ15 to MDQ8 MDQ7 to MDQ0 Quadword Address 0 (First access:.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 72 of 1658 REJ09B0261-0100 Access Size Address MDQ31 to MDQ24 MDQ23 to MDQ16 MDQ15 to MDQ8 MDQ7 to MDQ0 Word Address 0 Data 15 to 8 Data .
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 73 of 1658 REJ09B0261-0100 Table 12.7 Data Alignment for Access in Littl e Endian when External Data Bus Width Is Set to 16 Bits Access S.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 74 of 1658 REJ09B0261-0100 Access Size Address MDQ15 to MDQ8 MDQ7 to MDQ0 Longword Address 0 (First access: Address 2) Data 31 to 24 Data.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 75 of 1658 REJ09B0261-0100 Table 12.8 Data Alignment for Access in Big Endian when External Data Bus Width Is Set to 16 Bits Access Size .
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 76 of 1658 REJ09B0261-0100 Access Size Address MDQ15 to MDQ8 MDQ7 to MDQ0 Longword Address 0 (First access: Address 0) Data 31 to 24 Data.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 77 of 1658 REJ09B0261-0100 When the external bus width is set to 16 bits Address 16n + 0 Address 16n + 8 1st access 2nd access 16n + 0 16.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 78 of 1658 REJ09B0261-0100 When the external bus width is set to 32 bits Address 16n + 0 Address 16n + 8 1st access 16-byte read/write ac.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 79 of 1658 REJ09B0261-0100 12.4 Register Descriptions Table 12.9 sho ws the DBSC2 re gister configuration; Tabl e 12.10 sh ows register st ates in the different processing modes. The register bit width is 32 bits, and the longwor d size (32 bits) should be used for re gister access.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 80 of 1658 REJ09B0261-0100 Table 12.9 DBSC2 Register Confi guration Register Name Abbreviation R/W P4 Area Address Area 7 Address Access .
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 81 of 1658 REJ09B0261-0100 Table 12.10 Register Status i n each Processing Mode Power-On Reset Manual Reset Sleep/Deep Sleep Register Nam.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 82 of 1658 REJ09B0261-0100 12.4.1 DBSC2 Status Re gister (DBSTATE) The DBSC2 st atus register (DBSTATE) i s a read-onl y register. Writing is invalid. It is initialized only upon po wer-on reset.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 83 of 1658 REJ09B0261-0100 12.4.2 SDRAM Operati on Enable Regis ter (DBEN) The SDRAM operation ena ble register (DBEN) is a r eada b le/writable regi ster. It is initialized only upon power- on reset.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 84 of 1658 REJ09B0261-0100 12.4.3 SDRAM Com mand Control Register (DBCMDCNT ) The SDRAM c ommand cont rol regist er (DBCMDC NT) is a readable/writable register. It is initialized only upon power-on reset.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 85 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 CMD2 to CMD0 000 R/W SDRAM Command Issue Bit These bits are used to issue commands necessary to execute the DDR2-SDRAM initialization se quence and self-refresh transition/cancellation.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 86 of 1658 REJ09B0261-0100 12.4.4 SDRAM Configuration Setting Re gister (DBCONF) The SDRAM config uration set ting register (DB CONF ) is a rea dable/writable register. It is initialized only up on power-on reset.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 87 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 10 ⎯ All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. Operation when a value other than 0 is writte n is not guaranteed.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 88 of 1658 REJ09B0261-0100 12.4.5 SDRAM Timing Register 0 (DBTR0) The SDRAM timing register 0 (DBTR0) is a readable/w ritable register.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 89 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 23 to 20 ⎯ All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. Operation when a value other than 0 is writte n is not guaranteed.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 90 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 14 to 8 TRFC6 to TRFC0 000 0101 R/W tRFC (REF-ACT/REF period) Setting Bits These bits set the REF-ACT/REF minimum period constraint These bits should be set accordin g to the DDR2-SDRAM specifications.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 91 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 TRCD2 to TRCD0 001 R/W tRCD (ACT-READ/WRITE period) Setting Bits These bits set the ACT-READ/WRITE minimum period.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 92 of 1658 REJ09B0261-0100 12.4.6 SDRAM Timing Register 1 (DBTR1) The SDRAM timing register 1 (DBTR1) is a readable/writable register.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 93 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 11 ⎯ All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. Operation when a value other than 0 is writte n is not guaranteed.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 94 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 TWR2 to TWR0 001 R/W tWR (write recovery period) S etting Bits These bits set the write recovery minimum period constraint.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 95 of 1658 REJ09B0261-0100 12.4.7 SDRAM Timing Re gister 2 (DBTR2) The SDRAM timing register 2 (DBTR2) is a readable/w ritable register.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 96 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 20 to 16 TRC4 to TRC0 0 0100 R/W tRC (ACT-ACT/REF period) Setting Bits These bits set the constraint for the minimum time from ACT command to ACT command (in the same bank)/ REF command.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 97 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 to 8 RDWR3 to RDWR0 0011 R/W READ-WRITE Command Mi nimum Interval Setting Bits These bits set the READ-WRITE command minimum interval constraint.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 98 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 to 0 WRRD3 to WRRD0 0011 R/W WRITE-READ Command Mi nimum Interval Setting Bits These bits set the WRITE-READ command minimum interval constraint.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 99 of 1658 REJ09B0261-0100 12.4.8 SDRAM Refr esh Control Register 0 (DBRFCNT0) The SDRAM refresh control re gister 0 (DBRFCNT 0) is a readable/writabl e register. It is initialized only upon power-on reset.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 00 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 SRFEN 0 R/W Self-Refresh Mode Bit Performs transition to or cancellation of self-r efresh mode. By writing 1, a transiti on is made to self-refresh.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 01 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 12 to 0 TREFI12 to TREFI0 0 0010 0000 0000 R/W Averag e Refresh Interval Setting Bits These bits set the average interval for auto-refresh operation.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 02 of 1658 REJ09B0261-0100 12.4.10 SDRAM Refr esh Control Register 2 (DBRFCNT2) The SDRAM refresh control re gister 2 (DBRFCNT 2) is a readable/writabl e register. It is initialized only up on power-on reset.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 03 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 8 ⎯ All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. Operation when a value other than 0 is writte n is not guaranteed.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 04 of 1658 REJ09B0261-0100 12.4.11 SDRAM Refresh S t atus Register (DBRF STS) The SDRAM refres h status register (DBRFSTS) is a read able/writable register. It is initialized only upon po wer-on reset.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 05 of 1658 REJ09B0261-0100 12.4.12 DDRPAD Frequenc y Setti ng Register (DBFREQ) The DDRPAD frequen cy setting register (DBFREQ) is a readable/writable register. It is initialized only upon po wer-on reset.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 06 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 FREQ2 to FREQ0 000 R/W Frequency Setting Bits These bits set the operatin g frequency of the data bus in the DDR2-SDRAM.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 07 of 1658 REJ09B0261-0100 12.4.13 DDRPAD DIC, ODT, O CD Setting Re gister (DBDICODTOCD) The SDRAM refres h status register (DBRFSTS) is a read able/writable register. It is initialized only upon po wer-on reset.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 08 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 18 DIC_DQ 0 R/W Data Pin Impedanc e value This bit should be set to the same value as the value set for DIC of EMRS(1) in the DDR2-SDRAM.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 09 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 10 ODT_ EARLY 0 R/W ODT Assertion Period Settin g Sets the ODT assertion perio d. The number of cycles is the number of DDR clock cycles.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 10 of 1658 REJ09B0261-0100 12.4.14 SDRAM Mode Setting Regi ster (DBMRCNT) The SDRAM mode setting register (DBMRCNT) is a write-only register. If it is read, correct operation ca nnot be guarantee d.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 11 of 1658 REJ09B0261-0100 By writing to this register, th e DDR2-SDRAM ad dress and bank address pin s can be directly manipulated t o set the mode and exte nded mode registers.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 12 of 1658 REJ09B0261-0100 12.5 DBSC2 Operation 12.5.1 Supported SDRAM Commands Table 12.11 lists the SDRAM comm ands issued by the DBSC2. Th ese commands are issued to the DDR2-SDRAM in synchronously with MCK0, MCK0 , MCK1, and MCK 1 .
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 13 of 1658 REJ09B0261-0100 12.5.2 SDRAM Command Issue (1) Basic Access The DBSC2 st ores in a que ue the requests received via t he SuperHywa y bus.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 14 of 1658 REJ09B0261-0100 16-bit external bus Read (16 bytes) Read (1, 2, 4, 8, or 16 bytes) Read (32 bytes) Write (1, 2, 4, 8, or 16 by.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 15 of 1658 REJ09B0261-0100 command to be issued at time 2 from the following request que ue. From the search results it is seen that advance prec harge processing can be exec uted for the third read (8-byte ) request and the fourth read (16-byte) request.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 16 of 1658 REJ09B0261-0100 12.5.3 Initialization Sequence The following shows an examp le of the initialization sequence. For detailed information such as the power supply and timing parameter s, please refer to the datasheet for the DDR2-SDRAM being used.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 17 of 1658 REJ09B0261-0100 10. Writing to DBMRCNT issues the MRS command to the SDRAM and sets the variou s parameters. At this point, the op erating mode is set to normal mode, the DLL reset is set to reset, the burst length is set to 4, and the burs t type is set t o sequential.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 18 of 1658 REJ09B0261-0100 Because access is disabled in self-refresh mode, any attempt to access data in the DDR2-SDRAM will be ignored. The following procedure is used to mak e a transition to self-refresh mode.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 19 of 1658 REJ09B0261-0100 1. Check to make sure the DBSC2 is not being acce ssed. The time required for transition to self- refresh must not exceed t h e auto-refresh i nterv al requested by the SDRA M by interr upts or some other ca uses.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 20 of 1658 REJ09B0261-0100 12.5.5 Auto-Refresh Operation When the auto-refresh enab le bit (ARFEN) in the SD RAM refresh control register 0 (DBRFCNT0) is 1, the a u to-refresh com mand is issued periodically.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 21 of 1658 REJ09B0261-0100 LV1TH LV0TH 0 Time Refresh counter value Max. value (Avera g e refresh interval + LV1TH) Level 1 (Refreshin g .
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 22 of 1658 REJ09B0261-0100 Table 12.12 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Se.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 23 of 1658 REJ09B0261-0100 Table 12.13 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Se.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 24 of 1658 REJ09B0261-0100 Table 12.14 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Se.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 25 of 1658 REJ09B0261-0100 Table 12.15 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Se.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 26 of 1658 REJ09B0261-0100 Table 12.16 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Se.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 27 of 1658 REJ09B0261-0100 Table 12.17 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Se.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 28 of 1658 REJ09B0261-0100 Table 12.18 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Se.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 29 of 1658 REJ09B0261-0100 Table 12.19 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Se.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 30 of 1658 REJ09B0261-0100 12.5.7 Regarding SDRAM Access an d Timing Constraints In this section, waveforms at t he various pins du ri ng.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 31 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT bank A bank A Invalid Invalid.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 32 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11 ] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT bank A READ bank A Invalid I.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 33 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT bank A bank A Invalid Invalid.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 34 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT bank A bank A Invalid Invalid.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 35 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] Invalid MDQS[3:0] MDQ[31:0] MDM[3:0] Invalid Invalid Invalid Invalid PALL Invalid REF SDRAM command Hi g h level Figure 12.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 36 of 1658 REJ09B0261-0100 example is shown in section 12.5.11, Method for Securing Time Requir ed for Initialization, Self- Refresh Cancellation, etc.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 37 of 1658 REJ09B0261-0100 command, the constraint tRCD betwee n th e ACT comm and and READ co mmand, and the constraint tRAS between the ACT command a n d the PRE command a re involved. The DBSC2 waits to issue commands until each of the constraints is satisfied.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 38 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT bank A READ bank A Invalid In.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 39 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] bank A Invalid MDQS[3:0] MDQ[31:0.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 40 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT bank A READ bank A Invalid In.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 41 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] WRITE any bank Invalid MDQS[3:0] .
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 42 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] Invalid MDQS[3:0] MDQ[31:0] MDM[3.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 43 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT any bank tRFC Invalid Invalid.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 44 of 1658 REJ09B0261-0100 12.5.8 Important Inf ormation Regardin g Use of 8-Bank DDR2-S DRAM Products The DDR2-SD RAM specificat ions limit the number of ba nks in an 8-bank product w hich can be activated simultaneously.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 45 of 1658 REJ09B0261-0100 write MCK Command Data MCKE MODT Terminatin g resistor in SDRAM As shown in the above fi g ure, when CL is 4, the effective ODT control si g nal (MODT) to the SDRAM can be asserted at the same timin g as the issue of the WRITE command.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 46 of 1658 REJ09B0261-0100 write MCK Command Data MCKE MODT Terminatin g resistor in SDRAM read The above fi g ure shows an example when a product with CL = 5 is used. As the ODT control si g nal (MODT) is extended for one cycle, the product with CL = 5 or g reater is required.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 47 of 1658 REJ09B0261-0100 This LSI MCKE M BKPRS T IO cell Internal CKE DBSC2 External device SDRAM This LSI MCKE M BKPRS T IO cell Internal CKE DBSC2 Low level input Low level output Hi g h level input 1.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 48 of 1658 REJ09B0261-0100 MCKE to high level, upon power-on reset the data within the SDRAM is destroyed. Hence if the state signal is not set in advance to a state ot he r than power supp ly back up state, there is the danger that the destroyed data may be treated as the correct data.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 49 of 1658 REJ09B0261-0100 5. The SDRAM configuration se tting register ( DBCONF), S DRAM timing register 0 (DBTR0), SDRAM timing register 1 (DBTR1), and SDRAM timing register 2 (DBTR2) shou ld be set.
12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 50 of 1658 REJ09B0261-0100 12.5.13 Regarding MCKE Si gnal Operation The MCKE signal operation is explaine d using fi gure 12.24. Here, the ex planation assume s that MBKPRST is high-le vel input.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 51 of 1658 REJ09B0261-0100 Section 13 PCI Controller (PCIC) The PCI cont roller (PCIC) controls t he PCI bus and enables dat a transfers bet w een memory connected to an external bus and a PCI device conn ected to the P CI bus.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 52 of 1658 REJ09B0261-0100 • Cache snoop functions are sup ported when the PCIC is a ta rget (cache coherency can be supported by sacrific ing perfor mance).
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 53 of 1658 REJ09B0261-0100 Figure 13.1 sh ows a block diagra m of the PCIC. PCI bus PCIC module Internal bus (SHwybus) SHwy bus interface Data F.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 54 of 1658 REJ09B0261-0100 13.2 Input/Output Pins Table 13.1 sho ws the pin co nfiguration o f the PCIC.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 55 of 1658 REJ09B0261-0100 Signal Name PCI Standard Signal I/O Description LOCK / ODDF LOCK STRI PCI Lock Exclusive access (the target resource .
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 56 of 1658 REJ09B0261-0100 Signal Name PCI Standard Signal I/O Description MODE12 MODE11 — IN PCI Operating Mode Select 00: PCI host mode, or .
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 57 of 1658 REJ09B0261-0100 13.3 Register Descriptions Table 13.2 sho ws a list of PC IC registers. The addresses and offset s of PC I configuratio n registers are the values used when the PCIC is in little endian mode.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 58 of 1658 REJ09B0261-0100 Name Abbreviation SH * 1 R/W PCI * 2 R/W P4 address Area 7 address Sync Clock Access Size * 3 PCI interrupt line re g.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 59 of 1658 REJ09B0261-0100 Name Abbreviation SH * 1 R/W PCI * 2 R/W P4 address Area 7 address Sync Clock Access Size * 3 PCI power management in.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 60 of 1658 REJ09B0261-0100 Table 13.3 Register States in Eac h Processing Mode Name Abbreviation Power-On R eset Manual Reset Sleep Mode Control.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 61 of 1658 REJ09B0261-0100 Name Abbreviation Power-On R eset Manual Reset Sleep Mode PCI power consumption/dissipation data register PCIPCDD H&a.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 62 of 1658 REJ09B0261-0100 13.3.1 PCIC Enable Contr ol Register (PCIEC R) PCIECR is a register that specifies wh ethe r the PCIC is valid or invalid.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 63 of 1658 REJ09B0261-0100 13.3.2 Configuration Registers The configurat ion regist ers define t he programmi ng model and usage rules of t he configurat ion register space in a PCI compliant device.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 64 of 1658 REJ09B0261-0100 (3) PCI Comm and Register (PCICMD) PCICMD cont rols the basic functions of the PCIC t o generate and respond to PC I cycles. Whe n 0 is written to this register, t his register ig nores access c ommands from the external PCI device, other than configuration access.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 65 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 PER 0 SH: R/W PCI: R/W Parity Error Response Controls the response of the device when the PCIC detects a parity error or receives a parity error.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 66 of 1658 REJ09B0261-0100 (4) PCI Status Register (P CISTATUS) PCISTATUS is use d to record status in formation fo r events related to the PCI bus. The reserved bits are read-only bits that ar e read as 0.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 67 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 12 RTA 0 SH: R/WC PCI: R/WC Target Abort Receive Status This bit indicates that a transaction was completed by target abort when the PCIC is a master.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 68 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 6 ⎯ 0 SH: R/W PCI: R Reserved These bits are always read as 0. The write value should always be 0. 5 66C 0 SH: R/W PCI: R 66MHz-Operation Capable Status Indicates whether the PCIC can op erate at 66MHz.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 69 of 1658 REJ09B0261-0100 (6) PCI Progra m Int erface R egister ( PCIPIF) This field is the programming interface for the cla ss code of the IDE cont roller. For details of the code value, see appendix D in PCI Local Bus Specification Revision 2.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 70 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 0 OMP 0 SH: R/W PCI: R PCI Operating Mode (Primary) If this bit is written during register initialization (PCICR.CFINT = 0) in the PCIC, the value of this bit is updated.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 71 of 1658 REJ09B0261-0100 (8) PCI Base Clas s Code Register (PCIBCC) This field defi nes the base class code. For deta il s of the class code, see appendix D in PCI L ocal Bus Specification R evision 2.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 72 of 1658 REJ09B0261-0100 (10) PCI Latency Timer Register (P CILTM) 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 LTM R/W R/W R/W R/W R/W R/W R/W R/W Bit: In.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 73 of 1658 REJ09B0261-0100 (12) PCI BIST Register (PCIBI ST) R R R R R R R R PCI R/W: 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 — — — — — — .
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 74 of 1658 REJ09B0261-0100 (13) PCI I/O Base Address Register (PCIIBAR) This register is the I/O space base a ddress register of the PCI configuratio n register space header that is defined in PCI local bus specification.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 75 of 1658 REJ09B0261-0100 (14) PCI Memory Base Addre ss Register 0 (PCIMBAR0) This register is the memory base address register of the PCI configuratio n register space header that is define d in PCI local bus specificat ion.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 76 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 19 to 4 MBA2 H'0000 SH: R PCI: R Memory Space 0 Base Address (lower 16 bit s) These bits are fixed to H'0000 by hardware.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 77 of 1658 REJ09B0261-0100 (15) PCI Memory Base Addre ss Register 1 (PCIMBAR1) This register is the memory base address register of the PCI configuratio n register space header that is define d in PCI local bus specificat ion.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 78 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 19 to 4 MBA2 H'0000 SH: R PCI: R Memory Space 1 Base Address (lower 16 bit s) These bits are fixed to H'0000 by hardware.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 79 of 1658 REJ09B0261-0100 (16) PCI Subsyst em Vender ID Regist er (PCISVID ) See the description of each register in PCI Local Bus Specification Revision 2.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 80 of 1658 REJ09B0261-0100 (18) PCI Capability Pointer Register (PCICP) This register i s the extensi on function p ointer regist er of the PC I configurat ion register t hat is defined in t he PCI Power M anagement Spec ification.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 81 of 1658 REJ09B0261-0100 (20) PCI Interrupt Pin Register (PCIINTPIN) 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 INTPIN R/W R/W R/W R/W R/W R/W R/W R/W Bi.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 82 of 1658 REJ09B0261-0100 (22) Maximum Latency Register (P CIMAXLAT ) This register is not programmable.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 83 of 1658 REJ09B0261-0100 (24) PCI Next Item Pointer Re gister (PCINIP) PCINIP indicates the locatio n of the next item i n the list o f extension f unction.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 84 of 1658 REJ09B0261-0100 (25) PCI Power Management Register (P CIPMC) PCIPMC is a 16-bit regi ster that pr ovides info rmation on t he functions related t o power management.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 85 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 8 to 6 ⎯ All 0 SH: R PCI: R Reserved These bits are always read as 0. The write value should always be 0. 5 DSI 0 SH: R PCI: R DSI The write value should always be 0.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 86 of 1658 REJ09B0261-0100 (26) PCI Power Management Control/ Status Register (PCIPMCSR) This register m anages power management events (PME ) of the PC I function. For details, see section 3, PCI Power Management Interf ace in PCI Bus Power Management Interface Specification Re vision 1.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 87 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1, 0 PS 00 SH: R/W PCI: R/W Power State These bits specify the power state. If an unsupported state is spec ified, a state transition is not made.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 88 of 1658 REJ09B0261-0100 (27) PCIPMCSR Bridge Support Extensi on Register (PCIPMCSRBSE) This register supports the function s specific to the PCI bridge and is required for all PCI-to -PCI bridges.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 89 of 1658 REJ09B0261-0100 (28) PCI Power Consumption/ Radiation Register (PCIPCDD) The data regist er is an 8-bit optional register (rea d-only from the PCI bus) that notifies operation data such as po wer consumpt ion dependi ng on the state and heat dissi pation.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 90 of 1658 REJ09B0261-0100 13.3.3 PCI Local Registers (1) PCI Control Register (PCICR) PCICR is a 3 2-bit regi ster which c ontrols the operatio n of the PC IC in this LSI. Writing to this register is valid only when the valu e of bits 31 to 24 are H'A5.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 91 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 10 FTO 0 SH: R/W PCI: R PCI TRDY /Control Enable Specifies the function that negates TRDY within 5 cycles before disconnection in a target access.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 92 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 IOCS 0 SH: R/W PCI: R INTA Output Controls the INTA output by software. This bit is valid only when the PCIC operates in normal mode.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 93 of 1658 REJ09B0261-0100 (2) PCI Local Space Register 0 (PCILSR0) See section 13.4.4 (1), Accessi ng Memory Space in This LSI.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 94 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 19 to 1 ⎯ All 0 SH: R PCI: R Reserved These bits are always read as 0.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 95 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 28 to 20 LSR 0 0000 0000 SH: R/W PCI: R Capacity of Local Address Spaces 1 (9 bits) These bits specify the size of the local address space 1 (address space for this LSI internal bus) in byte units.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 96 of 1658 REJ09B0261-0100 (4) PCI Local Address Register 0 (PCILAR0) See section 13.4.3 (2), Accessing PCI Memory Space.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 97 of 1658 REJ09B0261-0100 (5) PCI Local Address Register 1 (PCILAR1) See section 13.4.3 (2), Accessing PCI Memory Space.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 98 of 1658 REJ09B0261-0100 (6) PCI Interrupt Re gister (PCIIR) PCIIR records interrupt sourc es. When an interrupt occurs, the corresponding bit is set to 1. When multiple inte rrupts occ u r, onl y the first source is re gistered.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 99 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 9 TMTOI 0 SH: R/WC PCI: R Target Memory Read Retry Timeout Interrupt Indicates that the master did not perform retry processing within 2 15 clocks in PCICLK when the PCIC is a target.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 00 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 SDI 0 SH: R/WC PCI: R SERR Detection Interrupt Indicates that the assertion of SERR was det ected when the PCIC is a host.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 01 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 TADIM 0 SH: R/WC PCI: R Target Abort Detection Interrupt for Master Indicates that transaction was terminated by a target abort when the PCIC is a master.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 02 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 MRDPEI 0 SH: R/WC PCI: R Master Read Data Pa rity Error Interrupt Indicates that the PCIC detected a par ity error during data read from the target when the PCIC is a master.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 03 of 1658 REJ09B0261-0100 (7) PCI Interrup t Mask Register (PCIIMR) This register is the mask register for PCIIR.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 04 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 6 SDIM 0 SH: R/W PCI: R SERR Detection Interrupt Mask 0: SEDI disabled (m.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 05 of 1658 REJ09B0261-0100 (8) PCI Error Ad dress Informati on Register ( PCIAIR) This register records PCI address info rmation when an error is detected. The value of this register is undefined until an interrupt is detected.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 06 of 1658 REJ09B0261-0100 (9) PCI Error Command Infor mation Register (P CICIR) This register records the PC I command in formation when an error is d etected. The value of this register is undefined until an interrupt is detected.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 07 of 1658 REJ09B0261-0100 (10) PCI Arbiter Interrupt Register (PCIAINT) In host mode, this re gister records interrupt s our ces. When multiple interrup ts occur, only the first source is regi stered.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 08 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 MBTOI 0 SH: R/WC PCI: R Master Bus Time-Out Interrupt An interrupt is detected when IRDY is not asserted within 8 clock cycles during da ta transfer.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 09 of 1658 REJ09B0261-0100 (11) PCI Arbi ter Interrupt Mask Register (P CIAINTM) This register is the mask register fo r PCIAINT.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 10 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 MAIM 0 SH: R/WC PCI: R Master-Abort Interrupt Mask 0: MAI disabled (mask.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 11 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 5 ⎯ All 0 SH: R PCI: R Reserved These bits are always read as 0.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 12 of 1658 REJ09B0261-0100 (13) PCI PIO Address Re gister (PCIPAR) Setting this register generates configu ration cycles on the PCI b us. For detai ls, see section 13 .4.5 (2), Config uration Space Acc ess.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 13 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 11 DN xxxxx SH: R/W PCI: ⎯ Device Number These bits specify a device number for the configuration access target. A device number is represented by a 5-bit value in the range from 0 to 31.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 14 of 1658 REJ09B0261-0100 (14) PCI Power Management Int errupt Register (PCIPINT) This register regist ers power manageme nt interrupt so urces.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 15 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 PMD0 0 SH: R/WC PCI: ⎯ PCI Power Management D0 Status Transition Interrupt Indicates that an interrupt to request a transition to the PCI bus power-down mode was gen erated.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 16 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 1 PMD1M 0 SH: R/W PCI: ⎯ PCI Power Management D1 Status Transition Inte.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 17 of 1658 REJ09B0261-0100 (17) PCI Memory Bank Mask Register 0 (PCIMBMR0) This register is the mask regist er for PCIMBR0 . This register sp ecifies the memory space size on the PCI bus for a memory read or write to the PCI memory space 0 by the CPU or DMAC.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 18 of 1658 REJ09B0261-0100 (18) PCI Memor y Bank Register 1 (PCIMBR1) This register specifies the upper 14 bits of t he memory space addr ess on the PC I bus for a memory read or write to the PCI memory space 1 by t he CPU or DM AC.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 19 of 1658 REJ09B0261-0100 (19) PCI Memory Bank Mask Register 1 (PCIMBMR1) This register is the mask regist er for PCIMBR1 . This register sp ecifies the memory space size on the PCI bus for a memory read or write to the PCI memory space 1 by the CPU or DMAC.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 20 of 1658 REJ09B0261-0100 (20) PCI Memor y Bank Register 2 (PCIMBR2) This register specifies the upper 14 bits of t he memory space addr ess on the PC I bus for a memory read or write to the PCI memory space 2 by t he CPU or DM AC.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 21 of 1658 REJ09B0261-0100 (21) PCI Memory Bank Mask Register 2 (PCIMBMR2) This register is the mask regist er for PCIMBR2 . This register sp ecifies the memory space size on the PCI bus for a memory read or write to the PCI memory space 2 by the CPU or DMAC.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 22 of 1658 REJ09B0261-0100 (22) PCI I/O Bank Re gister (PCIIOBR) This register specifies the upper 14 bits of t he I/O sp ace address on the PCI bu s for an I/O-read or I/O-write to the PCI I/O space by the CPU or DMAC.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 23 of 1658 REJ09B0261-0100 (23) PCI I/O Bank Mask Register (P CIIOBMR) This register is the mask register for PCIIOB R. This register specifies the I/O space size on the PCI bus for an I/O-read or I/O-write to the PCI I/O space by the CPU or DMAC.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 24 of 1658 REJ09B0261-0100 (24) PCI Cache Snoop Control Re gister 0 (PCICSCR 0) An external PCI device ca n access memory of this LSI via the PC IC. When an PCI device accesses a cacheable area, the PCIC can issue cac he snoop commands to th e on-c hip caches.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 25 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 1, 0 SNPMD All 0 SH: R/W PCI: — Snoop Mode for PCICSAR0 These bits specify whether PCICSAR0 is compared with the SuperHyway bus address req uested by an external device, or not.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 26 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 31 to 5 ⎯ All 0 SH: R PCI: — Reserved These bits are always read as 0.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 27 of 1658 REJ09B0261-0100 (26) PCI Cache Snoop Addre ss Register 0 (PCICSAR0) This register specifies the addres s to be compared with the PCI ad dress reque sted by an external PCI device to the PCIC.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 28 of 1658 REJ09B0261-0100 (27) PCI Cache Snoop Addre ss Register 1 (PCICSAR1) This register specifies the addres s to be compa red with the PCI ad dress reque sted by an external PCI device to the PC IC.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 29 of 1658 REJ09B0261-0100 (28) PCI PIO Data Register (PCI PDR) By reading or writing to this register, a config uration cycle is generated on the PCI bu s. For details, see section 13.4.5 (2 ), Configuration Space Access.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 30 of 1658 REJ09B0261-0100 13.4 Operation 13.4.1 Supported P CI Commands Table 13.4 Supported P CI Commands C/ BE [3:0] Commands PCI Master PCI .
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 31 of 1658 REJ09B0261-0100 13.4.2 PCIC Initialization After a power-on reset, the ENBL bit in PCIE CR and the CFINIT bit in PCICR are cleared.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 32 of 1658 REJ09B0261-0100 13.4.3 Master Access This section describes how software contro ls the PCI whe n the PCIC is a bus master. This section describes the c ases where the PCIC is used i n both host mode and normal mode.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 33 of 1658 REJ09B0261-0100 (2) Accessing PCI Memory Space Figure 13.2 s hows the mem ory map fr om the SuperH yway bus to the PCI bus.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 34 of 1658 REJ09B0261-0100 For PCI memo ry space 0, t he middle six bits ([ 23:18]) are controlled by P CIMBMR0.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 35 of 1658 REJ09B0261-0100 For PCI memory space 2 acce sses, the middl e eleven bits ([28:18]) are c ontrolled by PCIMBMR2.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 36 of 1658 REJ09B0261-0100 (3) Accessing PCI I/O Space Burst transfers are not supported in I/O transfers. A ccess wit hin the size of 4-byte. The PCI I/O address space is a llocated from H' FD20 0000 to H'FE3F FFFF (2 M bytes).
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 37 of 1658 REJ09B0261-0100 MSB 31 0 LSB SHwy data PCI bus data 1. Little endian A' B' C' D' A B C A' B' C' D' A B A B C PCI_Addr[2] = 1 PCI_Addr[2] = 0 31 0 SHwy data PCI bus data 2.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 38 of 1658 REJ09B0261-0100 MSB 31 0 LSB SHwy data PCI bus data 1. Little endian A' B' C' D' A B C A' B' C' D' A BC D D A BC D PCI_Addr[2] = 1 PCI_Addr[2] = 0 MSB 31 0 LSB SHwy data PCI bus data 2.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 39 of 1658 REJ09B0261-0100 31 0 A 31 0 A 31 0 A 31 0 A B B B B C C C C D D D D AB AB BA AB CD CD DC CD CD AB CD DC CD AB AB BA Size Byte Word lo.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 40 of 1658 REJ09B0261-0100 13.4.4 Target Access This section describes how the PCIC in this LSI is accessed by an external PCI local bus master when the PCIC is used in both the host mode and normal mo de.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 41 of 1658 REJ09B0261-0100 To access the address space in this LSI, use PCIMBAR0/1, PCILSR0/1, and PC ILAR0/1. PCI addresses can be allocated to by software. Th e PCIC has two types of registers for me mory mapping, Local Address Sp ace 0 (base 0) and Local Address Space 1 (base 1).
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 42 of 1658 REJ09B0261-0100 MBARE PCI address 31 28 20 0 29 19 PCIMBAR0/1 PCILSR0/1 PCILAR0/1 SHwy bus address Compare 0 31 20 0 29 0 31 28 20 0 29 19 19 28 31 20 29 19 28 31 20 29 19 28 Figure 13.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 43 of 1658 REJ09B0261-0100 (3) Accessing PCIC Registers Configuration Re gisters: Configuration registers should be read or written with (off set from configuration register space base address) by configuration accesses.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 44 of 1658 REJ09B0261-0100 (6) Endian This LSI supports both the big and little en dian formats. Since the PCI local bus is inherently little endian, the PC IC supports both b yte swappi ng and non-byte swap ping.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 45 of 1658 REJ09B0261-0100 31 MSB LSB 0 PCI bus data SHwy data 1. Little endian A' B' C' D' A B C A' B' C' D&.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 46 of 1658 REJ09B0261-0100 31 0 A 31 0 A 31 0 A 31 0 A B B B B C C C C D D D D AB AB BA AB CD CD DC CD CD AB CD DC CD AB AB BA Size Byte Wor d L.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 47 of 1658 REJ09B0261-0100 (7) Cache Coherency The PCIC su pports cache co herency fu nction. When the PCIC functions as a ta rget device, cache coherency is guaranteed on the PCI bus for accesses from a master device both i n host mode and normal mode.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 48 of 1658 REJ09B0261-0100 13.4.5 Host Mode (1) Operation in Host Mode The PCI interface of this LSI supp orts a subset of the PCI versio n 2.2 and can be connect ed to a device with a PCI bus in terface.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 49 of 1658 REJ09B0261-0100 31 30 24 16 23 15 11 10 87 2 1 0 Confi g uration address re g ister PCI bus address Reserved Bus No. Function No. Re g ister No. 0 0 0 0 Only one bit is set to 1. 31 11 1 0 8 7 2 1 0 Enable bit 0: Disabled 1: Enabled Device No.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 50 of 1658 REJ09B0261-0100 Subsequentl y, after the PCIC requi res the bus an d transfer data and the request is permitted, the priority chang e.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 51 of 1658 REJ09B0261-0100 The PCIC can retain err or information on t he PCI bus. When a n error occurs , the error address is stored in PCIAIR and the transf er type an d comma nd information are stored in PCICIR.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 52 of 1658 REJ09B0261-0100 D0 (Nomal state) D2 (Clock stopped) D1 (Bus idle) D3 (Power-down) Figure 13.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 53 of 1658 REJ09B0261-0100 13.4.8 PCI Local Bus Basic Inter face The PCI interface of this LSI supports subset s in the PCI bus ve rsion 2.2 and it can be co nnected to a device with a PCI bus i nterface.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 54 of 1658 REJ09B0261-0100 PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY D E VS EL T RDY IDSEL R E Q G NT Addr D0 AP DP0 Com BE0 L OCK Le g end: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 55 of 1658 REJ09B0261-0100 Addr D0 AP DP0 Co m BE0 D1 DPn-1 DPn BE1 BEn Dn PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY D E VS EL T RDY.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 56 of 1658 REJ09B0261-0100 Addr D0 AP DP0 Com BE0 D1 DPn-1 DP n BE1 BEn Dn PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY D E VS EL T RDY.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 57 of 1658 REJ09B0261-0100 (2) Target Read/Write Cycle Timing The PCIC returns retries to targ et memory read accesses from a n ex ternal master until 8 longword (32-bit) data are prepared in the PCIC internal FIFO.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 58 of 1658 REJ09B0261-0100 Addr D0 AP DP0 Co m BE0 Disconnect Confi g uration space access Lock PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME .
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 59 of 1658 REJ09B0261-0100 DP0 Addr D0 AP Co m BE0 Disconnect Confi g uration space access Lock PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME .
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 60 of 1658 REJ09B0261-0100 Addr D0 AP DP0 Com BE0 Disconnect Lock D1 DPn-1 DPn BE1 B En Dn PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 61 of 1658 REJ09B0261-0100 Addr D0 AP DP0 Com BE0 Disconnect Lock D1 DPn-1 DPn BE1 B En Dn PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 62 of 1658 REJ09B0261-0100 (3) Address/Data Stepping Timing By writing 1 to the SC bit in PCICMD, a wait (stepping ) of one clock can be inserted when the PCIC is dri ving the A D bus. As a result, the PCIC dri ves the AD bus with 2 cloc ks.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 63 of 1658 REJ09B0261-0100 D1 BE1 PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY D E VS EL T RDY Le g end: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Addr D0 AP DP0 Com BE0 Dn DPn-1 DPn BEn Figure 13.
13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 64 of 1658 REJ09B0261-0100.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 65 of 1658 REJ09B0261-0100 Section 14 Direct Memory Access Controller (DMAC) This LSI includes an on-c hip direct memory acce ss controller (DM A C).
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 66 of 1658 REJ09B0261-0100 Figure 14.1 sh ows a block diagra m of the DMAC. P er ipheral bus controller DMA transfer end si g .
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 67 of 1658 REJ09B0261-0100 14.2 Input/Output Pins The DMAC-related external pins are shown below. Table 14.1 shows the configuratio n of the pins th at are connected to external device.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 68 of 1658 REJ09B0261-0100 14.3 Register Descriptions Table 14.2 sho ws the register configuration.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 69 of 1658 REJ09B0261-0100 Channel Name Abbr ev. R/W P4 Address Area 7 Address Access Size * 3 Sync clock 0 DMA source address.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 70 of 1658 REJ09B0261-0100 Channel Name Abbr ev. R/W P4 Address Area 7 Address Access Size * 3 Sync clock 6 to 11 DMA operatio.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 71 of 1658 REJ09B0261-0100 Table 14.2 Register Config uration of the DMAC (2) Channel Name Abbrev.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 72 of 1658 REJ09B0261-0100 Channel Name Abbrev. Power-on Reset by PRESET Pin/WDT/ H-UDI Manual Reset by WDT/Mu ltiple Exceptio.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 73 of 1658 REJ09B0261-0100 Channel Name Abbrev. Power-on Reset by PRESET Pin/WDT/ H-UDI Manual Reset by WDT/Mu ltiple Exceptio.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 74 of 1658 REJ09B0261-0100 Channel Name Abbrev. Power-on Reset by PRESET Pin/WDT/ H-UDI Manual Reset by WDT/Mu ltiple Exceptio.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 75 of 1658 REJ09B0261-0100 14.3.1 DMA Source Address Registers 0 to 11 (SAR0 to SAR11) SAR are 32-bit readable/writable registers that specify the source addres s of a DMA transfer.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 76 of 1658 REJ09B0261-0100 14.3.2 DMA Source Address Registers B0 to B3, B6 to B9 (SARB0 to SARB3, SARB6 to SARB9) SARB are 32-bit readable/writable reg isters that sp ecify the source address of a DMA transfer that is set in SAR again i n repeat/reload mode.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 77 of 1658 REJ09B0261-0100 14.3.3 DMA Destina tion Address Regis ters 0 to 11 (DAR0 to DA R11) DAR are 32-bit readable/writable registers t hat sp ecify the destination address of a DMA transfer.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 78 of 1658 REJ09B0261-0100 14.3.4 DMA Desti nation Address Registers B0 t o B3, B6 to B9 (DARB0 to DARB 3, DARB6 to DARB9) DARB are 32-bit readable/writab l e registers that specify the destinati on address of a DMA transfer that is set in DAR agai n in repeat/reload m ode.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 79 of 1658 REJ09B0261-0100 14.3.5 DMA Trans fer Count Regi sters 0 to 11 (TCR0 t o TCR11) TCR are 32-bit readable/writable registers th at speci fy the DMA transfer coun t.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 80 of 1658 REJ09B0261-0100 14.3.6 DMA Transfe r Count Registers B0 to B 3, B6 to B9 (TCRB0 to TCRB 3, TCRB6 to TCRB9) TCRB are 32-bit readable/writable registers. Th e da ta written to TCR by the CPU is also written to TCRB.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 81 of 1658 REJ09B0261-0100 14.3.7 DMA Channe l Control Registers 0 to 11 (CHCR 0 to CHCR11) CHCR are 32-bit readable/writable reg ister s that con trol the DMA tr ansfer mod e.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 82 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 27 to 25 RPT[2:0] 000 R/W DMA Setting Update Specific ation These bits are valid in only CHCR0 to CH CR3, and CHCR6 to CHCR9.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 83 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 21 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 20 TS2 0 R/W DMA Transfer Size Specificati on Specifies the DMA transfer size with TS1 and TS0.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 84 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 19 HE 0 R/(W) * Half End Flag After HIE (bit 18) is set to 1 and the number of transfers is half of TCR (one bit shift to right) which is set before transfer, HE is 1.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 85 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 17 AM 0 R/W Acknowledge Mode Selects whether DACK is output in a data read cycle or in a data write cycle.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 86 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 15, 14 DM[1:0] 00 R/W Destinati on Address Mode 1, 0 Specify whether the DMA destination address is incremented or decremented.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 87 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 11 to 8 RS[3:0] 0000 R/W Resource Sele ct 3 to 0 Specify the transfer request source. To change the transfer request source, the DMA enable (DE) bit should be cleared to 0.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 88 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 2 IE 0 R/W Interrupt Enab le Specifies whether an interrupt request is generated to the CPU at the end of the final DMA transfer.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 89 of 1658 REJ09B0261-0100 14.3.8 DMA Operati on Register 0, 1 (D MAOR0 and DM AOR1) DMAOR are 16-bit readable/writable registers that specify the priority of channels in DMA transfer.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 90 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 11, 10 ⎯ All 0 R Reserved These bits are always read as 0.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 91 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 2 AE 0 R/(W) * Address Error Flag Indicates that an address error occurred during DMA transfer. This bit is set under following conditions.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 92 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 0 DME 0 R/W DMA Master Enable Enables or disables DMA transfers on all chann els (channels 0 to 5) correspondi ng to DMAOR0, and all channels (channels 6 to 11) correspond ing to DMAOR1.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 93 of 1658 REJ09B0261-0100 14.3.9 DMA Extende d Resource Selectors 0 to 5 (DMARS0 to DMARS5) DMARS are 16-bit readab le/writable regist ers.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 94 of 1658 REJ09B0261-0100 • DMARS4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 95 of 1658 REJ09B0261-0100 • DMARS1 Bit Bit Name Initial Value R/W Descriptions 15 14 13 12 11 10 C3MID5 C3MID4 C3MID3 C3MID2 C3MID1 C3MID0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Transfer request source mo dule ID5 to ID0 for DMA channel 3 (MID) See table 14.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 96 of 1658 REJ09B0261-0100 • DMARS2 Bit Bit Name Initial Value R/W Descriptions 15 14 13 12 11 10 C5MID5 C5MID4 C5MID3 C5MID2 C5MID1 C5MID0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Transfer request source mo dule ID5 to ID0 for DMA channel 5 (MID) See table 14.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 97 of 1658 REJ09B0261-0100 • DMARS3 Bit Bit Name Initial Value R/W Descriptions 15 14 13 12 11 10 C7MID5 C7MID4 C7MID3 C7MID2 C7MID1 C7MID0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Transfer request source mo dule ID5 to ID0 for DMA channel 7 (MID) See table 14.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 98 of 1658 REJ09B0261-0100 • DMARS4 Bit Bit Name Initial Value R/W Descriptions 15 14 13 12 11 10 C9MID5 C9MID4 C9MID3 C9MID2 C9MID1 C9MID0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Transfer request source mo dule ID5 to ID0 for DMA channel 9 (MID) See table 14.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 99 of 1658 REJ09B0261-0100 • DMARS5 Bit Bit Name Initial Value R/W Descriptions 15 14 13 12 11 10 C11MID5 C11MID4 C11MID3 C11MID2 C11MID1 C11MID0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Transfer request source mo dule ID5 to ID0 for DMA channel 11 (MID) See table 14.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 00 of 1658 REJ09B0261-0100 Table 14.3 List of Transfer Request Sources Peripheral Module Setting Value for One Channel (MID an.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 01 of 1658 REJ09B0261-0100 14.4 Operation When DMA transfe r is requested, t he DMAC starts transfer according to the determi n ed channel priority. When the transfer end conditio ns are satisfied, the DMAC ends transfer.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 02 of 1658 REJ09B0261-0100 Choose whether DREQ is detected by edg e or level with the DREQ level (DL) bit and DREQ select (DS) bit in CHCR0 to CHCR3 shown in tabl e 14.5. The source of th e transfer request does not have to be the tra nsfer source o r transfer desti nation.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 03 of 1658 REJ09B0261-0100 (3) On-Chip Peripheral Module Request Mode On-chip peri pheral module request m ode is a mode that perf orms transfer b y DMA trans fer request signal from an on-chi p peripheral module.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 04 of 1658 REJ09B0261-0100 Table 14.8 List of On-Chip Peripheral Module Request Modes CHCR DMARS RS[3:0] MID RID DMA Transfer .
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 05 of 1658 REJ09B0261-0100 CHCR DMARS RS[3:0] MID RID DMA Transfer Request Source DMA Transfer R equest Signal Source Destinat.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 06 of 1658 REJ09B0261-0100 14.4.2 Channel Priority When the DMAC recei ves transfer requests on tw o or more channels simu ltaneously, it transfers data according to a determined priority.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 07 of 1658 REJ09B0261-0100 CH1 > CH2 > CH3 > CH4 > CH5 > CH0 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 C.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 08 of 1658 REJ09B0261-0100 Figure 14. 3 shows ho w the priori ty changes when channel 0 and cha nnel 3 tra nsfers are request ed simultaneousl y and a channel 1 transfer i s re quested during the channel 0 transfer.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 09 of 1658 REJ09B0261-0100 14.4.3 DMA Transfe r Types Tables 14.9 an d 14.10 sh ow the trans fer directi ons that can be s upported by the DM AC. DMA transfer type su pports dual address mode.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 10 of 1658 REJ09B0261-0100 Table 14.10 DMA Transfer Directions for On-Chip Peripheral Module Request * 2 * 3 Transfer Destinat.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 11 of 1658 REJ09B0261-0100 (1) Dual Address Mode In dual address mode, both the transfer source and tr ansfer destination are accessed by address. The source and destination ca n be sp ecified externally or internally.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 12 of 1658 REJ09B0261-0100 Transfer source address Transfer destination address CLKOUT A25 to A0 C Sn RD WEn D31 to D0 DACKn (Active-low) Figure 14.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 13 of 1658 REJ09B0261-0100 (2) Bus Modes Bus mode s include cycle steal m ode and burst mode. Th e modes are ch osen by th e TB and LCKN bits in CHCR. (a) Cycle Steal Mode • Normal mode 1 (CHCR.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 14 of 1658 REJ09B0261-0100 • Intermitte nt mode 16 (DMAOR. CMS = 10, CHCR.LCKN = 0 o r 1, CHCR .TB = 0) • Intermitte nt mode 64 (DMAOR. CMS = 11, CHCR.LCKN = 0 o r 1, CHCR .
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 15 of 1658 REJ09B0261-0100 SuperHyway bus cycle Read Write Read Write Read Write DR E Q CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU Figure 14.9 DMA Transf er Ti ming Example in Burst Mode (DREQ Low Level Detection) (3) Bus Mode and Channel Pri ority Figure 14.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 16 of 1658 REJ09B0261-0100 DMA CH0 Cycle steal CH0 transfer source (a) CH0: Cycle steal mode CH1: Cycle steal mode Priority: C.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 17 of 1658 REJ09B0261-0100 14.4.4 DMA Transfe r Flow After intended transfer conditio ns are set to SAR, DAR, TCR, CHCR, DMAOR, and DMARS, the DMAC transfers data according to the following procedure.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 18 of 1658 REJ09B0261-0100 Notes: 1. In repeat mode, a transfer request is acceptted with TE =1 when HIE = 1 and HE = 0 (half end interrupt is enable and clear the HE to 0 after HE is set to 1).
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 19 of 1658 REJ09B0261-0100 14.4.5 Repeat Mode Trans f er A repeat mode transfer of th e DMAC enab les a DMA tr ansfer to repeat without specifyi ng the transfer settings be fore a transfer.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 20 of 1658 REJ09B0261-0100 This function enables sequential voice compression by switching a storing buffer for data received consequenti ally and a data buffer f o r processing signals alternately.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 21 of 1658 REJ09B0261-0100 14.4.7 DREQ Pin Sampling Timing Figures 14.13 to 14.22 show t he timing that the DREQ input is sampled in each bus mode. Figures 14.13, 14.16, and 14.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 22 of 1658 REJ09B0261-0100 : Non-sensitive period CLK OUT Bus cycle DREQ (Risin g ed g e) DRAK (Hi g h-active) D ACK (Hi g h-a.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 23 of 1658 REJ09B0261-0100 CLKOUT Bus cycle DREQ ( Overrun 0, Hi g h level) DRAK (Hi g h-active) DACK (Hi g h-active) CLKOUT B.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 24 of 1658 REJ09B0261-0100 Bus cycle DREQ ( Overrun 0, Hi g h level) DRAK (Hi g h-active) DACK (Hi g h-active) Bus cycle DREQ .
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 25 of 1658 REJ09B0261-0100 Acceptance started Accepted after one cycle of CLKOUT after the end of the first of the multiple bu.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 26 of 1658 REJ09B0261-0100 Bus cycle ( Overrun 0, Hi g h level) DRAK (Hi g h-active) DACK (Hi g h-active) Bus cycle ( Overrun .
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 27 of 1658 REJ09B0261-0100 Acceptance started Accepted after one cycle of CLK OUT at the first fallin g ed g e of the divided-.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 28 of 1658 REJ09B0261-0100 Acceptance started Accepted after one cycle of CLK OUT after the end of the first of the multiple b.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 29 of 1658 REJ09B0261-0100 14.5 DMAC Interrupt Sources In the DMAC, each c hannel has 14 interrupt so urces: a DMA transfer en.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 30 of 1658 REJ09B0261-0100 14.6 Usage Notes Note the following things in using this DMAC.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 31 of 1658 REJ09B0261-0100 14.6.6 DACK/DRE Q Setting If the IWRRD, IWRRS, and IWW bits in CSnBCR are set to B'000 (no idle cycles), DAC K of two or more DMA transfers may be connected.
14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 32 of 1658 REJ09B0261-0100.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 33 of 1658 REJ09B0261-0100 Section 15 Clock Pulse Generator (CPG) The CPG generates cloc ks provided to the i n ternal and external bus interf aces of the SH7785, a nd controls p ower-down mode.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 34 of 1658 REJ09B0261-0100 Oscillator circuit Control section Crystal oscillator circuit Divider 1 × 1 PLL circuit 1 × 72 × 36 Clock f.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 35 of 1658 REJ09B0261-0100 The function of each block in the CP G is as follows. • PLL circuit 1 PLL circuit 1 multiplies the input clock frequen cy on the PLL circuit by 36 or 72.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 36 of 1658 REJ09B0261-0100 15.2 Input/Output Pins Table 15.1 sho ws the CPG pi n configurati on.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 37 of 1658 REJ09B0261-0100 15.3 Clock Operating Modes Table 15.2 sho ws the relation ship between s etting of the mode pi ns (MODE0 to MODE4) an d the clock operating modes.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 38 of 1658 REJ09B0261-0100 Table 15.3 Clock Operating Modes a nd Frequency Mul tiplication Ratio for E ach Clock (Both MODE 12 and MODE11.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 39 of 1658 REJ09B0261-0100 15.4 Register Descriptions Table 15.5 lists the registers. Table 15.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 40 of 1658 REJ09B0261-0100 Table 15.6 Register State in Eac h Processing M ode Register Name Abbreviation Power-on Reset by the PRESET Pi.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 41 of 1658 REJ09B0261-0100 15.4.1 Frequency Control Re gister 0 (FRQ CR0) FRQCR0 is a 32-bit readable and partially writab le register that executes a sequence for c hanging the frequency of each clock.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 42 of 1658 REJ09B0261-0100 15.4.2 Frequency Control Re gister 1 (FRQ CR1) FRQCR1 is a 32-bit readable /writable register that ca n select.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 43 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 30 29 28 IFC3 IFC2 IFC1 IFC0 0 0 0 0 R/W R/W R/W R/W Frequency d.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 44 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 10 9 8 S2FC3 S2FC2 S2FC1 S2FC0 0 0 0 0 R/W R/W R/W R/W Frequency.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 45 of 1658 REJ09B0261-0100 15.4.3 Frequency Displ ay Register 1 (FRQ MR1) FRQMR1 is a 32-bit reada ble regi ster that reads t he division.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 46 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19 18 17 16 BFST3 BFST2 BFST1 BFST0 x x x 1 R R R R Frequency divis.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 47 of 1658 REJ09B0261-0100 15.4.4 PLL Control Register (PLLCR) PLLCR is a 32-bit readable/writabl e register that controls the cl ock output on the CLKOUT pin. This register c an only be accessed in lo ngwords.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 48 of 1658 REJ09B0261-0100 15.5 Calculating the Frequency Table 15.7 sho ws the relation ship between t he division rat io of divi der 2 descri bed for freque ncy control regist er FRQCR1 a nd frequency disp lay regist er FRQMR1, an d the EXTAL input.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 49 of 1658 REJ09B0261-0100 15.6 How to Change the Frequency To change t he frequenc y of the i nternal clock a nd the local bus clock (CLKOUT) with software, set frequency cont rol registers FRQCR0 and FR QCR1 accordi ng to the following proce dure.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 50 of 1658 REJ09B0261-0100 4. Set H 'CF000001 in FRQCR0 to enable ex ecution of the sequence that chang es the frequency. The sequence that change s the frequenc y starts. 5. The CLKOUTENB pin output changes to lo w leve l.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 51 of 1658 REJ09B0261-0100 Table 15.8 Selectable Combinations of Clock Frequency (CPU Clock: × 1/2, DDR Clock: × 1/4) Division ratio of.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 52 of 1658 REJ09B0261-0100 Division ratio of divider 2 FRQMR1 read value CPU clock Ick RAM clock Uck SuperHyway clock SHck GDTA clock GAc.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 53 of 1658 REJ09B0261-0100 Division ratio of divider 2 FRQMR1 read value CPU clock Ick RAM clock Uck SuperHyway clock SHck GDTA clock GAc.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 54 of 1658 REJ09B0261-0100 Table 15.10 Selectable Combinations of Clock Frequency (CPU Clo ck: × 1/2, DDR Cl ock: × 1/6) Division ratio.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 55 of 1658 REJ09B0261-0100 Table 15.11 Selectable Combinations of Clock Frequency (CPU Clo ck: × 1/6, DDR Cl ock: × 1/6) Division ratio.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 56 of 1658 REJ09B0261-0100 15.7 Notes on Designing Board 1. Note on Using a Crystal Resonator Place the crystal resonator and ca pacitors clos e to the EXTAL and XTAL pins as muc h as possible.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 57 of 1658 REJ09B0261-0100 CB1 RCB1 CPB1 CB2 RCB2 CPB2 CB3 RCB3 CPB3 CB4 RCB4 CPB4 CB5 RCB5 CPB5 Power supply 1 Power supply 2 SH7785 VDD.
15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 58 of 1658 REJ09B0261-0100.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 59 of 1658 REJ09B0261-0100 Section 16 Watchdog Timer and Reset (WDT) The watchdog timer and reset module (WDT) comprises a reset control unit and a w atchdog timer control uni t, and cont rols the powe r-on reset seq uence and inter nal reset of the L SI.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 60 of 1658 REJ09B0261-0100 Figure 16. 1 is a block diagram of t h e WDT. PRESET MRESETOU T Watchdo g Timer and Reset module (WDT) STATU.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 61 of 1658 REJ09B0261-0100 16.2 Input/Output Pins Table 16.1 shows the pin configuration of the WDT module. Table 16.1 Pin Configuration Pin name Function I/O Description PRESET Power-on reset input Input A low level input to this pin places the LSI in the power-on reset state.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 62 of 1658 REJ09B0261-0100 16.3 Register Descriptions Table 16.2 shows the registers of the WDT module.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 63 of 1658 REJ09B0261-0100 16.3.1 Watchdog Timer Stop Time Re gister (WDTST) WDTST is a 32-bit readable/writable register that specifies the time until wa tchdog timer counter WDTCNT overflows.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 64 of 1658 REJ09B0261-0100 16.3.2 Watchdog Timer Control/Status Register (WDTCSR) WDTCSR is a 32 -bit readable /writable register com prising timer m ode-selecting bits and overflow flags.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 65 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 RSTS 0 R/W Reset Select Specifies the type of reset on WDTCNT overflow in watchdog timer mode. This setting is ignored in interval timer mode.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 66 of 1658 REJ09B0261-0100 16.3.3 Watchdog Timer Base Stop Time Register (WDTBST) WDTBST is a 32-bit readable/writable reg ister that specifies the tim e until counter WDTBCNT overflows when th e bus clock frequency has been ch anged.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 67 of 1658 REJ09B0261-0100 16.3.4 Watchdog Timer Counter (WDTCNT ) WDTCNT is a 32-bit read-onl y register comprising a 1 2-bit count er that is incremented by the WDTBCNT overflow signal.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 68 of 1658 REJ09B0261-0100 16.3.5 Watchdog Timer Base Counter (WDTBC NT) WDTBCNT is a 32-bit read- only regi ster comprisi ng an 18-bit c o unter tha t is incremente d by the peripheral cl ock (Pck).
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 69 of 1658 REJ09B0261-0100 16.4 Operation 16.4.1 Reset Request Power-on reset and manual re set are available.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 70 of 1658 REJ09B0261-0100 (2) Manual Re set • Requesting sou rces ⎯ A general e xception ot her than a use r break whil e the BL b it in SR is set t o 1.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 71 of 1658 REJ09B0261-0100 16.4.2 Using Watc hdog Timer Mo de 1. Set th e WDTCNT overflow time in WDTST. 2. Set the WT/ IT bit in WDTCSR to 1, and select the type of reset with the RSTS bit.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 72 of 1658 REJ09B0261-0100 16.4.4 Time until WDT Counters Overflow The relationshi p between WDTCNT and WDTBCNT is shown in figure 1 6.2. The exampl e shown in the figure is the operation in in terval timer mode, where WDTCNT restarts counting after it has overflowe d.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 73 of 1658 REJ09B0261-0100 WDTBCNT is an 18-bit counter th at is incremented by the peripheral cloc k. If the period of peripheral cl ock Pck is represented a s tPck (ns), t he overflow t ime of WDTB CNT is expresse d as follows.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 74 of 1658 REJ09B0261-0100 16.5 Status Pin Change Timing during Reset 16.5.1 Power-On Reset by PRESET Pin Since the PLL circuit is initialized when the LSI enters the power-on reset state, the PLL oscillation settling time needs to be ensured.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 75 of 1658 REJ09B0261-0100 (2) Power-On Re set Caused by PRESET Input during Normal Op eration It is necessary to ensure the PLL oscillation settli ng time wh en a power-on reset is initiated by low level input on the PRESET pin during normal operation.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 76 of 1658 REJ09B0261-0100 (3) Power-On Re set Caused by PRESET Input in Sleep Mode It is necessary to ensure the PLL oscillation settling time when a power-on reset is initiated by a low level inp ut on the PRESET pin du ring sleep m ode.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 77 of 1658 REJ09B0261-0100 16.5.2 Power-On Reset by Wa tchdog Timer Overflow The time period taken b y power-on reset o n watc hdog time r overflow (WDT reset holding time) is equal to or m o re than 40 c ycles of the pe ripheral clock (Pck).
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 78 of 1658 REJ09B0261-0100 (2) Power-On Re set Caused by Watchd og Timer Overflow in Sleep Mode The timing of indicating t he reset sta.
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 79 of 1658 REJ09B0261-0100 16.5.3 Manual Reset by Watc hdog Timer Overflow The time period taken by manual re set on watchdog timer overf low (WDT manual reset ho lding time) is equal to or more than 30 cy cles of the peripheral clock (Pck).
16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 80 of 1658 REJ09B0261-0100 (2) Manual Reset Cause d by Watchd og Timer Overflow in Sleep Mode The timing of indicating t he reset state.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 81 of 1658 REJ09B0261-0100 Section 17 Power-Down Mode In power-down mod e, some of the on-chip mo dules and the CPU are stopped.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 82 of 1658 REJ09B0261-0100 Table 17.1 States of Power-Down Modes State On-Chip Peripheral Module Power- Down Mode Conditions of Transition CPG CPU On-Chip Memory DMAC GDTA Others Pin DDR2-SDRAM Releasing Methods Sleep mode SLEEP instruction executed (see section 17.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 83 of 1658 REJ09B0261-0100 17.2 Input/Output Pins Table 17.2 shows the pins rel ated to power-down mode.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 84 of 1658 REJ09B0261-0100 Table 17.4 Register States of CPG in E a ch Processing Mode Power-on Reset Manual Reset Sleep/ Deep Sleep Register Name Abb.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 85 of 1658 REJ09B0261-0100 17.3.1 Sleep Control Register (SLPCR) SLPCR is a 32-bit readable/writabl e register that can specify tr ansition to deep sleep mode.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 86 of 1658 REJ09B0261-0100 17.3.2 Standby Control Register 0 (MSTPCR0) MSTPCR0 is a 32-bit readable/wr itable re gister that can specify whether each peripheral module operates or is stopped. M STPCR can be accessed only i n longword.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 87 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 21, 20 MSTP[21:20] All 0 R/ W Module Stop Bit [21:20] Specify that the clock sup.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 88 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 9, 8 MSTP[9:8] All 0 R/W Module Stop Bit [9:8] Specify that the clock supp ly to.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 89 of 1658 REJ09B0261-0100 17.3.3 Standby Control Register 1 (MSTPCR1) MSTPCR1 is a 32-bit readab le/writable register that each module of H-UDI, UBC, DMAC, and GDTA operates or is stopped. MSTP CR1 can be accessed only in longword.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 90 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 16 to 6 ⎯ All 0 R/W Reserve d These bits are always read as 0.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 91 of 1658 REJ09B0261-0100 17.3.4 Standby Display Register (MSTPM R) MSTPMR is a 32-bit readable register that indicates whether th e PCIC/display unit (DU)/DMAC/GDTA modules are i n the module st andby state.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 92 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5, 4 MSTPS105 MSTPS104 All 0 R Module Stop Display Bit 105, 104 Indicates the st.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 93 of 1658 REJ09B0261-0100 17.4 Sleep Mode 17.4.1 Transition to Sleep Mode When the SLEEP instruction is executed, the state is changed from t he program execution state to sleep mode. Al though the CPU is stop ped aft er th e instruction is executed, the conte nts of the CPU register are retained.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 94 of 1658 REJ09B0261-0100 17.5 Deep Sleep Mode 17.5.1 Transition to Deep Sleep Mode If a SLEEP instruction is e xecuted when the DSLP bit in SLPCR is set to 1, the chip switches from the pro gram executio n state to deep sl eep mode.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 95 of 1658 REJ09B0261-0100 17.5.2 Releasing Deep Sleep Mode Deep sleep mode is released by means of a n interrupt (NMI , IRL, IRQ, GPIO, WDT inter val timer, or H-UDI) or a reset. In deep sleep mode, an inte rrupt request is accepted even if the BL bit in SR is set to 1.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 96 of 1658 REJ09B0261-0100 17.6 Module Standby Functions This LSI supports the module standby state, wh ere the clock supplied to on-chip mo dules is stopped. 17.6.1 Transition to Module Standby M ode By setting the MSTP bits in MSPTCR, the clock supply can be stopped to the corresponding module*.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 97 of 1658 REJ09B0261-0100 17.7 Timing of the Changes on the STATUS Pins 17.7.1 Reset For details, see section 16.5, Status Pin Cha nge Timing during Reset. 17.7.2 Releasing Sleep Mode (1) When Sleep Mode Is Rele ased by an Interrupt Figure 17.
17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 98 of 1658 REJ09B0261-0100.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 7 99 of 1658 REJ09B0261-0100 Section 18 Timer Unit (TMU) This LSI incl udes an on-c hip 32-bi t timer uni t (TMU), whic h has six c hannels (chan nels 0 to 5) . 18.1 Features The TMU has the following features.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 00 of 1658 REJ09B0261-0100 Figure 18.1 show s a block diagra m of the TMU. Channel 0, 1 Channel 2 Channel 3, 4, 5 TCR TSTR0 TSTR1 Clock controller TC.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 01 of 1658 REJ09B0261-0100 18.2 Input/Output Pins Table 18.1 sho ws the TMU pi n configuratio n. Table 18.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 02 of 1658 REJ09B0261-0100 18.3 Register Descriptions Tables 18.2 and 18.3 show t he TMU regi ster configurati on.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 03 of 1658 REJ09B0261-0100 Table 18.3 Register Configuration (2) Channel Register Nam e Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset .
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 04 of 1658 REJ09B0261-0100 18.3.1 Timer Start Registers (TST Rn) (n = 0, 1 ) The TSTR registers are 8-bit r eadable/writable registers that specifies whether TCNT of the corresponding channel is operated or stopped.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 05 of 1658 REJ09B0261-0100 • TSTR1 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 STR3 STR4 STR5 — — — — — R/W R/W R/W R R R R R BIt: Initial value: R/W: Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 06 of 1658 REJ09B0261-0100 18.3.2 Timer Constant Regi sters (TCORn) (n = 0 to 5) The TCOR registers are 32-bi t readable/writ able registers. When a TCNT counte r underflows while counting do wn, the TCOR value is set in that TCNT, which con tinues counting down from the set value.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 07 of 1658 REJ09B0261-0100 18.3.4 Timer Control Registers (TCR n) (n = 0 to 5) The TCR registers are 16-bit read able/writable registers.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 08 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 6 ICPE1 * 1 ICPE0 * 1 0 0 R/W R/W Input Capture Control These bits, provided .
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 09 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Timer Prescaler 2 to 0 These bits select the TCNT count clock.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 10 of 1658 REJ09B0261-0100 18.4 Operation Each channel h as a 32-bit t imer counter (TCNT) and a 32-bit ti mer constant regi ster (TCOR).
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 11 of 1658 REJ09B0261-0100 (2) Auto-Rel oad Count Operation Figure 18.3 sh ows the TCNT auto-rel oad operation. TCNT value TCOR H'0000 0000 STR0 to STR5 UNF TCOR value is set in TCNT on underflow Time Figure 18.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 12 of 1658 REJ09B0261-0100 (3) TCNT Count Timing • Operating on internal cl ock Any of fi ve internal c ount cloc ks (Pck/4, Pc k/16, Pck/64, Pck/2 56, or Pck/ 1024) scaled fr om the peripheral clock can be selected as the co unt clock by m eans of the TP SC2 to TPSC0 bits in TCR.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 13 of 1658 REJ09B0261-0100 18.4.2 Input Capture Function Channel 2 has an input capture function. The procedure for using t he input captu re function i s as follows: 1. Use bits TPSC2 to TPSC 0 in TCR2 to set an internal cl ock as the timer operating cl ock.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 14 of 1658 REJ09B0261-0100 18.5 Interrupts There are seven TMU in terrupt sources: underflow interrupts and the input capture inter rupt when the input capture function is used. Underflow interrupts are generate d on each of the channels, and input capture interrupts on chan nel 2 only.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 15 of 1658 REJ09B0261-0100 18.6 Usage Notes 18.6.1 Register Writes When writi ng to a TMU register, timer count ope ration must be stopped by clearing the sta rt bit (STR5 to STR0) for the relevant channel in TSTR.
18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 16 of 1658 REJ09B0261-0100.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 17 of 1658 REJ09B0261-0100 Section 19 Display Unit (DU) 19.1 Features The display unit (DU) has the fol lowing feat ures. Plane: The display surfaces normally called the fo reground, background, and cursor, are called planes in this section.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 18 of 1658 REJ09B0261-0100 CRT Scan Mode (CRT Sc an Method): Internal register settings can be used t o select from among three scan modes.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 19 of 1658 REJ09B0261-0100 Figure 19.1 sh ows a block diagra m of the display unit (DU). Pin control (output timin g adjustment) Display data format.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 20 of 1658 REJ09B0261-0100 19.2 Input/Output Pins Table 19.1 sho ws the pin co nfiguration o f the display unit (DU).
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 21 of 1658 REJ09B0261-0100 Pin Name Number I/O Function Signal Name Used in This Section DG5 1 Output Digital green 5 DB0 1 Output Digita l blue 0 D.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 22 of 1658 REJ09B0261-0100 • Display mo de register (DSM R) ⎯ VSPM bit ( VSYNC pin mode) ⎯ ODPM bit (ODPM pin mode) ⎯ ODDF bit (OD DF pin mo.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 23 of 1658 REJ09B0261-0100 Table 19.2 Register Configuration Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock Display contro.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 24 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock DE signal start position register DESR R/W H&apo.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 25 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock Plane 1 wrap-around memory width register P1WAMW.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 26 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock Plane 3 memory width register P3MWR R/W H'F.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 27 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock Plane 4 display area start address 0 registe r P.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 28 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock Plane 5 wrap-around memory width register P5WAMW.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 29 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock Color palette registers Color palette 1 register.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 30 of 1658 REJ09B0261-0100 Table 19.3 Status of Re gisters in Each Processing Mode Register Name Abbr.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 31 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standb.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 32 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standb.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 33 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standb.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 34 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standb.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 35 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standb.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 36 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standb.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 37 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standb.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 38 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standb.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 39 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standb.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 40 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standb.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 41 of 1658 REJ09B0261-0100 19.3.1 Display Unit System Contro l Register The display unit system c ontrol re gister (DS YSR) sets the system operati on for the display unit (DU).
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 42 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 16 IUPD 0 R/W Yes Internal Updating Disable When DRES = 1, internal update is performed regardless of this bit. For details of internal update, see (2) Internal Update in section 19.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 43 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9 DRES 1 R/W None Display Reset 8 DEN 0 R/W Yes Display Enable 00: Starts display synchronization operation.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 44 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 7, 6 TVM 10 R/W None TV Synchroniz ation Mode 00: Master mode .
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 45 of 1658 REJ09B0261-0100 19.3.2 Display Mode Register (DSMR) The display m ode register (DSMR) set s the displa y operation of the display uni t.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 46 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 24 CSPM 0 R/W * CSYNC Pin Mode Settings in DSYSR are given priority over settings in this register.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 47 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 14, 13 CDEM 00 R/W * CDE Output Mode 00: CDE signal is output .
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 48 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 7, 6 CSY 00 R/W None CSYNC Mode For details of CSYNC waveform, refer to section 19.5.2, CSYNC. 00: The relation among VSYNC, HSYNC, and CSYNC is as follows.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 49 of 1658 REJ09B0261-0100 19.3.3 Display Stat us Register (DS SR) The display st atus regist er (DSSR) is a register used to read, f rom outside, the internal state of the display unit (DU).
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 50 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 20 DFB5 0 R None Display Frame Buffer 5 Flag 0: The address in.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 51 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 16 DFB1 0 R None Display Frame Buffer 1 Flag 0: The address in.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 52 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 13, 12 ⎯ All 0 R ⎯ Reserved These bits are always read as 0.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 53 of 1658 REJ09B0261-0100 19.3.4 Display Unit Status Registe r Clear Regi ster (DSRCR) The display unit status register cl ear register (DSRCR) is a regist er wh ich clears the various flags in DSSR.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 54 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9 RICL Undefined W None Vertical Blanking Flag Clear 0: The RINT flag in DSSR is not changed. 1: The RINT flag in DSSR is cleared to 0.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 55 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 31 to 16 ⎯ All 0 R ⎯ Reserved These bits are always read as 0.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 56 of 1658 REJ09B0261-0100 The followin g are condit ions, base d on DSSR and this re gister, for i ssuing a n interrupt t o the CPU from the displa y unit (DU).
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 57 of 1658 REJ09B0261-0100 19.3.6 Color Palette Co ntrol Register (CPC R) The color palette control register (CPCR) is a regi ster which enables switchi ng of the col or palette. For information on color palette switching, refer to section 19.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 58 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 18 CP3CE 0 R/W Yes Color Palette 3 Change Enable 0: Switching of color palette 3 is not performed. 1: Switching of color palette 3 is performed.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 59 of 1658 REJ09B0261-0100 19.3.7 Display Plane Priority Re gister (DPPR) The display plane pri o rity regist er (DPPR) sets the priori ty order for combining planes and turns the display on and of f.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 60 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 19 DPE5 0 R/W Yes Display Plane Priority 5 Enable 18 to 16 DPS.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 61 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 11 DPE3 0 R/W Yes Display Plane Priority 3 Enable 10 to 8 DPS3.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 62 of 1658 REJ09B0261-0100 19.3.8 Display Unit Extensional Function Enable Register (DEFR) The display unit extensio nal function e nable register (DEFR) e nables exten sion functio ns.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 63 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 4 ABRE 0 R/W None Alpha Blend R atio Enable 0: The 31 to 24 bits in the color palette registers 1 to 4 and the PnBRSL bits in the plane n blend ratio registers (PnALPHAR) are disabled.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 64 of 1658 REJ09B0261-0100 19.3.9 Horizontal Di splay Start Re gister (HDSR) The horizontal display start register (HDSR) sets the horizontal display sta rt position. T he value is retained during power-on reset and manu al reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 65 of 1658 REJ09B0261-0100 19.3.10 Horizontal Display End Register (H DER) The horizontal display end register ( HDER) sets t he horizontal display end po sition. The value is retained during powe r-on reset and ma nual reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 66 of 1658 REJ09B0261-0100 19.3.11 Vertical Displ ay Start Register (VDS R) The vertical display start regi ster (VDSR) sets the vertical display sta rt position. The value is retained during power-on reset and manu al reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 67 of 1658 REJ09B0261-0100 19.3.12 Vertical Displ ay End Register (VDER) The vertical display end register (VDER) set s the vertical displa y end position. The value is retained during powe r-on reset and ma nual reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 68 of 1658 REJ09B0261-0100 19.3.13 Horizontal Cycle Register (HCR) The horizontal cycle register (HCR) sets the horizontal scan cycle.(period). Th e value is retained during powe r-on reset and manual reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 69 of 1658 REJ09B0261-0100 19.3.14 Horizontal Sync Width Re gister (HSWR) The horizontal sync width register (HS WR) sets the low -level pulse wi dth of the horizontal sync signal. The val ue is retained during power -on reset and ma nual reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 70 of 1658 REJ09B0261-0100 19.3.15 Vertical Cycle Register (VCR) The vertical cycle register (VCR) sets the vertical scan interval.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 71 of 1658 REJ09B0261-0100 19.3.16 Vertical Sync Point Register (VSPR) The vertical s ync point re gister (VSPR) sets the star t position of the vertical sync signal in raster line units. The value is retain ed during power-on reset and manual reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 72 of 1658 REJ09B0261-0100 19.3.17 Equal Pulse Width Re gister (EQWR) The equal puls e width regi ster (EQWR ) sets the low -level pulse width of a pulse equi valent to the CSYNC signal. The value is retained duri ng power-on reset and ma nual reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 73 of 1658 REJ09B0261-0100 19.3.18 Separation Width Re gister (SPWR) The separation width regi ster (SPWR) sets the low -level pulse width of the se paration pulse for the CSYNC sig nal. The value is retained during pow er-on reset and manual reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 74 of 1658 REJ09B0261-0100 19.3.19 CLAMP Signal Start Register (CL AMPSR) The CLAMP s ignal start re gister (CLAMPSR) sets the risi ng edge position of t he CLAMP signal . For timing charts for the CLAMP sign al and the DE signal, refer to section 19.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 75 of 1658 REJ09B0261-0100 19.3.20 CLAMP Signal Width Register (CLAM PWR) The CLAMP signal width register (CLA MPWR) sets the high-level width of the CLAMP signal. The value is retained during power-on reset an d manual reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 76 of 1658 REJ09B0261-0100 19.3.21 DE Signal Start Regis ter (DESR) The DE signal start re gister (DESR) sets the risi ng edge position of the DE signal. The value is retained during power-on reset and manu al reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 77 of 1658 REJ09B0261-0100 19.3.22 DE Signal Width Re gister (DEW R) The DE signal width regi ster (DEWR) set s the high -level width of the DE s ignal. The val ue is retained during powe r-on reset and ma nual reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 78 of 1658 REJ09B0261-0100 19.3.23 Color Palette 1 Transparen t Color Register (CP1 TR) The color palette 1 transp arent color register (C P1TR) specifies the t ransparent color for c o lor palette 1.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 79 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 12 CP1IC 0 R/W Yes Color Palette 1 Index C 0: The color with index C in color palette 1 is not set to the transparent color.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 80 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 5 CP1I5 0 R/W Yes Color Palette 1 Index 5 0: The color with index 5 in color palette 1 is not set to the transparent color.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 81 of 1658 REJ09B0261-0100 19.3.24 Color Palette 2 Transparen t Color Register (CP2 TR) The color palette 2 transp arent color register (C P2TR) specifies the transpa rent color of color palette 2.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 82 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 12 CP2IC 0 R/W Yes Color Palette 2 Index C 0: The color with index C in color palette 2 is not set to the transparent color.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 83 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 5 CP2I5 0 R/W Yes Color Palette 2 Index 5 0: The color with index 5 in color palette 2 is not set to the transparent color.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 84 of 1658 REJ09B0261-0100 19.3.25 Color Palette 3 Transparen t Color Register (CP3 TR) The color palette 3 transp arent color register (C P3TR) specifies the transpa rent color of color palette 3.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 85 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 12 CP3IC 0 R/W Yes Color Palette 3 Index C 0: The color with index C in color palette 3 is not set to the transparent color.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 86 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 5 CP3I5 0 R/W Yes Color Palette 3 Index 5 0: The color with index 5 in color palette 3 is not set to the transparent color.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 87 of 1658 REJ09B0261-0100 19.3.26 Color Palette 4 Transparen t Color Register (CP4 TR) The color palette 4 transp arent color register (C P4TR) specifies the transpa rent color of color palette 4.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 88 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 12 CP4IC 0 R/W Yes Color Palette 4 Index C 0: The color with index C in color palette 4 is not set to the transparent color.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 89 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 5 CP4I5 0 R/W Yes Color Palette 4 Index 5 0: The color with index 5 in color palette 4 is not set to the transparent color.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 90 of 1658 REJ09B0261-0100 19.3.27 Display Off Mode Output Register (DOOR) The display off mode output regist er (DOOR) sets the displ ay data output whe n the displa y is turned off. The valu e is retained during power-on reset and manual reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 91 of 1658 REJ09B0261-0100 19.3.28 Color Detection Re gister (CDER) The color detection register (CDER) sets the color for color detection. When the display output data match the settin gs of this register, high level is output from the CDE pin.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 92 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 1, 0 ⎯ All 0 R ⎯ Reserved These bits are always read as 0.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 93 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9, 8 ⎯ All 0 R ⎯ Reserved These bits are always read as 0.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 94 of 1658 REJ09B0261-0100 19.3.30 Raster Interrupt Offset Register (RINTOFSR) The raster interrupt of fset register (R INTOFSR) se ts t he raster offset value for raster interrupts. The value is retained during power-on reset an d manual reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 95 of 1658 REJ09B0261-0100 19.3.31 Plane n Mode Register (PnMR) (n = 1 to 6) The plane n mode re gisters (PnMR, n = 1 to 6) set the dis p lay operatio n for plane n.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 96 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 14 to 12 PnSPIM 0 R/W Yes Plane n Super Impose Mode 000: Transparent color processing is p erformed for plane n. When plane n is in the transparent color, the lower plane is displayed.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 97 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9, 8 PnCPSL 0 R/W Yes Plan e n Color Palette Select When the PnDDF bit is set to 8 bits/pixel, specifies the color palette to be used.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 98 of 1658 REJ09B0261-0100 19.3.32 Plane n Memory Width Register (PnMWR) (n = 1 to 6) The plane n m emory width regist ers (PnMWR , n = 1 to 6) s et the memory width f or plane n. The value is retained during power-on reset an d manual reset.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 99 of 1658 REJ09B0261-0100 19.3.33 Plane n Blending Ratio Register (PnALPHAR) (n = 1 to 6) The plane n bl ending ratio registers (PnALPHAR , n = 1 to 6) set the blen d ratios an d blend rat io selection for plane n.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 00 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description Plane n Blending Ratio Select This bit is valid when the following two conditions are satisfied. • When the PnSPIM bit in PnMR specifies blending.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 01 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 7 to 0 PnALPHA Undefined R/W Yes Plane n Blending Rati o The alpha value ( α ) which is the bl end ratio for plane n should be set.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 02 of 1658 REJ09B0261-0100 19.3.35 Plane n Display Size Y Register (PnDSYR) (n = 1 to 6) The plane n display size Y registers (PnDSYR, n = 1 to 6) set the display size in the vertical direction for plane n.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 03 of 1658 REJ09B0261-0100 19.3.36 Plane n Display Position X Register (PnDPXR) (n = 1 to 6) The plane n di splay posi tion X regi sters (PnDP XR, n = 1 to 6) set the horizontal start positions on the display monito r for plane n.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 04 of 1658 REJ09B0261-0100 19.3.37 Plane n Display Positio n Y Register (PnDPY R) (n = 1 to 6) The plane n display position Y registers (PnDPYR, n = 1 to 6) set the vertical start pos ition on the display mo nitor of pl ane n.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 05 of 1658 REJ09B0261-0100 19.3.38 Plane n Display Area Start Address 0 Register (Pn DSA0R) (n = 1 to 6) The plane n display area start addr ess 0 registers (PnDSA0R, n = 1 to 6) set the memory area in frame buffer 0 for plane n.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 06 of 1658 REJ09B0261-0100 19.3.39 Plane n Display Area Start Address 1 Register (Pn DSA1R) (n = 1 to 6) The plane n display area start addr ess 1 registers (PnDSA1R, n = 1 to 6) set the memory area in frame buffer 1 for plane n.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 07 of 1658 REJ09B0261-0100 19.3.40 Plane n Start Positi on X Register (PnSP XR) (n = 1 to 6) The plane n start position X registers (PnSPXR, n = 1 to 6) set the horizontal start position of plane n in me mory.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 08 of 1658 REJ09B0261-0100 19.3.41 Plane n Start Positi on Y Register (PnSP YR) (n = 1 to 6) The plane n start position Y registers (PnSPYR, n = 1 to 6) set the vertical start position of plane n in memory.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 09 of 1658 REJ09B0261-0100 19.3.42 Plane n Wrap Around Start Position Re gister (PnWASPR) (n = 1 to 6) The plane n wrap-around star t pos ition re gisters (PnW ASPR, n = 1 t o 6) set t he Y direction st art position of one wrap-around area of pl ane n.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 10 of 1658 REJ09B0261-0100 19.3.43 Plane n Wrap Around Mem o ry Width Register (Pn WAMWR) (n = 1 to 6) The plane n w rap-arou nd memory wi dth registers (PnWA MWR, n = 1 t o 6) set the wrap-aro und Y-direction me mory width for plane n.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 11 of 1658 REJ09B0261-0100 19.3.44 Plane n Blinking Time Regis ter (PnBTR) (n = 1 to 6) The plane n bl inking time regi sters (PnBTR, n = 1 to 6) set the displa y interval length fo r plane n.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 12 of 1658 REJ09B0261-0100 19.3.45 Plane n Transparent Color 1 Register (PnTC1R) (n = 1 to 6) The plane n transparent col o r 1 regi sters (PnTC1R, n = 1 to 6) set a transparent color for plane n, in 8 bits/pixel data format.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 13 of 1658 REJ09B0261-0100 19.3.46 Plane n Transparent Color 2 Register (PnTC2R) (n = 1 to 6) The plane n transparent col o r 2 regi sters (PnTC2R, n = 1 to 6) set a transparent color for plane n in the 16 bits/pixel, ARGB data fo rmat.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 14 of 1658 REJ09B0261-0100 19.3.47 Plane n Memory Length Register (PnMLR) (n = 1 to 6) The plane n memory length registers (PnM LR, n = 1 to 6) set th e memory length (Y-direction memory area) for plane n.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 15 of 1658 REJ09B0261-0100 19.3.48 Color Palett e 1 Register 000 to 255 (CP1_0 00R to CP1_255R ) The color palette 1 registers 000 to 255 (CP1_ 000R.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 16 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9, 8 ⎯ All 0 R ⎯ Reserved These bits are always read as 0.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 17 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 31 to 24 CP2_000A to CP2_255A Undefined R/W Yes Color Palette 2_000 to 255 Bl ending Ratio To enable this bit, the ABRE bit in DEFR should be set to 1.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 18 of 1658 REJ09B0261-0100 19.3.50 Color Palett e 3 Register 000 to 255 (CP3_0 00R to CP3_255R ) The color palette 3 registers 000 to 255 (CP3_ 000R.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 19 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9, 8 ⎯ All 0 R ⎯ Reserved These bits are always read as 0.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 20 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 31 to 24 CP4_000A to CP4_255A Undefined R/W Yes Color Palette 4_000 to 255 Bl ending Ratio To enable this bit, the ABRE bit in DEFR should be set to 1.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 21 of 1658 REJ09B0261-0100 19.3.52 External Sync hronization Control Re gister (ESCR) The external synchronization control regi ster (ESCR) controls the dot clock.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 22 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 4 to 0 FRQSEL 0 R/W None Frequency Select To enable this bit, the DCKE bit in DEFR should be set to 1. In the initial state, bit 4 is fixed at 0, and the frequency division ratio is up to 16.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 23 of 1658 REJ09B0261-0100 19.3.53 Output Signal Timing Adju stment Register (OTAR) The output signal timing adjustme nt register (OTAR) selects the timing for the output signal. For information on adjustment timing, refer to secti on 19.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 24 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 30 to 28 DEA 0 R/W None DE Output Timing Adjustment 000: Adjustment of output timing is not performed. The DE signal is output at the rising edge of the dot clock, with the reference timing.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 25 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 26 to 24 CLAMPA 0 R/W None CLAMP Output Timing Adjust ment 000: Adjustment of output timing is not performed. The CLAMP signal is output at the rising edge of the dot clock, with the reference timing.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 26 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 22 to 20 DRGBA 0 R/W None Digital IR GV Output Timing Adjustment 000: Adjustment of output timing is not performed.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 27 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 10 to 8 CDEA 0 R/W None CDE Output Timing Adjustment 000: Adjustment of output timing is not performed. The CDE signal is output at the rising edge of the dot clock, with the reference timing.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 28 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 6 to 4 DISPA 0 R/W None DISP Output Timing Adjustment 000: Adjustment of output timing is not performed. The DISP signal is output at the rising edge of the dot clock, with the reference timing.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 29 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 2 to 0 SYNCA 0 R/W None SYNC * Output Timing Adjustment 000: Adjustment of output timing is not performed. The SYNC * signal is output at the rising edge of the dot clock, with the reference timing.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 30 of 1658 REJ09B0261-0100 19.4 Operation 19.4.1 Configuration of O utput Screen The display unit (DU) e xecutes wind ow displays with up to a maximum of six win dow layers. Each of these windows is cal led a "plane", a n d the orde r of stacking of the plane s can be set arbitrarily.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 31 of 1658 REJ09B0261-0100 Table 19.4 Displa y Functions of Planes Display Data Format Display On/Off 8 bits/ pixel 16 bits/ pixel ARGB YC Superposi.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 32 of 1658 REJ09B0261-0100 F rame buff er 2 A double-b uffer function is used to s witch the frame buff er between drawing side and display side The superpositioning order can be specified arbitrarily .
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 33 of 1658 REJ09B0261-0100 19.4.2 Display On/Off All plane di splay ca n be turned on and off usi ng the DEN bit in DSY SR. When t h e DEN bit is 0, the display data set in DOO R is displayed. Display is turned on and off for planes 1 to 6 usi ng DPPR.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 34 of 1658 REJ09B0261-0100 19.4.3 Plane Parameter For each plane, a display area start position, memory wid th, display start position, and d isplay size are set using registers.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 35 of 1658 REJ09B0261-0100 Table 19.6 Memory Parameter/ Mo ni tor Parameter Settin g Registers No. Names Used in the Figure Setting Registers Description 1 MWX (Plane memory width) PnMWR The plane X-direction memory width is set between 16 and 4096 pixe ls, in 16 pixel units.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 36 of 1658 REJ09B0261-0100 19.4.4 Memory Allocation A display start address for the di splay screen can be set indi vidu ally for each plane. Leading addresses for the memory areas us ed are set in each of t he display area start address regi sters.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 37 of 1658 REJ09B0261-0100 19.4.5 Input Display Da ta Format The following format is u sed for input color data used in display. • 8 bit/pixel A color palette index is u sed. The color palette is used to conv ert and display image data into RGB data with 6 bits for each RGB color (RGB666).
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 38 of 1658 REJ09B0261-0100 • 16 bit/pixel: ARGB The ARGB le vels are rep resented usi ng A:1, R :5, G:5, B: 5 bits (ARGB 555).
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 39 of 1658 REJ09B0261-0100 • UYVY format A+3 A+2 A+1 A A A+1 A+2 A+3 31 23 15 7 0 31 23 15 7 0 Address A Y1 V0 Y0 U0 Address A U0 Y0 V0 Y1 Address.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 40 of 1658 REJ09B0261-0100 19.4.6 Output Data Format When outputting digital RG B data from the display unit (DU), the d isplay data format is expanded into the RGB 666 format before output. The format at the time of output is as indicated in the following table.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 41 of 1658 REJ09B0261-0100 Endian conve rsion in each of the u nits indica ted below is shown i n figure 1 9.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 42 of 1658 REJ09B0261-0100 19.4.8 Color Palettes 8 bits/pixel data employs color palettes. Four co lor palettes can be used; these are called color palette 1, color palette 2 , color palette 3, and color palette 4.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 43 of 1658 REJ09B0261-0100 19.4.9 Superposition ing of Planes For each plane, three types of combined s uperposit ioning are p ossible: α blending, transparent colors, and EOR operations. By settin g the PnSPIM bits in PnMR, the superpositioned disp lay type can be selected.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 44 of 1658 REJ09B0261-0100 Table 19.11 RGB888 Bit Configurat ion in Each Display Data Format Data Format R (8 bits) G (8 bits) B (8 bits) 8 bits/pix.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 45 of 1658 REJ09B0261-0100 When the PnDDF bit in PnMR is set to ARGB, and moreover th e PnSPIM bit in PnMR is set to perform ble nding, α blending is performed a ccording to the A value of the i nput ARGB data format.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 46 of 1658 REJ09B0261-0100 Table 19.12 Transparent Colo r Specification Registers Data Format Transparent Color Specification Bit Color Palette Sele.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 47 of 1658 REJ09B0261-0100 19.4.10 Display Conte ntion Color Palette Contention: Whe n performing α blending and EOR operat ions, if the same col or palette is selected for bot h planes with the input display data format at 8 bi ts/pixel, color palette contention ma y occur.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 48 of 1658 REJ09B0261-0100 P1 P1 P2 P3 ΔΔΔ X X P2 ΔΔ X Δ X P3 Δ X ΔΔ X P1 P1 P1 P1 P2 P2 P3 BPOR P1 P1 P1 α P3 P1 P2 ⊕ P3 P2 ⊕ P3 P2 P.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 49 of 1658 REJ09B0261-0100 Plane Priority Order: The display priority order fo r planes is set using DPPR; if one plane is set in two or more places in the priority order, the place with highe st priority is selected.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 50 of 1658 REJ09B0261-0100 19.4.12 Scroll Display By setting display area and display screen sizes and start positio ns independently for each plane, smooth scroll processing can be pe rformed independently for each plane.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 51 of 1658 REJ09B0261-0100 19.4.13 Wraparoun d Display In addition to display scrolling, wrap-around display, which can be used in spherical scrolling , is possible for each plane. Whe n en abling wra p-around dis play, the Pn WAE bit in P nMR is set.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 52 of 1658 REJ09B0261-0100 19.4.14 Upper-Left Overflow Displ ay For each plane, a display start position i n memory (PnSPXR, PnSPYR ) and dis play s.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 53 of 1658 REJ09B0261-0100 19.4.15 Double Buffer Control The double buffer c ontrol of the displa y unit (DU) includes two types of f unctions, whi .
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 54 of 1658 REJ09B0261-0100 19.4.16 Sync Mode In order to facilitate synchronization with external equipment, in addition to master mod e, a TV synchronizatio n function is provided. Sel ection of master mode an d TV sync mo de is performe d using the TVM bit in DSYSR.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 55 of 1658 REJ09B0261-0100 TV (sync signal generation circuit): Master Clock HSYNC VSYNC R,G,B This LSI: Slave DCLKIN DR5-DR0 DG5-DG0 DB5-DB0 Input 2 Input 1 Output Display Switching between master (input 2) and slave (input 1) by CDE.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 56 of 1658 REJ09B0261-0100 19.5 Display Control 19.5.1 Display Timing Generation In the displa y unit (DU), displ ay timing is generated for the horiz ontal direction and ve rtical direction of t he display screen .
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 57 of 1658 REJ09B0261-0100 Table 19.13 Variables Defined in Display Screen Variables Contents Units hc * 1 Horizontal scan period Dot clock hsw Hori.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 58 of 1658 REJ09B0261-0100 Table 19.14 Correspondence Tabl e of Settin gs of Display Timing Genera tion Regi sters Synchronization Method Register N.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 59 of 1658 REJ09B0261-0100 19.5.2 CSYNC When in master mo de, a CSYNC (composite sync) si gnal is output. EQWR is use d to set the low- level pulse width of the CSYNC equ al pulse. SPWR is used to set the low-level pulse width of the CSYNC separa tion pulse.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 60 of 1658 REJ09B0261-0100 VSYNC CSYNC (CSY = 00) EQW (CSY = 10) (CSY = 11) 1/2HC 1/2HC SPW HSW HSYNC HC Equivalent pulse: 2.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 61 of 1658 REJ09B0261-0100 19.5.3 Scan Meth od The scan method can be selected from among non-interlaced mode, i nterlaced sy nc mode, and interlaced sync & video mode . The mode is selected usi ng the SCM bit in DSYSR.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 62 of 1658 REJ09B0261-0100 Raster scanned in an odd field Raster scanned in an even field 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04 05 06 07 08 0.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 63 of 1658 REJ09B0261-0100 • Example of verti cal scan period Non-interlaced mode: 1/60 seco nd/field, 1/30 second/field Interlaced m ode: 1/30 se.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 64 of 1658 REJ09B0261-0100 • Display in interlaced method At every sca n period VC of the input vi deo signal, even lines an d odd line s are swit.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 65 of 1658 REJ09B0261-0100 19.5.4 Color Detection When output display data matches a col or set in CDER, high level is output fr om the CDE pi n. The CDEM bit in DSMR can be used to fix th e level outside display intervals.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 66 of 1658 REJ09B0261-0100 19.5.5 Output Signal Timing Adju stment The display unit (DU) e nables selection of output timing, with respect to t he o.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 67 of 1658 REJ09B0261-0100 19.5.6 CLAMP Signal and DE Signal The display unit (DU) ge nerates a CLAMP signal a nd DE signal, independent of the DIS P signal indicating the display interval.
19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 68 of 1658 REJ09B0261-0100 19.6 Power-Down Sequence When execu ting the power-dow n sequence by the follow ing modes or function s, turn off the display in advance. 1. Sleep mode 2. Deep sleep mode 3.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 69 of 1658 REJ09B0261-0100 Section 20 Graphics Data Translati on Accelerator (GDTA) This block i ncorporates a YUV data .
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 70 of 1658 REJ09B0261-0100 Figure 20. 1 shows the GDTA bloc k diagram. SuperHyway bus External memory Tar g et interface.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 71 of 1658 REJ09B0261-0100 (1) Target Interface The target interface controls access by t he CPU to the GDTA i nternal registers, buffer RAM 0/1, and CL and MC function blocks (i mage processing functi on bloc ks).
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 72 of 1658 REJ09B0261-0100 (6) Buffer RA M Buffer RAM consists of two SRAM units each w ith an 8-Kbyte capacity. The RAM is used to store color c onversion table dat a for CL f unctions (b uffer RAM 0) and t o store IDC T data for M C functions (buff er RAM 1).
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 73 of 1658 REJ09B0261-0100 20.2 GDTA Address Space Figure 20.2 shows the GDTA addr ess space (physical addresses). Th e GDTA consists of a number of functio n blocks; the address space is divi ded into function bl ock units owned b y the respect ive blocks.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 74 of 1658 REJ09B0261-0100 20.3 Register Descriptions Table 20.1 to 20.3 show t he register c onfiguration of the GDT A. Table 20.4 t o 20.6 show the register states i n each processi ng mode.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 75 of 1658 REJ09B0261-0100 Table 20.2 GDTA Regis ter Configuration (CL Block) Name Abbreviation R/W P4 Address Area 7 Ad.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 76 of 1658 REJ09B0261-0100 Table 20.3 GDTA Regis ter Configuration (MC Block) Name Abbreviation R/W P4 Address Area 7 Ad.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 77 of 1658 REJ09B0261-0100 Table 20.4 GDTA Register State s in Each Processing Mode (G DTA Common Registers ) Register A.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 78 of 1658 REJ09B0261-0100 Table 20.6 GDTA States in Each Processing Mode (MC Block) Register Abbreviation Power-On Rese.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 79 of 1658 REJ09B0261-0100 20.3.1 GA Mask Register (GACMR) GACMR is in t he GDTA commo n re gister bl ock and enables writing t o the GA enable regist er (GACER). Writing to GACER is enabled by writing of the key code to this register.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 80 of 1658 REJ09B0261-0100 20.3.2 GA Enable Register (GACER) GACER is in t h e GDTA co mmon register block and c ontrols t he block operat ion.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 81 of 1658 REJ09B0261-0100 20.3.3 GA Interrupt Source Indica ting Register (GACISR) GACISR is in the GDTA common register block an d indicates the stat es of interr upt source s for each module.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 82 of 1658 REJ09B0261-0100 20.3.4 GA Interrupt Source Indicati on Clear Register (GACICR) GACICR is in the GDTA c ommon register bloc k and clears interrupt so urce indication for each module.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 83 of 1658 REJ09B0261-0100 20.3.5 GA Interrupt Enable Register (GACIER) GACIER is i n the GDT A common re gister block and sets interrupt output fo r each mod ule.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 84 of 1658 REJ09B0261-0100 20.3.6 GA CL Input Data Ali gnment Register (DRCL _CTL) DRCL_CTL is in the GDTA common regist er block and specifies data al ignment of C L input data.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 85 of 1658 REJ09B0261-0100 20.3.7 GA CL Output Data Ali gnment Register (DWCL_CTL) DWCL_CTL i s in the GDT A common re gister block and specifies data alignment of CL out put data.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 86 of 1658 REJ09B0261-0100 20.3.8 GA MC Input Data Alignment Register (D RMC_CTL) DRMC_CTL i s in the GDTA common re gister block an d specifies data al ignment of MC input data.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 87 of 1658 REJ09B0261-0100 20.3.9 GA MC Output Data Alignment Regist er (DWMC_CTL) DWMC_CTL i s in the GDT A common re gister block an d specifies data alignment of MC output data.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 88 of 1658 REJ09B0261-0100 20.3.10 GA Buffer RAM 0 Data Alignment Register (DCP_CTL) DCP_CTL is i n the GDT A common regi ster bloc k an d specifies d ata alignment of the data stored in buffer RAM 0.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 89 of 1658 REJ09B0261-0100 20.3.11 GA Buffer RAM 1 Data Alig nment Register (DID_CTL) DID_CTL is i n the GDTA co mmon register block and specifies data alignment of the data st ored in buffer RAM 1.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 90 of 1658 REJ09B0261-0100 20.3.12 CL Command FIFO (CLCF) CLCF is in the CL register block and receives co mma nds. This register uses the FIFO method and recognizes four command parameters according to the writin g order.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 91 of 1658 REJ09B0261-0100 2. Setting Method When Setting Values in Succession When setting values in this register in succe ssion, the CL module is able to receive the next command while the CL_CFF bit in CLSR is 0.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 92 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1 CL_OA 0 R/W Specifi es output address mode 0: Ou.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 93 of 1658 REJ09B0261-0100 20.3.14 CL Status Re gister (CLSR) CLSR is in t he CL regi ster block an d i ndicates the i nternal states of the CL.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 94 of 1658 REJ09B0261-0100 20.3.15 CL Frame Width Settin g Register (CLWR) CLWR is in the CL regi ster block a nd sets the in put image wi dth in pi xel units.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 95 of 1658 REJ09B0261-0100 20.3.16 CL Frame Height Settin g Register (CLHR) CLHR is in the CL register block and sets the input image heigh t in line units.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 96 of 1658 REJ09B0261-0100 20.3.17 CL Input Y P adding Size Setting Regis ter (CLIYPR) CLIYPR is in the CL re gister bloc k and sets t he input Y pa dding size in byte uni ts.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 97 of 1658 REJ09B0261-0100 20.3.18 CL Input UV Padding Size Setting Re gister (CLIUVPR) CLIUVPR is in the CL register bloc k and sets the input U V padding size in byte units.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 98 of 1658 REJ09B0261-0100 20.3.19 CL Output Padding Size Setting Re gister (CLOPR) CLOPR is i n the CL regi ster block a n d sets the o utput paddin g size in byt e units.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 99 of 1658 REJ09B0261-0100 20.3.20 CL Palette Pointer Register (CLPLPR) CLPLPR is in the CL register block and sets the color conversion table pointer. Th e RAM 0 address used for a work area shoul d be specified.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 000 of 1658 REJ09B0261-0100 20.3.21 MC Command FIFO (MCCF) MCCF is in the MC register block a nd receives commands. This register uses the FIFO method and recognizes a maximum of eight comman d parameters a ccording to the writing or der.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 001 of 1658 REJ09B0261-0100 Writing Order Intra Macroblock Processing Forward Macroblock Processing Reverse Macroblock P.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 002 of 1658 REJ09B0261-0100 ⎯ Bit 26: In dicates whether or not the V IDCT data exists (0: I DCT data is i nvalid, 1: .
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 003 of 1658 REJ09B0261-0100 20.3.22 MC Status Register (MCSR) MCSR is in t he MC regi ster block a nd in dicates the internal states of the MC.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 004 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 2 to 0 MC_CFS All 0 R Command pointer status dis.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 005 of 1658 REJ09B0261-0100 20.3.24 MC Frame Hei ght Setting Regi ster (MCHR ) MCHR is in t he MC register block a n d sets t he input imag e height in l ine units.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 006 of 1658 REJ09B0261-0100 20.3.25 MC Y Padding Size Setting Register (MCYPR) MCYPR is in the MC register block and set s the input Y padding si ze in byte unit s.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 007 of 1658 REJ09B0261-0100 20.3.26 MC UV Padding Size Setti ng Regis t er (MCUVPR) MCUVPR is i n the MC regi ster block and sets the in put UV paddin g size in byte units.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 008 of 1658 REJ09B0261-0100 20.3.27 MC Outpu t Frame Y Poin ter Register (MCOYPR) MCOYPR is i n the MC re gister block and specifies t he Y poi nter address f or an outp ut frame.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 009 of 1658 REJ09B0261-0100 20.3.29 MC Outpu t Frame V Poin ter Register (MCOVPR) MCOVPR is i n the MC re gister block and specifies t he V poi nter address f or an outp ut frame.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 010 of 1658 REJ09B0261-0100 20.3.31 MC Past Frame U Pointer Register (MCPUPR) MCPUPR is i n the MC regist er block and speci fies the U pointer address fo r a past frame.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 011 of 1658 REJ09B0261-0100 20.3.33 MC Future Frame Y P ointer Register (MCFYPR) MCFYPR is i n the MC regist er block and specifi es the Y pointer addre ss for a future frame.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 012 of 1658 REJ09B0261-0100 20.3.35 MC Future Frame V P ointer Register (MCFVPR) MCFVPR is i n the MC regist er block and specifi es the V pointer addre ss for a future frame.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 013 of 1658 REJ09B0261-0100 20.4 GDTA Operation 20.4.1 Explanation of CL Operation By writing 1 to the CL_EN bit in GACER, re gisters in the CL register unit can be accessed.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 014 of 1658 REJ09B0261-0100 Table 20.7 shows YU YV4:2:2 conv ersion sequen ce shown in figur e 20.3. No. in the table corresponds to th e number used in figure 20.3. Table 20.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 015 of 1658 REJ09B0261-0100 (2) Overview of ARGB Conver sion Functions The following shows an outlin e of the ARGB conversion specification.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 016 of 1658 REJ09B0261-0100 Table 20.8 shows ARGB 8888 conversion sequence sh own in figure 20 .4. No. in the table corres ponds to the n umber used i n figure 20.4. (1) and (2) corresp ond to the numbers in figure 20.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 017 of 1658 REJ09B0261-0100 No. Operation Description (4) ARGB conversion ARGB data is generated from color information read from buffer RAM 0 using the following formula, and the conv erted data is output in the format shown in the display image of figure 20.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 018 of 1658 REJ09B0261-0100 [Step (1) Clear the CL access mask] After the CPU sets the key code in GACMR within the bus interface, set GACER to enable access to the CL function block.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 019 of 1658 REJ09B0261-0100 20.4.2 Explanation of MC Operation By writing 1 to the MC_EN bit in GACER, registers in the MC register unit can be accessed.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 020 of 1658 REJ09B0261-0100 (1) Estimated Im age Generation Fu nction The following shows an outlin e of the estimated image generation function .
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 021 of 1658 REJ09B0261-0100 Table 20.9 shows estimated image generation sequ ence shown in figure 20.6. No. in the table corresponds to th e number used in figure 20.6 . Table 20.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 022 of 1658 REJ09B0261-0100 No. Operation Description (2) Calculation of output position (nth row and below) The following formulae are used to co mpute output positions (nth row and below) (DDR2-SDRAM output address).
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 023 of 1658 REJ09B0261-0100 No. Operation Description (3) Calculation of input position (first row) The following formulae are used to comput e input position (first row) (DDR2- SDRAM input address).
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 024 of 1658 REJ09B0261-0100 No. Operation Description (3) Calculation of input position (first row) • U/V input compar.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 025 of 1658 REJ09B0261-0100 No. Operation Description (4) Calculation of input position (nth row and below) The following formulae are used to compute input positions (nth row and below) (DDR2-SDRAM input addr ess).
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 026 of 1658 REJ09B0261-0100 No. Operation Description (6) Half-pixel correction processing Half-pixel correction processing is performe d for the data read in (5).
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 027 of 1658 REJ09B0261-0100 No. Operation Description (7) IDCT data reading IDCT data stored in buffer RAM 1 is read. (Only blocks specified by a CBP setting of 1 are read from buffer RAM 1.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 028 of 1658 REJ09B0261-0100 Start End Is an interrupt used to recognize processing completion ? Continuous processing ? .
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 029 of 1658 REJ09B0261-0100 20.5 Interrupt Processing In the GDTA, there are four type s of interrupt source s. There ar e three interrupt flags for C L processing end, MC processing end, an d CL/MC errors, use d to identify interrupt sources.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 030 of 1658 REJ09B0261-0100 D0 D1 D2 D3 D4 D5 D6 D7 D4 D5 D6 D7 D0 D1 D2 D3 D7 D6 D5 D4 D3 D2 D1 D0 D0 D1 D2 D3 D4 D5 D6.
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 031 of 1658 REJ09B0261-0100 20.7 Usage Notes When using the GDTA, note the following: 20.7.1 Regarding Module Stoppage During GDTA operation, t he CPG register setti ngs must not be done to sto p a module (ot h er modules as well as the GDT A).
20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 032 of 1658 REJ09B0261-0100 20.7.3 Regarding Frequenc y Changes During GDTA operatio n, the CPG register set ting must not be used t o change frequency .
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 033 of 1658 REJ09B0261-0100 Section 21 Serial Communi cation Interface with FIFO (SCIF) This LSI is equipped with a 6-ch annel serial communication inte rface with built-i n FIFO buffers (Serial Communication Interface with FIFO: SCIF).
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 034 of 1658 REJ09B0261-0100 • Full-duplex communication cap ability The transmitter and receiver are independent units, e nabling transmission and reception to be performed sim ultaneously.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 035 of 1658 REJ09B0261-0100 Figure 21.1 show s a block diagra m of the SCIF. Figures 21. 2 to 21.6 show bloc k diagrams of the I/O ports in the SCIF . There are six cha nnels in this LSI.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 036 of 1658 REJ09B0261-0100 SPTRW D7 D6 R Q D RTSIO C SPTRR SPTRW R Q D RTSDT C SCIF0_RTS Reset Reset Peripheral bus .
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 037 of 1658 REJ09B0261-0100 SPTRW D5 D4 R Q D CTSIO C SPTRR SPTRW R Q D CTSDT C SCIF0_CTS Le g end: SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Note: * The SCIF0_CTS pin function is desi g nated as modem control by the MCE bit in SCFCR.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 038 of 1658 REJ09B0261-0100 SPTRW D3 D2 R Q D SCKIO C SPTRR SPTRW R Q D SCKDT C Clock output enab le si g nal * Seria.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 039 of 1658 REJ09B0261-0100 SPTRR Le g end: SPTRR: Read from SCSPTR SCIFn_RXD Peripheral bus Serial receive data Figure 21.6 SCIFn_RXD Pin (n = 0 to 5) 21.2 Input/Output Pins Table 21.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 040 of 1658 REJ09B0261-0100 21.3 Register Descriptions The SCIF has t he following registers. Si nce the register functions a re the same in eac h channel, the channel number is omitted in th e description below.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 041 of 1658 REJ09B0261-0100 Ch. Register Name Abbrev. R/ W P4 Address Area 7 Address Size Sync Clock 2 Serial mode re.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 042 of 1658 REJ09B0261-0100 Ch. Register Name Abbrev. R/ W P4 Address Area 7 Address Size Sync Clock 4 Serial mode re.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 043 of 1658 REJ09B0261-0100 Table 21.2 Register Configuration (2) Ch.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 044 of 1658 REJ09B0261-0100 Ch. Register Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/M u.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 045 of 1658 REJ09B0261-0100 Ch. Register Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mul.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 046 of 1658 REJ09B0261-0100 21.3.1 Receive Shift Register (SCRSR) SCRSR is the register used to receive se rial data.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 047 of 1658 REJ09B0261-0100 21.3.3 Transmit Shift Register (SCTSR) SCTSR is a register used to transmit serial data.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 048 of 1658 REJ09B0261-0100 21.3.5 Serial Mode Register (SCSMR) SCSMR is a 16-bit register used to set the SCIF's serial communication format and select the baud rate generator cl ock source.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 049 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 PE 0 R/W Parity Enable In asynchronous mode, selects whether or n ot parity bit addition is performed in transmission, and p arity bit checking is performed in reception.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 050 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 STOP 0 R/W Stop Bit Length In asynchronous mode, selects 1 or 2 bits as the stop bit length. The stop bit se tting is valid only in asynchronous mode.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 051 of 1658 REJ09B0261-0100 21.3.6 Serial Control Register (SCSCR) SCSCR is a register used to enable/disable tran smission/reception by SCIF, serial clock output, interrupt requests, and t o select transmission/reception cloc k source for the SCIF.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 052 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 RIE 0 R/W Receive Interrupt Enable * 1 Enabl.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 053 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 4 RE 0 R/W Receiv e Ena ble Enables or disables the start of serial recepti on by the SCIF.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 054 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1 0 CKE1 CKE0 0 0 R/W R/W Clock Enable 1, 0 These bits select the SCIF clock source and whether to enable or disable the clock output from the SCIF_SCK pin.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 055 of 1658 REJ09B0261-0100 21.3.7 Serial Status Register n (SCFSR) SCFSR is a 16-bit register that consists of stat us flags that indicate th e opera ting status o f the SCIF.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 056 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 ER 0 R/W * 1 Receiv e Error Indicates that a framing error or parity error occurred during reception.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 057 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 TDFE 1 R/W * 1 Transmit FIFO Data Empty Indi.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 058 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 FER 0 R Framing Error Display In asynchronous mode, indicates whether o r not a framing error has been found in the data that is to be read from SCFRDR.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 059 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1 RDF 0 R/W * 1 Receive FIFO Data Full Indicat.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 060 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 DR 0 R/W * 1 Receive Data Ready In asynchron.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 061 of 1658 REJ09B0261-0100 21.3.8 Bit Rate Regis t er n (SCB RR) SCBRR is an 8-bit register tha t sets the serial transmission/reception bit rate in accorda nce with the baud rate g enerator operat ing clock selec t ed by the CKS1 and CKS0 bits in SCSMR.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 062 of 1658 REJ09B0261-0100 21.3.9 FIFO Control Register n (SCF CR) SCFCR is a register that performs data count resetting and trigger data number setting for transmit and receive FIFO registers, a nd also contains a loopback test enable bit.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 063 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 4 TTRG1 TTRG0 0 0 R/W R/W Transmit FIFO Data Count Trigger These bits are used to set the number of remaining transmit data bytes that sets the TDFE flag in SCFSR.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 064 of 1658 REJ09B0261-0100 21.3.10 Transmit FIFO Data Count Register n (SCTFDR) SCTFDR is a 16-bit register t hat indicates the nu mber of transmit data bytes stored in SCFTDR.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 065 of 1658 REJ09B0261-0100 21.3.11 Receive FIFO Data Coun t Register n (SCRFDR) SCRFDR is a 16-bit register that indicates t he number of receive data bytes stored in SCFRDR.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 066 of 1658 REJ09B0261-0100 21.3.12 Serial Port Regi ster n (SCSPTR) SCSPTR is a 1 6-bit readable/ writable regi ster that co ntrols input/ output and dat a for the port pins multiplexed with th e serial communication interface (SCIF) pins at all time s.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 067 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 RTSDT * — R/W Serial Port SCIF_RTS Port Data Specifies the serial port SCIF_RTS pin input/output data.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 068 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 SCKDT — R/W Serial Port Clock Port Data Specifies the serial port SCIF_SCK pin input/output data.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 069 of 1658 REJ09B0261-0100 21.3.13 Line Status Register n (SCLSR) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 .
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 070 of 1658 REJ09B0261-0100 21.3.14 Serial Error Register n (SCRER) SCRER is a 16-bit register tha t indicates the numb er of rece ive errors in the data in SCFRDR. SCRER can always be read from t h e CPU.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 071 of 1658 REJ09B0261-0100 21.4 Operation 21.4.1 Overview The SCIF can perform serial communication i n asynchro nou.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 072 of 1658 REJ09B0261-0100 Clocked Synchron ous Mode • Data length: Fixed at 8 bits • LSB first for data transmi.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 073 of 1658 REJ09B0261-0100 Table 21. 5 SCSMR and S CSCR Sett ings for SCIF Clock Source Selectio n SCSMR SCSCR Setti.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 074 of 1658 REJ09B0261-0100 21.4.2 Operation in Asynchronous Mode In asynchronous mode, a character that consists of data wit h a start bit in dicating the st art of communication a nd a stop bit indicating the end of communication is transm itted or r eceived.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 075 of 1658 REJ09B0261-0100 (1) Data Transfer Format Table 21.6 shows the data transfe r formats that can be u sed. Any of 8 tr ansfer formats can be selected according to the SCSMR settings.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 076 of 1658 REJ09B0261-0100 (2) Clock Either an inte rnal clock generated b y the on-c hip baud rat e generator or an.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 077 of 1658 REJ09B0261-0100 Figure 21.8 shows a sample SCIF initialization flowch art.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 078 of 1658 REJ09B0261-0100 (4) Serial Da ta Transmissi on (Asynchron ous Mode) Figure 21.9 s hows a sample flow chart for se rial transmission. Use the following procedure for serial data transmi ssion af ter enab ling the SCI F for transmis sion.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 079 of 1658 REJ09B0261-0100 In serial transmission, the SCIF operates a s follows. 1. Wh en data is written to SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmission.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 080 of 1658 REJ09B0261-0100 Figure 21.10 s h ows an exa mple of the operation for transmission in asynch ronous mode.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 081 of 1658 REJ09B0261-0100 (5) Serial Data Reception (Asynchronous Mode) Figure 21.12 shows a sample flowchart fo r serial reception. Use the following procedure for serial data recep tion after enabling th e SCIF for reception.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 082 of 1658 REJ09B0261-0100 Error handlin g Receive error handlin g ER = 1? BRK = 1? Break handlin g DR = 1? Read rec.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 083 of 1658 REJ09B0261-0100 In serial reception, the SCIF operates as follows. 1. Th e SCIF monitors the transmission line, an d if a 0-start bit is detected, performs internal synchronization and starts receptio n.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 084 of 1658 REJ09B0261-0100 5. When modem cont rol is ena bled, the SCIF_RTS signal is output when SCFRDR is empt y.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 085 of 1658 REJ09B0261-0100 21.4.3 Operation in Clocked Sync hronous Mode Clocked synchronous mode, in which data is transmitted or receive d in synchron ization with clock pulses, is suitable for fast serial communication.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 086 of 1658 REJ09B0261-0100 (1) Data Transfer Format A fixed 8-bit data format is us ed.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 087 of 1658 REJ09B0261-0100 Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFCL and RFCL bits in SCFC.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 088 of 1658 REJ09B0261-0100 (4) Serial Da ta Transmissi on (Clocked Sync hronous Mode) Figure 21.17 sh ows a sample flowchart fo r serial transmission. Use the follow ing proced ure for serial data transmissi on after e nabling the SCIF for tra nsmission.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 089 of 1658 REJ09B0261-0100 In serial transmission, the SCIF operates a s follows. 1. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmitting.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 090 of 1658 REJ09B0261-0100 (5) Serial Data Reception (C locked Synchronous Mode ) Figure 21.19 shows a sample flowchart fo r serial reception. Use the following procedure for serial data r eception after enabling th e SCIF for reception.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 091 of 1658 REJ09B0261-0100 Error handlin g Clear ORER fla g in SCLSR to 0 End Overrun error handlin g ORER = 1? Yes No Figure 21.19 Sample Serial Reception Flowchart (2) In serial reception, the SCIF operates as follows.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 092 of 1658 REJ09B0261-0100 Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RXI interrupt request One frame Data read from .
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 093 of 1658 REJ09B0261-0100 (6) Transmitting and Receiving Serial Data Si multaneously (Clocked Synchronous Mode) Figure 21.21 shows a sa mple flowchart for tr ansmitting and receiving data simultaneousl y.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 094 of 1658 REJ09B0261-0100 21.5 SCIF Interrupt Sources and the DMAC The SCIF has four i nterrupt sources for each ch.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 095 of 1658 REJ09B0261-0100 Table 21.7 SCIF Interrupt Sources Interrupt Source Description DMAC Activation Priority o.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 096 of 1658 REJ09B0261-0100 21.6 Usage Notes Note the following when using the SCIF.
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 097 of 1658 REJ09B0261-0100 (4) Sending a Break Signal The input/o utput condit ion and le vel of the SCIF_TXD pin are dete rmined by bits SPB2IO a nd SPB2DT in SCSPTR .
21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 098 of 1658 REJ09B0261-0100 Thus, the reception margin i n asynchrono us mode is given by formula (1). 1 | D - 0.5 | M= (0.5 - 2N ) - (L - 0.5) F - N (1 + F) × 100 % .
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 099 of 1658 REJ09B0261-0100 Section 22 Serial I/O with FIFO (SIOF) This LSI is eq uipped wi th a clock-sync hronized serial I/O mo dule with F IFO (SIOF).
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 100 of 1658 REJ09B0261-0100 Figure 22.1 show s a block diagra m of the SIOF. P/S Transmit FIFO (32 bits × 16 sta g es) Pck 1/nMCLK SIOF_M.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 101 of 1658 REJ09B0261-0100 22.2 Input/Output Pins Table 22.1 sho ws the pin co nfiguration.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 102 of 1658 REJ09B0261-0100 22.3 Register Descriptions Table 22.2 sho ws the register configuration of th e SIOF.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 103 of 1658 REJ09B0261-0100 Table 22.3 Register States in Eac h Operating Mode Name Abbreviation Power-On Reset Manual Reset Module Standb.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 104 of 1658 REJ09B0261-0100 22.3.1 Mode Re gister (S IMDR) SIMDR is a 16-bit readable/writable regist er that sets the SIOF operating mode.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 105 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 TXDIZ 0 R/W SIOF_TXD Pin Output when Transmission is Invalid * 0:.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 106 of 1658 REJ09B0261-0100 22.3.2 Control Regis ter (SICTR) SICTR is a 16-bit readable/writab le register that sets the SIOF operating state.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 107 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 RXE 0 R/W Receive Enable 0: Disables data reception from SIOF_RXD.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 108 of 1658 REJ09B0261-0100 22.3.3 Transmit Dat a Register (SITDR) SITDR is a 32-bit write-only register that specifies SIO F transmit data.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 109 of 1658 REJ09B0261-0100 22.3.4 Receive Data Register (SIRDR) SIRDR is a 32-bit read-onl y register that reads recei ve data of the SIOF.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 110 of 1658 REJ09B0261-0100 22.3.5 Transmit Control Data Register (SITCR) SITCR is a 32-bit readable/writab le register that specifies transmit control data of the SIOF. The setting of SITCR is valid only w hen bits FL3 to FL0 in SIMDR are set to 1x xx (x: any value).
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 111 of 1658 REJ09B0261-0100 22.3.6 Receive Control Data Register (SIRCR) SIRCR is a 32-bit readable/writable register that stores receive c ontrol data of the SIOF. The setting of SIRCR is valid only wh en bits FL3 to FL0 in SIMDR are set to 1xxx (x: any value).
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 112 of 1658 REJ09B0261-0100 22.3.7 Status Regis ter (SISTR) SISTR is a 16-bit readable/writable register that indi cates the SIOF state. Each bit in this register becomes an SIOF interrupt sour ce when the corresponding bit in SIIER is set to 1.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 113 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 12 TDREQ 0 R Transmit Data Transfer Request 0: Indicates that the size of empty space in the transmit FIFO does not exceed the size specified by the TFWM bit in SIFCTR.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 114 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 9 RFFUL 0 R Receiv e FIFO Full 0: Receive FIFO not full 1: Receive FIFO full • This bit is valid when the RXE bit in SICTR is 1.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 115 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 SAERR 0 R/W Slot Assign Err or 0: Indicates that no slot assign error occurs 1: Indicates that a slot assign error occurs A slot assign error occurs when the settings in SITDAR, SIRDAR, and SICDAR overlap.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 116 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 TFOVF 0 R/W Transmit FIFO Overflow 0: Indicates that no transmit .
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 117 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1 RFUDF 0 R/W Receiv e FIFO Underflow 0: Indicates that no receive .
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 118 of 1658 REJ09B0261-0100 22.3.8 Interrupt Enable Register (SIIER) SIIER is a 16-bit readable/writable register th at enables the issuance of SIOF interrupts. When each bit in this register is set to 1 a nd the corresponding bit in SIST R is set to 1, the SIOF issues an interrupt .
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 119 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 10 RCRDYE 0 R/W Receive Control Data R eady Enable 0: Disables inte.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 120 of 1658 REJ09B0261-0100 22.3.9 FIFO Control Register (SIF CTR) SIFCTR is a 16-bit readable/writable regist er that indicates the area available for the transmit/receive FIFO transfer.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 121 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 to 5 RFWM[2:0] 000 R/W Receive FIFO Watermark 000: Issue a transfer request when 1 stage or more of the receive FIFO are valid.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 122 of 1658 REJ09B0261-0100 22.3.10 Clock Select Register (SISCR) SISCR is a 16-bit readable/writable register th at se ts the seri al clock generation condi tions for t he master clock. SCSCR can be specified when th e TRMD1 and TRMD0 bits in SIMDR are set to B'10 or B'11.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 123 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 BRDV[2:0] 000 R/W Baud Rate Generator's Division Ratio Settin g These bits set the frequency division ratio for the output stage of the baud rate generator.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 124 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 to 8 TDLA[3:0] 0000 R/W Transmit Left-Chan nel Data Assigns 3 to 0 These bits specify the positio n of left-channel data in a transmit frame as B'0000 (0) to B'1110 (14).
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 125 of 1658 REJ09B0261-0100 22.3.12 Receive Data Assign Register (SIRDAR) SIRDAR is a 16-bit readable/writabl e register that specifies the po sition of the receive data in a frame.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 126 of 1658 REJ09B0261-0100 22.3.13 Control Data Assign Regist er (SICDAR) SICDAR is a 16-bit readable/writable register that sp ecifies the position of the control data in a frame. SICDAR can be specified only when the FL bits in SIMDR ar e set to 1xxx (x: don 't care.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 127 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 to 0 CD1A[3:0] 0000 R/W Control Cha nnel 1 Data Assigns 3 to 0 These bits specify the positio n of control channel 1 dat a in a receive or transmit frame as B'0000 (0) to B'1110 (14).
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 128 of 1658 REJ09B0261-0100 22.4 Operation 22.4.1 Serial Clocks (1) Master/Slave Modes The following two modes are ava ilable as the SIOF clock mode.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 129 of 1658 REJ09B0261-0100 Table 22.5 sho ws an example of serial clock frequency . Table 22.5 SIOF Serial Clock Frequency Sampling Rate * Frame Length 8 kHz 44.1 kHz 48 kHz 32 bits 256 kHz 1.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 130 of 1658 REJ09B0261-0100 SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC 1-bit delay Start bit data 1 frame SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC Lch. Start bit of left channel data (1/2 frame len g th) 1 frame No delay Rch.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 131 of 1658 REJ09B0261-0100 SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD (a) Fallin g -ed g e samplin g (REDG = 0) SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD (b) Risin g -ed g e samplin g (REDG = 1) Receive timin g Transmit timin g Receive timin g Transmit timin g Figure 22.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 132 of 1658 REJ09B0261-0100 (2) Frame Length The frame leng th to be trans ferred by the SIOF is specified by the FL3 t o FL0 bits in SIMDR. Table 22.7 sho ws the relation ship between t he setting valu es and frame le ngth.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 133 of 1658 REJ09B0261-0100 22.4.4 Register Alloc ation of Trans fer Data (1) Transmit/Receive Data Writing and reading of transmit/receive dat a is performed for the following registers.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 134 of 1658 REJ09B0261-0100 Table 22.8 Audio Mode Specifi cation for Transmit Data Bit Mode TDLE TDRE TLREP Monaural 1 0 x Stereo 1 1 0 Left and right same audio output 1 1 1 Legend: x: Don't care Table 22.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 135 of 1658 REJ09B0261-0100 The number of channels in c ontrol data is specified by the CD0E an d CD1E bit s in SICDAR . Table 22.10 s hows the rel ationshi p between t he number of channels in c ontrol data and bit settings.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 136 of 1658 REJ09B0261-0100 (2) Control by Se condary FS (Slave Mode 2) The CODEC norm ally output s the SIOF_SYNC signal as synchronization pulse (FS).
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 137 of 1658 REJ09B0261-0100 22.4.6 FIFO (1) Overview The transmit and receive FIFO systems of the SIOF have t he following features.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 138 of 1658 REJ09B0261-0100 Table 22.12 Conditions to Issue Receive Request RFWM2 to RFWM0 Number of Requested Stages * Receive Requ est U.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 139 of 1658 REJ09B0261-0100 22.4.7 Transmit and Receive Procedures Set each register after setting the PFC. (1) Transmission in Master Mode Figure 22.9 shows an examp le of settings and operation for master mode transmission.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 140 of 1658 REJ09B0261-0100 (2) Reception in Master Mode Figure 22.10 sh ows an example of settings and op eration for master mode r eception.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 141 of 1658 REJ09B0261-0100 (3) Transmission in Slave Mode Figure 22.11 shows an examp le of settings and operation for slave mode transmission . Start End Set the TXE bit in SICTR to 1 Set SITDR Clear the TXE bit in SICTR to 0 TDREQ = 1 Transfer ended? No Yes No Yes No.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 142 of 1658 REJ09B0261-0100 (4) Reception in Slave Mode Figure 22.12 shows an exampl e of settings and ope ratio n for slave mode reception. Start End Set the RXE bit in SICTR to 1 Read SIRDR Clear the RXE bit in SICTR to 0 RDREQ = 1 Transfer ended? No Yes No Yes No.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 143 of 1658 REJ09B0261-0100 (5) Transmit/Receive Re set The SIOF can separately rese t the transmit and recei ve units by setting the following bits to 1. • Transmit reset: TXRST bit in SICTR • Receive reset: RXRST bit in SICTR Table 22.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 144 of 1658 REJ09B0261-0100 22.4.8 Interrupts The SIOF has one ty pe of interrupt. (1) Interrupt Sources Interrupts ca n be issued b y several so urces. Each source is shown as an SIOF st atus in SISTR.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 145 of 1658 REJ09B0261-0100 (2) Regarding Transmi t and Receive Classificati on The tran smit sourc es and rece ive sources are signals indicating the state; after being set, if the state changes, they are automati cally cleared by the SIOF.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 146 of 1658 REJ09B0261-0100 22.4.9 Transmit and Receive Timing Figures 22.13 to 22.19 show examples of th e SIOF serial transm ission and reception. (1) 8-bit Monaural Data (1) Synchronous pulse method, falling edge sampling, slot No.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 147 of 1658 REJ09B0261-0100 (2) 8-bit Monaural Data (2) Synchronous pulse method, falling ed ge sampling, slot No.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 148 of 1658 REJ09B0261-0100 (4) 16-bit Stereo Data (1) L/R method, ri sing edge sam pling, slot N o.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 149 of 1658 REJ09B0261-0100 (6) 16-bit Stereo Data (3) Synchronous pulse method, fa lling edge sam p ling, sl ot No.0 used f or left-channel data, slot No.1 used for ri ght-channel data, slot No.
22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1 150 of 1658 REJ09B0261-0100 (8) Synchronization-Pulse Outp ut Mode at End of Each Slot (SYNCAT Bit = 1) Synchronous pulse method, fa lling edge sam p ling, sl ot No.0 used f or left-channel data, slot No.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 151 of 1658 REJ09B0261-0100 Section 23 Serial Peripheral Interface (HSPI) This LSI incorporates one channel of the Serial Protocol Interface (HSPI). 23.1 Features The HSPI has the following features.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 152 of 1658 REJ09B0261-0100 Figure 23.1 is a block di agram of the HSPI. HSPI_CLK HSPI_TX HSPI_RX LSB MSB SPCR HSPI_CS SPSR SPSCR S.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 153 of 1658 REJ09B0261-0100 23.2 Input/Output Pins The input/output pins of the HS PI is shown in table 23.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 154 of 1658 REJ09B0261-0100 Table 23.3 Register Configuration (2) Register Name Abbrev.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 155 of 1658 REJ09B0261-0100 23.3.1 Control Register (SPCR) SPCR is a 32-bit readable/writable register th at c ontrols t he transfer dat a of shift ti ming and specifies the clock polarity and fre quency.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 156 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 IDIV 0 R/W Initial Cl ock Division Ratio 0: The peripheral.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 157 of 1658 REJ09B0261-0100 The serial cloc k frequency can be c omputed using the fol lowing fo rmula: Peripheral clock frequency .
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 158 of 1658 REJ09B0261-0100 23.3.2 Status Regis ter (SPSR) SPSR is a 32-bit readable/writable register. T hroug h the status flags in SPSR, it can be confirmed whether or not the system is correctly operating.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 159 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 TXEM 1 R Transmit FIFO Empty Flag This status flag is enabled only in FIFO mode. The flag is set to 1 when the transmit FIFO is empty of data to transmit.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 160 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 RXOW 0 R/W * Receiv e Buffer Overrun Warning Flag This status flag is set to 1 when a new serial data transfer has started before th e previous received data is read from SPRBR.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 161 of 1658 REJ09B0261-0100 23.3.3 System Control Re gister (SPSCR) SPSCR is a 3 2-bit readabl e/writable re gister that enables or disabl es interrupt s or FIFO m ode, selects either LSB first or MSB first in transm itting/receiving data, and master or sla v e mode.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 162 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 FFEN 0 R/W FIFO Mode Enable Enables or disables the FIFO mode. When FIFO mode is enabled, two 8-entry FIFOs are made available, one for transmit data and one for receive data.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 163 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 RXDE 0 R/W Receive DMA Enab le 0: Receive DMA transfer req.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 164 of 1658 REJ09B0261-0100 23.3.5 Receive Buffer Re gister (SPRBR) SPRBR is a 32-bit read-only regist er that stores received da ta.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 165 of 1658 REJ09B0261-0100 23.4 Operation 23.4.1 Operation Overview with FIFO Mode Disabled Figure 23.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 166 of 1658 REJ09B0261-0100 The HSPI_CS pin should be used to select the HSPI modu le and pre p are it to receive data from an external master when th e HSPI is configured as a slave.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 167 of 1658 REJ09B0261-0100 23.4.3 Timing Di agrams The followin g diagrams expl ain the timing relationshi p of all shift and sample p rocesses in the HSPI. Figure 23.3 shows the conditions wh en FBS = 0, figure 23.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 168 of 1658 REJ09B0261-0100 Data transfer cycle HSPI_CLK (CLKP = 0) HSPI_CLK (CLKP = 1) 1 4 3 2 8 7 6 5 MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB * HSPI_TX HSPI_RX HSPI_CX Figure 23.5 Timing Conditions when FBS = 1 HSPI_CLK (CLKP = 0) HSPI_CLK (CLKP = 1) 1 8 .
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 169 of 1658 REJ09B0261-0100 23.4.4 HSPI Software Reset If any of the contr ol bits, exce pt for SPCR and the interrupt and chip select value bits of SPSCR, are changed, then the HSPI software reset is gene rated.
23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1 170 of 1658 REJ09B0261-0100 23.4.7 Flags and Interrupt Timing The interrupt timing when th e flags of the status register (SPSR) and the system control register (SPSCR) are s et is shown in figu re 23.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 171 of 1658 REJ09B0261-0100 Section 24 Multimedia Card Interface (MMCIF) This LSI supports a multimedia card interfa ce (MMCIF).
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 172 of 1658 REJ09B0261-0100 Figure 24.1 show s a block diagra m of the MMCIF. MMCDAT MMCCMD MMCCLK MMCIF FIFO F S TAT TRAN ERR FRD Y.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 173 of 1658 REJ09B0261-0100 24.3 Register Descriptions Table 24.2 sho ws the MMCIF re gister configuration.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 174 of 1658 REJ09B0261-0100 Register Name Abbrev. R/W P4 Address Area 7 Address Size Sync Clock Response register 5 RSPR5 R/W H&apos.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 175 of 1658 REJ09B0261-0100 Table 24.3 Register Configuration (2) Register Name Abbrev.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 176 of 1658 REJ09B0261-0100 Register Name Abbrev. Power-on Reset by PRESET Pin/WDT/ H-UDI Manual Reset by WDT/ Multiple Exception Sl.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 177 of 1658 REJ09B0261-0100 24.3.1 Command Registers 0 to 5 (CMDR0 to CMD R5) The CMDR registers are six 8-bit registers. A command is written to CMDR as shown in table 24.4, and the command is tran smitted when the CMDSTART bit in CMDSTRT is set to 1.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 178 of 1658 REJ09B0261-0100 (2) CMDR5 Bit: Initial value: R/W: 7654321 0 00000000 R CRC End RR R R RR R Bit Bit Name Initial Value R/W Description 7 to 1 CRC All 0 R These bits are alwa ys read as 0.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 179 of 1658 REJ09B0261-0100 Bit: Initial value: R/W: 7654321 0 00000000 R CMD START RRRRRR R / W ⎯⎯⎯ ⎯⎯⎯ ⎯ Bit Bit Name Initial Value R/W Description 7 to 1 — All 0 R Reserved These bits are always read as 0.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 180 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 — 0 R Reserved This bit is always read as 0.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 181 of 1658 REJ09B0261-0100 In write data transmission, the contents of th e command response and data response should b e analyzed, and t hen transmission shoul d be tri ggered.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 182 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 FIFO_EMPTY 0 R FIFO Empty This bit is set to 1 when the FIFO becomes empty while data is being sent to the card, and cle ared to 0 when DATA_EN is set to 1 or the command sequence is completed.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 183 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 REQ 0 R Interrupt Request Indicates whether an interrupt is requested or not. When any of the INTSTR0, INTSTR1 and INTSTR2 flags is set, this bit is set to 1.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 184 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 4 DTIE 0 R/W Data Transfer End Interrupt Flag Setting Enable 0: Disables data transfer end interrupt (dis ables DTI flag setting).
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 185 of 1658 REJ09B0261-0100 (2) INTCR1 Bit: Initial value: R/W: 7654321 0 00000 0 00 R/W INTR Q2E INTR Q1E INTR Q0E CRCE RIE DTE RIE CTE RIE R/W R/W R R R/W R/W R/W ⎯ ⎯ Bit Bit Name Initial Value R/W Description 7 INTRQ2E 0 R/W ERR Interrupt Enable 0: Disables ERR interrupt.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 186 of 1658 REJ09B0261-0100 (3) INTCR2 Bit: Initial value: R/W: 7654321 0 00000 0 00 R/W FRDYIE R R R R R R R/W ⎯ ⎯⎯ ⎯ ⎯⎯ INTR Q3E Bit Bit Name Initial Value R/W Description 7 INTRQ3E 0 R/W FRDY Interrupt Enable 0: Disables FRDY interrupt.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 187 of 1658 REJ09B0261-0100 24.3.6 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2) The INTSTR r egisters enabl e or disable M MCIF interr upts FSTAT, TR AN, ERR and FRDY, a nd interrupt flags.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 188 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description Interrupt output 5 DRPI 0 R/W Data Res ponse Interrupt Flag 0: No interrupt [Clearing condition] Write 0 after reading DRPI = 1.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 189 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description Interrupt output 2 CMDI 0 R/W Command Transmit End Interrupt Flag 0: No interrupt [Clearing condition] Write 0 after reading CMDI = 1.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 190 of 1658 REJ09B0261-0100 (2) INTSTR1 Bit: Initial value: R/W: 7654321 0 00000 0 00 R CRC ERI DTERI CTERI R R R R R/W R/W R/W ⎯⎯ ⎯⎯⎯ Bit Bit Name Initial Value R/W Description Interrupt output 7 to 3 — All 0 R Reserve d These bits are always read as 0.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 191 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description Interrupt output 0 CTERI 0 R/W Command Timeout Error Interrupt Flag 0: No interrupt [Clearing condition] Write 0 after reading CTERI = 1.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 192 of 1658 REJ09B0261-0100 (3) INTSTR2 Bit: Initial value: R/W: 7654321 0 00000 0 0 R FRDY _TU FRDYI R R R R R R R/W —— ——— — — Bit Bit Name Initial Value R/W Description Interrupt output 7 to 2 ⎯ All 0 R Reserved These bits are always read as 0.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 193 of 1658 REJ09B0261-0100 24.3.7 Transfer Clock Control Re gister (CLKON) CLKON cont rols the t ransfer clock f requency a nd clock O N/OFF. At this time, use a sufficiently slow clo ck for transfer through open-d rain type output in MMC mode.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 194 of 1658 REJ09B0261-0100 24.3.8 Command Timeou t Control Register (CT OCR) CTOCR specifies the period to generate a ti meout for the command respon se.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 195 of 1658 REJ09B0261-0100 24.3.9 Transfer Byte Number Count Register (TBCR) TBCR is an 8-bit readable/writable reg ister that specifies the number of bytes to be transferred (block size) for each single bl ock transfer co mmand.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 196 of 1658 REJ09B0261-0100 24.3.10 Mode Register (MODER ) MODER is an 8-bit readabl e/writable register that specifies the MMCIF operating mode.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 197 of 1658 REJ09B0261-0100 24.3.11 Command Type Register (CMDTYR) CMDTYR is an 8-bit readab le/writable register that specifies the comman d fo rmat in con junction with RSPTYR.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 198 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 TY3 0 R/W Type 3 Set this bit to 1 when specifying stream transfer. Bits TY1 and TY0 should be set to 01 or 10.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 199 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 RTY6 0 R/W Response Type 5 Sets data busy status from the MMC card.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 200 of 1658 REJ09B0261-0100 Table 24.5 summarizes the correspondence between the comman ds described in the MultiMediaCard System Specificatio n Version 3.1 and the settin gs of the CMDTYR and RSPTYR regist ers.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 201 of 1658 REJ09B0261-0100 CMD CMDTYR RSPTYR INDEX Abbreviation resp 6 5 4 3 2 [1:0] 6 5 4 [2:0] CMD32 * 1 TAG_SECTOR_START R1 00 *.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 202 of 1658 REJ09B0261-0100 24.3.13 Transfer Block Number Counter (TBNCR) A value other than 0 must be written to the TBNCR register if a mu ltiple block transfer is selected through the TY 5 and TY6 bits in the CMDTYR.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 203 of 1658 REJ09B0261-0100 24.3.14 Response Regi sters 0 to 16, D (RSPR0 to RSPR 16, RSPRD) RSPR0 to RS PR16 are com mand resp onse registers, w hich are seve nteen 8-bit re gisters.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 204 of 1658 REJ09B0261-0100 (1) RSPR0 t o RSPR16 Bit: Initial value: R/W: 76543210 00000000 R/W RSPR R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 to 0 RSPR H'00 R/W These bits are clear ed to H'00 by writing an arbitrary value.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 205 of 1658 REJ09B0261-0100 24.3.15 Data Timeout Re gister (DTOUTR) DTOUTR specifies the period to generate a data timeout. The 16-bit counter (DTOUTC) and a prescaler, to which the peripheral bus does not have access, count the peri pheral clock to monitor the data time out.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 206 of 1658 REJ09B0261-0100 24.3.16 Data Register (D R) DR is a re gister for rea ding/writi ng FIFO dat a.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 207 of 1658 REJ09B0261-0100 H'01 1 word (2 bytes) 64 words H'23 H'45 .
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 208 of 1658 REJ09B0261-0100 24.3.18 DMA Control Register (DMACR ) DMACR sets DMA reque st signal output. D MAEN enable s or disables a DMA re quest signal. The DMA request signal is output based on a value th at has been set to SET2 to SET0.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 209 of 1658 REJ09B0261-0100 24.4 Operation The multimedia card is an extern al storage media that can be easily connected or disconnected . The MMCIF operates in MMC mode. Insert a card and suppl y power to it.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 210 of 1658 REJ09B0261-0100 (1) Operation of B roadcast Comman ds CMD0, CMD1, CMD2, and CMD4 are broadcas t commands. These commands a nd the CMD3 command compri se a sequenc e assigning relative addresses to individual cards.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 211 of 1658 REJ09B0261-0100 (3) Operation of Commands Not Requiring Command Response Some broadcast command s do not require a command response. Figure 24.3 s hows an exam ple of the command seque nce for co mmands that do not require a command response.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 212 of 1658 REJ09B0261-0100 Ye s Star t of command sequence Set command data in CMDR0 to CMDR4 Set command type in CMDTYR Set command response type in RSPTYR Set the CMDST ART bit in CMDSTRT to 1 (CMDI) interrupt detected? End of command sequence No Figure 24.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 213 of 1658 REJ09B0261-0100 • The command response is received from the card. If the card returns no command response, th e co mmand response is detected by the command timeout error (CTERI ).
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 214 of 1658 REJ09B0261-0100 MMCCLK MMCCMD MMCD A T CMDSTRT (CMDST ART) INTSTR0 (CMDI) CSTR (CWRE) (BUSY) (REQ) (CRPI) (DBSYI) (DTBUS.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 215 of 1658 REJ09B0261-0100 Star t of command sequence Set command data in CMDR0 to CMDR4 Set command type in CMDTYR Set command res.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 216 of 1658 REJ09B0261-0100 (5) Commands with Read Data Flash memory operation commands include a nu mber of commands involvin g read data.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 217 of 1658 REJ09B0261-0100 • The end of t he command sequence is detected by poling the BUSY flag in CSTR, by the data transfer end interrupt (DTI) or pre-defi ned multiple block transfer end (BTI).
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 218 of 1658 REJ09B0261-0100 MMCCLK MMCCMD MMCD A T CMDSTRT (CMDST ART) INTSTR0 (CMDI) (CMDOFF) CSTR (CWRE) (BUSY) (REQ) (CRPI) (DTI).
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 219 of 1658 REJ09B0261-0100 MMCCLK MMCCMD MMCD A T CMDSTRT (CMDST ART) INTSTR0 (CMDI) (CMDOFF) CSTR (CWRE) (BUSY) (REQ) (CRPI) (DTI).
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 220 of 1658 REJ09B0261-0100 CMD11 (READ_D A T_UNTIL_STOP) CMD12 (ST OP_TRANSMISSION) Input/output pins T ransfer clock transmission .
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 221 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Execute CMD16 Read response re g ister Execute CMD17 (Set CMDR then.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 222 of 1658 REJ09B0261-0100 Star t of command sequence Clear FIFO Execute CMD16 Read response re g ister Execute CMD18 (Set CMDR the.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 223 of 1658 REJ09B0261-0100 End of command sequence Ye s No FFI interrupt detected? Set CMDOFF to 1 Read data from FIFO Set RD_CONTI.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 224 of 1658 REJ09B0261-0100 Star t of command sequence Clear FIFO Execute CMD16 Read response re g ister Execute CMD18 (Set CMDR the.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 225 of 1658 REJ09B0261-0100 End of command sequence Ye s No FFI interrupt detected? Set CMDOFF to 1 Read data from FIFO Set RD_CONTI.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 226 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Read response re g ister Execute CMD11 (CMDR to CMDSTRT) No Ye s (C.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 227 of 1658 REJ09B0261-0100 (6) Commands with Write Data Flash memory ope ration commands include a n umber of comman ds involvin g write data.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 228 of 1658 REJ09B0261-0100 • The end of t he command sequence is detected by poling the BU SY flag in CSTR, data transfer end interrupt (DTI), dat a respon se interrupt (DRPI), o r pre-defi ned multipl e block trans f er end (BTI).
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 229 of 1658 REJ09B0261-0100 MMCCLK MMCCMD MMCD A T CMDSTRT (CMDST ART) (CMDI) CSTR (CWRE) (BUSY) (DTBUSY) (DTBUSY_TU) (REQ) (CRPI) (.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 230 of 1658 REJ09B0261-0100 MMCCLK MMCCMD MMCD A T CMDSTRT (CMDST ART) INTSTR0 (CMDI) (CMDOFF) CSTR (CWRE) (BUSY) (DTBUSY) (DTBUSY_T.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 231 of 1658 REJ09B0261-0100 MMCCLK MMCCMD MMCDA T CMDSTRT (CMDST AR T) INTSTR0 (CMDI) (CMDOFF) CSTR (CWRE) (BUSY) (DTBUSY) (DTBUSY_T.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 232 of 1658 REJ09B0261-0100 MMCCLK MMCCMD MMCD A T CMDSTRT (CMDST ART) INTSTR0 (CMDI) (CMDOFF) CSTR (CWRE) (BUSY) (DTBUSY) (DTBUSY_T.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 233 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Execute CMD16 Read response re g ister Execute CMD24 (Set CMDR then.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 234 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Execute CMD16 Read response re g ister Execute CMD25 (Set CMDR then.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 235 of 1658 REJ09B0261-0100 No End of command sequence Write data to FIFO Set DA T AEN to 1 Ye s No Next b lock write? Ye s DTBUSY d.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 236 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Execute CMD16 Set the number of blocks in TBNCR Read response re g .
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 237 of 1658 REJ09B0261-0100 No End of command sequence Write data to FIFO Set DA T AEN to 1 Ye s DTBUSY detected? Ye s DBSYI interru.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 238 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Read response re g ister Execute CMD20 (Set CMDR then CMDSTRT) No Y.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 239 of 1658 REJ09B0261-0100 24.5 MMCIF Interrupt Sources Table 24.7 lists the MMCIF interrupt sources. The in terrupt sources are classi fied into four grou ps, and four int errupt vectors a r e assigned.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 240 of 1658 REJ09B0261-0100 24.6 Operations when Using DMA 24.6.1 Operation in Read Sequence In order to transfer data in FIFO with the DMAC, set MMCIF (DMACR) after setting the DMAC*.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 241 of 1658 REJ09B0261-0100 • An error in a command sequence (during da ta reception) is detected through the CRC error flag or d ata timeou t flag. When these fl ags ar e detected, set the CMDO FF bit in OP CR to 1, issue CMD12 and suspend the command se quence.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 242 of 1658 REJ09B0261-0100 Start of command sequence End of command sequence Clear FIFO Execute CMD16 Confi g ure the DMAC Set DMAC.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 243 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Execute CMD16 Confi g ure the DMAC Set DMACR (in the MMCIF) Read re.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 244 of 1658 REJ09B0261-0100 End of command sequence Set DMACR to H'84 Clear DMACR to H'00 Set CMDOFF to 1 Clear DMACR to H.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 245 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Execute CMD16 Confi g ure the DMAC Set DMACR (in the MMCIF) Read re.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 246 of 1658 REJ09B0261-0100 End of command sequence Set DMACR to H'84 Clear DMACR to H'00 Set CMDOFF to 1 Clear DMACR to H.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 247 of 1658 REJ09B0261-0100 Start of command sequence End of command sequence Clear FIFO Confi g ure the DMAC Set DMACR (in the MMCI.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 248 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Execute CMD16 Confi g ure the DMAC Set DMACR (in the MMCIF) (Specif.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 249 of 1658 REJ09B0261-0100 End of command sequence Set DMACR to H'84 Set CMDOFF to 1 Clear DMACR to H'00 Clear DMA CR to .
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 250 of 1658 REJ09B0261-0100 24.6.2 Operation in Write Sequence To transfer data to FIFO with the DMAC, se t MMCIF (DMACR) after setting the DMAC. Then, start transfer to the card after a FIFO ready interrupt.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 251 of 1658 REJ09B0261-0100 • An error in a command sequence (during da ta transmission) is detected through the CRC error flag (CRCERI) or data timeout error flag.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 252 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Execute CMD16 Confi g ure the DMAC Set DMACR (in the MMCIF) Read re.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 253 of 1658 REJ09B0261-0100 End of command sequence Set CMDOFF to 1 Set the DA T AEN bit to 1 DRPI interrupt detected? No Ye s DBSYI.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 254 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Execute CMD16 Confi g ure the DMAC Set DMACR (in the MMCIF) Read re.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 255 of 1658 REJ09B0261-0100 End of command sequence Set DA T AEN to 1 DRPI interrupt detected? No Ye s DBSYI interrupt detected? No .
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 256 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Execute CMD16 Confi g ure the DMAC Set DMACR (in the MMCIF) Read re.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 257 of 1658 REJ09B0261-0100 End of command sequence Set DA T AEN to 1 DRPI interrupt detected? No Ye s DBSYI interrupt detected? No .
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 258 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Confi g ure the DMAC Set DMACR (in the MMCIF) Read response re g is.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 259 of 1658 REJ09B0261-0100 Start of command sequence Clear FIFO Execute CMD16 Confi g ure the DMAC Set DMACR (in the MMCIF) Read re.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 260 of 1658 REJ09B0261-0100 End of command sequence BTI interrupt detected? No Ye s DBSYI interrupt detected? No Ye s CRCERI or WRER.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 261 of 1658 REJ09B0261-0100 24.7 Register Accesses with Little Endian Specification When the little endian is specifi ed, the access size for registers or that for memory where the correspondin g data is store d should be fixed.
24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1 262 of 1658 REJ09B0261-0100.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 263 of 1658 REJ09B0261-0100 Section 25 Audio Codec Interface (HAC) The HAC, the audio codec digital controller interface, supports a subset of Audio C odec 97 (AC'97) Ver sion 2.1. T he HAC pr ovides serial transmission t o/reception from the AC 97 codec.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 264 of 1658 REJ09B0261-0100 Figure 25.1 show s a block diagra m of the HAC. HAC receiv er Shift re g ister for slot 1 Shift re g ister for.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 265 of 1658 REJ09B0261-0100 25.2 Input/Output Pins Table 25.1 des cribes the HAC pin configur ation.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 266 of 1658 REJ09B0261-0100 25.3 Register Descriptions The following shows the HAC registers. In t his manual, the regist ers are not discriminat ed by the channel. Table 25.2 Register Configuration (1) Channel Register Name Abbrev.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 267 of 1658 REJ09B0261-0100 Table 25.2 Register Configuration (2) Channel Register Name Abbrev.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 268 of 1658 REJ09B0261-0100 Channel Register Name Abbrev. Power-on Reset by PRESET Pin/WDT/ H-UDI Manual Reset by WDT/ Multiple Exceptions.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 269 of 1658 REJ09B0261-0100 25.3.1 Control an d Status Regis ter (HACCR) HACCR is a 32-bit read/write reg ister for contro lling input/output and mon itoring the interface status.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 270 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 10 WMRT 0 W HAC Warm Reset Use a warm reset only after power-up, or only to exit from the power-down mode by the power-do wn command.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 271 of 1658 REJ09B0261-0100 25.3.2 Command/Status Address Regis ter (HACCSAR) HACCSAR is a 32-bit read/write reg ister that specifi es the address of the codec register to be read /written.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 272 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 18 17 16 15 14 13 12 CA6/SA6 CA5/SA5 CA4/SA4 CA3/SA3 CA2/SA2 CA1/SA.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 273 of 1658 REJ09B0261-0100 25.3.3 Command/St atus Data Register (HAC CSDR) HACCSDR is a 32-bit read/write d ata register us ed for accessing the code c register. Write the command data to HACCSDR and set the ST bit in the HACCR register to 1.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 274 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 20 ⎯ All 0 R Reserved These bits are always read as 0.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 275 of 1658 REJ09B0261-0100 25.3.4 PCM Left Channel Register (HACPCML) HACPCML is a 32-bit read/write register used for accessing the left channel of t he codec in digital audi o recordin g or stre am playback.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 276 of 1658 REJ09B0261-0100 In 16-bit pac ked DMA mode, HAC PCML is defined as foll ows: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 -.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 277 of 1658 REJ09B0261-0100 25.3.5 PCM Right C hannel Register (HA CPCMR) HACPCMR is a 32-bit read/write register used for accessi ng the right channel of the codec in digital audi o recordi ng or stre am playback.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 278 of 1658 REJ09B0261-0100 25.3.6 TX Interrupt Enable Register (HACTIER) HACTIER is a 32-bit read/write reg ister that enables or disables HAC TX interrupts.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 279 of 1658 REJ09B0261-0100 25.3.7 TX Status Register (HACTSR) HACTSR is a 32-bit read/write register that indicat es th e status of the HAC TX controller. Writing 0 to the bit will initialize it.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 280 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W * 2 Description 27 to 10 ⎯ All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. 9 PLTFUN 0 R/W PCML TX Underrun 0: No PCML TX underrun has occurred.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 281 of 1658 REJ09B0261-0100 25.3.8 RX Interrupt Enable Register (HACRIER) HACRIER is a 32-bit read/write register that en ables or disables HAC RX interrupts.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 282 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 12 PRRFOVIE 0 R/W PCMR RX Overrun Interrupt Enable 0: Disables PCMR RX overrun interrupts. 1: Enables PCMR RX overrun interrupts.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 283 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W * Description 31 to 23 ⎯ All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. 22 STARY 0 R/W Status Address Ready 0: HACCSAR (status address) is not ready.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 284 of 1658 REJ09B0261-0100 25.3.10 HAC Control Regi ster (HACAC R) HACACR is a 32-bit read/wri te register used for co ntrolling the HAC interface.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 285 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 25 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 24 RXDMAL_EN 0 R/W RX DMA Left Enable 0: Disables 20-bit RX DMA for HACPCML.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 286 of 1658 REJ09B0261-0100 25.4 AC 97 Frame Slot Structure Figure 25.2 s hows the AC 97 frame slot structure. This LSI su pports slots 0 to 4 only. Sl ots 5 to 12 (hatched area) are out of scope.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 287 of 1658 REJ09B0261-0100 Table 25.4 AC97 Receive Frame Structure Slot Name Description 0 SDATA_IN TAG Tags in dicating valid data 1 Sta.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 288 of 1658 REJ09B0261-0100 25.5 Operation 25.5.1 Receiver The HAC receiver receives se rial audio data in put on the HAC_SDIN pi n, synchronous to HAC_BITCLK. From slot 0, the receiver extracts tag bits that indicate which other slots contain valid data.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 289 of 1658 REJ09B0261-0100 25.5.3 DMA The HAC supports DMA transf er for slots 3 and 4 of both the RX and TX frames. Specify th e slot data size for DMA transfer, 16 or 20 bi ts, w ith the DMARX16 an d DMATX16 bi ts in HACACR.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 290 of 1658 REJ09B0261-0100 25.5.5 Initialization Sequence Figure 25.3 s hows an exam ple of the init ialization se quence.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 291 of 1658 REJ09B0261-0100 No No Yes Yes Yes Write to codec Return Error Write 0 to TSR.CMDAMT Write 0 to TSR.CMDDMT Prerequisite: ACR.TX12_ATOMIC = 1 Wait for 1 μ s LoopCnt++ Clear RetryCnt to 0 Set data in CSDR Set Addr.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 292 of 1658 REJ09B0261-0100 Read codec No Yes No Yes No Yes Yes Yes Yes No Yes Re g V = H'7C (Vender ID1) Last_Re g : Address of the .
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 293 of 1658 REJ09B0261-0100 No Yes Send_read_request Write 0 to RSR.STARY Write 0 to RSR.STDRY Notes: E2: Loop count required in the tar g et system (13 < E2) LoopCnt2: Software counter for wait insertion Addr: Variable to hold CSAR read value.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 294 of 1658 REJ09B0261-0100 No No Yes WaitLoop_CMDAMT Notes: E3, E4: Loop count required in the tar g et system (21 < E3, 21 < E4 < 1000) LoopCnt3: Software counter for wait insertion LoopCnt4: Software counter for wait insertion Write 0 to TSR.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 295 of 1658 REJ09B0261-0100 25.5.6 Power-Down Mode It is possibl e to stop or res u me the su pply of cl ock to the HAC using the MSTP16 and M STP17 bits in the st andby cont rol regist er 0 (MSTP CR0), which is a register used in po wer-down m odes.
25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1 296 of 1658 REJ09B0261-0100.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 297 of 1658 REJ09B0261-0100 Section 26 Serial Soun d Interface (SSI) Module This LSI incorporates two channels of serial sound interface (SSI ) modules that send or receive audio data t o or from a variety of devices.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 298 of 1658 REJ09B0261-0100 Figure 26. 1 is a block diagram of t h e SSI m odule.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 299 of 1658 REJ09B0261-0100 26.2 Input/Output Pins Table 26.1 lists the pin configurations relating to the SSI module.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 300 of 1658 REJ09B0261-0100 26.3 Register Descriptions The SSI has th e following re gisters. In this manual, the register descri ption is not discrimi nated by the channel. Table 26.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 301 of 1658 REJ09B0261-0100 26.3.1 Control Register (SSICR) SSICR is a 32-bit readable/writable register that co ntrols interrupts, select s each polarity status, and sets operati ng mode.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 302 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 23 22 CHNL1 CHNL0 0 0 R/W R/W Channels These bits indicate the number of channels in each system word. These bits are ignored if CPEN = 1.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 303 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 14 SWSD 0 R/W Serial WS Direction 0: Serial word select input, slave mode 1: Serial word select output, master mode Note: In non-compressed mode (SSICR.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 304 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 12 SWSP 0 R/W Serial WS Polarity The function of this bit depends on whether the SSI module is in non-compressed mode or compressed mode.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 305 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 9 PDTA 0 R/W Parallel Data Alignment This bit is ignored if CPEN = 1. If the data word length = 32, 16 or 8 then this bit has no meaning.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 306 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 DEL 0 R/W Serial Data Delay Set this bit to 1, if CPEN=1 .
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 307 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 CPEN 0 R/W Compressed M ode Enable 0: Compressed mode disabl ed 1: Compressed mode enabled Note: In compressed mode (CPEN=1), using oper ation mode except slave transmitter (SWSD= 0 and TRMD=1).
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 308 of 1658 REJ09B0261-0100 26.3.2 Status Regis ter (SSISR) SSISR is configured by status fl ags that indicate the operating st atus of the SSI m odule and bits that indicate the current chan nel n umber a nd word number.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 309 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 27 UIRQ 0 R/W * Underfl ow Error Interrupt Status Flag This status flag indicates that the data has been supplied at a lower rate than the req uired rate.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 310 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 26 OIRQ 0 R/W * Overflow Error Interrupt Status Flag This status flag indicates that the data has been supplied at a higher rate than the require d rate.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 311 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 24 DIRQ 0 R Data Interrupt Status Flag This status flag indicates that the SSI module requires that data be either read out or written in.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 312 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1 SW NO 1 R Serial Word Number The number indicates the current word num ber. When TRMD = 0 (Receive Mode): This bit indicates which system word the current data in SSIRDR is.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 313 of 1658 REJ09B0261-0100 26.3.3 Transmit Dat a Register (SSITDR) SSITDR is a 32-bit register that stores d ata to be transmitted. Data written to SSITDR is transferred to the shift re gister as it is required for transmission.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 314 of 1658 REJ09B0261-0100 26.4 Operation 26.4.1 Bus Format The SSI module can operate a s a transmitter or a receiver and can be configured into many serial bus formats in either mode.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 315 of 1658 REJ09B0261-0100 26.4.2 Non-Compressed Modes The non-compressed mode is design ed to support all serial audio streams which are sp lit into channels. It can suppo rt Philips, Sony and Matsushi ta mod es as well as many more variants on these modes.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 316 of 1658 REJ09B0261-0100 1. Philips Format Figures 26.2 an d 26.3 show the supported Philips proto col both with p adding and w ithout. Padding occurs wh en the data word length is smaller than the system word length.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 317 of 1658 REJ09B0261-0100 2. Sony Format System word 1 System word 2 Data word 1 Data word 2 Paddin g Paddin g SCKP = 0, SWSP = 0, DEL = 1, CHNL = 00, SPDP = 0, SDTA = 0 System word len g th > data word len g th MSB LSB MSB LSB next SSI_SCK SSI_WS SSI_SDATA Figure 26.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 318 of 1658 REJ09B0261-0100 Table 26.4 Number of Padding Bits for Each Valid Configuration Padding Bits Per System W ord DWL[2:0] .
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 319 of 1658 REJ09B0261-0100 In the case of the SSI modu le configured as a transmitter then each word that is written to SSITDR is transmitted in order on the serial audio bus.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 320 of 1658 REJ09B0261-0100 System word 2 Data word 1 Data word 2 Data word 3 Data word 4 Data word 5 Data word 6 Data word 7 Data.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 321 of 1658 REJ09B0261-0100 (7) Configuration Fields—Signal Format Fields There are several more configuration bits in non-compre ssed mode which will no w be demonstrated.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 322 of 1658 REJ09B0261-0100 1. Inverte d Clock System word 1 System word 2 As basic sample format confi g uration except SCKP = 1 SSI_SCK SSI_WS SSI_SDATA 0 0 0 0 0 0 TD28 TD31 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 Figure 26.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 323 of 1658 REJ09B0261-0100 4. Padding Bits First, Follow ed by Serial Data, with Delay System word 1 System word 2 As basic sample format confi g uration except SDTA = 1 0 0 0 TD28 0 0 TD30 TD29 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 SSI_SCK SSI_WS SSI_SDATA Figure 26.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 324 of 1658 REJ09B0261-0100 7. Parallel Right Aligned wit h Delay As basic sample format confi g uration except PDTA = 1 System word 1 System word 2 0 0 0 0 00 TD3 TD0 TD3 TD2 TD1 TD0 TD3 TD2 TD1 TD0 SSI_SCK SSI_WS SSI_SDATA Figure 26.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 325 of 1658 REJ09B0261-0100 The word selec t pin in this mode doe s not act as a s ystem word start sign al as in non-compressed mode, but instead is use d to indicate that the receiver can receive anothe r data burst, or the transmitter can transmit another data burst.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 326 of 1658 REJ09B0261-0100 (1) Slave Recei ver This mode allows the module to receive a se rial bit stream from anothe r device and store it in memory. The shift regist er clock can be suppli ed from an external de vice or from an internal clock.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 327 of 1658 REJ09B0261-0100 26.4.4 Operation Modes There are three modes of operation: configurat ion, enable d and disabl ed. Figure 26.20 show s the transition dia g ram between these operation modes.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 328 of 1658 REJ09B0261-0100 26.4.5 Transmit Ope ration Transmission can be controlled in one of two ways: either DMA or an interru pt driven. DMA drive n is prefe rred to re duce the CPU load.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 329 of 1658 REJ09B0261-0100 (1) Transmissi on Using DMA Controller No Yes Yes Start End * Release reset, specify confi g uration b.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 330 of 1658 REJ09B0261-0100 (2) Transmission using Interru pt Data Flow Control Start End Release reset, specify confi g uration b.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 331 of 1658 REJ09B0261-0100 26.4.6 Receive Operation As with transmission the rece ption can be contro lled in one of two ways: either DMA or an interrupt driven. Figures 26.23 and 26 .
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 332 of 1658 REJ09B0261-0100 (1) Reception Using DMA Controller Start End * Release reset, specify confi g uration bits in SSICR Se.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 333 of 1658 REJ09B0261-0100 (2) Reception Using Interr up t Data Flow Control Start End Release reset, specify confi g uration bit.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 334 of 1658 REJ09B0261-0100 When an un derflow or overflow error conditio n is met (UIRQ = 1 or OIRQ = 1), the C HNO[1:0] and SWNO bit s can be used t o recover the S SI module to a known status.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 335 of 1658 REJ09B0261-0100 26.5 Usage Note 26.5.1 Restrictions when an Overflow O ccurs during Receive DMA Operation If an overflow occurs during receive DMA op eration, the module mu st be reactivated.
26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1 336 of 1658 REJ09B0261-0100 SCK SSI_WS SSI_SDATA SSISR.IDST SSICR.EN Data transmission One system word Idle or data transmission S.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 337 of 1658 REJ09B0261-0100 Section 27 NAND Flash Me mory Controller (FLCTL) The NAND flash memory controller (FLCTL) provides interf aces with an external NAND-type flash memory. 27.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 338 of 1658 REJ09B0261-0100 (5) Data Transfer FIFO • On-chip 224 -byte FLDTFIF O for data transf er of flash memory • On-chip.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 339 of 1658 REJ09B0261-0100 Figure 27.1 show s a block diagra m of the FLCTL. DMAC 32 32 Flash interface 32 8 8 8 32 32 FLCTL FCL.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 340 of 1658 REJ09B0261-0100 27.2 Input/Output Pins Table 27.1 sho ws the pin co nfiguration of t he FLCTL.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 341 of 1658 REJ09B0261-0100 Corresponding Flash Memory Pin Pin Name Function I/O NAND Type Description FR/ B Ready/busy Input R/ B Ready/Busy Indicates ready state at high level. Indicates busy state at low level.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 342 of 1658 REJ09B0261-0100 27.3 Register Descriptions Table 27.2 sho ws the register configuration of FL CTL. Table 27.3 shows the register states in each processing mode. Table 27.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 343 of 1658 REJ09B0261-0100 Table 27.3 Register States in Eac h Processing Mode Register Abbreviation Power-On Reset Manual Reset.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 344 of 1658 REJ09B0261-0100 27.3.1 Common Control Register (FLCMN CR) FLCMNCR is a 32-bit readable/writable reg ister th at specifies the type (NAND) of flash memory, access mode, and FCE pin out put.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 345 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 FCKSEL 0 R/W Flash Clock Select 0: Divides the operatin.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 346 of 1658 REJ09B0261-0100 27.3.2 Command Co ntrol Register (FLCMDCR) FLCMDCR is a 32-bit readable/wr itable register that issues a command in command access mode, specifies address issue, a nd specifies destination of data to be input or output.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 347 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 25 CDSRC 0 R/W Data Buffer Specification Specifies the data buffer to be read from or written to in the data stage * in command access mode.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 348 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 16 DOCMD1 0 R/W First Command Stage * Execution Specification Specifies whether the first command stage * is executed in command access mode.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 349 of 1658 REJ09B0261-0100 27.3.4 Address Register (FLADR ) FLADR is a 32-bit readable/writab le register that specifies an address to be output in command access mode.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 350 of 1658 REJ09B0261-0100 • Sector access mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 .
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 351 of 1658 REJ09B0261-0100 27.3.5 Address Register 2 (FL ADR2) FLADR2 is a 32-bit readable/writable register that is valid when the ADRCNT2 bit in FLCMDCR is 1. This re gister specifies the value t o be output as a n address i n command m ode.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 352 of 1658 REJ09B0261-0100 27.3.6 Data Counter Regi ster (FLDTCNTR) FLDTCNTR is a 32-bit readable/writab le register that specifies the number of bytes to be read or written in command access mode.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 353 of 1658 REJ09B0261-0100 27.3.7 Data Register (FLDATA R) FLDATAR is a 32-bit readabl e/writable re gister. It sto res data to be input or o utput used whe n the CDSRC bit in FLCMDCR is cleared to 0 in command access mode .
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 354 of 1658 REJ09B0261-0100 27.3.8 Interrupt DMA Control Re gister (FLINTDMACR) FLINTDMACR is a 32-bit readable/writable regist er that enables or di sables DMA transfer requests or interrupts.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 355 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 22 — All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. 21, 20 FIFOTRG [1:0] 00 R/W FIFO Trigger Setting Change the condition for the FIFO transfer request.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 356 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 18 AC0CLR 0 R/W FLDTFIFO Clear Clears the address counter of FLDTFIFO. 0: Retains the address counter valu e of FLDTFIFO.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 357 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 BTOERB 0 R/W Timeout Error This bit is set to 1 if a timeout error occurs (bits RBTIMCNT20 to RBTIMCNT0 in FLBSYCNT are set to 0 after they are decremented).
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 358 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 BTOINTE 0 RW Interrupt Enab le at Timeout Error Enables or disables an interr upt request to the CPU when a timeout error has occurred.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 359 of 1658 REJ09B0261-0100 27.3.9 Ready Busy Ti meout Setting Register (FLBSYTMR) FLBSYTMR is a 32-bit readab le/writable register that specifies the timeout time wh en the FRB pin is bus y .
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 360 of 1658 REJ09B0261-0100 27.3.10 Ready Busy Timeout Counter (FLBSYCNT) FLBSYCNT is a 32-bit rea d-only re gister. The status of flash memory read by the status read is stored in the bits STAT7 to STAT0.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 361 of 1658 REJ09B0261-0100 27.3.11 Data FIFO Register (FL DTFIFO) FLDTFIFO is used to read from or write to the data FIFO area. The read and write directions sp ecified by the SELRW bit in FL CMDCR must match the read or write access directions specified in this register.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 362 of 1658 REJ09B0261-0100 27.3.12 Control Code FIFO Register (FLECFIFO) FLECFIFO is used to read from or write to the control co de FIFO area.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 363 of 1658 REJ09B0261-0100 27.3.13 Transfer Control Register (FLTRCR) Setting the TRSTRT bit to 1 starts access to flas h memory. The completion of the access can be checked by the TREND bit.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 364 of 1658 REJ09B0261-0100 27.4 Operation 27.4.1 Operating Modes Two operating mod es are supported.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 365 of 1658 REJ09B0261-0100 Figures 27.3 and 27.4 show examples of writing oper ation for NAND- type flash memory (512 + 16 bytes). H'80 A2 A1 A3 1 2 3 4 5 6 CLE ALE I/O7 to I/O0 R/B WE RE Figure 27.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 366 of 1658 REJ09B0261-0100 (2) NAND-Type Flash Mem ory Access (2048 + 64 Bytes) Figure 27.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 367 of 1658 REJ09B0261-0100 Figures 27.6 and 27.7 show examples of w riting operat ion for NAND-t ype flash memory (2048 + 64 bytes). CLE ALE I/O7 to I/O0 R/B WE RE H'80 A1 A2 A3 A4 1 2 3 4 H'10 Figure 27.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 368 of 1658 REJ09B0261-0100 27.4.3 Sector Access Mode In sector access mode, flas h memory can be read from or written to in sector units by specifying the number of physical sectors to be accessed.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 369 of 1658 REJ09B0261-0100 (1) Physical Sector Figure 27.9 s hows the rela tionship between the ph ysical sector a ddress and flash memory address of NAND-type flash memory.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 370 of 1658 REJ09B0261-0100 (2) Continuous S ector Access Continuous physical sectors can be read from or wr itten to by specifying th e start physical sector address of NAND-typ e flash memory and the number of sectors to be tran sferred.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 371 of 1658 REJ09B0261-0100 27.4.4 Status Read The FLCTL can read the status re gister of a N AND-t ype flash memory. The data in the st atus register of a N AND-type flas h memory is in put throug h the I/O7 t o I/O0 pins and stored in the bits STAT7 to ST AT0 in FLBSYCNT.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 372 of 1658 REJ09B0261-0100 (2) Status Read of NAND -Type Flash Memory (2048 + 64 Byte s) The status read of NAND- type flash memory can be performed by inputtin g the command H'70 to NAND-type flash memor y.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 373 of 1658 REJ09B0261-0100 27.5 Example of Register Setting The examples of setting and starting registers in each access mode are shown below.
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 374 of 1658 REJ09B0261-0100 Start of sector access (flash write) FLTRCR.TREND = B'1? End of sector access (flash write) DMA .
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 375 of 1658 REJ09B0261-0100 Start of command access (flash read) FLTRCR.TREND = B'1? End of command access (flash read) Yes .
27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1 376 of 1658 REJ09B0261-0100 27.6 Interrupt Processing The FLCTL has f our interrupt sources. Each of the interrupt sources has its corresponding interrupt flag. The int errupt reque st is generated in dependent ly if the i nterrupt is e nabled by the interrupt enable b it.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 377 of 1658 REJ09B0261-0100 Section 28 General Pu rpose I/O Ports (GPIO) 28.1 Features This LSI has sixteen general -purpose p orts (A to H , J to N, and P to R), which p rovide 111 input/out put pins.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 378 of 1658 REJ09B0261-0100 Table 28.1 Multiplexed Pins Cont rolled by Port Control Registers Pin Name Port GPIO Selectable Module GP.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 379 of 1658 REJ09B0261-0100 Pin Name Port GPIO Selectable Module GPIO Interrupt D33/AD1/DR1 * 2 D PD1 input/output LBSC/PCIC/DU ⎯ D.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 380 of 1658 REJ09B0261-0100 Pin Name Port GPIO Selectable Module GPIO Interrupt SCIF0_TXD/HSPI_TX/ FWE * 1 H PH0 input/output SCIF0/H.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 381 of 1658 REJ09B0261-0100 Pin Name Port GPIO Selectable Module GPIO Interrupt SCIF5_SCK/HAC1_SDOUT/ SSI1_SDATA * 1 N PN6 input/outp.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 382 of 1658 REJ09B0261-0100 28.2 Register Descriptions The followin g registers are provided to contr ol the GPIO ports.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 383 of 1658 REJ09B0261-0100 Register Name Abbrev. R/W P4 Address * 1 Area 7 Address * 1 Access Size * 2 Sync Clock Port K data regist.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 384 of 1658 REJ09B0261-0100 Table 28.2 Register Configuration (2) Register Name Abbrev.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 385 of 1658 REJ09B0261-0100 Register Name Abbrev. Power-on Reset by RESET Pin/WDT/ H-UDI Manual Reset by WDT/ Multiple Exception Slee.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 386 of 1658 REJ09B0261-0100 28.2.1 Port A Control Reg ister (PACR) PACR is a 16-bit readable/writab le register that selects the pin function and controls the input pull-up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 387 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 9 8 PA4MD1 PA4MD0 0 0 R/W R/W PA4 Mode 00: LBSC/PCIC module (D60/ AD28) * When the bus mode is set to DU via the bus-mode pins (MODE11 and MODE12), port input (pull-up MOS: On) is selected.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 388 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 1 0 PA0MD1 PA0MD0 0 0 R/W R/W PA0 Mode 00: LBSC/PCIC module (D56/ AD24) * When the bus mode is set to DU via the bus-mode pins (MODE11 and MODE12), port input (pull-up MOS: On) is selected.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 389 of 1658 REJ09B0261-0100 28.2.2 Port B Control Register (PBCR) PBCR is a 16-bit readable/writable register th at se lects the pin function and controls the input pu ll- up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 390 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 9 8 PB4MD1 PB4MD0 0 0 R/W R/W PB4 Mode 00: LBSC/PCIC module (D52/ AD20) * When the bus mode is set to DU via the bus-mode pins (MODE11 and MODE12), port input (pull-up MOS: On) is selected.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 391 of 1658 REJ09B0261-0100 28.2.3 Port C Control Reg ister (PCCR) PCCR is a 16-bit readable/writable register th at se lects the pin function and controls the input pu ll- up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 392 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PC3MD1 PC3MD0 0 0 R/W R/W PC3 Mode 00: LBSC/PCIC/DU module.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 393 of 1658 REJ09B0261-0100 28.2.4 Port D Control Reg ister (PDCR) PDCR is a 16-bit readable/writab le register that selects the pin function and controls the input pull-up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 394 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PD3MD1 PD3MD0 0 0 R/W R/W PD3 Mode 00: LBSC/PCIC/DU module.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 395 of 1658 REJ09B0261-0100 28.2.5 Port E Control Register (PECR) PECR is a 16-bit readable/writable register th at selects the pin function and con trols the input pull- up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 396 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 5 4 PE2MD1 PE2MD0 0 0 R/W R/W PE2 Mode 00: PCIC module ( GNT1 ) When the bus mode is set to the local bus or DU via the bus mode pins (MODE1 and MODE2), port input (pull-up MOS: On) is selected.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 397 of 1658 REJ09B0261-0100 28.2.6 Port F Control Register (PFCR) PFCR is a 16-bit readable/writable register that sel ects the pin functi on and cont rols the input pull- up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 398 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PF3MD1 PF3MD0 0 0 R/W R/W PF3 Mode 00: LBSC module (D27) 0.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 399 of 1658 REJ09B0261-0100 28.2.7 Port G Control Register (PGCR) PGCR is a 16-bit readable/writab le register that selects the pin function and controls the input pull-up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 400 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PG3MD1 PG3MD0 0 0 R/W R/W PG3 Mode 00: LBSC module (D19) 0.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 401 of 1658 REJ09B0261-0100 28.2.8 Port H Control Register (PHCR) PHCR is a 16-bit readable/writab le register that selects the pin function and controls the input pull-up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 402 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PH3MD1 PH3MD0 1 1 R/W R/W PH3 Mode 00: SCIF[0]/HSPI/FLCTL .
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 403 of 1658 REJ09B0261-0100 28.2.9 Port J Control Register (PJCR) PJCR is a 16- bit readable /writable regi ster that sel ects the pin fu nction and controls the i nput pull- up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 404 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PJ3MD1 PJ3MD0 1 1 R/W R/W PJ3 Mode 00: SIOF/HAC module (SI.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 405 of 1658 REJ09B0261-0100 28.2.10 Port K Control Register (PKCR) PKCR is a 16-bit readable/writab le register that selects the pin function and controls the input pull-up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 406 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PK3MD1 PK3MD0 1 1 R/W R/W PK3 Mode 00: DMAC module ( DREQ0.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 407 of 1658 REJ09B0261-0100 28.2.11 Port L Control Register (PL C R) PLCR is a 16-bit readable/writable register th at selects the pin function and con trols the input pull- up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 408 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PL3MD1 PL3MD0 1 1 R/W R/W PL3 Mode 00: INTC/FLCTL module (.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 409 of 1658 REJ09B0261-0100 28.2.12 Port M Control R egister (PMCR) PMCR is a 16- bit readable/ writable regi ster that selects t he pin functi on and cont rols the input pull-up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 410 of 1658 REJ09B0261-0100 28.2.13 Port N Control R egister (PNCR) PNCR is a 16-bit readable/writab le register that selects the pin function and controls the input pull-up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 411 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PL3MD1 PL3MD0 1 1 R/W R/W PN3 Mode 00: SCIF[3]/FLCTL modul.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 412 of 1658 REJ09B0261-0100 28.2.14 Port P Control Register (PP C R) PPCR is a 16-bit readable/writable register that sel ects the pin functi on and cont rols the input pull- up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 413 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PP3MD1 PP3MD0 0 0 R/W R/W PP3 Mode 00: PCIC/DU module ( LOCK /ODDF) * When the bus mode is set to the local bus by the bus mode pins (MODE11 and MODE12), port input (pull-up MOS: On) is selected.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 414 of 1658 REJ09B0261-0100 28.2.15 Port Q Control Register (PQCR) PQCR is a 16-bit readable/writab le register that selects the pin function and controls the input pull-up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 415 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 5 4 PQ2MD1 PQ2MD0 0 0 R/W R/W PQ2 Mode 00: PCIC module ( REQ0 / REQOUT ) When the bus mode is set to the local bus or DU via the bus mode pins (MODE1 and MODE2), port input (pull-up MOS: On) is selected.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 416 of 1658 REJ09B0261-0100 28.2.16 Port R Control R egister (PRCR) PRCR is a 16-bit readable/writable register th at se lects the pin function and controls the input pu ll- up MOS.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 417 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 3 2 PR1MD1 PR1MD0 0 0 R/W R/W PR1 Mode 00: LBSC/PCIC module ( WE5 / CBE1 ) * When the bus mode is set to DU via the bus-mode pins (MODE11 and MODE12), port input (pull-up MOS: On) is selected.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 418 of 1658 REJ09B0261-0100 28.2.17 Port A Data Register (PADR) PADR is an 8-bit readable/writab le register that stores port A data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 419 of 1658 REJ09B0261-0100 28.2.18 Port B Data Register (PBDR) PBDR is an 8-bit readable/writab le register that stores port B data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 420 of 1658 REJ09B0261-0100 28.2.19 Port C Data Register (PCDR) PCDR is an 8-bit readable/writab le register that stores port C data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 421 of 1658 REJ09B0261-0100 28.2.20 Port D Data Register (PDDR) PDDR is an 8-bit readable/writab le register that stores port D data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 422 of 1658 REJ09B0261-0100 28.2.21 Port E Data Register (PEDR) PEDR is an 8-bit readable/writable register th at stores port E data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 423 of 1658 REJ09B0261-0100 28.2.22 Port F Data Regist er (PFDR) PFDR is an 8-bit readable/writable register that stores port F data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 424 of 1658 REJ09B0261-0100 28.2.23 Port G Data Register (PGDR) PGDR is an 8-bit readable/writab le register that stores port G data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 425 of 1658 REJ09B0261-0100 28.2.24 Port H Data Register (PHDR) PHDR is an 8-bit readable/writab le register that stores port H data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 426 of 1658 REJ09B0261-0100 28.2.25 Port J Data Register (PJDR) PJDR is an 8-bit readable/writable register that stor es port J data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 427 of 1658 REJ09B0261-0100 28.2.26 Port K Data Register (PKDR) PKDR is an 8-bit readable/writab le register that stores port K data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 428 of 1658 REJ09B0261-0100 28.2.27 Port L Data Register (PLDR) PLDR is an 8-bit readable/writable register th at stores port L data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 429 of 1658 REJ09B0261-0100 28.2.28 Port M Data Register (PMDR) PMDR is an 8-bit readable/writab le register that stores port M data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 430 of 1658 REJ09B0261-0100 28.2.29 Port N Data Register (PNDR) PNDR is an 8-bit readable/writab le register that stores port N data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 431 of 1658 REJ09B0261-0100 28.2.30 Port P Data Regist er (PPDR) PPDR is an 8-bit readable/writable register that stores port P data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 432 of 1658 REJ09B0261-0100 28.2.31 Port Q Data Register (PQDR) PQDR is an 8-bit readable/writab le register that stores port Q data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 433 of 1658 REJ09B0261-0100 28.2.32 Port R Data Register (PRDR) PRDR is an 8-bit readable/writab le register that stores port R data.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 434 of 1658 REJ09B0261-0100 28.2.33 Port E Pull-Up Control Register (PEPUPR) PEPUPR is an 8-bit readable /writable register that performs the p ull-up cont rol for each of the port E3 and E0 (PE3 and PE0 ) pins when th e pins are used by periph eral module s.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 435 of 1658 REJ09B0261-0100 28.2.34 Port H Pull-Up C ontrol Reg ister (PHPUPR) PHPUPR is an 8-bit readable/writable register that performs the p ull-up cont rol for each of the port H7 to H0 (PH7 to PH0) pins whe n the port H pi ns are used by perip heral modul es.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 436 of 1658 REJ09B0261-0100 28.2.35 Port J Pull-U p Control Re gister (PJP UPR) PJPUPR is an 8-bit readable/writable register that performs the pull-up con trol for each of the port J7 to J0 (PJ7 to PJ0) pins when the port J pins are used by periph eral modules.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 437 of 1658 REJ09B0261-0100 28.2.36 Port K Pull-Up Control Register (PKPUPR) PKPUPR is an 8-bit readable/writable register that performs the p ull-up cont rol for each of the port K7 to K0 (PK7 to PK0) pins whe n the port K pi ns are used by perip heral modul es.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 438 of 1658 REJ09B0261-0100 28.2.37 Port L Pull-Up Control Register (PLPUPR) PLPUPR is an 8-bit readable /writable register that performs the p ull-up cont rol for each of the port L7 to L0 (PL 7 to PL0) pi ns when the port L pins are used by peripheral m odules.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 439 of 1658 REJ09B0261-0100 28.2.38 Port M Pull-Up Control Register (PMPUPR) PMPUPR is an 8-bit readable/writable register that performs the pull-up cont rol for each of the port M1 and M 0 (PM1 to PM0) pi ns when the port M pi ns are used by peri pheral modul es.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 440 of 1658 REJ09B0261-0100 28.2.39 Port N Pull-Up Control Register (PN PUPR) PNPUPR is an 8-bit readable/writable register that performs the pul l-up control for eac h of the port N7 to N0 (PN7 to PN0) pins whe n the port N pi ns are used by perip heral modul es.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 441 of 1658 REJ09B0261-0100 28.2.40 Input-Pin Pull-Up Control Regis ter 1 (PPUPR1) PPUPR1 is a 16-bit readable/writable register that performs the pull-up control for the pin corresponding to each bit of the register field.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 442 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 15 to 8 — All 1 R/W Reserved These bits are always read as 1, and the writ e value should always be 1.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 443 of 1658 REJ09B0261-0100 28.2.42 Peripheral Module Select Register 1 (P1MSELR) P1MSELR is a 16-bit readab le/writable register. This register can be used to select the module that uses multipl exed pins .
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 444 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 12 11 PMSEL12 PMSEL11 0 0 R/W R/W Out of the modules DMAC, SCIF[2], MMCIF, and SIOF, selects the one uses the pins DACK3 /SCIF2_SCK/MMCDAT/SIOF_SCK and DACK2 /SCIF2_TXD/MMCCMD/SIOF_TXD.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 445 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 6 5 P1MSEL6 P1MSEL5 0 0 R/W R/W Out of the modules SCIF[2] and SIOF, selects the one using the pin SCIF2_RXD/SIOF_RXD.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 446 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 0 P1MSEL0 0 R/W Out of the modul es SCIF[3] and SCIF[4], and F.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 447 of 1658 REJ09B0261-0100 28.2.43 Peripheral Module Select Register 2 (P2MSELR) P2MSELR is a 16-bit readab le/writable register. This register can be used to select the module that uses multipl exed pins .
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 448 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 15 to 3 — All 0 R/W Reserved These bits are always read as 0, and the writ e value should always be 0. 2 P2MSEL2 0 R/W Out of the modules RESET and INTC, select s the one which uses the pin MRESETOUT / IRQOUT .
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 449 of 1658 REJ09B0261-0100 28.3 Usage Example Setting proce dure examples are descri bed below.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 450 of 1658 REJ09B0261-0100 28.3.2 Port Input function To input the data via t he GPIO po rt, write B '10 or B'11 to the cor responding t wo bits i n port control regist ers (PACR t o PRCR).
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 451 of 1658 REJ09B0261-0100 28.3.3 Peripheral Module Function The procedure s for setting t he peripheral module funct ion are descri bed below.
28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1 452 of 1658 REJ09B0261-0100.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 453 of 1658 REJ09B0261-0100 Section 29 User Break Controller (UBC) The user brea k controlle r (UBC) pr ovides versat ile functio ns to facilit ate program debu gging.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 454 of 1658 REJ09B0261-0100 Figure 29. 1 shows the UBC block diagram. SAB Internal bus Access comparator Address comparator Channel 0 oper.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 455 of 1658 REJ09B0261-0100 29.2 Register Descriptions The UBC has the following registers.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 456 of 1658 REJ09B0261-0100 Table 29.2 Register Status in Each Pr ocessing State Register Name Abbreviation Power-on Reset Manual Reset Sl.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 457 of 1658 REJ09B0261-0100 29.2.1 Match Conditio n Setting Reg isters 0 and 1 (CBR0 an d CBR1) CBR0 and CBR1 are readable/writable 32-bit reg i sters which specify the break conditions for channels 0 and 1, respectively.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 458 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 29 to 24 MFI 100000 R/W Match Flag Specify Specifies the match flag to be included in the match conditions.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 459 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7, 6 CD All 0 R/W Bus Select Specifies the bus to be included in the match cond itions. This bit is valid only when the operand acc ess cycle is specified as a match condition.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 460 of 1658 REJ09B0261-0100 • CBR1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0010000000000000 MFE AIE MFI AIV DBE SZ ETBE CD ID RW.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 461 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 23 to 16 AIV All 0 R/W ASID Specify Specifies the ASID value to be included in the match conditions. 15 DBE 0 R/W Data Value Enable * 3 Specifies whether or not to include the data value in the match condition.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 462 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7, 6 CD All 0 R/W Bus Select Specifies the bus to be included in the match conditions. This bit is valid only when the o perand access cycle is specified as a match condition.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 463 of 1658 REJ09B0261-0100 29.2.2 Match Operation Settin g Registers 0 and 1 (CRR0 and CRR1) CRR0 and CRR1 are readable/writable 32-bit reg ist ers which specify the operation to b e executed when channels 0 and 1 satisfy the matc h condition, res p ectively.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 464 of 1658 REJ09B0261-0100 • CRR1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000000 PCB BIE RRRRRRRRRRRRRRR R 15 14 13 1.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 465 of 1658 REJ09B0261-0100 29.2.3 Match Address Settin g Registers 0 and 1 (CAR 0 and CAR1) CAR0 and C AR1 are reada ble/writable 32-bit regist ers specifyin g the virtual ad dress to be included i n the break con ditions for c h annels 0 a nd 1, respectively.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 466 of 1658 REJ09B0261-0100 29.2.4 Match Addres s Mask Settin g Registers 0 and 1 (CAMR 0 and CAMR 1) CMAR0 and C MAR1 are readable/wri ta.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 467 of 1658 REJ09B0261-0100 • CAMR1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CAM CAM R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W .
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 468 of 1658 REJ09B0261-0100 29.2.5 Match Data Settin g Register 1 (CD R1) CDR1 is a readable/writable 32-b it register which specifies the data value to be included in the break cond itions for channel 1.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 469 of 1658 REJ09B0261-0100 29.2.6 Match Data Mask Setting Register 1 (CDMR1) CDMR1 is a readable/writab le 32-bit register whic h specifies the bits to be masked among the data value bit s specified us ing the match data setting register.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 470 of 1658 REJ09B0261-0100 29.2.7 Execution Count Break Register 1 (CETR1) CETR1 is a readable/writable 32-bit reg ister which specifies the numb er of the channel hits before a break occurs.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 471 of 1658 REJ09B0261-0100 29.2.8 Channel Match Flag Registe r (CCMFR) CCMFR is a readable/writable 32-bit register wh ic h indi cates whether or not the match c onditions have been sati sfied for each c hannel.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 472 of 1658 REJ09B0261-0100 29.2.9 Break Control Register (CBCR) CBCR is a readable/writable 32-bit register which specifies whether or not to use the user break debugging support fu nction.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 473 of 1658 REJ09B0261-0100 29.3 Operation Description 29.3.1 Definition of Words Relate d to Accesses "Instruction fetch" refers to an access in whic h an instruction is fetched.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 474 of 1658 REJ09B0261-0100 29.3.2 User Break Operation Sequence The followin g describes the s equence from when the break condit ion is set unt il the user break exception handling is initiated.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 475 of 1658 REJ09B0261-0100 6. While the BL bit in the SR re gister is 1, no break re quests are accepted. Howe ver, whether or not the condition h as been satisfied is determined. When the condition is determined to be satisfied, the corresponding co ndition match flag is set.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 476 of 1658 REJ09B0261-0100 29.3.4 Operand Access Cycle Brea k 1. Table 29.4 shows the relat ion betwee n the operand si zes specified using the match conditi on setting register (CBR0 or CBR1) and the add ress bits to be compared for the operand access cycle break.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 477 of 1658 REJ09B0261-0100 4. If the operand bus is selected, a break occurs after executi ng the instr uction whic h has satisfie d the conditions and immediately before executing the next instru ction.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 478 of 1658 REJ09B0261-0100 • When the match conditio n is satisfied at the instruction fetch cy cle for the first channel in the sequen.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 479 of 1658 REJ09B0261-0100 29.3.6 Program Counter Va lue to be Save d When a break has occurred, the address of the instruction t o be executed when the pr ogram restarts is saved in the SPC then the exception handling state is initiated.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 480 of 1658 REJ09B0261-0100 29.4 User Break Debugging Support Function By using the user break debugging support function, t he branch de stination a d dress can b e modified when the CPU accepts the use r break re quest.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 481 of 1658 REJ09B0261-0100 29.5 User Break Examples (1) Match Conditions Are Specified for an Instruction Fetch Cycle • Example 1-1 Reg.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 482 of 1658 REJ09B0261-0100 With the above settings, the user break occurs after executing the in struction at address H'00037226 wher e ASID is H'80 before executing the instru ction at address H'0003722E where ASID is H'70 .
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 483 of 1658 REJ09B0261-0100 With the above settings, the user break occurs after executing the in struction at address H'00037226 where ASID is H'80 and before ex ecuting the instru ction at address H'0003722 E where ASID is H'70 .
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 484 of 1658 REJ09B0261-0100 ⎯ Channel 1 Address: H'000080 10 / Address mask: H '00000006 / ASID: H'70 Data: H'000000.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 485 of 1658 REJ09B0261-0100 29.6 Usage Notes 1. A desired break ma y not occur between the t ime when the instr uction for re writing the U BC register is executed and the time when the writte n value is actually reflected on the register.
29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1 486 of 1658 REJ09B0261-0100 ⎯ If the post-instruction-exec ution break and da ta access break have occ urred simultaneously with the re-.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 487 of 1658 REJ09B0261-0100 Section 30 User Debu gging Interface (H-UDI) The H-UDI is a serial input/outpu t interface which supports to a su bset of JTAG (IEE E 1149.1). The H-UDI is used to connect emulators.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 488 of 1658 REJ09B0261-0100 TDO TDI TRST TMS TCK SDIR ASEBRK /BRKACK Boundary- scan TAP controller Break controller TAP controller De.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 489 of 1658 REJ09B0261-0100 30.2 Input/Output Pins Table 30.1 sho ws the pin co nfiguration o f the H-UDI. Table 30.1 Pin Configuration of H-UDI Pin Name Function I/O Description When Not in Use TCK Clock Input The functions are the same as the serial clock input pin of JTAG.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 490 of 1658 REJ09B0261-0100 Notes: 1. This pin is pulled up in the chip. In des igning the boar d that can connect an emulator, or using interrupts or resets through the H-UDI, there is no problem with putting the pu ll-up resistor outside this LSI.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 491 of 1658 REJ09B0261-0100 30.3 Register Description The H-UDI has the following re gisters.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 492 of 1658 REJ09B0261-0100 30.3.1 Instruction Register (SDIR) SDIR is a 16-bit read-only register that ca n be read from the CPU. Commands are set via the serial input pin (TDI). SDIR is initialized by TRST or in the Test-Logic-Reset state of the TAP.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 493 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 1 ⎯ All 0 R Reserved These bits are always read as 0.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 494 of 1658 REJ09B0261-0100 Table 30.5 Boundary Scan Register Configuration Number Pin Name Type Number Pin Name Type From TDI 525 DR.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 495 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 499 NMI Input 467 REQ0 / REQOUT Control 498 NMI Control 466 REQ.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 496 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 435 WE7 / CBE3 Input 403 D57/AD25 Output 434 WE7 / CBE3 Control.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 497 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 371 D46/AD14/DB2 Control 340 D36/AD4/DR4 Output 370 D46/AD14/DB.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 498 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 309 WE0 Input 277 CS0 Output 308 WE0 Control 276 A25 Input 307 .
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 499 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 245 A15 Control 213 A4 Input 244 A15 Output 212 A4 Control 243 .
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 500 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 181 D26 Output 149 D15 Control 180 D25 Input 148 D15 Output 179.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 501 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 117 D4 Input 86 MODE9/TXD4/FD1 Input 116 D4 Control 85 MODE9/TX.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 502 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 55 SCK5/HAC1/SDOUT/SSI1/ SDATA Control 26 SCK1 Input 54 SCK5/HA.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 503 of 1658 REJ09B0261-0100 30.4 Operation 30.4.1 Boundary-Scan TAP Contr oller (IDCOD E, EXTEST, SAMPLE/PRELOAD, a nd BYPASS) In the H-UDI in this LSI, the boundary-scan TAP controller is separated from the T AP controller for other H- UDI functio n control.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 504 of 1658 REJ09B0261-0100 00010000 T est-Lo g ic -Reset Run-T est -Idle Run-T est-Idle T est-Lo g ic -Reset Shift-IR T est-Lo g ic .
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 505 of 1658 REJ09B0261-0100 30.4.2 TAP Control Figure 30.3 s hows the inte rnal states of the TAP controller. The controller supports the state transitions specified in JTAG w ith the subset.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 506 of 1658 REJ09B0261-0100 30.4.3 H-UDI Re set The H-UDI is reset by a power-on reset by the SDIR command. To reset the H-UDI, se nd the H- UDI reset assert command fr om the H-UDI pi n, and then s end the H-UDI reset negate comma nd (see figure 30.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 507 of 1658 REJ09B0261-0100 30.4.4 H-UDI Interr upt The H-UDI int errupt function generat es an interr upt by setti ng a command value in SDI R through the H-UDI.
30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1 508 of 1658 REJ09B0261-0100.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 509 of 1658 REJ09B0261-0100 Section 31 Register List This section is a summary of t he contents of the descript ions of on -chip I/O registers in t he individual sect ions. 31.1 Register Address List The addresses of the I/O registers incorporated in the SH 7785 are listed in tabl e 31.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 510 of 1658 REJ09B0261-0100 Table 31.1 Register Address List Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size TRAPA excepti.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 511 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size INTC Interrupt mask clear register 1 INTMSKCLR.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 512 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size LBSC CS1 Bus Control Register CS1BCR R/W H&apo.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 513 of 1658 REJ09B0261-0100 Modul e Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size PCIC Control register space (physical addres .
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 514 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size PCIC PCI minimum grant registe r PCIM INGNT R .
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 515 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size PCIC PCI memory bank register 0 PCIMBR0 R/W H&.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 516 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size DMAC DMA destination address register 4 DAR4 R.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 517 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size DMAC DMA destination address register 8 DAR8 R.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 518 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size Frequency control register 0 FRQ CR0 R/W H&apo.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 519 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size TMU Timer constant register 5 TC OR5 R/W H&apo.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 520 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size DU Base color register BPO R R/W H'FFF800.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 521 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size DU Plane 2 wrap-around memory width regist er .
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 522 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size DU Plane 4 start position X register P4SPXR R/.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 523 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size DU Plane 6 display position Y register P6DPYR .
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 524 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size GCTA GA interrupt enable register GACIER R/W H.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 525 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size SCIF Serial mode register 0 SC SMR0 R/W H&apos.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 526 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size SCIF FIFO control register 2 SC FCR2 R/W H&apo.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 527 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size SCIF Bit rate register 5 SCB RR5 R/W H'FF.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 528 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size MMCIF Command register 0 CMDR0 R/W H'FFE6.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 529 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size MMCIF Response register 11 RSPR 11 R/W H'.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 530 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size HAC RX interrupt enable register 1 HACRIER1 R/.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 531 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size GPIO Port H control regis t er PHCR R/W H&apos.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 532 of 1658 REJ09B0261-0100 Module Name Name Abbrevi ation R/W P4 Area Address Area 7 Address Access Size GPIO Port N pull-up con trol register PNPUPR R.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 533 of 1658 REJ09B0261-0100 31.2 States of the Registers in th e Individual Operating Modes The states of the I/O registers incorporated in the SH7785 in the ind ividual operating modes are listed in tables 31.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 534 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 535 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 536 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 537 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 538 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 539 of 1658 REJ09B0261-0100 Table 31.3 States of the Registers in the Individual Operating Modes (2) Module Name Name Abbrev.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 540 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 541 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 542 of 1658 REJ09B0261-0100 Table 31.4 States of the Registers in the Individual Operating Modes (3) Module Name Name Abbrev.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 543 of 1658 REJ09B0261-0100 Table 31.5 States of the Registers in the Individual Operating Modes (4) Module Name Name Abbrev.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 544 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 545 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 546 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 547 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 548 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 549 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 550 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 551 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 552 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 553 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 554 of 1658 REJ09B0261-0100 Table 31.6 States of the Registers in the Individual Operating Modes (5) Module Name Name Abbrev.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 555 of 1658 REJ09B0261-0100 Table 31.7 States of the Registers in the Individual Operating Modes (6) Module Name Name Abbrev.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 556 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 557 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 558 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 559 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep/ Deep Sleep b.
31. Register List Rev.1.00 Jan. 10, 2008 Page 1 560 of 1658 REJ09B0261-0100 Table 31.8 States of the Registers in the Individual Operating Modes (7) Module Name Name Abbrev.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 561 of 1658 REJ09B0261-0100 Section 32 Electrical Characteristi cs 32.1 Absolute Maximum Ratings Table 32.1 Absolute Maximum Ratings * 1, 2 Item Symbol Value Unit V DDQ V DDQ-PLL1 V DDQ-PLL2 I/O, CPG, PCI power supply voltage V DDQ-TD − 0.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 562 of 1658 REJ09B0261-0100 32.2 DC Characteristics Table 32.2 DC Character istics (T a = − 20 to 85/ − 40 to 85 °C) Item Symbol Min. Typ. Max. Unit Test Conditions V DDQ V DDQ-PLL1/2 V DDQ-TD 3.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 563 of 1658 REJ09B0261-0100 Item Symbol Min. Typ. Max. Unit Test Conditions PRESET , NMI, TRST V IH V DDQ × 0.9 ⎯ V DDQ +0.3 V DDQ = 3.0 to 3.6 V V DDQ × 0.8 ⎯ V DDQ +0.3 ~34MHz External clock input EXTAL V DDQ × 1.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 564 of 1658 REJ09B0261-0100 Item Symbol Min. Typ. Max. Unit Item AC differential input voltage V ID (AC) 0.5 V DD-DDR +0.6 AC differential cross point voltage V IX (AC) V DD-DDR × 0.5 – 0.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 565 of 1658 REJ09B0261-0100 Item Symbol Min. Typ. Max. Unit Test Conditions PCI pins 2.4 ⎯ ⎯ V DDQ = 3.0 V I OH = –4 mA DDR pins V TT +0.603 ⎯ ⎯ AUDCK, AUDSYNC, AUDATA0, AUDATA1, AUDATA2, AUDATA3 V TT +0.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 566 of 1658 REJ09B0261-0100 Table 32.3 Permissible Output Currents Item Symbol Min. Typ. Max.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 567 of 1658 REJ09B0261-0100 32.3 AC Characteristics In principle, t his LSI's input should be synchronous. Unless specified othe rwise, ensure that the setup time and hold times for each input signal are observed.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 568 of 1658 REJ09B0261-0100 32.3.1 Clock and Control Signal T iming Table 32.6 Clock and Co ntrol Signal Timing Item Symbol Min.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 569 of 1658 REJ09B0261-0100 Item Symbol Min. Max. Unit Figure MODE13 to MODE11, MODE8 to MODE5 t MDRH 20 ⎯ ns 32.6 MODE reset hold time MODE14, MODE10, MODE9, MODE4 to MODE0 32.4 PRESET assert time t RESW 20 ⎯ t cyc 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 570 of 1658 REJ09B0261-0100 t CKOcyc t CKOH1 t CKOL1 t CKOr t CKOf 1/2V DDQ V OH V OH V OL V OL V OH 1/2V DDQ Figure 32.2 CLKOUT Clock Output Ti ming (1) t CKOH2 1.5V 1.5V 1.5V t CKOL2 Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 571 of 1658 REJ09B0261-0100 VDD t OSC1 V DD min t MDRH t OSCMD t TRSTRH t RESW CLKOUT Notes: 1.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 572 of 1658 REJ09B0261-0100 t MDRH PRESET MODE13 to MODE11 MODE8 to MODE5 t MDRS t PRr t PRf Figure 32.6 MODE Pin Setup/Hold Timing 32.3.2 Control Signal Timing Table 32.7 Control Sign al Timing Conditions : V DDQ = 3.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 573 of 1658 REJ09B0261-0100 t BREQH t BREQS t BREQH t BREQS t BACKD t BACKD t BOFF1 t BON1 CKIO BREQ BACK A[25:0], CSn , BS , RD/ WR , CE2A , CE2B , RAS , WEn , RD , CASn Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 574 of 1658 REJ09B0261-0100 32.3.3 Bus Timing Table 32.8 Bus Timing Conditions : V DDQ = 3.0 to 3.6 V, V DD = 1.1 V, T a = − 20 t o +85/ − 40 to 85°C, C L = 30 pF Item Symbol Min. Max. Unit Notes Address delay time t AD 1.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 575 of 1658 REJ09B0261-0100 CLKOUT A25 to A0 CSn RD RD/ WR D31 to D0 D31 to D0 (Write) (Read) DACKn (SA: IO ← memory) (SA: IO → memory) DACKn DACKn (DA) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 576 of 1658 REJ09B0261-0100 A25 to A0 D31 to D0 D31 to D0 (Write) (Read) (SA: IO ← memory) (SA: IO → memory) Legend : IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 577 of 1658 REJ09B0261-0100 A25 to A0 D31 to D0 D31 to D0 (Write) (Read) (SA: IO ← memory) (SA: IO → memory) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 578 of 1658 REJ09B0261-0100 A25 to A0 D31 to D0 D31 to D0 (Write) (Read) (SA: IO ← memory) (SA: IO → memory) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 579 of 1658 REJ09B0261-0100 D31 to D0 (Read) (SA: IO ← memory) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 580 of 1658 REJ09B0261-0100 D31 to D0 (Read) (SA: IO ← memory) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 581 of 1658 REJ09B0261-0100 D31 to D0 (Read) (SA: IO ← memory) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 582 of 1658 REJ09B0261-0100 D31 to D0 (Read) (SA: IO ← memory) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 583 of 1658 REJ09B0261-0100 D15 to D0 D15 to D0 (Write) (Read) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 584 of 1658 REJ09B0261-0100 D15 to D0 D15 to D0 (Write) (Read) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 585 of 1658 REJ09B0261-0100 Tpci0 Tpci1 Tpci2w Tpci2 Tpci1w Tpci0 Tpci1 Tpci2w Tpci2 Tpci1w CLKOUT C Exx R EG ( W E 0 ) A0 RD/ WR I C I OWR.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 586 of 1658 REJ09B0261-0100 Tm1 Tmd1w Tmd1 Tm0 Tmd1w Tmd1 Tmd1w CLKOUT RD / F R AME RD/ WR W E n RD Y BS D31 to D0 CSn DACKn (DA) t FMD t F.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 587 of 1658 REJ09B0261-0100 Tm1 Tmd1w Tmd1 t FMD t FMD t BSD t BSD t CSD t CSD t DACD t RDYH t RDYS t DACD t WED1 t WED1 Tm1 Tmd1 t FMD t F.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 588 of 1658 REJ09B0261-0100 D31 to D0 (2) 1st data: No internal wait, 2nd to 8th data: No internal wait + external wait control Information.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 589 of 1658 REJ09B0261-0100 D31 to D0 (2) 1st data: One internal wait cycle, 2nd to 8th data: No internal wait + external wait control Info.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 590 of 1658 REJ09B0261-0100 A25 to A0 D31 to D0 (Read) (SA: IO ← memory) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 591 of 1658 REJ09B0261-0100 A25 to A0 D31 to D0 (Read) (SA: IO ← memory) Legend: IO: DACK device SA: Single-address DMA transfer DA: Dual-address DMA transfer Note: DACK is configured as active-high.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 592 of 1658 REJ09B0261-0100 32.3.4 DBSC2 Signal Timing Table 32.9 DBSC2 Signal Timing Conditions : V DD-DDR = 1.7 to 1.9 V, V re f = 0.9 V, V DD = 1.1 V, T a = − 20 to +85/ − 40 t o 85 ° C, C L = 30 pF, ODT=on), Dr ive Strength=N ormal Item Symbol Min.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 593 of 1658 REJ09B0261-0100 Item Symbol Min. Max. Unit Figure Notes Write command to first MDQS delay time (Rising edge) t WDQSS WL − 0.18 WL +0.18 t MCK MDQS falling edge setup time to MCK rising edge (Write) t WDSS 0.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 594 of 1658 REJ09B0261-0100 MCK0, MCK1 (solid line) MCK0 , MCK1 (dotted line) t IH MCKE, MCS , MRAS , MCAS , MWE , MBA[2:0], MA[14:0] t IS t IPW Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 595 of 1658 REJ09B0261-0100 MDQS[3:0] (solid line) MDQS[ 3 :0] (dotted line) t RDQSH t RPRE t RPST t RDQSL HiZ HiZ Figure 32.29 Restrict ion of MDQS Input Waveform (Rea d) WRITE Command MDQS[3:0] (solid line) MDQS[ 3 :0] (dotted line) tWDQSS (Min.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 596 of 1658 REJ09B0261-0100 MDQS[3:0] (solid line) MDQS[ 3 :0] (dotted line) MDQ[31:0] MDM[3:0] t WDS t WDH t WDS t WDH t WDIPW t WDIPW Figure 32.32 MD QS and MDQ/MD M Output W aveform (Write) MDQS[3:0] (solid line) MDQS[ 3 :0] (dotted line) t HZ HiZ HiZ HiZ MDQ[31:0] Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 597 of 1658 REJ09B0261-0100 32.3.5 INTC Modu le Signal Ti ming Table 32.10 INTC Module Sign al Timing Conditions : V DDQ = 3.0 to 3.6 V, V DD = 1.1 V, T a = − 40 to 85 ° C, C L = 30 pF, PLL2 on Item Symbol Min.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 598 of 1658 REJ09B0261-0100 NMI IRQ t NMIIH t NMIIL t IRQIH t IRQIL Figure 32.35 Interrupt Signal Input Timing (2) CLK OUT t IRQOD t IRQOD IRQOUT Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 599 of 1658 REJ09B0261-0100 32.3.6 PCIC Module Sign al Timing Table 32.11 PCIC Signal Timing (i n PCIREQ/PCIGNT Non-Port Mode) (1) Conditions : V DDQ = 3.0 to 3.6 V, V DD = 1.1 V, T a = –40 to 85 ° C, C L = 30 pF 33 MHz 66 MHz Pin Item Symbol Min.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 600 of 1658 REJ09B0261-0100 0.5V DDQ 0.5V DDQ t PCICYC t PCIHIGH t PCILOW t PCIf t PCIr V L V L V H V H V H Figure 32.37 PCI Cloc k Input Timing t PCIVAL 0.4V DDQ 0.4V DDQ PCICLK Tri-state output Output delay t PCION t PCIOFF Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 601 of 1658 REJ09B0261-0100 t PCISU 0.4V DDQ PCICLK Input 0.4V DDQ t PCIH Figure 32.39 PCI Input Signal Timing 32.3.7 DMAC Module Signal Timing Table 32.12 DMAC Modu le Signal Timi ng Conditions : V DDQ = 3.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 602 of 1658 REJ09B0261-0100 32.3.8 TMU Modul e Signal T iming Table 32.13 TMU Module Signal Timing Conditions : V DDQ = 3.0 to 3.6 V, V DD = 1.1 V, T a = − 40 to 85 ° C, C L = 30 pF, PLL2 on Module Item Symbol Min.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 603 of 1658 REJ09B0261-0100 32.3.9 SCIF Module Sign al Timing Table 32.14 SCIF Module Signal Timing Conditions : V DDQ = 3.0 to 3.6 V, V DD = 1.1 V, T a = − 40 to 85 ° C, C L = 30 pF, PLL2 on Module Item Symbol Min.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 604 of 1658 REJ09B0261-0100 t Scyc t TXD t RXS t RXH SCIFn_CLK SCIFn_TXD SCIFn_RXD t TXD Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 605 of 1658 REJ09B0261-0100 32.3.10 H-UDI Mod ule Signal T iming Table 32.15 H-UDI Module Signal Timi ng Conditions : V DDQ = 3.0 to 3.6 V, V DD = 1.1 V, T a = − 40 to 85 ° C, C L = 30 pF, PLL2 on Item Symbol Min.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 606 of 1658 REJ09B0261-0100 ASEBRK BRKACK RESET t ASEBRKH t ASEBRKS Figure 32.45 RESET Hold Timing TDI TMS TCK TDO t TCKcyc t TDO t TDIH t TDIS Figure 32.46 H-UDI Data Transfer Timing t PINBRK ASEBRK Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 607 of 1658 REJ09B0261-0100 32.3.11 GPIO Signal Timi ng Table 32.16 GPIO Signal Timing Item Symbol Min. Max. Unit Figure GPIO output delay time t IOPD — 8 ns 32.48 GPIO input setup time t IOPS 3.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 608 of 1658 REJ09B0261-0100 32.3.12 HSPI Module Signal Timing Table 32.17 HSPI Module Signal Timing Item Symbol Min. Max. Unit Figure HSPI clock frequency (master) T SPICYC — Pck/8 MHz 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 609 of 1658 REJ09B0261-0100 32.3.13 SIOF Module Signal Timing Table 32.18 SIOF Module Signal Timing Item Symbol Min. Max. Unit Figure SIOF_MCLK clock input cycle time t MCYC t pcyc — ns 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 610 of 1658 REJ09B0261-0100 SIOF_SCK (Output) SIOF_SYNC (Output) SIOF_TXD SIOF_RXD t FSD t FSD t SICYC t SWHO t SWLO t STDD t STDD t SRDS t SRDH Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 611 of 1658 REJ09B0261-0100 SIOF_SCK (Output) SIOF_SYNC (Output) SIOF_TXD SIOF_RXD t FSD t FSD t SICYC t SWHO t SWLO t STDD t STDD t STDD t STDD t SRDS t SRDH Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 612 of 1658 REJ09B0261-0100 SIOF_SCK (Output) SIOF_SYNC (Output) SIOF_TXD SIOF_RXD t SICYC t SWHI t SWLI t FSH t FSS t STDD t STDD t SRDS t SRDH Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 613 of 1658 REJ09B0261-0100 32.3.14 MMCIF Mod ule Signal T iming Table 32.19 MMCIF Modul e Signal Ti ming Item Symbol Min. Max. Unit Figure MMCCLK clock cycle time t MMcyc 50 — ns MMCCLK clock high level widt h t MMW H 0.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 614 of 1658 REJ09B0261-0100 t MMRCS t MMRCH MMCCLK MMCCMD (Input) MMCD A T (Input) t MMRDS t MMRDH Figure 32.57 MMCIF Reception Timi ng (S ampling on Rising Edges) 32.3.15 HAC Interface Module Signal Timing Table 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 615 of 1658 REJ09B0261-0100 HACn_SYNC HACn_BITCLK t SYN_HIGH Figure 32.59 HAC Warm Reset Timing HACn_BITCLK t ICL_HIGH t ICL_LOW Figure 32.60 HAC Clock Input Timing HACn_BITCLK HACn_SDIN HACn_SDOUT t SDNHD t SDNSU t SDCUTD t SYNCD1 t SYNCD2 HACn_SYNC Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 616 of 1658 REJ09B0261-0100 32.3.16 SSI Interface Module Signal Timing Table 32.21 SSI Interface Module Signal Timing Item Symbol Min.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 617 of 1658 REJ09B0261-0100 t DTR t HTR SSIn_SCK SSIn_WS SSIn_SD A T A Figure 32.64 SSI T ransmission Ti ming (2) t SR t HTR SSIn_SCK SSIn_WS SSIn_SD A T A Figure 32.65 SSI Reception Timing (1) t HTR t SR SSIn_SCK SSIn_WS SSIn_SD A T A Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 618 of 1658 REJ09B0261-0100 32.3.17 FLCTL Module Signal Timing Table 32.22 NAND-Type Flash Memory Interface Timing Item Symbol Min. Max. Unit Figure Command issue setup time t NCDS 2 × t fcyc − 10 — ns Command issue hold time t NCDH 1.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 619 of 1658 REJ09B0261-0100 FCE (Low) (Hi g h) (Hi g h) FCLE FR/ B FD7 to FD0 FRE FWE F ALE Command t NCDAD1 t NCDS t NWP t NDOS t NDOH t NCDH Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 620 of 1658 REJ09B0261-0100 FD7 to FD0 (Low) (Low) (Hi g h) FCE FCLE FALE FWE FRE FR/ B t NRBDR2 t NADRB t NRBDR1 t NSP t NRDS t NRDS t NRDH t NRDS t NRDH t NSCC t NSPH t NSP t NSP Data Data Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 621 of 1658 REJ09B0261-0100 FCE FCLE F ALE FRE FR/ B FD7 to FD0 FWE (Low) (Low) (Hi g h) t NCDS t NDOS t NRDS t NRDH t NDOH t NWP t NCDH t NSTS t NCDSR t NCDFSR t NSP Command Status Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 622 of 1658 REJ09B0261-0100 32.3.18 Display Unit Si gnal Timing Table 32.23 PCICLK/DCLKIN Signal Timing Conditions : V DDQ = 3.3 V ± 0.3 V, Ta = -40°C to + 85°C, GND = V SSQ = 0 V Item Symbol Min.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 623 of 1658 REJ09B0261-0100 Table 32.25 Classification of Pins Pin Classification Display Input Control Signal * 1 Display Output Control S.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 624 of 1658 REJ09B0261-0100 t DS t DH PCICLK/DCLKIN (Input) Display input control si g nal * 1 (Input) Figure 32.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 625 of 1658 REJ09B0261-0100 t EXHL W t EXHHW t EXVHW t OD1 t OD2 IRD Y / HS Y NC (Input) IRD Y / HS Y NC (Input) LOCK /ODDF (Input) Figure 32.75 Display Timin g in TV Synch ronous Mode 32.4 AC Characteristic Test Conditions The AC characteristic test conditions are as follows.
32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1 626 of 1658 REJ09B0261-0100 The following figure shows the output load circuit. I OL I OH C L R T Reference level LSI output pin DUT output Figure 32.76 Output Load Circuit Notes: 1. CL is the total valu e, including the capacitance of the test jig.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 627 of 1658 REJ09B0261-0100 Appendix A. Package Dimensions Figure A.1 P ackage Dime nsions (436-P in BGA) Note: The Tj (junction temperature) of this LSI becomes ov er 125 ° C. So a careful thermal design is necessary.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 628 of 1658 REJ09B0261-0100 B. Mode Pin Settings The MODE14–M ODE0 pin values are input in the event of a power-on reset via th e PRESET pin. Note: The MODE6 pin is output stat e after power- on reset. Legend: H: High level input L: Low level input Table B.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 629 of 1658 REJ09B0261-0100 Table B.2 Area 0 Memory Type and Bus Width Pin Value MODE7 MODE6 * MODE5 Memory Interface Bus Width L L L MPX interface 64 bits H Set.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 630 of 1658 REJ09B0261-0100 Table B.6 Bus Mo de Pin Value MODE12 MODE11 Bus Mode L L PCI host bus bridge H PCIC normal (non-host) H L Local bus H Display unit Table B.7 Boot Address Mode Pin Value MODE13 Boot address Mode L 29-bit address mode H 32-bit address extended mode Table B.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 631 of 1658 REJ09B0261-0100 C. Pin Functions C.1 Pin States Table C.1 Pin States in Reset, Power- Down State, and Bus-Released State Reset Pin Name (LSI level) P.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 632 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Power -on Manual Sleep Module Standby Bus Release DACK0 Port K1.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 633 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Power -on Manual Sleep Module Standby Bus Release Port K3 (defa.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 634 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Power -on Manual Sleep Module Standby Bus Release AD[31:24] PCI.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 635 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Power -on Manual Sleep Module Standby Bus Release GNT3 PCIC O P.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 636 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Power -on Manual Sleep Module Standby Bus Release PCIRESET PCIR.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 637 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Power -on Manual Sleep Module Standby Bus Release MODE2 (power-.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 638 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Power -on Manual Sleep Module Standby Bus Release MDOE9 (power-.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 639 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Power -on Manual Sleep Module Standby Bus Release Port H3 (defa.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 640 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Power -on Manual Sleep Module Standby Bus Release Port J5 (defa.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 641 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Power -on Manual Sleep Module Standby Bus Release Port N6 (defa.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 642 of 1658 REJ09B0261-0100 C.2 Handling of Unused Pins Table C.2 Treatment of Unused Pins Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Us.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 643 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use Port K5 (default) GPIO I/O DACK2 DMAC O SCIF2_TXD SCIF O MMCC.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 644 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use MCLK[1:0] MCLK[1:0] DBSC2 O Open MCLK[1:0] MCLK[1:0] DBSC2 O .
Appendix Rev.1.00 Jan. 10, 2008 Page 1 645 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use AD[11:8] PCIC I/O D[43:40] LBSC I/O DG[5:2] DU O D[43:40]/ AD.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 646 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use PCIFRAME PCIC I/O VSYNC DU I/O PCIFRAME / VSYNC Port P0 GPIO .
Appendix Rev.1.00 Jan. 10, 2008 Page 1 647 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use TRDY PCIC I/O DISP DU O TRDY /DISP Port P2 GPIO I/O Open * 2 .
Appendix Rev.1.00 Jan. 10, 2008 Page 1 648 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use MODE4 (power-on reset) CPG I Must be used during power-on res.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 649 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use MODE11 (power-on reset) LBSC I Must be used during power-on r.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 650 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use Port H2 (default) GPIO I/O SCIF0_SCK SCIF I/O HSPI_CLK HSPI I.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 651 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use Port J6 (default) GPIO I/O SIOF_TXD SIOF O HAC0_SDOUT HAC O S.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 652 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use AUDCK AUDCK H-UDI O Open AUDSYNC AUDSYNC H-UDI O Open AUDATA[.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 653 of 1658 REJ09B0261-0100 D. Turning On and Off Power Supply D.1 Turning On and Off Between Each Power Supply Series The order of the powe r supply between the 1.0V series p ower supply (VDD10: VDD and VDD- PLL1 to 2 an d VDDA-PLL 1), the 1.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 654 of 1658 REJ09B0261-0100 D.2 Power-On and Power-O ff Sequences for Power Supplies with Differ ent Potentials in DDR2-SDRAM Power Supply Backup Mode The power-on and power-off sequences for the 1.0 V power supply (VDD10 using pins VDD, VDD-PLL1, VDDA-PLL1, and VDD-PLL 2), 1.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 655 of 1658 REJ09B0261-0100 D.3 Turning On and Off Between the Same Power Suppl y Series The order of the power supp ly in the VDD10 series, the VDD18 series and the VDD33 ser ies power supply is as follows. Figure D.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 656 of 1658 REJ09B0261-0100 E. Version Registers (PVR, PRR) The SH7785 h as the read-onl y registers w hich show the version of a proc essor core, and t he version of a p roduct.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 657 of 1658 REJ09B0261-0100 F. Product Lineup Table F.1 SH7785 Product Lineup Product Type Voltage Operating Frequency Part Number Operating Temperature Package SH7785 1.
Appendix Rev.1.00 Jan. 10, 2008 Page 1 658 of 1658 REJ09B0261-0100.
Renesas 32-Bit RISC Microcomputer Hardware Manual SH7785 Publication Date: Rev.1.00, January 10, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Refer to " http://www.renesas.com/en/network " for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.
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SH7785 Hardware Manual.
Ein wichtiger Punkt beim Kauf des Geräts Renesas SH7781 (oder sogar vor seinem Kauf) ist das durchlesen seiner Bedienungsanleitung. Dies sollten wir wegen ein paar einfacher Gründe machen:
Wenn Sie Renesas SH7781 noch nicht gekauft haben, ist jetzt ein guter Moment, um sich mit den grundliegenden Daten des Produkts bekannt zu machen. Schauen Sie zuerst die ersten Seiten der Anleitung durch, die Sie oben finden. Dort finden Sie die wichtigsten technischen Daten für Renesas SH7781 - auf diese Weise prüfen Sie, ob das Gerät Ihren Wünschen entspricht. Wenn Sie tiefer in die Benutzeranleitung von Renesas SH7781 reinschauen, lernen Sie alle zugänglichen Produktfunktionen kennen, sowie erhalten Informationen über die Nutzung. Die Informationen, die Sie über Renesas SH7781 erhalten, werden Ihnen bestimmt bei der Kaufentscheidung helfen.
Wenn Sie aber schon Renesas SH7781 besitzen, und noch keine Gelegenheit dazu hatten, die Bedienungsanleitung zu lesen, sollten Sie es aufgrund der oben beschriebenen Gründe machen. Sie erfahren dann, ob Sie die zugänglichen Funktionen richtig genutzt haben, aber auch, ob Sie keine Fehler begangen haben, die den Nutzungszeitraum von Renesas SH7781 verkürzen könnten.
Jedoch ist die eine der wichtigsten Rollen, die eine Bedienungsanleitung für den Nutzer spielt, die Hilfe bei der Lösung von Problemen mit Renesas SH7781. Sie finden dort fast immer Troubleshooting, also die am häufigsten auftauchenden Störungen und Mängel bei Renesas SH7781 gemeinsam mit Hinweisen bezüglich der Arten ihrer Lösung. Sogar wenn es Ihnen nicht gelingen sollte das Problem alleine zu bewältigen, die Anleitung zeigt Ihnen die weitere Vorgehensweise – den Kontakt zur Kundenberatung oder dem naheliegenden Service.
