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RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C F AMIL Y / M16C/60 SERIES 16 Rev. 2.00 Revision date: Nov. 28, 2005 Hardware Manual www.renesas.com Before using this material, please visit our website to verify that this is the most updated document available.
Keep safety first in your circuit designs! Notes regarding these materials • Renesas T echnology Corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them.
How to Use This Manual 1. Introduction This hardware manual provides detailed information on the M16C/6N Group (M16C/6NK, M16C/6NM) of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
3. M16C Family Documents The following documents were prepared for the M16C family (1) . Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Har.
A-1 T able of Contents SFR Page Reference ............................................................................................................ B -1 1. Overview ...................................................................................
A-2 7.2 Bus Control ................................................................................................................ ................................ 46 7.2.1 Address Bus ................................................................
A-3 10.5.4 Interrupt Sequence ...................................................................................................... .................... 89 10.5.5 Interrupt Response T ime ..............................................................
A-4 16. A/D Converter .............................................................................................................. .... 202 16.1 Mode Description .......................................................................................
A-5 20. Programmable I/O Ports ................................................................................................. 247 20.1 PDi Register ....................................................................................................
A-6 23.9 DMAC ...................................................................................................................... .............................. 349 23.9.1 Write to DMAE Bit in DMiCON Register .......................................
B-1 SFR Page Reference PM0 PM1 CM0 CM1 CSR AIER PRCR CM2 WDTS WDC RMAD0 RMAD1 CSE PLC0 PM2 SAR0 DAR0 TCR0 DM0CON SAR1 DAR1 TCR1 DM1CON Address Register Symbol Page The blank areas are reserved.
B-2 Address Register Symbol Page 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh.
B-3 Address Register Symbol Page The blank areas are reserved. 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 01 10h 0 111 h 01 12h 01 13h 01 14h 01 15.
B-4 The blank areas are reserved. FMR1 FMR0 RMAD2 AIER2 RMAD3 Address Register Symbol Page 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0.
B-5 C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL1 1 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 C0CTLR C0STR C0SSTR C0ICR C0IDR C0CONR C0RECR C0TECR C0TSR C1.
B-6 Address Register Symbol Page 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh.
B-7 Address Register Symbol Page The blank areas are reserved. 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh 0310h 031 1h 0312h 0313h 0314h 0315h 0316.
B-8 T ABSR CPSRF ONSF TRGSR UDF TA 0 TA 1 TA 2 TA 3 TA 4 TB0 TB1 TB2 T A0MR T A1MR T A2MR T A3MR T A4MR TB0MR TB1MR TB2MR TB2SC U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON DM0SL DM1SL CRCD CRCIN The blank areas are reserved.
Rev.2.00 Nov 28, 2005 page 1 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev .2.00 Nov 28, 2005 Under development This document is under development and its contents are subject to change 1.
Rev.2.00 Nov 28, 2005 page 2 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. 1.2 Performance Outline Tables 1.1 and 1.2 list a performance outline of M16C/6N Group (M16C/6NK, M16C/6NM).
Rev.2.00 Nov 28, 2005 page 3 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. Table 1.2 Performance Outline of M16C/6N Group (128-pin Version: M16C/6NM) Item Performance Normal-ver.
Rev.2.00 Nov 28, 2005 page 4 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. 1.3 Block Diagram Figure 1.1 shows a block diagram of M16C/6N Group (M16C/6NK, M16C/6NM).
Rev.2.00 Nov 28, 2005 page 5 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. 1.4 Product List Table 1.3 lists the M16C/6N Group (M16C/6NK, M16C/6NM) products and Figure 1.
Rev.2.00 Nov 28, 2005 page 6 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. PIN CONFIGURATION (top view) Figure 1.3 Pin Configuration (Top View) (1) 1.
Rev.2.00 Nov 28, 2005 page 7 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. Table 1.4 Pin Characteristics for 100-Pin Package (1) Pin No.
Rev.2.00 Nov 28, 2005 page 8 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 9 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 10 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. Table 1.6 Pin Characteristics for 128-Pin Package (1) Pin No.
Rev.2.00 Nov 28, 2005 page 11 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 12 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 13 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. 1.6 Pin Description Tables 1.9 to 1.11 list the pin descriptions.
Rev.2.00 Nov 28, 2005 page 14 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 15 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Under development This document is under development and its contents are subject to change. Table 1.11 Pin Description (100-pin and 128-pin Versions) (3) 8-bit I/O ports in CMOS, having a direction register to select an input or output.
Rev.2.00 Nov 28, 2005 page 16 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 2. Central Processing Unit (CPU) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 17 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 2. Central Processing Unit (CPU) Under development This document is under development and its contents are subject to change. 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing.
Rev.2.00 Nov 28, 2005 page 18 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 3. Memory Under development This document is under development and its contents are subject to change. 3. Memory Figure 3.1 shows a memory map of the M16C/6N Group (M16C/6NK, M16C/6NM).
Rev.2.00 Nov 28, 2005 page 19 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. 4. Special Function Register (SFR) SFR (Special Function Register) is the control register of peripheral functions.
Rev.2.00 Nov 28, 2005 page 20 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 21 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 22 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 23 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 24 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.6 SFR Information (6) X: Undefined NOTE: 1.
Rev.2.00 Nov 28, 2005 page 25 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.7 SFR Information (7) X: Undefined NOTES: 1.
Rev.2.00 Nov 28, 2005 page 26 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 27 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 28 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. X: Undefined NOTE: 1. The blank areas are reserved and cannot be accessed by users.
Rev.2.00 Nov 28, 2005 page 29 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 30 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 31 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 32 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.14 SFR Information (14) X: Undefined NOTE: 1.
Rev.2.00 Nov 28, 2005 page 33 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. X: Undefined NOTES: 1. The TA2P to TA4P bits in the UDF register are set to "0" after reset.
Rev.2.00 Nov 28, 2005 page 34 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 35 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 5. Reset Under development This document is under development and its contents are subject to change. 5. Reset Hardware reset, software reset, watchdog timer reset and oscillation stop detection reset are available to reset the microcomputer.
Rev.2.00 Nov 28, 2005 page 36 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 5. Reset Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 37 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 5. Reset Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 38 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change. 6.1 Types of Processor Mode Three processor modes are available to choose from: single-chip mode, memory expansion mode, and microprocessor mode.
Rev.2.00 Nov 28, 2005 page 39 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change. 6.2 Setting Processor Modes Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register.
Rev.2.00 Nov 28, 2005 page 40 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change. Figure 6.1 PM0 Register NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Rev.2.00 Nov 28, 2005 page 41 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 42 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 43 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change. NOTES: 1. If the PM13 bit in the PM1 register is set to "0", 192 Kbytes of the internal ROM can be used.
Rev.2.00 Nov 28, 2005 page 44 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 45 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data _______ _______ input/output to and from external devices.
Rev.2.00 Nov 28, 2005 page 46 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. Figure 7.1 CSR Register 7.2 Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait.
Rev.2.00 Nov 28, 2005 page 47 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. ______ Figure 7.2 Example of Address Bus and CSi Signal Output NOTE: 1.
Rev.2.00 Nov 28, 2005 page 48 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. _____ ______ ________ Table 7.4 Operation of RD, WR and BHE Signals _____ ________ _________ Table 7.
Rev.2.00 Nov 28, 2005 page 49 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 50 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. __________ HOLD > DMAC > CPU __________ 7.2.7 HOLD Signal This signal is used to transfer control of the bus from CPU or DMAC to an external circuit.
Rev.2.00 Nov 28, 2005 page 51 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 52 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 53 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 54 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change. Figure 7.7 Typical Bus Timings Using Software Wait (1) NOTE: 1.
Rev.2.00 Nov 28, 2005 page 55 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 56 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 57 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 58 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 8.2 CM0 Register System Clock Control Register 0 (1) NOTES: 1.
Rev.2.00 Nov 28, 2005 page 59 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 60 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 61 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 8.5 PCLKR Register NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
Rev.2.00 Nov 28, 2005 page 62 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 63 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 64 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. The following describes the clocks generated by the clock generating circuit.
Rev.2.00 Nov 28, 2005 page 65 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.1.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit.
Rev.2.00 Nov 28, 2005 page 66 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.1.3 On-chip Oscillator Clock This clock, approximately 1 MHz, is supplied by a on-chip oscillator.
Rev.2.00 Nov 28, 2005 page 67 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 8.11 Procedure to Use PLL Clock as CPU Clock Source Set the PLC02 to PLC00 bits (multiplying factor).
Rev.2.00 Nov 28, 2005 page 68 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 69 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.4 Power Control Normal operation mode, wait mode and stop mode are provided as the power consumption control.
Rev.2.00 Nov 28, 2005 page 70 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.4.1.6 On-chip Oscillator Mode The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock.
Rev.2.00 Nov 28, 2005 page 71 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer.
Rev.2.00 Nov 28, 2005 page 72 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 73 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Rev.2.00 Nov 28, 2005 page 74 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 8.4.3.3 Exiting Stop Mode _______ Stop mode is exited by a hardware reset, NMI interrupt or peripheral function interrupt.
Rev.2.00 Nov 28, 2005 page 75 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 76 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 77 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 78 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 79 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 80 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 9. Protection Under development This document is under development and its contents are subject to change. 9. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily.
Rev.2.00 Nov 28, 2005 page 81 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 82 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. 10.2 Software Interrupts A software interrupt occurs when executing certain instructions.
Rev.2.00 Nov 28, 2005 page 83 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. 10.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
Rev.2.00 Nov 28, 2005 page 84 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. Figure 10.2 Interrupt Vector 10.4.1 Fixed Vector Tables The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh.
Rev.2.00 Nov 28, 2005 page 85 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 86 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. 10.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted.
Rev.2.00 Nov 28, 2005 page 87 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 88 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. 10.5.1 I Flag The I flag enables or disables the maskable interrupt.
Rev.2.00 Nov 28, 2005 page 89 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 90 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 91 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. 10.5.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack.
Rev.2.00 Nov 28, 2005 page 92 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 93 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 94 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. ______ 10.6 INT Interrupt _______ INTi interrupt (i = 0 to 8) (1) is triggered by the edges of external inputs.
Rev.2.00 Nov 28, 2005 page 95 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 96 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 97 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 98 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change. ______ 10.7 NMI Interrupt _______ _______ ______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low.
Rev.2.00 Nov 28, 2005 page 99 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 100 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 101 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1 1. Watchdog T imer Under development This document is under development and its contents are subject to change. 11. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control.
Rev.2.00 Nov 28, 2005 page 102 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 1 1. Watchdog T imer Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 103 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. 12. DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Rev.2.00 Nov 28, 2005 page 104 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 105 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 106 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 107 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 108 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. 12.1 Transfer Cycle The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle.
Rev.2.00 Nov 28, 2005 page 109 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. Figure 12.5 Transfer Cycles for Source Read NOTE: 1. The same timing changes occur with the respective conditions at the destination as at the source.
Rev.2.00 Nov 28, 2005 page 110 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change. 12.2 DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible.
Rev.2.00 Nov 28, 2005 page 111 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 112 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 113 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 114 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 115 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. 13.1 Timer A Figure 13.3 shows a block diagram of the timer A.
Rev.2.00 Nov 28, 2005 page 116 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 117 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 118 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 119 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 120 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 121 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 122 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 123 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 124 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 125 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 126 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 127 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. 13.1.4 Pulse Width Modulation (PWM) Mode In pulse width modulation mode, the timer outputs pulses of a given width in succession.
Rev.2.00 Nov 28, 2005 page 128 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 129 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 130 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. 13.2 Timer B Figure 13.15 shows a block diagram of the timer B.
Rev.2.00 Nov 28, 2005 page 131 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 132 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 133 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 134 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 135 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 136 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 137 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 13. T imers Under development This document is under development and its contents are subject to change. Figure 13.22 Operation Timing When Measuring Pulse Width Figure 13.
Rev.2.00 Nov 28, 2005 page 138 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 139 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 140 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 14.2 INVC0 Register NOTES: 1.
Rev.2.00 Nov 28, 2005 page 141 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 142 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 143 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 144 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 145 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 146 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 147 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 148 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 149 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15. Serial Interface Serial interface is configured with 7 channels: UART0 to UART2 and SI/O3 to SI/O6 (1) .
Rev.2.00 Nov 28, 2005 page 150 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 151 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 152 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 153 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.5 U0TB to U2TB Registers, U0RB to U2RB Registers, and U0BRG to U2BRG Registers Nothing is assigned When write, set to "0".
Rev.2.00 Nov 28, 2005 page 154 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 155 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 156 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 157 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 158 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 159 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data.
Rev.2.00 Nov 28, 2005 page 160 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 161 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Table 15.3 lists the functions of the input/output pins during clock synchronous serial I/O mode.
Rev.2.00 Nov 28, 2005 page 162 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 163 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 164 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format.
Rev.2.00 Nov 28, 2005 page 165 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 166 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 167 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 168 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 169 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Table 15.7 lists the functions of the input/output pins during UART mode.
Rev.2.00 Nov 28, 2005 page 170 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 171 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 172 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 173 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.21 TXD and RXD I/O Polarity Inverse 15.
Rev.2.00 Nov 28, 2005 page 174 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 175 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.3 Special Mode 1 (I 2 C Mode) I 2 C mode is provided for use as a simplified I 2 C interface compatible mode.
Rev.2.00 Nov 28, 2005 page 176 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 177 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 178 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 179 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.24 Transfer to UiRB Register and Interrupt Timing i = 0 to 2 This diagram applies to the case where the following condition is met.
Rev.2.00 Nov 28, 2005 page 180 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined.
Rev.2.00 Nov 28, 2005 page 181 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Table 15.13 STSPSEL Bit Functions Figure 15.26 STSPSEL Bit Functions 15.
Rev.2.00 Nov 28, 2005 page 182 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 15.
Rev.2.00 Nov 28, 2005 page 183 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 184 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.4 Special Mode 2 Multiple slaves can be serially communicated from one master.
Rev.2.00 Nov 28, 2005 page 185 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 186 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 187 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 188 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.29 Transmission and Reception Timing (CKPH = 0) in Slave Mode (External Clock) Figure 15.
Rev.2.00 Nov 28, 2005 page 189 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.1.5 Special Mode 3 (IE Mode) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Rev.2.00 Nov 28, 2005 page 190 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 191 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 192 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 193 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.32 Transmit and Receive Timing in SIM Mode The above timing diagram applies to the case where data is received in the direct format.
Rev.2.00 Nov 28, 2005 page 194 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. Figure 15.33 shows the example of connecting the SIM interface.
Rev.2.00 Nov 28, 2005 page 195 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 196 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.2 SI/Oi (i = 3 to 6) (1) SI/Oi is exclusive clock-synchronous serial I/Os.
Rev.2.00 Nov 28, 2005 page 197 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 198 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 199 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 200 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change. 15.2.1 SI/Oi Operation Timing Figure 15.39 shows the SI/Oi operation timing.
Rev.2.00 Nov 28, 2005 page 201 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 202 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 203 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 204 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 205 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. Figure 16.3 ADCON2 Register, and AD0 to AD7 Registers NOTES: 1.
Rev.2.00 Nov 28, 2005 page 206 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 207 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 208 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. 16.1.2 Repeat Mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code.
Rev.2.00 Nov 28, 2005 page 209 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 210 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. 16.1.3 Single Sweep Mode In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code.
Rev.2.00 Nov 28, 2005 page 211 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 212 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. 16.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code.
Rev.2.00 Nov 28, 2005 page 213 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 214 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 215 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 216 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change. 16.2 Function 16.2.1 Resolution Select Function The desired resolution can be selected using the BITS bit in the ADCON1 register.
Rev.2.00 Nov 28, 2005 page 217 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 218 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 219 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 17. D/A Converter Under development This document is under development and its contents are subject to change. 17. D/A Converter This is an 8-bit, R-2R type D/A converter.
Rev.2.00 Nov 28, 2005 page 220 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 17. D/A Converter Under development This document is under development and its contents are subject to change. Figure 17.2 DACON Register, DA0 and DA1 Registers Figure 17.
Rev.2.00 Nov 28, 2005 page 221 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 18. CRC Calculation Under development This document is under development and its contents are subject to change. 18. CRC Calculation The Cyclic Redundancy Check (CRC) operation detects an error in data blocks.
Rev.2.00 Nov 28, 2005 page 222 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 18. CRC Calculation Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 223 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 224 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.1 CAN Module-Related Registers The CANi (i = 0, 1) module has the following registers.
Rev.2.00 Nov 28, 2005 page 225 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.2 CANi Message Box (i = 0, 1) Table 19.1 shows the memory mapping of the CANi message box.
Rev.2.00 Nov 28, 2005 page 226 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. Figures 19.2 and 19.3 show the bit mapping in each slot in byte access and word access.
Rev.2.00 Nov 28, 2005 page 227 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. Figure 19.4 Bit Mapping of Mask Registers in Byte Access 19.
Rev.2.00 Nov 28, 2005 page 228 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.4 CAN SFR Registers Figures 19.6 to 19.11 show the CAN SFR registers.
Rev.2.00 Nov 28, 2005 page 229 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 230 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 231 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 232 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 233 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 234 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.5 Operational Modes The CAN module has the following four operational modes.
Rev.2.00 Nov 28, 2005 page 235 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.5.2 CAN Operation Mode The CAN operation mode is activated by setting the Reset bit in the CiCTLR register (i = 0, 1) to “ 0 ” .
Rev.2.00 Nov 28, 2005 page 236 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.5.5 Bus Off State The bus off state is entered according to the fault confinement rules of the CAN specification.
Rev.2.00 Nov 28, 2005 page 237 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.6 Configuration CAN Module System Clock The M16C/6N Group (M16C/6NK, M16C/6NM) has a CAN module system clock select circuit.
Rev.2.00 Nov 28, 2005 page 238 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 239 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. Figure 19.16 Correspondence of Mask Registers to Slots Figure 19.
Rev.2.00 Nov 28, 2005 page 240 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 241 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 242 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 243 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.15 Reception and Transmission Table 19.3 shows configuration of CAN reception and transmission mode.
Rev.2.00 Nov 28, 2005 page 244 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 245 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.15.2 Transmission Figure 19.21 shows the timing of the transmit sequence.
Rev.2.00 Nov 28, 2005 page 246 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Under development This document is under development and its contents are subject to change. 19.16 CAN Interrupt The CAN module provides the following CAN interrupts.
Rev.2.00 Nov 28, 2005 page 247 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 248 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. 20.1 PDi Register (100-pin Version: i = 0 to 10, 128-pin Version: i = 0 to 13) Figure20.
Rev.2.00 Nov 28, 2005 page 249 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure20.1 I/O Ports (1) NOTES: 1. Symbolizes a parasitic diode.
Rev.2.00 Nov 28, 2005 page 250 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 251 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 252 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 253 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 254 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure20.7 PD0 to PD13 Registers Nothing is assigned.
Rev.2.00 Nov 28, 2005 page 255 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 256 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Pull-up Control Register 0 (1) Bit Name Bit Symbol RW b7 b6 b5 b4 b3 b2 b1 b0 PUR0 03FCh 00h Symbol Address After Reset NOTES: 1.
Rev.2.00 Nov 28, 2005 page 257 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 258 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 259 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure 20.12 Unassigned Pins Handling NOTES: 1.
Rev.2.00 Nov 28, 2005 page 260 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 261 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.1 Memory Map The flash memory contains the user ROM area and a boot ROM area.
Rev.2.00 Nov 28, 2005 page 262 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 263 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 264 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 265 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 266 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 267 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.3.1 FMR00 Bit This bit indicates the flash memory operating status.
Rev.2.00 Nov 28, 2005 page 268 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.3.7 FMR07 Bit This is a read-only bit indicating the auto erase operation status.
Rev.2.00 Nov 28, 2005 page 269 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.6 Setting and Resetting of EW1 Mode Figure 21.
Rev.2.00 Nov 28, 2005 page 270 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 271 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.4 Precautions on CPU Rewrite Mode 21.3.
Rev.2.00 Nov 28, 2005 page 272 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.4.9 Writing Command and Data Write commands and data to even addresses in the user ROM area.
Rev.2.00 Nov 28, 2005 page 273 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.5 Software Commands Software commands are described below.
Rev.2.00 Nov 28, 2005 page 274 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.8 Program Command 21.3.5.4 Program Command (40h) The program command writes 2-byte data to the flash memory.
Rev.2.00 Nov 28, 2005 page 275 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 21.9 Block Erase Command 21.3.5.5 Block Erase Command The block erase command erases each block.
Rev.2.00 Nov 28, 2005 page 276 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.5.6 Erase All Unlocked Block The erase all unlocked block command erases all blocks except the block A.
Rev.2.00 Nov 28, 2005 page 277 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.5.8 Read Lock Bit Status Command (71h) The read lock bit status command reads the lock bit state of a specified block.
Rev.2.00 Nov 28, 2005 page 278 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.3.6 Data Protect Function Each block in the flash memory has a nonvolatile lock bit.
Rev.2.00 Nov 28, 2005 page 279 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 280 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 281 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 282 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 283 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Table 21.7 Pin Functions for Standard Serial I/O Mode NOTES: ____________ 1.
Rev.2.00 Nov 28, 2005 page 284 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 285 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 286 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.4.2 Example of Circuit Application in Standard Serial I/O Mode Figures 21.
Rev.2.00 Nov 28, 2005 page 287 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 288 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 289 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 290 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 291 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 21.6.2 Example of Circuit Application in CAN I/O Mode Figure 21.
Rev.2.00 Nov 28, 2005 page 292 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. 22. Electrical Characteristics 22.
Rev.2.00 Nov 28, 2005 page 293 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 294 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Table 22.3 Recommended Operating Conditions (2) (1) Main Clock Input Oscillation N o Wait Mask ROM Version V C C = 3.
Rev.2.00 Nov 28, 2005 page 295 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Table 22.4 Electrical Characteristics (1) (1) V CC -2.
Rev.2.00 Nov 28, 2005 page 296 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 297 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 298 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 299 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 300 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Timing Requirements (Referenced to VCC = 5V, VSS = 0V, at Topr = – 40 to 85 ° C unless otherwise specified) Table 22.
Rev.2.00 Nov 28, 2005 page 301 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 302 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 303 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 304 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 305 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 306 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.5 Timing Diagram (2) Measuring conditions : VCC = 5 V Input timing voltage : Determined with V IL = 1.
Rev.2.00 Nov 28, 2005 page 307 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.6 Timing Diagram (3) BCLK CSi t d(BCLK-CS) 25ns.
Rev.2.00 Nov 28, 2005 page 308 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.7 Timing Diagram (4) BCLK CSi t d(BCLK-CS) 25ns.
Rev.2.00 Nov 28, 2005 page 309 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 310 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 311 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 312 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 313 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Table 22.28 Electrical Characteristics (1) V CC -0.
Rev.2.00 Nov 28, 2005 page 314 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 315 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Timing Requirements (Referenced to VCC = 3.
Rev.2.00 Nov 28, 2005 page 316 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 317 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 318 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 319 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 320 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 321 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.14 Timing Diagram (2) Measuring conditions : VCC = 3.
Rev.2.00 Nov 28, 2005 page 322 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.15 Timing Diagram (3) BCLK CSi t d(BCLK-CS) 30ns.
Rev.2.00 Nov 28, 2005 page 323 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change. Figure 22.16 Timing Diagram (4) BCLK CSi t d(BCLK-CS) 30ns.
Rev.2.00 Nov 28, 2005 page 324 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 325 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 326 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 327 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 328 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. 22.2 Electrical Characteristics (T/V-ver.
Rev.2.00 Nov 28, 2005 page 329 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 330 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. Table 22.48 Recommended Operating Conditions (2) (1) Main Clock Input Oscillation N o Wait Flash Memory VCC = 4 .
Rev.2.00 Nov 28, 2005 page 331 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. Table 22.49 Electrical Characteristics (1) (1) V CC -2.
Rev.2.00 Nov 28, 2005 page 332 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 333 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change. Table 22.51 A/D Conversion Characteristics (1) (NOTE 2) 8 1.
Rev.2.00 Nov 28, 2005 page 334 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 335 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 336 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 337 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V -ver .) Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 338 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23. Usage Precaution 23.1 SFR There is the SFR which can not be read (containg bits that will result in unknown data when read).
Rev.2.00 Nov 28, 2005 page 339 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.2 External Bus (Normal-ver. only) When resetting CNVSS pin with "H" input, contents of internal ROM cannot be read out.
Rev.2.00 Nov 28, 2005 page 340 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.3 External Clock Do not stop the external clock when it is connected to the XIN pin and the main clock is selected as the CPU clock.
Rev.2.00 Nov 28, 2005 page 341 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.4 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met.
Rev.2.00 Nov 28, 2005 page 342 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 343 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. • Suggestions to reduce power consumption. Ports The processor retains the state of each I/O port even when it goes to wait mode or to stop mode.
Rev.2.00 Nov 28, 2005 page 344 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 345 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 346 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.8 Interrupt 23.8.1 Reading Address 00000h Do not read the address 00000h in a program.
Rev.2.00 Nov 28, 2005 page 347 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 348 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 349 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.9 DMAC 23.9.1 Write to DMAE Bit in DMiCON Register (i = 0, 1) When both of the conditions below are met, follow the steps below.
Rev.2.00 Nov 28, 2005 page 350 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.10 Timers 23.10.1 Timer A 23.10.1.1 Timer A (Timer Mode) The timer remains idle after reset.
Rev.2.00 Nov 28, 2005 page 351 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.10.1.2 Timer A (Event Counter Mode) The timer remains idle after reset.
Rev.2.00 Nov 28, 2005 page 352 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.10.1.3 Timer A (One-shot Timer Mode) The timer remains idle after reset.
Rev.2.00 Nov 28, 2005 page 353 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.10.1.4 Timer A (Pulse Width Modulation Mode) The timer remains idle after reset.
Rev.2.00 Nov 28, 2005 page 354 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.10.2 Timer B 23.10.2.1 Timer B (Timer Mode) The timer remains idle after reset.
Rev.2.00 Nov 28, 2005 page 355 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.10.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) The timer remains idle after reset.
Rev.2.00 Nov 28, 2005 page 356 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 357 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.12 Serial Interface 23.12.1 Clock Synchronous Serial I/O Mode 23.
Rev.2.00 Nov 28, 2005 page 358 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 359 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 360 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.13 A/D Converter Set the ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger occurs).
Rev.2.00 Nov 28, 2005 page 361 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 362 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 363 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 364 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 365 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 366 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 367 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 368 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.16 Dedicated Input Pin When dedicated input pin voltage is larger than VCC pin voltage, latch up occurs.
Rev.2.00 Nov 28, 2005 page 369 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 370 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.18 Mask ROM Version When using the masked ROM version, write nothing to internal ROM area.
Rev.2.00 Nov 28, 2005 page 371 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 372 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 373 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 374 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution Under development This document is under development and its contents are subject to change. 23.21 Noise Connect a bypass capacitor (approximately 0.
Rev.2.00 Nov 28, 2005 page 375 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) Appendix 1. Package Dimensions Under development This document is under development and its contents are subject to change. Appendix 1. Package Dimensions Terminal cross section b 1 c 1 b p c 2.
Rev.2.00 Nov 28, 2005 page 376 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) Appendix 1. Package Dimensions Under development This document is under development and its contents are subject to change.
Rev.2.00 Nov 28, 2005 page 377 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) Register Index Under development This document is under development and its contents are subject to change. Register Index A AD0 to AD7 ..........................
Rev.2.00 Nov 28, 2005 page 378 of 378 REJ09B0124-0200 M16C/6N Group (M16C/6NK, M16C/6NM) Register Index Under development This document is under development and its contents are subject to change. U U0BCNIC t o U2BCNIC ..................... 86 U0BRG to U2BRG .
REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Rev . Date Description Page Summary C-1 1.00 Sep. 30, 2004 1.01 Nov. 01, 2004 1.10 Jul. 01, 2005 – First edition issued – Revised edition issued * Revised parts and revised contents are as follows (except for expressional change).
REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Rev . Date Description Page Summary C-2 212 Figure 18.11 C0RECR, C1RECR Registers, C0TECR, C1TECR Registers, C0TSR, C1TSR Registers, and C0AFS, C1AFS Registers • C0RECR, C1RECR Registers: NOTE 2 is deleted.
REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Rev . Date Description Page Summary C-3 37 5.2 Software Reset, 5.3 Watchdog Timer Reset, 5.4 Oscillation Stop Detection Reset: Last sentence (Processor mode remains ...) is added to each section.
REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Rev . Date Description Page Summary C-4 108 12.1.3 Effect of Software Wait: 3rd to 9th lines is moved from next section of 12.1.2. ________ 12.1.4 Effect of RDY Signal is added. 110 Table 12.
REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Rev . Date Description Page Summary C-5 258 Table 20.3 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode (Normal-ver. only) is added. 259 Figure 20.12 Unassigned Pins Handling • Figure of memory expansion mode or microprocessor mode is added.
REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Rev . Date Description Page Summary C-6 291 Figure 21.19 Circuit Application in CAN I/O Mode: “VCC1” and “VCC2” are added. 293 Table 22.2 Recommended Operating Conditions (1) is partly revised.
M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Publication Data : Rev.1.00 Sep 30, 2004 Rev.2.00 Nov 28, 2005 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual 2- 6 -2, Ote-machi, Chiyoda-ku, Tokyo, 1 00-0004, Japan.
Ein wichtiger Punkt beim Kauf des Geräts Renesas M16C/6NK (oder sogar vor seinem Kauf) ist das durchlesen seiner Bedienungsanleitung. Dies sollten wir wegen ein paar einfacher Gründe machen:
Wenn Sie Renesas M16C/6NK noch nicht gekauft haben, ist jetzt ein guter Moment, um sich mit den grundliegenden Daten des Produkts bekannt zu machen. Schauen Sie zuerst die ersten Seiten der Anleitung durch, die Sie oben finden. Dort finden Sie die wichtigsten technischen Daten für Renesas M16C/6NK - auf diese Weise prüfen Sie, ob das Gerät Ihren Wünschen entspricht. Wenn Sie tiefer in die Benutzeranleitung von Renesas M16C/6NK reinschauen, lernen Sie alle zugänglichen Produktfunktionen kennen, sowie erhalten Informationen über die Nutzung. Die Informationen, die Sie über Renesas M16C/6NK erhalten, werden Ihnen bestimmt bei der Kaufentscheidung helfen.
Wenn Sie aber schon Renesas M16C/6NK besitzen, und noch keine Gelegenheit dazu hatten, die Bedienungsanleitung zu lesen, sollten Sie es aufgrund der oben beschriebenen Gründe machen. Sie erfahren dann, ob Sie die zugänglichen Funktionen richtig genutzt haben, aber auch, ob Sie keine Fehler begangen haben, die den Nutzungszeitraum von Renesas M16C/6NK verkürzen könnten.
Jedoch ist die eine der wichtigsten Rollen, die eine Bedienungsanleitung für den Nutzer spielt, die Hilfe bei der Lösung von Problemen mit Renesas M16C/6NK. Sie finden dort fast immer Troubleshooting, also die am häufigsten auftauchenden Störungen und Mängel bei Renesas M16C/6NK gemeinsam mit Hinweisen bezüglich der Arten ihrer Lösung. Sogar wenn es Ihnen nicht gelingen sollte das Problem alleine zu bewältigen, die Anleitung zeigt Ihnen die weitere Vorgehensweise – den Kontakt zur Kundenberatung oder dem naheliegenden Service.
