Benutzeranleitung / Produktwartung 4514 des Produzenten Renesas
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Regar ding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas T echnology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas T echnology Corporation on April 1st 2003.
MITSUBISHI 4-BIT SINGLE-CHIP MICROCOMPUTER 4500 SERIES 4513/4514 Group User’ s Man ual.
keep safety first in your circuit designs ! ● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Preface This user’s manual describes the hardware and instructions of Mitsubishi’s 4513/4514 Group CMOS 4-bit microcomputer. After reading this manual, the user should have a through knowledge of the functions and features of the 4513/4514 Group and should be able to fully utilize the product.
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. Organization CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function.
4513/4514 Group User’s Manual i T ab le of contents CHAPTER 1 HARDWARE DESCRIPTION ............................................................................................................................... . 1-3 FEATURES .......................
ii 4513/4514 Group User’s Manual CHAPTER 2 APPLICATION 2.1 I/O pins .................................................................................................................................... 2- 2 2.1.1 I/O ports ...........................
4513/4514 Group User’s Manual iii CHAPTER 3 APPENDIX 3.1 Electrical characteristics ..................................................................................................... 3- 2 3.1.1 Absolute maximum ratings ...........................
iv 4513/4514 Group User’s Manual List of figures CHAPTER 1 HARDWARE PIN CONFIGURATION (TOP VIEW) 4513 Group ..................................................................... 1 -4 PIN CONFIGURATION (TOP VIEW) 4514 Group ..........................
4513/4514 Group User’s Manual v List of figures Fig. 42 Ceramic resonator external circuit ............................................................................... 1-58 Fig. 43 External clock input circuit ....................................
vi 4513/4514 Group User’s Manual CHAPTER 3 APPENDIX Fig. 3.2.1 A-D conversion characteristics data ........................................................................ 3-14 Fig. 44 External 0 interrupt program example ...........................
4513/4514 Group User’s Manual vii List of tables CHAPTER 1 HARDWARE Table Selection of system clock ................................................................................................ 1-11 Table 1 ROM size and pages ....................
viii 4513/4514 Group User’s Manual List of tables Table 2.5.1 A-D control register Q1 .......................................................................................... 2-50 Table 2.5.2 A-D control register Q2 ...............................
CHAPTER 1 CHAPTER 1 HARD W ARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD LIST OF PRECAUTIONS S.
1-2 HARD W ARE 4513/4514 Group User’s Manual.
4513/4514 Group User’s Manual HARD W ARE 1-3 DESCRIPTION The 4513/4514 Group is a 4-bit single-chip microcomputer de- signed with CMOS technology . Its CPU is that of the 4500 series using a simple, high-speed instruction set.
1-4 HARD W ARE 4513/4514 Group User’s Manual PIN CONFIGURA TION (T OP VIEW) 4513 Gr oup M34513Mx-XXXSP M34513E4SP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 .
4513/4514 Group User’s Manual HARD W ARE 1-5 PIN CONFIGURA TION (T OP VIEW) 4514 Gr oup P1 2 P1 1 P1 0 P0 3 P0 2 P0 1 P0 0 A IN3 /CMP1+ A IN2 /CMP1- A IN1 /CMP0+ A IN0 /CMP0- P3 1 /INT1 P3 0 /INT0 V.
1-6 HARD W ARE 4513/4514 Group User’s Manual BLOCK DIAGRAM (4513 Group) |[go 1 Voltage drop detection circuit 4 S e ria l I/O (8 b i ts ✕ 1) Voltage comparator (2 circuits) X IN –X OUT I/O port .
4513/4514 Group User’s Manual HARD W ARE 1-7 BLOCK DIAGRAM (4514 Group) Voltage drop detection circuit S e ria l I/O (8 b i ts ✕ 1) Voltage comparator (2 circuits) X IN —X OUT I/O port Internal .
1-8 HARD W ARE 4513/4514 Group User’s Manual PERFORMANCE O VERVIEW Function 123 128 0.75 µ s (at 4.0 MHz oscillation frequency , in high-speed mode) 2048 words ✕ 10 bits 4096 words ✕ 10 bits 61.
4513/4514 Group User’s Manual HARD W ARE 1-9 PIN DESCRIPTION Name Power supply Ground V oltage drop detec- tion circuit enable CNV SS Reset input System clock input System clock output I/O port D (Input is examined by skip decision.
1-10 HARD W ARE 4513/4514 Group User’s Manual Notes 1: Pins except above have just single function. 2: The input of D 6 , D 7 , P2 0 –P2 2 , CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P3 0 , P3 1 , P4 0 –P4 3 can be used even when CNTR0, CNTR1, S CK , S OUT , S IN , INT0, INT1, and A IN0 –A IN7 are selected.
4513/4514 Group User’s Manual HARD W ARE 1-11 Notes 1: The 4513 Group does not have P3 2 and P3 3 . 2: The 4513 Group does not have these ports. DEFINITION OF CLOCK AND CYCLE ● System clock The system clock is the basic clock for controlling this product.
1-12 HARD W ARE 4513/4514 Group User’s Manual PORT BLOCK DIAGRAMS PIN DESCRIPTION D T Q Ai P0 0 ,P0 1 K0 0 PU 0 0 D T Ai P0 2 ,P0 3 K0 1 PU 0 1 D T Ai P1 0 ,P1 1 K0 2 PU 0 2 D T Ai P1 2 ,P 1 3 K0 3 .
4513/4514 Group User’s Manual HARD W ARE 1-13 PORT BLOCK DIAGRAMS (continued) PIN DESCRIPTION Synchronous clock input for serial transfer Register A IAP2 instruction P2 0 /S CK J1 0 Synchronous cloc.
1-14 HARD W ARE 4513/4514 Group User’s Manual PORT BLOCK DIAGRAMS (continued) PIN DESCRIPTION A IN0 /CMP0- Q1 Q3 0 A IN1 /CMP0+ + - Q3 2 A IN2 /CMP1- Q3 1 A IN3 /CMP1+ + - Q3 3 OP4A instruction IAP4.
4513/4514 Group User’s Manual HARD W ARE 1-15 PORT BLOCK DIAGRAMS (continued) PIN DESCRIPTION P5 0 –P5 3 D T Q OP5A instruction Ai Register A IAP5 instruction D 0 –D 5 SD instruction S R Q Decod.
1-16 HARD W ARE 4513/4514 Group User’s Manual External interrupt circuit structure PIN DESCRIPTION 0 1 I2 2 0 1 EXF1 I2 1 SNZI1 P3 1 /INT1 0 1 I1 2 Wakeup Skip 0 1 EXF0 I1 1 SNZI0 P3 0 /INT0 Rising .
4513/4514 Group User’s Manual HARD W ARE 1-17 FUNCTION BLOCK OPERATIONS FUNCTION BLOCK OPERA TIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit ar ithmetic such as 4- bit data addition, compar ison, AND oper ation, OR operation, and bit manipulation.
1-18 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (5) Stack registers (SK S ) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program.
4513/4514 Group User’s Manual HARD W ARE 1-19 FUNCTION BLOCK OPERATIONS (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address).
1-20 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS PROGRAM MEMOY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). T able 1 shows the R OM size and pages .
4513/4514 Group User’s Manual HARD W ARE 1-21 FUNCTION BLOCK OPERATIONS D A T A MEMOR Y (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memor y area. A RAM address is specified b y a data pointer .
1-22 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interr upt source. An interrupt occurs when the following 3 conditions are satisfied.
4513/4514 Group User’s Manual HARD W ARE 1-23 FUNCTION BLOCK OPERATIONS (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 14). • Program counter (PC) An interrupt address is set in program counter.
1-24 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (6) Interrupt control registers • Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction.
4513/4514 Group User’s Manual HARD W ARE 1-25 FUNCTION BLOCK OPERATIONS (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt en- able bits (V1 0 –V1 3 and V2 0 –V2 3 ), and interrupt request flag are “1.
1-26 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS T able 7 External interrupt activated conditions Name External 0 interrupt External 1 interrupt Input pin P3 0 /INT0 P3 1 /INT.
4513/4514 Group User’s Manual HARD W ARE 1-27 FUNCTION BLOCK OPERATIONS (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to P3 0 /INT0 pin.
1-28 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (3) External interrupt control registers • Interrupt control register I1 Register I1 controls the valid waveform for the external 0 inter- rupt. Set the contents of this register through register A with the TI1A instruction.
4513/4514 Group User’s Manual HARD W ARE 1-29 FUNCTION BLOCK OPERATIONS TIMERS The 4513/4514 Group has the programmable timers. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n.
1-30 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS Count source • Instruction clock • Prescaler output (ORCLK) • Timer 1 underflow • Prescaler output (ORCLK) • CNTR0 i.
4513/4514 Group User’s Manual HARD W ARE 1-31 FUNCTION BLOCK OPERATIONS Fig. 19 Timers structure T4F T3F 10 01 00 W3 1 ,W3 0 0 1 W3 3 (Note 3) 0 1 W4 3 (Note 3) 11 T1F (T2AB) T2F (TAB2) 0 1 W2 3 (No.
1-32 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS T able 10 Timer control register s 0 1 0 1 0 1 0 1 W2 1 0 0 1 1 Stop (state initialized) Operating Instruction clock divided b.
4513/4514 Group User’s Manual HARD W ARE 1-33 FUNCTION BLOCK OPERATIONS (1) Timer control register s • Timer control register W1 Register W1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ra- tio and count operation of prescaler .
1-34 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (6) Timer 3 (interrupt function) Timer 3 is an 8-bit binar y down counter with the timer 3 reload reg- ister (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instr uction.
4513/4514 Group User’s Manual HARD W ARE 1-35 FUNCTION BLOCK OPERATIONS W A TCHDOG TIMER Watchdog timer pro vides a method to reset the system when a pro- gram runs wild. W atchdog timer consists of a 16-bit timer (WDT), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2).
1-36 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS SERIAL I/O The 4513/4514 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data.
4513/4514 Group User’s Manual HARD W ARE 1-37 FUNCTION BLOCK OPERATIONS Fig. 23 Serial I/O register state when transferring (1) Serial I/O register SI Serial I/O register SI is the 8-bit data transfer serial/parallel conver- sion register . Data can be set to register SI through registers A and B with the TSIAB instruction.
1-38 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (5) How to use serial I/O Figure 24 shows the serial I/O connection example. Serial I/O inter- rupt is not used in this example. In the actual wiring, pull up the wir ing betw een each pin with a resistor .
4513/4514 Group User’s Manual HARD W ARE 1-39 FUNCTION BLOCK OPERATIONS Fig. 25 Timing of serial I/O data transfer S IN S OUT SCK S OUT S IN S 0 S 7 ’S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 0 S 7 ’ S 1 S .
1-40 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS T able 13 Processing sequence of data transfer fr om master to slave 1-b yte data is serially transf erred on this process. Subsequently , data can be transferred continuously by repeating the process from *.
4513/4514 Group User’s Manual HARD W ARE 1-41 FUNCTION BLOCK OPERATIONS A-D CONVERTER The 4513/4514 Group has a built-in A-D conversion circuit that performs conversion by 10-bit successive comparison method. T able 14 shows the characteristics of this A-D conv er ter .
1-42 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS Q1 3 Q1 2 Q1 1 Q1 0 A-D control register Q1 Not used Analog input pin selection bits (Note 2) at reset : 0000 2 at RAM back-up : state retained 0 1 Q1 2 0 0 0 0 1 1 1 1 Q1 1 0 0 1 1 0 0 1 1 This bit has no function, but read/write is enabled.
4513/4514 Group User’s Manual HARD W ARE 1-43 FUNCTION BLOCK OPERATIONS T able 16 Change of successive comparison register AD during A-D con version Comparison v oltage (V ref ) value Change of succ.
1-44 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS Fig. 28 Setting registers 0 ✕✕ 1 (Bit 3) (Bit 0) A-D control register Q2 A IN4 function selected A-D conversion mode A-D c.
4513/4514 Group User’s Manual HARD W ARE 1-45 FUNCTION BLOCK OPERATIONS (10) Operation at comparator mode The A-D con verter is set to comparator mode by setting bit 3 of the register Q2 to “1.” Belo w , the operation at comparator mode is described.
1-46 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (15) Notes f or the use of A-D conver sion 2 Do not change the operating mode (both A-D conv ersion mode and comparator mode) of A-D conv erter with bit 3 of register Q2 while A-D converter is operating.
4513/4514 Group User’s Manual HARD W ARE 1-47 FUNCTION BLOCK OPERATIONS V OL T A GE COMP ARA T OR The 4513/4514 Group has 2 voltage comparator circuits that perform compar ison of v oltage betw een 2 pins. T able 17 sho ws the characteristics of this voltage comparison.
1-48 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS V oltage compar ator control register Q3 (Note 2) at reset : 0000 2 at RAM back-up : state retained Q3 3 Q3 2 Q3 1 Q3 0 V olta.
4513/4514 Group User’s Manual HARD W ARE 1-49 FUNCTION BLOCK OPERATIONS RESET FUNCTION System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions.
1-50 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (1) Power-on reset Reset can be performed automatically at power on (power-on re- set) by connecting resistors, a diode, and a capacitor to RESET pin. Connect RESET pin and the external circuit at the shortest dis- tance.
4513/4514 Group User’s Manual HARD W ARE 1-51 FUNCTION BLOCK OPERATIONS • Program counter (PC) ......................................................................................................... . Address 0 in page 0 is set to prog ram counter .
1-52 HARD W ARE 4513/4514 Group User’s Manual V OL T A GE DR OP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Fig. 37 V oltage dr op detection cir cuit operation waveform Fig.
4513/4514 Group User’s Manual HARD W ARE 1-53 RAM BACK-UP MODE The 4513/4514 Group has the RAM back-up mode. When the EPOF and POF instructions are e xecuted continuously , system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not ex- ecuted before the POF instruction.
1-54 HARD W ARE 4513/4514 Group User’s Manual (4) Return signal An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped.
4513/4514 Group User’s Manual HARD W ARE 1-55 Fig. 38 State transition Fig. 39 Set source and clear source of the P flag Fig. 40 Start condition identified example using the SNZP in- struction S R Q.
1-56 HARD W ARE 4513/4514 Group User’s Manual T able 22 K ey-on wakeup control register , pull-up control register , and interrupt contr ol register K0 3 K0 2 K0 1 K0 0 Key-on wakeup control registe.
4513/4514 Group User’s Manual HARD W ARE 1-57 CLOCK CONTROL The clock control circuit consists of the following circuits. • System clock generating circuit • Control circuit to stop the clock oscillation Fig.
1-58 HARD W ARE 4513/4514 Group User’s Manual Clock signal f(X IN ) is obtained by externally connecting a ceramic resonator . Connect this external circuit to pins X IN and X OUT at the shortest distance. A feedbac k resistor is built in betw een pins X IN and X OUT .
4513/4514 Group User’s Manual HARD W ARE 1-59 LIST OF PRECAUTIONS ➀ Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx.
1-60 HARD W ARE 4513/4514 Group User’s Manual ➉ A-D converter-1 When the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 in a program, be careful about the following notes.
4513/4514 Group User’s Manual HARD W ARE 1-61 16 V oltage compar ator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode . Accordingly , be careful about such state because it causes the increase of the operation current in the RAM back- up mode.
1-62 HARD W ARE 4513/4514 Group User’s Manual SYMBOL The symbols shown below are used in the following instruction function table and instruction list.
4513/4514 Group User’s Manual HARD W ARE 1-63 LIST OF INSTRUCTION FUNCTION Group- ing RAM addresses Function (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP.
1-64 HARD W ARE 4513/4514 Group User’s Manual LIST OF INSTRUCTION FUNCTION (continued) Function (T1F) = 1 ? After skipping (T1F) ← 0 (T2F) = 1 ? After skipping (T2F) ← 0 (T3F) = 1 ? After skippi.
4513/4514 Group User’s Manual HARD W ARE 1-65 LIST OF INSTRUCTION FUNCTION (continued ) Mnemonic TK0A T AK0 TPU0A T APU0 TFR0A* T ABSI TSIAB T AJ1 TJ1A SST SNZSI Function (K0) ← (A) (A) ← (K0) (.
1-66 HARD W ARE 4513/4514 Group User’s Manual INSTR UCTION CODE T ABLE (f or 4513 Gr oup) D 3 –D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1.
4513/4514 Group User’s Manual HARD W ARE 1-67 INSTR UCTION CODE T ABLE (contin ued) (f or 4513 Group) – – TJ1A – TQ1A TQ2A TQ3A – – – – – – – TW1A TW2A TW3A TW4A – TW6A – –.
1-68 HARD W ARE 4513/4514 Group User’s Manual INSTR UCTION CODE T ABLE (f or 4514 Group) NOP – POF SNZP DI EI RC SC – – AM AMC TY A – TBA – BLA CLD – INY RD SD – DEY AND OR TEAB – CM.
4513/4514 Group User’s Manual HARD W ARE 1-69 INSTR UCTION CODE T ABLE ( contin ued ) (f or 4514 Group) – – TJ1A – TQ1A TQ2A TQ3A – – – – – – – TW1A TW2A TW3A TW4A – TW6A – .
Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-70 HARD W ARE 4513/4514 Group User’s.
Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-71 MACHINE INSTRUCTIONS T ransfers the contents of register B to register A. T ransfers the contents of register A to register B . T ransfers the contents of register Y to register A.
Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-72 HARD W ARE 4513/4514 Group User’s.
Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-73 MACHINE INSTRUCTIONS Continuous description – – – Overflow = 0 – – – – (CY) = 0 – – .
Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-74 HARD W ARE 4513/4514 Group User’s.
Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-75 MACHINE INSTRUCTIONS – – – – – – – – Skip at uncondition – – (EXF0) = 1 (EXF1) = 1 Branch within a page : Branches to address a in the identical page.
Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-76 HARD W ARE 4513/4514 Group User’s.
Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-77 MACHINE INSTRUCTIONS When bit 2 (I1 2 ) of register I1 is “1” : Skips the next instruction when the level of INT0 pin is “H.” When bit 2 (I1 2 ) of register I1 is “0” : Skips the next instruction when the level of INT0 pin is “L.
Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-78 HARD W ARE 4513/4514 Group User’s.
Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-79 MACHINE INSTRUCTIONS – – – – – – – – – – – – – – – – – – – – – – – – (T1F) = 1 (T2F) =1 (T3F) = 1 (T4F) = 1 T ransfers the contents of timer 1 to registers A and B.
Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-80 HARD W ARE 4513/4514 Group User’s.
Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-81 MACHINE INSTRUCTIONS – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – (D(Y)) = 0 (Y) = 0 to 7 – – – – – T ransfers the input of port P0 to register A.
Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-82 HARD W ARE 4513/4514 Group User’s.
Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-83 MACHINE INSTRUCTIONS – – – – – (SIOF) = 1 – – – – – – (ADF) = 1 – – – – .
1-84 HARD W ARE 4513/4514 Group User’s Manual V1 3 V1 2 V1 1 V1 0 V2 3 V2 2 V2 1 V2 0 Serial I/O interrupt enable bit A-D interrupt enable bit Timer 4 interrupt enab le bit Timer 3 interrupt enab le.
4513/4514 Group User’s Manual HARD W ARE 1-85 0 1 0 1 0 1 0 1 W2 1 0 0 1 1 Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Ope.
1-86 HARD W ARE 4513/4514 Group User’s Manual Selected pins A IN0 A IN1 A IN2 A IN3 A IN4 (Not available for the 4513 Group) A IN5 (Not available for the 4513 Group) A IN6 (Not available for the 4513 Group) A IN7 (Not available for the 4513 Group) This bit has no function, but read/write is enabled.
4513/4514 Group User’s Manual HARD W ARE 1-87 K0 3 K0 2 K0 1 K0 0 Key-on wakeup control register K0 PU0 3 PU0 2 PU0 1 PU0 0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wa.
1-88 HARD W ARE 4513/4514 Group User’s Manual T able 25 Product of built-in PR OM version Product M34513E4SP/FP M34513E8FP M34514E8FP ROM type One Time PR OM version [shipped in blank] PROM size ( ✕ 10 bits) 4096 words 8192 words 8192 words RAM size ( ✕ 4 bits) 256 words 384 words 384 words Package SP: 32P4B FP: 32P6B-A 32P6B-A 42P2R-A Fig.
4513/4514 Group User’s Manual HARD W ARE 1-89 Fig. 52 Flow of writing and test of the product shipped in blank Fig. 51 PROM memory map (1) PROM mode The built-in PROM version has a PROM mode in addition to a nor- mal operation mode. The PR OM mode is used to write to and read from the built-in PROM.
1-90 HARD W ARE 4513/4514 Group User’s Manual BUILT-IN PROM VERSION.
CHAPTER 2 CHAPTER 2 APPLICA TION 2.1 I/O pins 2.2 Interrupts 2.3 Timers 2.4 Serial I/O 2.5 A-D converter 2.6 Voltage comparator 2.7 Reset 2.8 Voltage drop detection circuit 2.
2-2 APPLICA TION 2.1 I/O pins 4513/4514 Group User’s Manual 2.1 I/O pins The 4513/4514 Group has the twenty-eight I/O pins (eighteen I/O pins for 4513 Group), three input pins. (Ports P2 0 –P2 2 , P3 0 , P3 1 , D 6 and D 7 are also used as serial I/O pins S CK , S OUT , S IN , and INT0, INT1, CNTR0 and CNTR1 pins, respectively).
4513/4514 Group User’s Manual APPLICA TION 2-3 2.1 I/O pins (4) Port P3 Port P3 is a 4-bit I/O port for the 4514 Group, and a 2-bit I/O port for the 4513 Group. ■ Input/output of port P3 ● ● ● ● Data input to port P3 Set the output latch of specified port P3i (i=0 to 3) to “1” with the OP3A instruction.
2-4 APPLICA TION 2.1 I/O pins 4513/4514 Group User’s Manual (7) Port D D 0 –D 7 are eight independent I/O ports. ■ Input/output of port D Each pin of port D has an independent 1-bit wide I/O function. For I/O of ports D 0 –D 7 , select one of port D with the register Y of the data pointer first.
4513/4514 Group User’s Manual APPLICA TION 2-5 2.1 I/O pins (2) Key-on wakeup control register K0 Register K0 controls the ON/OFF of the key-on wakeup function of ports P0 0 –P0 3 and P1 0 –P1 3 . Set the contents of this register through register A with the TK0A instruction.
2-6 APPLICA TION 2.1 I/O pins 4513/4514 Group User’s Manual (4) Direction register FR0 (The 4513 Group does not have this register.) Register FR0 is used to switch to input/output of P5 0 –P5 3 . Set the contents of this register through register A with the TFR0A instruction.
4513/4514 Group User’s Manual APPLICA TION 2-7 2.1 I/O pins 2.1.3 Port application examples (1) Key input by key scan Key matrix can be set up by connecting keys externally because port D output structure is an N- channel open-drain and port P0 has the pull-up resistor.
2-8 APPLICA TION 2.1 I/O pins 4513/4514 Group User’s Manual Fig. 2.1.2 Key scan input timing D 0 D 1 D 2 D 3 IAP0 IAP0 IAP0 IAP0 IAP0 “H” “L” “H” “L” “H” “L” “H” “L” .
4513/4514 Group User’s Manual APPLICA TION 2-9 2.1 I/O pins 2.1.4 Notes on use (1) Note when an I/O port except port P5 is used as an input port Set the output latch to “1” and input the port value before input. If the output latch is set to “0,” “L” level can be input.
2-10 APPLICA TION 2.1 I/O pins 4513/4514 Group User’s Manual Table 2.1.6 connections of unused pins Pin X OUT VDCE D 0 –D 5 D 6 /CNTR0 D 7 /CNTR1 P2 0 /S CK P2 1 /S OUT P2 2 /S IN P3 0 /INT0 P3 1 .
APPLICA TION 2.2 Interrupts 2-11 4513/4514 Group User’s Manual 2.2 Interrupts The 4513/4514 Group has eight interrupt sources : external (INT0, INT1), timer 1, timer 2, timer 3, timer 4, A-D, and serial I/O. This section describes individual types of interrupts, related registers, application examples using interrupts and notes.
APPLICA TION 2.2 Interrupts 2-12 4513/4514 Group User’s Manual (4) Timer 2 interrupt The interrupt request occurs by the timer 2 underflow. ■ Timer 2 interrupt processing ● When the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the interrupt enable flag INTE are set to “1.
APPLICA TION 2.2 Interrupts 2-13 4513/4514 Group User’s Manual (7) A-D interrupt The interrupt request occurs by the end of the A-D conversion. ■ A-D interrupt processing ● When the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt control register V2 and the interrupt enable flag INTE are set to “1.
APPLICA TION 2.2 Interrupts 2-14 4513/4514 Group User’s Manual (2) Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction.
APPLICA TION 2.2 Interrupts 2-15 4513/4514 Group User’s Manual Interrupt control register I1 at reset : 0000 2 at RAM back-up : state retained R/W This bit has no function, but read/write is enabled.
APPLICA TION 2.2 Interrupts 2-16 4513/4514 Group User’s Manual 2.2.3 Interrupt application examples (1) External 0 interrupt The INT0 pin is used for external 0 interrupt, of which valid waveforms can be chosen, which can recognize the change of both edges (“H” → “L” or “L” → “H”).
APPLICA TION 2.2 Interrupts 2-17 4513/4514 Group User’s Manual (6) Timer 4 interrupt Constant period interrupts by a setting value to timer 4 can be used. Outline: The constant period interrupts by the timer 4 underflow signal can be used. Specifications: Prescaler, timer 3 and timer 4 divide the system clock frequency f(X IN ) = 4.
APPLICA TION 2.2 Interrupts 2-18 4513/4514 Group User’s Manual Fig. 2.2.2 INT0 interrupt setting example Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock. ➁ Set Port Port used for INT0 interrupt is set to input port.
APPLICA TION 2.2 Interrupts 2-19 4513/4514 Group User’s Manual Fig. 2.2.3 INT1 interrupt operation example P3 1 /INT1 P3 1 /INT1 “H” “H” “L” “L” An interrupt occurs after the valid waveform “falling” is detected. An interrupt occurs after the valid waveform “rising” is detected.
APPLICA TION 2.2 Interrupts 2-20 4513/4514 Group User’s Manual Fig. 2.2.4 INT1 interrupt setting example Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock. ➁ Set Port Port used for INT1 interrupt is set to input port.
APPLICA TION 2.2 Interrupts 2-21 4513/4514 Group User’s Manual Fig. 2.2.5 Timer 1 constant period interrupt setting example b3 b0 01 b3 b0 1 g0 h b3 b0 1 11 0 0 b3 b0 ➀ Disable Interrupts Timer 1 interrupt is temporarily disabled.
APPLICA TION 2.2 Interrupts 2-22 4513/4514 Group User’s Manual Fig. 2.2.6 Timer 2 constant period interrupt setting example 0 b3 b0 ➀ Disable Interrupts Timer 2 interrupt is temporarily disabled.
APPLICA TION 2.2 Interrupts 2-23 4513/4514 Group User’s Manual Fig. 2.2.7 Timer 3 constant period interrupt setting example g0 h 0 b3 b0 ➀ Disable Interrupts Timer 3 interrupt is temporarily disabled.
APPLICA TION 2.2 Interrupts 2-24 4513/4514 Group User’s Manual Fig. 2.2.8 Timer 4 constant period interrupt setting example 0 b3 b0 ➀ Disable Interrupts Timer 4 interrupt is temporarily disabled.
APPLICA TION 2.2 Interrupts 2-25 4513/4514 Group User’s Manual 2.2.4 Notes on use (1) Setting of INT0 interrupt valid waveform Depending on the input state of P3 0 /INT0 pin, the external interrupt request flag (EXF0) may be set to “1” when the interrupt valid waveform is changed.
APPLICA TION 2.3 Timers 2-26 4513/4514 Group User’s Manual 2.3 Timer s The 4513/4514 Group has four 8-bit timers (each has a reload register) and a 16-bit fixed dividing frequency timer which has the watchdog timer function. This section describes individual types of timers, related registers, application examples using timers and notes.
APPLICA TION 2.3 Timers 2-27 4513/4514 Group User’s Manual 2.3.2 Related registers (1) Interrupt control register V1 The timer 1 interrupt enable bit is assigned to bit 2, and the timer 2 interrupt enable bit is assigned to bit 3. Set the contents of this register through register A with the TV1A instruction.
APPLICA TION 2.3 Timers 2-28 4513/4514 Group User’s Manual (3) Timer control register W1 The timer 1 count start synchronous circuit control bit is assigned to bit 0, the timer 1 control bit is assigned to bit 1, the prescaler dividing ratio selection bit is assigned to bit 2, and the prescaler control bit is assigned to bit 3.
APPLICA TION 2.3 Timers 2-29 4513/4514 Group User’s Manual (5) Timer control register W3 The timer 3 count source selection bits are assigned to bits 0 and 1, the timer 3 count start synchronous circuit control bit is assigned to bit 2 and the timer 3 control bit is assigned to bit 3.
APPLICA TION 2.3 Timers 2-30 4513/4514 Group User’s Manual 2.3.3 Timer application examples (1) Timer operation: measurement of constant period The constant period by the setting timer count value can be measured. Outline: The constant period by the timer 1 underflow signal can be measured.
APPLICA TION 2.3 Timers 2-31 4513/4514 Group User’s Manual (4) CNTR1 output control: square wave output control Outline: The output/stop of square wave from timer 3 every timer 4 underflow can be controlled. Specifications: 4 kHz square wave is output from timer 3 at system clock fr equency f(X IN ) = 4.
APPLICA TION 2.3 Timers 2-32 4513/4514 Group User’s Manual Fig. 2.3.3 Constant period measurement setting example g0 h 0 b3 b0 ➀ Disable Interrupts Timer 1 interrupt is temporarily disabled.
APPLICA TION 2.3 Timers 2-33 4513/4514 Group User’s Manual Fig. 2.3.4 CNTR0 output setting example g0 h 0 b3 b0 ➀ Disable Interrupts Timer 1 interrupt is temporarily disabled.
APPLICA TION 2.3 Timers 2-34 4513/4514 Group User’s Manual 0 b3 b0 ➀ Disable Interrupts Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 “0” .
APPLICA TION 2.3 Timers 2-35 4513/4514 Group User’s Manual Fig. 2.3.6 CNTR0 output control setting example b3 b0 ➀ Disable Interrupts Timer 3 and timer 4 interrupt are temporarily disabled.
APPLICA TION 2.3 Timers 2-36 4513/4514 Group User’s Manual Fig. 2.3.7 Timer start by external input setting example (1) 0 b3 b0 ➀ Disable Interrupts Timer 1 interrupt is temporarily disabled.
APPLICA TION 2.3 Timers 2-37 4513/4514 Group User’s Manual Fig. 2.3.8 Timer start by external input setting example (2) ( TI1A instruction) b3 b0 1 0 0 Processing in interrupt service routine ➇ St.
APPLICA TION 2.3 Timers 2-38 4513/4514 Group User’s Manual Fig. 2.3.9 Watchdog timer setting example g0 h • • • • • • ➀ Activate Watchdog Timer Watchdog timer is activated.
APPLICA TION 2.3 Timers 2-39 4513/4514 Group User’s Manual 2.3.4 Notes on use (1) Prescaler Stop the prescaler operation to change its frequency dividing ratio.
APPLICA TION 2.4 Serial I/O 2-40 4513/4514 Group User’s Manual 2.4 Serial I/O The 4513/4514 Group has a clock-synchronous serial I/O which can be used to transmit and receive 8-bit data. This section describes serial I/O functions, related registers, application examples using serial I/O and notes.
APPLICA TION 2.4 Serial I/O 2-41 4513/4514 Group User’s Manual 2.4.2 Related registers (1) Serial I/O register SI Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction.
APPLICA TION 2.4 Serial I/O 2-42 4513/4514 Group User’s Manual 2.4.3 Operation description Figure 2.4.2 shows the serial I/O connection example, Figure 2.4.3 shows the serial I/O register state, and Figure 2.4.4 shows the serial I/O transfer timing.
APPLICA TION 2.4 Serial I/O 2-43 4513/4514 Group User’s Manual Fig. 2.4.4 Serial I/O transfer timing S IN S OUT Slave S CK SST instruction S OUT S IN S 0 S 7 ’S 1 S 2 S 3 S 4 S 5 S 6 S 7 SST instr.
APPLICA TION 2.4 Serial I/O 2-44 4513/4514 Group User’s Manual The full duplex communication of master and slave is described using the connection example shown in Figure 2.4.2. (1) Transmit/receive operation of master ➀ The transmit data is written into the serial I/O register SI with the TSIAB instruction.
APPLICA TION 2.4 Serial I/O 2-45 4513/4514 Group User’s Manual (2) Transmit/receive operation of slave ➀ The transmit data is written into the serial I/O register SI with the TSIAB instruction.
APPLICA TION 2.4 Serial I/O 2-46 4513/4514 Group User’s Manual Fig. 2.4.5 Master serial I/O setting example g0 h b3 b0 ➀ Disable Interrupts Serial I/O interrupt is temporarily disabled.
APPLICA TION 2.4 Serial I/O 2-47 4513/4514 Group User’s Manual Fig. 2.4.6 Slave serial I/O example b3 b0 ➀ Disable Interrupts Serial I/O interrupt is temporarily disabled.
APPLICA TION 2.4 Serial I/O 2-48 4513/4514 Group User’s Manual 2.4.5 Notes on use (1) Note when an external clock is used as a synchronous clock: • An external clock is selected as the synchronous clock, the clock is not controlled internally. • Serial transfer is continued as long as an external clock is input.
APPLICA TION 2.5 A-D converter 2-49 4513/4514 Group User’s Manual 2.5 A-D con verter The 4513/4514 Group has an A-D converter with the 10-bit successive comparison method: 4 channels for the 4513 Group, 8 channels for the 4514 Group.
APPLICA TION 2.5 A-D converter 2-50 4513/4514 Group User’s Manual 2.5.1 Related registers (1) A-D control register Q1 Analog input pin selection bits are assigned to register Q1. Set the contents of this register through register A with the TQ1A instruction.
APPLICA TION 2.5 A-D converter 2-51 4513/4514 Group User’s Manual 2.5.2 A-D converter application examples (1) A-D conversion mode Outline: Analog input signal from a sensor can be converted into digital values. Specifications: Analog voltage values from a sensor is converted into digital values by using a 10- bit successive comparison method.
APPLICA TION 2.5 A-D converter 2-52 4513/4514 Group User’s Manual 2.5.3 Notes on use (1) Note when the A-D conversion starts again When the A-D conversion starts again with the ADST instruction during A-D conversion, the previous input data is invalidated and the A-D conversion starts again.
APPLICA TION 2.5 A-D converter 2-53 4513/4514 Group User’s Manual (5) A-D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison, the contents of ADF flag retains “0,” not set to “1.
APPLICA TION 2.6 Voltage comparator 2-54 4513/4514 Group User’s Manual 2.6 V olta ge comparator The 4513/4514 Group has two voltage comparators; CMP0-, CMP0+, CMP1-, CMP1+. This section describes the voltage comparator function, related registers, and notes.
APPLICA TION 2.6 Voltage comparator 2-55 4513/4514 Group User’s Manual 2.6.3 Notes on use ● Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode.
APPLICA TION 2-56 4513/4514 Group User’s Manual 2.7 Reset System reset is performed by applying “L” level to the RESET pin for 1 machine cycle or more when the following conditions are satisfied: the value of supply voltage is the minimum value or more of the recommended operating conditions oscillation is stabilized.
APPLICA TION 2-57 4513/4514 Group User’s Manual • Program counter (PC) ............................................................................................ Address 0 in page 0 is set to program counter. • Interrupt enable flag (INTE) ...
APPLICA TION 2-58 4513/4514 Group User’s Manual 2.8 Voltage drop detection circuit 2.8 V oltage dr op detection cir cuit The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value.
APPLICA TION 2-59 4513/4514 Group User’s Manual 2.9 RAM back-up 2.9 RAM back-up 2.9.1 RAM back-up mode The system enters RAM back-up mode when the POF instruction is executed after the EPOF instruction is executed. Table 2.9.1 shows the function and state retained at RAM back-up mode.
APPLICA TION 2-60 4513/4514 Group User’s Manual 2.9 RAM back-up Remarks Set the port using the key-on wakeup function selected with register K0 to “H” level before going into the RAM back-up state because the port P0 shares the falling edge detection circuit with port P1.
APPLICA TION 2-61 4513/4514 Group User’s Manual 2.9 RAM back-up (2) Pull-up control register PU0 Pull-up control register PU0 controls the pull-up functions of ports P0 0 –P0 3 , P1 0 –P1 3 . Set the contents of this register through register A with the TPU0A instruction.
APPLICA TION 2-62 4513/4514 Group User’s Manual 2.9 RAM back-up (4) Interrupt control register I2 The interrupt valid waveform for INT1 pin/return level selection bit is assigned to bit 2, the INT1 pin edge detection circuit control bit is assigned to bit 1, and the INT1 pin timer 1 control enable bit is assigned to bit 1.
APPLICA TION 2-63 4513/4514 Group User’s Manual 2.10 Oscillation circuit 2.10 Oscillation circuit The 4513/4514 Group has an internal oscillation circuit to produce the clock required for microcomputer operation. The clock signal f(X IN ) is obtained by connecting a ceramic resonator to X IN pin and X OUT pin.
APPLICA TION 2-64 4513/4514 Group User’s Manual 2.10 Oscillation circuit 2.10.2 Oscillation operation System clock is supplied to CPU and peripheral device as the standard clock for the microcomputer operation.
CHAPTER 3 CHAPTER 3 APPENDIX 3.1 Electrical characteristics 3.2 Typical characteristics 3.3 List of precautions 3.4 Notes on noise 3.5 Mask ROM confirmation form 3.
APPENDIX 3.1 Electrical characteristics 3-2 4513/4514 Group User’s Manual Parameter Supply voltage Input voltage P0, P1, P2, P3, P4, P5, RESET , X IN , VDCE Input voltage D 0 –D 7 Input v oltage A.
4513/4514 Group User’s Manual APPENDIX 3-3 3.1 Electrical characteristics Symbol V DD V RAM V SS V IH V IH V IH V IH V IL V IL V IL I OH (peak) I OH (avg) I OL (peak) I OL (peak) I OL (peak) I OL (p.
APPENDIX 3.1 Electrical characteristics 3-4 4513/4514 Group User’s Manual V DD = 2.5 V to 5.5 V V DD = 2.0 V to 5.5 V V DD = 2.5 V to 5.5 V V DD = 4.0 V to 5.5 V V DD = 2.5 V to 5.5 V V DD = 2.0 V to 5.5 V V DD = 4.0 V to 5.5 V V DD = 2 .5 V to 5.5 V V DD = 2 .
4513/4514 Group User’s Manual APPENDIX 3-5 3.1 Electrical characteristics 3.1.3 Electrical characteristics Table 3.1.4 Electrical characteristics (Mask ROM v ersion:T a = –20 °C to 85 °C, V DD = 2.0 V to 5.5 V , unless otherwise noted) (One Time PR OM v ersion:T a = –20 °C to 85 °C , V DD = 2.
APPENDIX 3.1 Electrical characteristics 3-6 4513/4514 Group User’s Manual 3.1.4 A-D converter recommended operating conditions Table 3.1.5 A-D converter recommended operating conditions (Comparator .
4513/4514 Group User’s Manual APPENDIX 3-7 3.1 Electrical characteristics 3.1.7 Basic timing diagram 3.1.6 Voltage comparator characteristics Table 3.1.8 Voltage comparator recommended operating conditions (T a = –20 °C to 85 °C, unless otherwise noted) Conditions V DD = 3.
3-8 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2 2.5 3 3.5 4 4.5 5 5.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.
4513/4514 Group User’s Manual APPENDIX 3-9 3.2 Typical characteristics Supply voltage V DD (V) Supply current I DD (mA) Supply voltage V DD (V) Supply current I DD (mA) (3) Ta = 25 °C (4) A-D operating, high-speed mode Ta = 25 °C f(X IN ) = 4 MHz f(X IN ) = 1 MHz 0 2 1 0.
3-10 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 2 2.5 3 3.5 4 4.5 5 5.5 Supply voltage V DD (V) Supply current I DD (nA) (5) RAM back-up Ta = .
4513/4514 Group User’s Manual APPENDIX 3-11 3.2 Typical characteristics 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 0 10 20 30 40 50 60 70 80 90 100 0 0.
3-12 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 0 10 20 30 40 50 60 70 80 90 100 0 0.
4513/4514 Group User’s Manual APPENDIX 3-13 3.2 Typical characteristics 0 50 100 150 200 250 300 350 2 2.5 3 3.5 4 4.5 5 5.5 6 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.
3-14 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual 3.2.5 A-D converter typical characteristics Fig. 3.2.1 A-D conversion characteristics data Figure 3.2.1 shows the A-D accuracy measurement data. (1) Non-linearity error ........
4513/4514 Group User’s Manual APPENDIX 3-15 3.2 Typical characteristics (1) V DD = 3.072 V, f(X IN ) = 2 MHz, high-speed mode -4.5 -3 -1.5 0 1.5 3 4.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 STEP No. ERROR / 1LSB WIDTH(mV) 1 LSB WID TH ERR O R -4.
3-16 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual (2) V DD = 5.12 V, f(X IN ) = 4 MHz, high-speed mode -7.5 -5 -2.5 0 2.5 5 7.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 STEP No. ERROR / 1LSB WIDTH(mV) 1 LSB WID TH ERR O R -7.
4513/4514 Group User’s Manual APPENDIX 3-17 3.2 Typical characteristics -25 -20 -15 -10 -5 0 5 10 15 20 25 0 0.5 1 1.5 2 2.5 3 -100 -80 -60 -40 -20 0 20 40 60 80 100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 3.2.6 Analog input current characteristics pins A IN0 –A IN7 (1) V DD = 3.
3-18 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual -200 -160 -120 -80 -40 0 40 80 120 160 200 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -50 -40 -30 -20 -10 0 10 20 30 40 50 0 0.5 1 1.5 2 2.5 3 (3) V DD = 3.0 V, f(X IN ) = 2 MHz, high-speed mode Ta = 25 °C Analog input voltage V AIN (V) Analog input current I AIN (nA) (4) V DD = 5.
4513/4514 Group User’s Manual APPENDIX 3-19 3.2 Typical characteristics 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 6 0 0.5 1 1.5 2 2.
3-20 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 6 (3) Pins INT0, INT1, CNTR0, CNTR1, S CK , S IN Ta = 25 °C Supply voltage V DD (V) V IH /V IL (V) V IH (rating value) V IL (rating value) V IH 3.
4513/4514 Group User’s Manual APPENDIX 3-21 3.3 List of precautions 3.3 List of precautions ➀ Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx.
3-22 APPENDIX 3.3 List of precautions 4513/4514 Group User’s Manual ➉ A-D con ver ter-1 When the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 in a program, be careful about the following notes.
4513/4514 Group User’s Manual APPENDIX 3-23 3.3 List of precautions 16 V oltage compar ator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode .
3-24 APPENDIX 3.4 Notes on noise 4513/4514 Group User’s Manual 3.4 Notes on noise Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
4513/4514 Group User’s Manual APPENDIX 3-25 3.4 Notes on noise (3) Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible.
3-26 APPENDIX 3.4 Notes on noise 4513/4514 Group User’s Manual ( 5 ) Wiring to V PP pin of O ne Time PROM version In the built-in PROM version of the 4513/4514 Group, the CNV SS pin is also used as the built-in PROM power supply input pin V PP .
4513/4514 Group User’s Manual APPENDIX 3-27 3.4 Notes on noise 3.4.3 Wiring to analog input pins • Connect an approximately 100 Ω to 1 k Ω resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
3-28 APPENDIX 3.4 Notes on noise 4513/4514 Group User’s Manual Fig. 3.4.9 Wiring to a signal line where potential levels change frequently (3) Oscillator protection using V SS pattern As for a two-s.
4513/4514 Group User’s Manual APPENDIX 3-29 3.4 Notes on noise <The main routine> • Assigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine.
3-30 APPENDIX 4513/4514 Group User’s Manual 3.5 Mask ROM order confirmation form 3.5 Mask ROM order confirmation form 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box).
4513/4514 Group User’s Manual APPENDIX 3-31 3.5 Mask ROM order confirmation form ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data.
3-32 APPENDIX 4513/4514 Group User’s Manual 3.5 Mask ROM order confirmation form ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data.
4513/4514 Group User’s Manual APPENDIX 3-33 3.5 Mask ROM order confirmation form ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data.
3-34 APPENDIX 4513/4514 Group User’s Manual 3.5 Mask ROM order confirmation form ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data.
4513/4514 Group User’s Manual APPENDIX 3-35 3.5 Mask ROM order confirmation form ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data.
3-36 APPENDIX 4513/4514 Group User’s Manual 3.6 Mark specification form 3.6 Mark specification form 32P4B (32-PIN SHRINK DIP) MARK SPECIFICA TION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
4513/4514 Group User’s Manual APPENDIX 3-37 3.6 Mark specification form 32P6B (32-PIN LQFP) MARK SPECIFICA TION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B), and enter the Mitsubishi catalog name and the special mark (if needed).
3-38 APPENDIX 4513/4514 Group User’s Manual 3.6 Mark specification form 42P2R-A (42-PIN SHRINK SOP) MARK SPECIFICA TION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed).
4513/4514 Group User’s Manual APPENDIX 3-39 3.7 Package outline 3.7 Package outline SDIP32-P-400-1.78 Weight(g) – 2.2 JEDEC Code EIAJ Package Code Lead Material Alloy 42/Cu Alloy 32P4B Plastic 32pin 400mil SDIP Symbol Min Nom Max A A 2 b b 1 b 2 c E D L Dimension in Millimeters A 1 0.
3-40 APPENDIX 4513/4514 Group User’s Manual 3.7 Package outline SSOP42-P-450-0.80 Weight(g) – JEDEC Code 0.63 EIAJ Package Code Lead Material Alloy 42/Cu Alloy 42P2R-A Plastic 42pin 450mil SSOP Symbol Min Nom Max A A 2 b c D E L L 1 y Dimension in Millimeters H E A 1 I 2 – – .
MITSUBISHI SEMICONDUCTORS USER’S MANUAL 4513/4514 Group Dec. First Edition 1998 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
Rev. Rev. No. date 1.0 First Edition 981211 REVISION DESCRIPTION LIST 4513/4514 GROUP USER'S MANUAL (1/1) Revision Description.
User’ s Man ual 4513/4514 Group © 1998 MITSUBISHI ELECTRIC CORPORATION. New publication, effective Dec. 1998. Specifications subject to change without notice.
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Wenn Sie Renesas 4514 noch nicht gekauft haben, ist jetzt ein guter Moment, um sich mit den grundliegenden Daten des Produkts bekannt zu machen. Schauen Sie zuerst die ersten Seiten der Anleitung durch, die Sie oben finden. Dort finden Sie die wichtigsten technischen Daten für Renesas 4514 - auf diese Weise prüfen Sie, ob das Gerät Ihren Wünschen entspricht. Wenn Sie tiefer in die Benutzeranleitung von Renesas 4514 reinschauen, lernen Sie alle zugänglichen Produktfunktionen kennen, sowie erhalten Informationen über die Nutzung. Die Informationen, die Sie über Renesas 4514 erhalten, werden Ihnen bestimmt bei der Kaufentscheidung helfen.
Wenn Sie aber schon Renesas 4514 besitzen, und noch keine Gelegenheit dazu hatten, die Bedienungsanleitung zu lesen, sollten Sie es aufgrund der oben beschriebenen Gründe machen. Sie erfahren dann, ob Sie die zugänglichen Funktionen richtig genutzt haben, aber auch, ob Sie keine Fehler begangen haben, die den Nutzungszeitraum von Renesas 4514 verkürzen könnten.
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