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OME-PIO-D96 User Manual OME-PIO-D96 User Manual (Ver.1.1, Mar/ 2003, PPH-008-11) ---- 1.
Table of Contents 1. INTRODUCTION ........................................................................................................................... 3 1.1 F EATURES .............................................................................
1. Introduction The OME-PIO-D96 provides 96 TTL dig ital I/O lines. The OME-PIO-D96 consists of four 24-bit bi-directional por ts. Each 24-bit port supports three 8-bit groups PA, PB & PC. Each 8-bit group can be configured to function as either inputs or latched outputs.
1.2 Specifications • All inputs are TTL compatible Logic high voltage: 2.4V (Min.) Logic low voltage: 0.8V (Max.) • All outputs are TTL compatible Sink current: 64mA (Max.
1.4 PCI Data Acquisition Family We provide a family of PCI bus data acquisition cards. These cards can be divided into three groups as follows: 1. OME-PCI-series: first generation, isolated or non-iso.
2. Hardware configuration 2.1 Board Layout CN1 PCI BUS CN2 CN3 CN4 OME- PIO-D96 port0 port1 port2 port3 port4 port5 port6 port7 port8 port 9 port10 port11 OME-PIO-D96 User Manual (Ver.
2.2 I/O port Location There are twelve 8-bit I/O por ts in the OME-PIO-D96. Every I/O port can be programmed as D/I or D/O port. W hen the PC is first powered up, all twelve ports are used as D/I port.
2.4 D/I/O Architecture disable input Latch Clock input D/O latch CKT RESET (Sec. 3.3.1) Data (Sec. 3.3.8) D/I/O disable Buffer input Clock input D/I buffer CKT Data (Sec.
2.5 Interrupt Operation All P2C0, P5C0, P8C0 and P11C0 can be us ed as interrupt signal sources. Refer to Sec. 2.1 & Sec. 2.7 for P2C0/P5C0/P8C0/P11C0 location. The interrupt of OME- PIO-D96 is level-trigger & Active_High . The interrupt signal can be inverted or non-inverted programmable.
2.5.1 Interrupt Block Diagram of OME-PIO-D96 INT_CHAN_0 INT_CHAN_1 INT_CHAN_2 INT_CHAN_3 INT Level_trigger initial_low active_high The interrupt output signal of OME-PIO-D96, INT, is Level_trigger & Active_Low . If the INT generate a low-pulse, the OME-PIO-D96 will interrupt the PC only once.
2.5.2 INT_CHAN_0/1/2/3 INT_CHAN_0 (1/2/3) Inverted/Noninverted select INV0(1/2/3) Enable/Disable select EN0(1/2/3) P2C0(P5C0/P8C0/P11C0) The INT_CHAN_0(1/2/3) must be fixed in low level state normally and generated a high_pulse to interrupt the PC. The EN0 (EN1/EN2/EN3) can be used to enable/disable the INT_CHAN_0(1/2/3) as follows: (Refer to Sec.
2.5.3 Initial_high, active_low Interrupt source If the P2C0 is an initial_high, active_lo w signal, the interrupt service routine should use INV0 to invert or not to i nvert the P2C0 for high_pulse generation as follows: (Refer to DEMO4.
2.5.4 Initial_low, active_high Interrupt source If the P2C0 is an initial_low, active_hi gh signal, the interrupt service routine should use INV0 to invert or not to i nvert the P2C0 for high_pulse generation as follows: (Refer to DEMO3.
2. 5 .5 Muliti Interrupt Source Assume: P2C0 is initial Low, active High, P5C0 is initial High, active Low P8C0 is initial Low, active High P11C0 is initial High, active Low as follows: P5C0 P2C0 P8C0 P11C0 P2C0 & P5C0 are return to normal at the same time.
void interrupt irq_service() { new_int_state=inportb(wBase+7)&0x0f; /* read all interrupt state */ int_c=new_int_state^now_int_state; /* compare which interrupt */ /* signal be change */ if ((int_.
2.6 Daughter Boards 2.6.1 OME-DB-37 The OME-DB-37 is a general purpose daughter board for D-sub 37 pins. It is designed for easy wire connection. 2.6.2 OME-DN-37 & OME-DN-50 The OME-DN-37 is a general purpose daughter board for D- sub 37 -pin connector .
2.6.4 OME-ADP-37/PCI & OME-ADP-50/PCI The OME-ADP-37/PCI & OME-ADP-50/PCI are extenders for 50-pin headers. One side of OME-ADP-37/PCI & OME-ADP-50/PCI can be connected to a 50-pin header. The other side can be mounted on the PC chassis as follows: OME-ADP-37/PCI: 50-pin header to D- sub 37 extender.
2.6.5 OME-DB-24P/24PD Isolated Input Board The OME-DB-24P is a 24 channel isolat ed digital input daughter board. The optically isolated inputs of the OME-DB -24P, consists of a bi-directional opto- coupler with a resistor for current sens ing.
2.6.6 OME-DB-24R/24RD Relay Board The OME-DB-24R, 24 channel relay output board, consists of 24 form C relays for efficient switch of load by programmed c ontrol. The relays are energized by apply 12V/24V signal to the appropriated relay ch annel on the 50-pin flat connector.
2.6.7 OME-DB-24PR/24POR/24C OME-DB-24PR 24*power relay, 5A/250V OME-DB-24POR 24*Photo MOS relay, 0.1A/350VAC OME-DB-24C 24*open collector, 100mA per channel, 30V max. The OME-DB-24PR, 24 channel power rela y output board, consists of 8 form C and 16 form A electromechanical relays for efficient switching of load by programmed control.
2.6.8 Daughter Boards Comparison Table 20-pin flat-cable 50-pin flat-cable D-sub 37-pin OME-DB-37 No No Yes OME-DN-37 No No Yes OME-ADP-37/PCI No Yes Yes OME-ADP-50/PCI No Yes No OME-DB-24P No Yes No .
2.7 Pin Assignment CN1: 37 pin of D-type female c onnector. (For Port0, Port1, Port2) Pin Number Description Pin Num ber Description 1 N. C. 20 VCC 2 N. C. 21 GND 3 P1B7 22 P2C7 4 P1B6 23 P2C6 5 P1B5 24 P2C5 6 P1B4 25 P2C4 7 P1B3 26 P2C3 8 P1B2 27 P2C2 9 P1B1 28 P2C1 10 P1B0 29 P2C0 11 GND 30 P0A7 12 N.
CN2/CN3/CN4: 50-pin of flat-cable connector (for Port3 ~ Port11) Pin Number Description Pin Num ber Description 1 P5C7/P8C7/P11C7 2 GND 3 P5C6/P8C6/P11C6 4 GND 5 P5C5/P8C5/P11C5 6 GND 7 P5C4/P8C4/P11C.
3. I/O Control Register 3.1 How to Find the I/O Address The plug & play BIOS will assign a prope r I/O address to every OME-PIO/PISO series card in the power-up stage.
3.1.1 PIO_DriverInit PIO_DriverInit(&wBoards, wSubVendor,w SubDevice,wSubAux) • wBoards=0 to N Æ number of boards found in this PC • wSubVendor Æ subVendor ID of board to find • wSubDevice Æ subDevice ID of board to find • wSubAux Æ subAux ID of board to find This function can detect all OME-PIO/PISO series card in the system.
OME - PIO - D96 U ser Manual ( Ver.1.1, Mar/2003) ---- 26 The Sub IDs of OME - PIO/PISO series card are given as follows: OME - PIO/PISO series card Description Sub_vendo Old (New) Sub_device Old (New) Sub_AUX OME - PIO - D144 (Rev4.0) 144 × D/I/O 80 (5C80) 01 00 O ME - PIO - D96 (Rev4.
3.1.2 PIO_GetConfigAddressSpace PIO_GetConfigAddressSpace(wBoardNo,*wBase,*w Irq, *wSubVendor, *wSubDevice,*wSubAux,*w SlotBus, *wSlotDevice) • wBoardNo=0 to N Æ totally N+1 boards found by PIO_DriveInit(….
3.1.3 Show_PIO_PISO Show_PIO_PISO(wSubVendor,wSubDevice,w SubAux) • wSubVendor Æ subVendor ID of board to find • wSubDevice Æ subDevice ID of board to find • wSubAux Æ subAux ID of board to find This function will output a text string for these special subIDs.
3.2 The Assignment of I/O Address The plug & play BIOS will assign the pr oper I/O address to PIO/PISO series card. If there is only one PIO/PISO board, the user can identify the board as card_0.
3.3 The I/O Address Map The I/O address of OME-PIO/PISO series card is automatically assigned by the main board ROM BIOS. The I/O address can also be re- assigned by user. It is strongly recommended not to change the I/O address by user. The plug & play BIOS will a ssign proper I/O address to each OME-PIO/PISO series card very well.
3.3.1 RESET Control Register (Read/Write): wBase+0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESET Note. Refer to Sec. 3.1 for more information about wBase. When the PC is first power-on, the RESET signal is in Low-state.
3.3.4 INT Mask Control Register (Read/Write): wBase+5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 EN3 EN2 EN1 EN0 Note. Refer to Sec. 3.1 for more information about wBase.
3.3.6 Interrupt Polarity Control Register (Read/Write): wBase+0x2A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 INV3 INV2 INV1 INV0 Note. Refer to Sec.
3.3.7 I/O Selection Control Register (Write): wBase+0xcc Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 Port2 Port1 Port0 (Write): wBase+0xdc Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0.
3.3.8 Read/Write 8-bit data Register (Read/Write):wBase+0xc0/0xc4/0xc8/0xd0/0xd4/0xd8/ 0xe0/0xe4/0xe8/0xf0/0xf4/0xf8/ Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 Note. Refer to Sec. 3.1 for more information about wBase. There are twelve 8-bit I/O port in the OME-PIO-D96.
4. Demo program It is recommended to read the release note f irst. All important inform ation will be given in release note as follows: 1. Where you can find the software driver & utility? 2. How to install software & utility? 3. Where is the diagnostic program? 4.
4.1 PIO_PISO /* ------------------------------------------------------------ */ /* Find all PIO_PISO series cards in this PC system */ /* step 1 : plug all PIO_PISO cards into PC */ /* step 2 : run PIO_PISO.EXE */ /* ------------------------------------------------------------ */ #include "PIO.
4.1.1 PIO_PISO.EXE for Windows User can find this utility in the software CD or floppy disk. It is useful for all OME-PIO/PISO series cards. After executing the utility, detailed information f or all OME-PIO/PISO cards that are installed in the PC will be shown as follows: OME-PIO-D96 User Manual (Ver.
4.2 DEMO1 /* demo 1 : D/O demo of CN1 */ /* step 1 : connect a OME-DB-24C to CN1 of OME-PIO-D96 */ /* step 2 : run DEMO1.EXE */ /* step 3 : check the LEDs of OME-DB-24C will turn on sequentially*/ /* -------------------------------------------------------------- */ #include "PIO.
4.3 DEMO2 /* demo 2 : DI/O demo of CN2 - CN3 */ /* step 1 : connect CN2 t0 CN3 of OME-PIO-D96 */ /* step 2 : run DEMO2.EXE */ /* step 3 : check the information on screen D/I will same as D/O */ /* -------------------------------------------------------------- */ #include "PIO.
4.4 DEMO3 /* demo 3 : Count high pulse of P2C0 */ /* (initial Low & active High) */ /* step 1 : run DEMO3.EXE */ /* -------------------------------------------------------------- */ #include "PIO.
{ irqmask=inportb(A1_8259+1); 0xfb); /* IRQ2 */ 0xff ^ (1<<(wIrq-8))); tportb(wBase+5,1); /* enable interrupt (P2C0) */ d interrupt irq_service() /* now P2C0 change to low */ rq>=8) outportb(.
4.5 DEMO4 /* demo 4 : Count high pulse of P2C0 */ /* (initial High & active Low) */ /* step 1 : run DEMO4.EXE */ /* -------------------------------------------------------------- */ #include "PIO.
{ irqmask=inportb(A1_8259+1); 0xfb); /* IRQ2 */ 0xff ^ (1<<(wIrq-8))); tportb(wBase+5,1); /* enable interrupt (P2C0) */ d interrupt irq_service() /* now P2C0 change to low */ outportb(A1_8259+1,.
4.6 DEMO5 /* demo 5 : Four interrupt sources */ /* P2C0 : initial Low , active High */ /* P5C0 : initial High , active Low */ /* P8C0 : initial Low , active High */ /* P11C0 : initial High , active Low */ /* step 1 : run DEMO5.EXE */ /* -------------------------------------------------------------- */ #include "PIO.
disable(); se+5,0); /* disable all interrupt */ mask=inportb(A1_8259+1); 0xff ^ (1<<wIrq)); mask=inportb(A1_8259+1); 0xfb); /* IRQ2 */ =0x05; +0x2a,invert); /* P2C0 = non-inverte input */ ------.
else /* now P5C0 change to low */ _L2++; =invert^2; /* generate a high pulse */ if ((new_int_state&0x04)!=0) /* now P8C0 change to high */ ((new_int_state&0x08)!=0) /* now P11C0 change to high.
W ARRANTY / DISCLAIMER OMEGA ENGINEERING, INC. warrants this unit to be free of defects in materials and workmanship for a period of 13 months from date of purchase. OME GA ’ s W ARRANTY adds an additional one (1) month grace period to the normal one (1) year product warranty to cover handling and shipping time.
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