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KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 1 of 120 Ver. 0.9 KS152JB2 1.0 INTR ODUCTION The 80C152 Uni versal Communications Controller is an 8-bit microcontroller designed for the intelligent management of peripheral systems or components.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 2 of 120 Ver. 0.9 KS152JB2 POR T 4 DRIVERS POR T 0 DRIVERS POR T 2 DIR VERS RAM ADDRESS REGISTER RAM 25.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 3 of 120 Ver. 0.9 KS152JB2 2.1 Pin Description T able 1: PIN DESCRIPTION Name Description Port 0 Port 0 is an 8-bit open drain bi-directional I/O Port. As an output port each pin can sink 8 LS TTL inputs.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 4 of 120 Ver. 0.9 KS152JB2 Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pullups. Port 3 pins that ha v e 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 5 of 120 Ver. 0.9 KS152JB2 ALE Address Latch Enable output signal for latching the lo w byte of the address during accesses to external memory .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 6 of 120 Ver. 0.9 KS152JB2 2.2 Special function Registers The follo wing table lists the SFR’ s present in 80152. Note that not all the addresses are occupied by SFR’ s.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 7 of 120 Ver. 0.9 KS152JB2 between the RST pin being pulled lo w and the internal reset being generated. During this time the CPU continues its normal operations.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 8 of 120 Ver. 0.9 KS152JB2 2.4 POR T STRUCTURES AND OPERA TION The ports are all bidirectional. Each port consists of two sections, the port SFR and the I/O pad.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 9 of 120 Ver. 0.9 KS152JB2 As sho wn in Figure abov e, Ports 0 and 2 can emit either their respectiv e SFR contents or the ADDR/D A T A and ADDRESS bus, depending upon the control lines IDN AMX and IDN AHI.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 10 of 120 Ver. 0.9 KS152JB2 Writing to a Port During the ex ecution of an instruction that changes the v alue of a port SFR, the ne w value arri v es at the port latch during S6P2.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 11 of 120 Ver. 0.9 KS152JB2 2.6 A CCESSING EXTERNAL MEMOR Y External Memory is accessed if either of the follo wing two conditions is met 1) The signal EA is lo w 2) Whene ver the program counter (PC) contains an address greater than 0FFFh.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 12 of 120 Ver. 0.9 KS152JB2 During External Memory Accesses, both Ports 0 and 2 are used for Address/ Data transfer and therefore cannot be used for general I/O purposes.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 13 of 120 Ver. 0.9 KS152JB2 The “T imer” or “Counter” function is selected by the “C/T” bit in the TMOD Special Function Register .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 14 of 120 Ver. 0.9 KS152JB2 MODE 1 Mode 1 is similar to Mode 0 except that the counting re gister form a 16 bit counter , rather than a 13 bit counter . This means that all the bits of THx and TLx are used.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 15 of 120 Ver. 0.9 KS152JB2 Mode 3 is used in cases where an extra 8 bit timer is needed. W ith T imer 0 in Mode 3, T imer 1 can be turned on and of f by switching it out of and into its own Mode 3.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 16 of 120 Ver. 0.9 KS152JB2 case of le vel triggered interrupt, the IE0 and IE1 flags are not cleared and will ha ve to be cleared by the software.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 17 of 120 Ver. 0.9 KS152JB2 Interrupt enable register for DMA and GSC interrupts. A 1 in an y bit position enables that interrupt. IEN1.0 (EGSR V) - Enables the GSC valid recei v e interrupt.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 18 of 120 Ver. 0.9 KS152JB2 The interrupt flags are sampled in S5P2 of e very machine c ycle. In the next machine c ycle, the sampled interrupts are polled and their priority is resolved.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 19 of 120 Ver. 0.9 KS152JB2 Execution continues from the v ectored address till an RETI instruction is ex ecuted. On ex ecution of the RETI instruction the processor pops the Stack and loads the PC with the contents at the top of the stack.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 20 of 120 Ver. 0.9 KS152JB2 v alues are polled only in the next machine c ycle. If a request is activ e and all three conditions are met, then the hardware generated LCALL is e x ecuted.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 21 of 120 Ver. 0.9 KS152JB2 2.9 P ower Down and Idle The processor has two Po wer Reduction modes, Idle and Po wer Do wn. Backup power is supplied through the VCC pin in these operations.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 22 of 120 Ver. 0.9 KS152JB2 There are two w ays to terminate the Idle mode. One way is to reset the processor and the other is by acti vation of an y enabled interrupt.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 23 of 120 Ver. 0.9 KS152JB2 The DMA circuitry stops operation in both Idle and po wer Down modes. Since operation is stopped in both modes, the process should be similar in each case.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 24 of 120 Ver. 0.9 KS152JB2 MODE 1 In Mode 1, the full duplex mode is used. Serial communication frames are made up of 10 bits transmitted on TXD and recei ved on RXD.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 25 of 120 Ver. 0.9 KS152JB2 Reception is enabled only if REN is high. The serial port actually starts the recei ving of serial data, with the detection of a falling edge on the RxD pin.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 26 of 120 Ver. 0.9 KS152JB2 If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set. Else the recei ved frame may be lost.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 27 of 120 Ver. 0.9 KS152JB2 MODE 3 This mode is similar to Mode 2 in all respects, except that the baud rate is programmable. In all four modes, transmission is started by any instruction that uses SB UF as a destination regis- ter .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 28 of 120 Ver. 0.9 KS152JB2 Baud Rates In Mode 0 the baud rate is fixed at 1/12 of the oscillator frequenc y . In Mode 2 the baud rate depends on the v alue of bit SMOD in PCON SFR.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 29 of 120 Ver. 0.9 KS152JB2 in auto-reload mode. In such a case the baud rate is gi ven by Mode 1,3 bau.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 30 of 120 Ver. 0.9 KS152JB2 2.11 SINGLE-STEP OPERA TION The processor does not ha ve an y pin which can directly force it to operate in the single-step mode.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA Inc. Page 31 of 120 Ver. 0.9 KS152JB2 T able 8: Instruction T able lsn msn 012345 6 - 7 8 - F 0 nop ajmp ljmp rr a.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 32 of 120 Ver. 0.9 KS152JB2 3.0 GLOB AL SERIAL CHANNEL 3.1 Introduction The Global Serial Channel (GSC) is a multi-protocol, high performance serial interface tar geted for data rates up to 2 MBPS with on-chip clock recov ery , and 2.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 33 of 120 Ver. 0.9 KS152JB2 T able 9: N-Not av ailable.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 34 of 120 Ver. 0.9 KS152JB2 External clock Internal clock NM NOONOOOOONOOOO OONOOOOOOOOOOOOO Control cp.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 35 of 120 Ver. 0.9 KS152JB2 CRC: NONE 16-bit CCITT 32-bitA UTODIN II NNN 1 1 11N N 11111111 OOO O O OOOOOOOO1 1 OO OOO O O OOOOOOOO1 1 OO Half Duples Full Duplex OOO O O OOOOOOOOOOOO NNN O O OONNOOOONNNP Ackno wledge: None Hardware User defined.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 36 of 120 Ver. 0.9 KS152JB2 Note 1: Programmable in Raw transmit or recei v e mode. Almost all the options a vailable from T able can be implemented with the proper software to per- form the functions that are necessary for the options selected.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 37 of 120 Ver. 0.9 KS152JB2 be in some other mode than the user intends for a significant amount of time after reset.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 38 of 120 Ver. 0.9 KS152JB2 PREAMBLE - The preamble is a series of alternating 1s and 0s. The length of the preamble is programmable to be 0, 8, 32, or 64 bits.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 39 of 120 Ver. 0.9 KS152JB2 The CRC generato r , as sh o wn in figure bel o w , operates by taking each bit as it is rece i v ed and XOR’ing it with bit 31 of the current CRC.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 40 of 120 Ver. 0.9 KS152JB2 link remains high for 2 or more bit times. 3.2.3 INTERFRAME SP A CE The interframe space is the amount of time that transmission is delayed after the link is sensed as being idle and is used to separate transmitted frames.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 41 of 120 Ver. 0.9 KS152JB2 3.2.4 CSMA/CD D A T A ENCODING Manchester encoding/decoding is automatically selected when the user software selects CSMA/ CD transmission mode (See Figure belo w).
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 42 of 120 Ver. 0.9 KS152JB2 Narro w Pulses A v alid Manchester wa veform must stay high or lo w for at least a half bit-time, nominally 4 sam- ple-times.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 43 of 120 Ver. 0.9 KS152JB2 3.2.6 RESOLUTION OF COLLISIONS Ho w the GSC responds to a detected collision depends on what it was doing at the time the colli- sion was detected.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 44 of 120 Ver. 0.9 KS152JB2 If a transmitting 8XC152 detects a collision during the preamble/BOF part of the frame that it is trying to transmit, it will complete the preamble/BOF and then begin the jam signal in the first bit time after BOF .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 45 of 120 Ver. 0.9 KS152JB2 Random Backoff In either of the random algorithms, the first thing that happens after a collision is detected is that a I gets shifted into the TCDCNT (T ransmit Collision Detect Count) re gister , from the right.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 46 of 120 Ver. 0.9 KS152JB2 BK OFF starts counting do wn from its preload v alue, counting slot times. At any time, the current v alue in BK OFF can be read by the CPU, but CPU writes to BK OFF ha ve no ef fect.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 47 of 120 Ver. 0.9 KS152JB2 The highest slot assignment in the network is written by each station’ s software into its TCDCNT register .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 48 of 120 Ver. 0.9 KS152JB2 interframe space and the preamble length such that the ackno wledge is completed before IFS expires. This is normally done by programming IFS lar ger than the preamble.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 49 of 120 Ver. 0.9 KS152JB2 3.3 SDLC Operation SDLC is a communication protocol de veloped by IBM and widely used in industry . It is based on a primary/ secondary architecture and requires that each secondary station hav e a unique address.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 50 of 120 Ver. 0.9 KS152JB2 number of address bits, but the automatic address recognition feature w orks on a maximum of 16- bits. In SDLC the address are normally unique for each station.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 51 of 120 Ver. 0.9 KS152JB2 that the correct remainder is left. The remainder that is checked for is 001110100001111B (1D0F Hex). If there is a mismatch, an error is generated.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 52 of 120 Ver. 0.9 KS152JB2 required for implementing bit stuf fing and striping are incorporated into the GSC hardware. This makes the operation transparent to the user .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 53 of 120 Ver. 0.9 KS152JB2 count must be done by the user software. The Hardw are Based Acknowledge option that is pro- vided in the C152 is not compatible with standard SDLC protocol.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 54 of 120 Ver. 0.9 KS152JB2 3.3.9 HDLC/SDLC COMP ARISON HDLC (High le vel Data Link Control) is a standard adopted by the International Standards Or ga- nization (ISO).
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 55 of 120 Ver. 0.9 KS152JB2 3.5 USING THE GSC 3.5.1 LINE DISCIPLINE Line discipline is ho w the management of the transfer of data ov er the physical medium is con- trolled.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 56 of 120 Ver. 0.9 KS152JB2 Some of the general areas that will impact the ov erall scheme on ho w to incorporate future changes to the system are: 1) Communication of the change to all the stations or the primary station.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 57 of 120 Ver. 0.9 KS152JB2 registers. On the DMA channel servicing the recei v er , the control re gister needs to be loaded as follo ws: DCONn.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 58 of 120 Ver. 0.9 KS152JB2 this same DMA bit. The interrupts EGSTE (IEN1.5), GSC transmit error; EGSTV (IEN1.3), GSC transmit v alid; EGSRE (IEN1.1), GSC recei ve error; and EGSR V (IEN1.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 59 of 120 Ver. 0.9 KS152JB2 specified in the data sheet.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 60 of 120 Ver. 0.9 KS152JB2 inquiry for the address check, a timer is also started. If the timer expires before the inquiry is responded to, then that station assumes the address chosen is okay .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 61 of 120 Ver. 0.9 KS152JB2 age and currents that the GSC is capable of providing are the same le v els as those for normal port operation. The signal used to enable the external dri v ers is DEN.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 62 of 120 Ver. 0.9 KS152JB2 3.5.9 T ransmit W avef orms The CSC is capable of three types of data encoding, Manchester , NRZI, and NRZ. Figure sho ws example of all three types of data encoding.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 63 of 120 Ver. 0.9 KS152JB2 3.5.10 Receiv er Clock Recovery The recei ver is al ways monitored at eight times the baud rate frequency , except when an e xternal clock is used.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 64 of 120 Ver. 0.9 KS152JB2 3.5.11 External Clocking T o select external clocking, the user is gi v en three choices. External clocking can be used with the transmitter , with the recei v er , or with both.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 65 of 120 Ver. 0.9 KS152JB2 to each station. When using 16-bit addressing, ADR0:ADR1 form one address and ADR2:ADR3 form the second address. If the recei ver is enabled, it looks for a matching address after e very BOF flag is detected.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 66 of 120 Ver. 0.9 KS152JB2 and then writing to TFIFO.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 67 of 120 Ver. 0.9 KS152JB2 expected. When this type of collision occurs the GSC automatically handles the retransmission attempts for as many as eight tries.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 68 of 120 Ver. 0.9 KS152JB2 would be one interframe space period after the line is sensed as being idle. As the number of stations approach 256 the probability of a successful transmission decreases rapidly .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 69 of 120 Ver. 0.9 KS152JB2 bits. Writing a one to a bit in AMSK0,1 masks out that corresponding bit in ADDR0,1. B A UD (94H) -GSC Baud Rate Generator - Contains the v alue of the programmable baud rate.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 70 of 120 Ver. 0.9 KS152JB2 can be masked in AMSK1:AMSK0. A recei v ed address of all ones will always be recognized in any mode. The user softw are is responsible for setting or clearing this flag.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 71 of 120 Ver. 0.9 KS152JB2 MYSLO T .0, 1,2,3,4,5 - Slot Address -The six address bits choose 1 of 64 slot addresses. Address 63 has the highest priority and address 1 has lo west.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 72 of 120 Ver. 0.9 KS152JB2 PCON.3(XRCLK) -GSC External Recei ve Clock Enable- Writing a 1 to XRCLK enables an external clock to be applied to pin 5(Port 1.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 73 of 120 Ver. 0.9 KS152JB2 data. The recei ve FIFO is a three byte b uf fer into which the recei ve data is loaded. A CPU read of the FIFO retrie ves the oldest data and automatically updates the FIFO pointers.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 74 of 120 Ver. 0.9 KS152JB2 TCDCNT (0D4H) - T ransmit Collision Detect Count Contains the number of collisions that ha ve occurred if probabilistic CSMA/CD is used.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 75 of 120 Ver. 0.9 KS152JB2 recei ved, TDN is not set. An ackno wledge is not expected follo wing a broadcast or multi-cast packet. The status of this flag is controlled by the GSC.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 76 of 120 Ver. 0.9 KS152JB2 4.0 DMA Operation The C152 contains DMA (Direct Memory Accessing) logic to .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 77 of 120 Ver. 0.9 KS152JB2 DMA Registers T wo bits in DCONn are used to specify the physical destination of the data transfer . These bits are D AS (Destination Address Space) and ID A (Increment Destination Address).
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 78 of 120 Ver. 0.9 KS152JB2 There are four modes in which the DMA channel can operate. These are selected by the bits DM and TM (Demand Mode and T ransfer Mode) in DCONn: The operating modes are described belo w .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 79 of 120 Ver. 0.9 KS152JB2 during the DMA, so interrupt flags may get set, but since program e xecution is suspended, the interrupts will not be serviced while the DMA is in progress.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 80 of 120 Ver. 0.9 KS152JB2 is still 1 and the DONE bit is still 0. An external interrupt is not generated in this case, since in le vel-acti v ated mode, pulling the pin to a logical 1 clears the interrupt flag.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 81 of 120 Ver. 0.9 KS152JB2 DMA T ransfer from Internal Memory to External Memory DMA T ransfer from Ex.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 82 of 120 Ver. 0.9 KS152JB2 4.3 Hold/Hold Acknowledge T wo operating modes of Hold/Hold Ackno wledge logic are a v ailable, and either or neither may be in v oked by software.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 83 of 120 Ver. 0.9 KS152JB2 The functions of the ARB and REQ bits in PCON, then, are 4.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 84 of 120 Ver. 0.9 KS152JB2 selects which CPU’ s ALE signal will be directed to the address latch. The Arbiter’ s ALE is selected if HLD A is high, and the Requester’ s ALE is selected if HLD A is lo w .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 85 of 120 Ver. 0.9 KS152JB2 When the arbiter wants to DMA the XRAM, it first acti v ates DMXRQ. This signal pre vents Q2 from being set if it is not already set.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 86 of 120 Ver. 0.9 KS152JB2 If the DMA is in alternate cycles mode, then each time DMA c ycle is completed DMXRQ goes to 0, thus de-acti v ating HLD.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc.oup, Inc. Page 87 of 120 Ver. 0.9 KS152JB2 Cycle is ex ecuted, on-chip arbitration logic determines which type of cycle is to be e xecuted ne xt.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 88 of 120 Ver. 0.9 KS152JB2 If the channel is configured to External Demand mode, then the first if-condition is not satisfied but the second one is. In that case the block of statements follo wing that if-condition and delim- ited by {.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 89 of 120 Ver. 0.9 KS152JB2 If the test for SARn = SBUF is true, and if the flag RI is set, mode_logic (n) returns as 1 and the remainder of the function is not ex ecuted.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 90 of 120 Ver. 0.9 KS152JB2 decides it wants to do Burst mode DMA. The sequence of e v ents might be: Instruction cycle (sets GO bit in DCON1) Instruction cycle (during which TFNF gets set) DMA0 cycle DMA1 cycle DMA1 cycle DMA1 cycle .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 91 of 120 Ver. 0.9 KS152JB2 4.5 Summary of DMA Contr ol Bits D AS specifies the Destination Address Space. If D AS = 0, the destination is in External Data Memory .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 92 of 120 Ver. 0.9 KS152JB2 ARB enables the DMA logic to detect HLD and generate HLD A. After it has acti v ated HLD A, the C152 will not begin a ne w DMA to or from External Data Memory as long as HLD is seen to be acti ve.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 93 of 120 Ver. 0.9 KS152JB2 As sho wn in Figure abov e, the Recei ve V alid interrupt can be signalled either by the RFNE flag (Recei ve FIFO Not Empty), or by the RDN flag (Recei v e Done).
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 94 of 120 Ver. 0.9 KS152JB2 Note that the locations of the basic 8051 interrupts are the same as in the rest of the MCS-51 Fam- ily . And relati ve to each other the y retain the same positions in the polling sequence.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 95 of 120 Ver. 0.9 KS152JB2 = 0 Disable EGSRE = 1 Enable GSC Recei ve Error Interrupt = 0 Disable EGSR .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 96 of 120 Ver. 0.9 KS152JB2 It is recommended that user software should ne ver write 1s to unimplemented bits in MCS-51 de vices. Further versions of the de vice may ha ve ne w bits installed in these locations.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 97 of 120 Ver. 0.9 KS152JB2 The UR bit can be set only if the DMA bit in the TST A T is set. The DMA bit being set informs the GSC hardware that TFIFO is being serviced by DMA.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 98 of 120 Ver. 0.9 KS152JB2 RDN from being set. A CRC Error means the CRC generator did not come to its correct v alue after calculating the CRC of the message plus recei ved CRC.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 99 of 120 Ver. 0.9 KS152JB2 AL - Address Length, see GMOD. AMSK0,1 (0D5H, 0E5H) - Address Match Mask 0,1 - Identifies which bits in ADR0,1 are “don’t care” bits.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 100 of 120 Ver. 0.9 KS152JB2 DCON0/1 (092H,093H) The DCON register control the operation of the DMA channels by determining the source of data to be transferred, the destination of the data to be transfer , and the v arious modes of operation.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 101 of 120 Ver. 0.9 KS152JB2 P1.2 is programmed to a 1. DM - DMA Mode, see DCON0 DMA - Direct Memory Access mode, see TST A T . DONE - DMA done bit, see DCON0.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 102 of 120 Ver. 0.9 KS152JB2 GMOD.0 (PR) - Protocol - If set SDLC protocols with NRZI encoding, zero bit insertion, and SDLC flags are used. If cleared, CSMA/CD link access with Manchester encoding is used.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 103 of 120 Ver. 0.9 KS152JB2 added to the 8051BH core to accomplish high-speed transfers of packetized serial data. GTxD - GSC T ransmit Data output, an alternate function of one of the port 1 pins (P1.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 104 of 120 Ver. 0.9 KS152JB2 IEN1 (0C8H) Interrupt enable register for DMA and GSC interrupts. A 1 in an y bit position enables that interrupt. IEN1.0 (EGSR V) - Enables the GSC valid recei v e interrupt.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 105 of 120 Ver. 0.9 KS152JB2 IPN1 (0F8H) Allo ws the user software two le v els of prioritization to be assigned to each of the interrupts in IEN1.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 106 of 120 Ver. 0.9 KS152JB2 MYSLO T .7 (DCJ) - Determines the type of Jam used during CSMA/CD operation when a collision occurs. If set to a 1 then a lo w D.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 107 of 120 Ver. 0.9 KS152JB2 PGSR V - Priority bit for GSC Receiv e V alid interrupt see IPN1. PGSTE - Priority bit for GSC T ransmit V alid interrupt, see IPN1.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 108 of 120 Ver. 0.9 KS152JB2 GREN has no ef fect on whether the recei v er detects a collision in CSMA/CD mode as the recei v er input circuitry always monitors the recei v e pin.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 109 of 120 Ver. 0.9 KS152JB2 SCON (098H) SCON.0 (RI) - Recei ve Interrupt Flag. SCON.1 - T ransmit Interrupt Flag. SCON.2 (RB8) - Recei v e Bit 8, contains the ninth bit that w as recei v ed in Modes 2 and 3 and stop bit in Mode 1 if SM20.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 110 of 120 Ver. 0.9 KS152JB2 TCON.3 (IE1) - External Interrupt 1 edge flag. TCON.4 (TR0) - T imer 0 run control bit. TCON.5 (TF0) - T imer 0 o verflo w flag.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 111 of 120 Ver. 0.9 KS152JB2 TMOD7 (GA TE) - Gating Mode bit for T imer 1.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 112 of 120 Ver. 0.9 KS152JB2 UR - Underrun Flag, see TST A T . XRCLK - External GSC Recei ve Clock Enable bit, see PCON. XTCLK - External GSC T ransmit Clock Enable bit, see GMOD.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 113 of 120 Ver. 0.9 KS152JB2 D A T A POINTER HIGH This is the high byte of the 16-bit data pointer . The DPH is reset to 00h by a reset. There is unrestricted read/write access to this SFR.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 114 of 120 Ver. 0.9 KS152JB2 TIMER MODE CONTR OL GA TE Gating control: When this bit is set, T imer/counter x is enabled only while INTx pin is high and TRx control bit is set.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 115 of 120 Ver. 0.9 KS152JB2 TL1.7-0 T imer 1 LSB The TL1 sfr is set to 00h on any reset. There is unrestricted read/write access to this SFR. TIMER 0 MSB TH0.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 116 of 120 Ver. 0.9 KS152JB2 SERIAL POR T CONTR OL SM0 Serial port, Mode 0 bit: The operation of SM0 is described below .
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 117 of 120 Ver. 0.9 KS152JB2 The SBUF sfr is set to 00h by a reset.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 118 of 120 Ver. 0.9 KS152JB2 CY Carry flag: Set for an arithmetic operation which results in a carry being generated from the ALU. It is also used as the accumulator for the bit operations.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 119 of 120 Ver. 0.9 KS152JB2.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 120 of 120 Ver. 0.9 KS152JB2.
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