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Docum ent N umber: 324971-002 Intel ® Xeon ® Processor E3-1200 Family Datasheet, Volum e 2 This is Volu me 2 of 2 June 201 1.
2 Datasheet , Volume 2 Legal L ines and Discl aimers INFORMAT ION IN THIS DOCUMENT IS PROVIDED IN CONNEC T ION WITH INTEL ® PROD UCTS. N O LICENSE, E XPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWI S E, TO ANY INT ELLECTUAL PROPE R TY RIGHTS IS G RANTED BY THIS D OCUMENT .
Datasheet , Volume 2 3 Contents 1 Intr oducti on .... ........ ........ ........ ...... ...... ........ ........ ...... ........ ........ ...... ........ .............. .. 11 2 Pro cessor Confi gur ation R egiste rs .... ........ ........ ...... .....
4 Datasheet , Volume 2 2.5. 9 SID—S ubs yste m Iden tificat ion R egis ter .. ........ ........ ...... ........ .......... ........ 5 4 2.5. 10 PXPEPB AR—P CI E xpre ss Egres s Po rt Ba se Addres s Regi ster . .... .......... ........ 5 5 2.5. 11 MCHBA R—Ho st Memo ry Map ped R egis ter Ra nge B ase Regi ster .
Datasheet , Volume 2 5 2.6. 25 PM_ CAPID 1—Pow er Ma nage ment Capab ilitie s Regis ter . .... ...... ........ ........ 106 2.6. 26 PM_ CS1—P ower M ana gemen t Co ntrol/S tatus Reg ister ......... ...... ........ ..... 1 07 2.6. 27 SS_C APID —Subsy stem ID and Ve ndor ID Ca pabil ities R egister .
6 Datasheet , Volume 2 2.10.4 P CIS TS6— PCI St atus Regis ter ... ........ ........ ........ ...... ........ ........ ...... ...... 1 49 2.10. 5 RID 6—Revi sion I dentific ation Regist er . ....... ........ ........ ........ ...... ........ .... 151 2.
Datasheet , Volume 2 7 2.12. 9 DMIV C1R CTL—DM I VC1 Reso urce Co ntrol Re giste r . . .... ........ ........ ...... .... 194 2.12. 10 D MIVC 1RST S—DM I VC 1 Res ource S tatu s Regi ste r . ........ ....... ........ ........ . 195 2.12. 11 D MIV CPRCAP —DMI V Cp Resou rce Ca pability Regi ster .
8 Datasheet , Volume 2 2.18.5 G STS _REG —Gl obal Sta tus Regis ter ..... ........ ........ ......... ...... ........ ........ .. 235 2.18.6 R TADD R_RE G—Ro ot- Entry Table A dd ress Re gist er ... ...... .......... ........ ...... 23 6 2.18.7 C CMD_ REG —Co ntext C omma nd R egis ter .
Datasheet , Volume 2 9 2.21. 16 PL MLIM IT_R EG—P rote cted L ow-M emory Limit R egi ster ... .......... ....... ....... 2 90 2.21. 17 PHM BAS E_REG —Pro tec ted Hi gh-Me mory B ase Reg ister .... ........ ........ ...... 29 1 2.21. 18 PHM LI MIT_RE G—P rotect ed Hig h-Mem or y Lim it Reg ister .
10 Datasheet , Volume 2 Revision History § § Revision Number Descrip tion Revision Date 001 Initial re lease April 2011 002 • Upda ted DSTS-Device S ta tus R e gister (B/D/F/T y pe: 0/ 1/0/PCI) • Added fou r registers t o Section 2.1 3, MCHBAR Registers in Mem ory Controller – Channel 0.
Datasheet , Volume 2 11 Introdu ction 1 Int rodu cti on This is V o lume 2 of the Da tashee t for the fo llowing produ cts: • Intel ® Xeon ® pr ocesso r E3- 1200 fa mily The p roces sor c ontai ns one or mor e PCI devic es wit hin a single p hysica l com ponen t.
Intr oductio n 12 Datasheet , Volume 2.
Datasheet , Volume 2 13 Processo r Configuration Reg isters 2 Pr oces sor Conf igur atio n Reg ist ers This chap ter con tains the fo llowin g: • Register termin ology • PCI De vic es and F unct ions o n pro cessor • System addre ss ma p • Proce ssor r egister i ntro duction • Detaile d re gister bi t des cript ions 2.
Proce ssor Config uration Registers 14 Datasheet , Volume 2 2.2 PCI D evices a nd Fun ctions on Proce ssor Note: 1. N ot all devices are enabled in a ll configurations. 2. S ee Section 2.8. 2, “DID2—D evice Identificatio n R egister” f or additional infor mation on graphics DID values.
Datasheet , Volume 2 15 Processo r Configuration Reg isters 2.3 Syste m Addre ss M ap The pro cess or suppo rts 51 2 GB (3 9 bit) o f addr essabl e me mory sp ace and 6 4 KB +3 of addres sabl e I/O space . This sectio n focu ses on how t he me mory s pace i s part ition ed and what the s eparate memo ry reg ions are u sed fo r .
Proce ssor Config uration Registers 16 Datasheet , Volume 2 The A ddr ess M ap incl udes a numb er of p rog rammabl e ranges : • Devic e 0 — PX PEPBA R – P xP egre ss po rt regi sters . (4 KB windo w) — MC HBAR – Me mory m ap ped rang e for i nternal MCH reg isters.
Datasheet , Volume 2 17 Processo r Configuration Reg isters Figu re 2-1 repr esent s sys tem m emory a ddre ss m ap in a s impli fied fo rm. Figu re 2- 1.
Proce ssor Config uration Registers 18 Datasheet , Volume 2 2.3.1 Legacy Address Range This area is divid ed into th e follow ing a ddress regio ns: • 0–640 KB – DOS Area • 640–7 68 K B – .
Datasheet , Volume 2 19 Processo r Configuration Reg isters 2. 3.1.2 Lega cy V ide o Are a (A _00 00 h–B _FF FFh) The l egacy 128 K B V GA mem ory r ang e, frame buffer , (00 0A_00 00h–0 00B_F FFF h) can be mapped to I GD (De vice 2), to PCI Express (Device 1 or D evice 6), and/o r to th e DM I Inte rface.
Proce ssor Config uration Registers 20 Datasheet , Volume 2 2. 3.1.3 PAM ( C_ 0000 h–F _FF FFh ) The 1 3 section s from 768 KB to 1 M B compris e what is al so kno wn as the PAM Memo ry Area. Ea ch sectio n h as Read e nable a nd Write e nable attrib utes .
Datasheet , Volume 2 21 Processo r Configuration Reg isters 2. 3.2.1 ISA Hol e (1 5 MB –1 6 MB ) The ISA Hole is enabled in th e L egacy A c cess Control Registe r in Device 0 co nfigur ation spac e. If n o hole is crea ted , the p roces sor w ill rout e the re ques t to D RAM.
Proce ssor Config uration Registers 22 Datasheet , Volume 2 for m anag ing DM A acc esses to ad dress es abo ve 4 GB . DMA-rem ap ping ha rdware imple me ntation s on p latforms sup port ing In tel TXT are req uired to s uppor t prot ected h igh-m em ory reg ion6, if t he platf orm su ppo rts m ain memo ry above 4 GB .
Datasheet , Volume 2 23 Processo r Configuration Reg isters 2. 3.2.6 GFX Stole n Spac es 2.3 .2.6.1 GTT S to l en Sp ace (GS M) GS M is allocated to st ore t he GF X transl ation ta ble en tries. GS M always e xist s regard less o f VT - d as lon g a s inter nal G FX is e nabl ed.
Proce ssor Config uration Registers 24 Datasheet , Volume 2 There are sub -ranges w ithin the PCI M em ory ad dress ran ge de fined as AP IC Con figuratio n Space , MS I Interr upt S pace , and H igh BIOS Addres s Range . The ex ceptions listed a bove fo r int ernal g raphics a nd t he PCI E xpress port s MUST NOT overl ap with th ese ran ges.
Datasheet , Volume 2 25 Processo r Configuration Reg isters 2. 3.3.1 APIC Con figu ratio n Sp ac e (FE C0_ 000 0 h–FEC F _FFFFh ) This range is reserve d for APIC c onfi guration sp ace. The I /O A PIC(s ) usual ly res ide in the PCH po rtion o f the c hip-s et, but m ay also ex ist a s sta nd-alo ne com pon ents li ke PXH.
Proce ssor Config uration Registers 26 Datasheet , Volume 2 2.3.4 Main Memory A dd ress Spa ce (4 GB to TOUUD) The p roces sor s uppor ts 39- bit add ressin g. The m axi mum m ain m emor y size support ed is 32 G B tota l DRA M mem ory . A hole bet ween TOLUD an d 4 GB occu rs wh en ma in m emory size approa ches 4 GB o r lar ger .
Datasheet , Volume 2 27 Processo r Configuration Reg isters 2. 3.4.1 Mem ory Re- clai m B ackg rou nd The fo llowin g are exa mples of Me mory M app ed I O devic es tha t a r e t ypical ly locat ed be.
Proce ssor Config uration Registers 28 Datasheet , Volume 2 2. 3.4.3 Mem ory Rem app ing An inco ming a dd ress (referr ed to as a logi cal addres s) i s chec ked to see if it falls in the memo ry re -ma p windo w . The b otto m of th e r e-map window is d efined by the val ue in the R EMA PBASE register .
Datasheet , Volume 2 29 Processo r Configuration Reg isters Case 1 – Less than 4 GB of Ph ysical Mem ory (no re map ) • P o pula ted Phys ical Memo ry = 2 GB • Addres s Spa ce a llocat ed to m e.
Proce ssor Config uration Registers 30 Datasheet , Volume 2 Case 2 – Great er tha n 4 G B of Phy sica l Memo ry In t his cas e th e amou nt of me mory re mapped is the range be twe en TOLU D and 4 G B. This ph ysical mem ory will be mapped t o the logica l a ddre ss r a nge de fined bet wee n the REMA PBA SE and the R EMAPL IMIT regist ers.
Datasheet , Volume 2 31 Processo r Configuration Reg isters The Re map w indow is in clusive o f the B ase a nd Lim it a ddress es. In the dec oder A[19: 0] of the Remap Ba se Ad dress a re ass ume d to be 0 s. Simi larly , A[1 9:0] of th e Remap Limit Addr ess are assu med to be Fhs.
Proce ssor Config uration Registers 32 Datasheet , Volume 2 Impl emen tatio n No tes • Remap appli es to tr ansactio ns from all int erfac es. All upstr eam PEG/D MI transac tions that are s nooped get re mappe d. • Upst ream P EG/ DMI trans actio ns that are n ot sn ooped ( “Sno op n ot requ ired” attrib ute s et) g et rem apped .
Datasheet , Volume 2 33 Processo r Configuration Reg isters 2.3.6 PCI Express* Graphics Attach (PEG) The p roces sor c an be programm ed to direc t me mory a ccess es to a PCI Expre ss inter face . Whe n add resse s are w ithin either of two r anges s pecifi ed us ing reg iste rs in each PEG(s ) config uration space .
Proce ssor Config uration Registers 34 Datasheet , Volume 2 2.3.7 Graphics Memory Address R anges The M CH c an be program med t o di rect memory acces ses to IGD whe n add resses are wit hin an y of five ra nges specified usin g regis ters in the proce ssor De vice 2 config uration spac e.
Datasheet , Volume 2 35 Processo r Configuration Reg isters 2.3.8 System Management Mod e (SMM) Unli ke FSB platfo rms, th e Core han dles a ll S MM mo de t r ans actio n routing . Also, the plat form no lo nger support s HS EG. The p roces sor will n e ver allow I/O d evices acc ess to CSEG/ TSEG/H SEG ranges.
Proce ssor Config uration Registers 36 Datasheet , Volume 2 2.3.11 I/O Address Space The s yste m agen t ge nerates either DMI Interfa ce o r PCI Expr ess * bus cycles for al l proc esso r I/O a ccesse s that it do es not clai m.
Datasheet , Volume 2 37 Processo r Configuration Reg isters The p roces sor a lso f orwards ac ces ses to the Le gacy VGA I /O rang es ac cording to th e set tings in the P EG con figuratio n reg iste rs BCT RL (VGA E nable ) and PCICM D (IOA E), unl ess a se cond a dapt er (m onochr ome ) is pr ese nt on the D MI Int erface/P CI (o r ISA ).
Proce ssor Config uration Registers 38 Datasheet , Volume 2 DM I Inte rface Access es t o th e Proc essor that C ro ss Devi ce Bo unda ries The p roces sor d oes no t supp ort tran sactio ns th at cros s devi ce bo undarie s. Th is s hould neve r occ ur bec ause PCI Exp res s transact ions a re no t allow ed to cross a 4 K B bou ndary .
Datasheet , Volume 2 39 Processo r Configuration Reg isters • VCm a ccess es — See the DMI2 specific ation for TC mappin g to VCm . VC m acc ess on ly ma p to ME stolen DRA M. Th ese tran sactio ns carry t he direct physical DRA M add ress (no redir ection o r rem appin g of any kin d will occur).
Proce ssor Config uration Registers 40 Datasheet , Volume 2 2. 3.13 .2 PC I Ex pres s* In te rface D ecode R ules All “S NOOP seman tic” P CI E xpre ss trans actions are kept coher ent w ith pro cess or cac hes. All “S noop n ot requ ired s em antic” cycles m ust refer ence the dire ct DR AM addres s range.
Datasheet , Volume 2 41 Processo r Configuration Reg isters 2. 3.13.3 Leg acy VGA and I/ O Ra ng e De code R ules The l egacy 128 K B V GA mem ory range 00 0A_00 00h-0 00B_F FFF h can be mapp ed to IG.
Proce ssor Config uration Registers 42 Datasheet , Volume 2 Acc esses t o the VG A memor y range are di rec ted to IGD de pend on th e confi guration . The c onf iguration i s spe cified by: • Intern al Graph ics C ontrol ler in Devic e 2 is enabl ed (DE VEN.
Datasheet , Volume 2 43 Processo r Configuration Reg isters For regio ns mappe d outs ide of th e IGD (o r if IGD is di sable d), the le gacy V GA me mory range A0000 h–BF FFFh is mapped eit her to .
Proce ssor Config uration Registers 44 Datasheet , Volume 2 Enabl e bi t is n ot set . If the VGA e nable bit is set, th en ac cesses to I/O a ddress range x3B Ch–x3BF h are forward ed to D MI Interfa ce.
Datasheet , Volume 2 45 Processo r Configuration Reg isters 2.4 Proce ssor Re giste r Introdu ction The p roces sor c ontai ns two s ets of soft ware a ccessib le r egisters , ac cessed usin g the Host p roces sor I /O ad dre ss space – Co ntrol regi sters a nd in ternal c onfigu ration reg isters.
Proce ssor Config uration Registers 46 Datasheet , Volume 2 2.4.1 I/O Mapped Registers The p roces sor c ontains two reg is ters that resid e in the processo r I/O addres s sp ace— the C onfigu ration Addres s (C ONFI G_ADD RESS) Register a nd th e Con figuratio n Dat a (CO NFIG_ DA T A) Register .
Datasheet , Volume 2 47 Processo r Configuration Reg isters 81h PAM 1 Programmable Attribute M ap 1 00h RW 82h PAM 2 Programmable Attribute M ap 2 00h RW 83h PAM 3 Programmable Attribute M ap 3 00h RW.
Proce ssor Config uration Registers 48 Datasheet , Volume 2 2.5.1 VID—Vendor Identifica tion Register This regist er , com bined with the Devic e Id entificatio n reg ister , u niquel y id entifie s any PCI device .
Datasheet , Volume 2 49 Processo r Configuration Reg isters 2.5.3 PCICMD—PCI C ommand Register Sin ce Dev ice 0 d oes not p hysically r esi de on P CI_A, many of the bits are not imple ment ed.
Proce ssor Config uration Registers 50 Datasheet , Volume 2 2.5.4 PCISTS—PCI St atus Register This status reg ister report s the occurren ce o f error events o n Dev ice 0's PCI interfa ce. Sin ce Dev ice 0 d oes not ph ysically res ide o n PCI_ A, many of the bits are n ot imple ment ed.
Datasheet , Volume 2 51 Processo r Configuration Reg isters 10:9 RO 00 b Un core DEVSEL Tim ing (DEVT) These bits a re h a rdwired t o " 00".
Proce ssor Config uration Registers 52 Datasheet , Volume 2 2.5.5 RID—Revision I dentification Register This reg ister co ntain s the re visio n numb er of D evic e 0. Thes e bits a re re ad only and writ es to th is reg iste r have n o effe ct. This regist er co ntain s the re visio n numb er of t he p roces sor .
Datasheet , Volume 2 53 Processo r Configuration Reg isters 2.5.6 CC—Class Code Regi ster This re gister id enti fies the basic functio n o f t he device , a mo re specifi c s ub-cl ass, and a reg ister-spec ific p rogramm ing inte rfac e.
Proce ssor Config uration Registers 54 Datasheet , Volume 2 2.5.8 SVID—Subsystem Vendor Ident ification Register This value i s used t o ide ntify the vendo r of t he subs yste m. 2.5.9 SID—Subsystem Identification Regis ter This value i s used t o ide ntify a partic ular subsystem .
Datasheet , Volume 2 55 Processo r Configuration Reg isters 2.5.10 PXPEPBAR—PCI Expr ess Egress Port Base Address Register This is the base a ddr ess f or the P CI Ex press Egress Port MM IO Conf iguration spa ce. There i s no physi cal me mory wi thin this 4 KB window that can be addre ssed.
Proce ssor Config uration Registers 56 Datasheet , Volume 2 2.5.11 MCHBAR—Host Memory Map ped Register Range Base Register This i s the bas e addres s for th e Host Mem or y Mapp ed Con figuratio n space . There is no phys ical me mory wi thin this 32 KB wi ndow tha t can be a ddre ssed.
Datasheet , Volume 2 57 Processo r Configuration Reg isters 2.5.12 GGC—GMCH Graphics Con t rol Regis ter Register All th e bit s in th is regi ster ar e Int el TXT locka ble.
Proce ssor Config uration Registers 58 Datasheet , Volume 2 2 RO 0h Rese rved 1 RW-L 0b Unc ore IGD VGA Dis able (IVD) 0 = Enable. Devi ce 2 (IGD) claims VG A memory an d I/O cycles, the S ub-Class Code within Device 2 Clas s Code registe r is 00. 1 = Disable.
Datasheet , Volume 2 59 Processo r Configuration Reg isters 2.5.13 DEVEN—Device Enable R egister This regist er allow s for e nabl ing/dis abling o f PCI devic es an d func tions that are wi thin the process or p acka ge.
Proce ssor Config uration Registers 60 Datasheet , Volume 2 2.5.14 PCIEXBAR—PCI Express Register Range Base Address Register This is the base addr ess for the P CI Ex press c onfigu ration spac e.
Datasheet , Volume 2 61 Processo r Configuration Reg isters B/D/F/Typ e: 0/0/0/PCI Address Offset: 60 –67h Reset Va lue: 0000_ 0000_0000_0000h Access: RW, RW -V Size: 64 bits BIOS Op timal Default 0.
Proce ssor Config uration Registers 62 Datasheet , Volume 2 2.5.15 DMIBAR—Root Complex Register Range Base Address Register This is the base addr ess fo r the Root Comple x c onfiguratio n spac e. Th is wi ndow o f addres ses con tains the Root Co mplex Registe r se t for t he PCI E xpre ss Hie rarchy ass ociate d with the H ost B ridge.
Datasheet , Volume 2 63 Processo r Configuration Reg isters 2.5.16 PAM0—Programmable Attribute M ap 0 Register This regist er cont rols th e read, writ e and sh adow ing at tribu tes of the BIOS ra nge fro m F_00 00h to F_F FFFh.
Proce ssor Config uration Registers 64 Datasheet , Volume 2 2.5.17 PAM1—Programma b l e Attribute Map 1 Register This regist er cont rols th e read , writ e and sh ado wing attribu tes of the BIOS range fro m C_0 000h t o C_7F FFh.
Datasheet , Volume 2 65 Processo r Configuration Reg isters 2.5.18 PAM2—Programmable Attribute M ap 2 Register This regist er cont rols th e read, writ e and sh adow ing at tribu tes of the BIOS ra nge fro m C_8 000h t o C_F FFFh.
Proce ssor Config uration Registers 66 Datasheet , Volume 2 2.5.19 PAM3—Programma b l e Attribute Map 3 Register This regist er cont rols th e read , writ e and sh ado wing attribu tes of the BIOS range fro m D00 00h to D7FF Fh.
Datasheet , Volume 2 67 Processo r Configuration Reg isters 2.5.20 PAM4—Programmable Attribute M ap 4 Register This regist er cont rols th e read, writ e and sh adow ing at tribu tes of the BIOS ra nge fro m D80 00h to DFF FFh.
Proce ssor Config uration Registers 68 Datasheet , Volume 2 2.5.21 PAM5—Programma b l e Attribute Map 5 Register This regist er cont rols th e read , writ e and sh ado wing attribu tes of the BIOS range fro m E_00 00h to E_7 FFFh.
Datasheet , Volume 2 69 Processo r Configuration Reg isters 2.5.22 PAM6—Programmable Attribute M ap 6 Register This regist er cont rols th e read, writ e and sh adow ing at tribu tes of the BIOS ra nge fro m E_80 00h to E_F FFF h.
Proce ssor Config uration Registers 70 Datasheet , Volume 2 2.5.23 LAC—Legacy Acces s Control Register This 8-bit r egis ter con trols s teerin g of MDA c ycles a nd a fixed D RAM h ole from 15 - 16 M B. There can only be at most one MD A de vice in the s yste m.
Datasheet , Volume 2 71 Processo r Configuration Reg isters 2 RW 0 b Un core PEG12 MDA Present (MDAP 12) This bit w orks w ith the VGA Ena bl e bits in the BCTRL reg ister of Device 1 Function 2 to control the routin g of processor initia ted transactions t argeting MDA co mpatible I/O and memory address ranges.
Proce ssor Config uration Registers 72 Datasheet , Volume 2 1 RW 0 b Unc ore PEG11 MDA Present (MDA P11) This bit works with the VGA Enable bits in the BC TRL register of Device 1 Funct ion 1 to contr ol the routing o f processor initiate d transactions t argeting MDA com patible I/O and memory addr ess ranges.
Datasheet , Volume 2 73 Processo r Configuration Reg isters 0 RW 0 b Un core PEG10 MDA Present (MDAP 10) This bit w orks w ith the VGA Ena bl e bits in the BCTRL reg ister of Device 1 Function 0 to control the routin g of processor initia ted transactions t argeting MDA co mpatible I/O and memory address ranges.
Proce ssor Config uration Registers 74 Datasheet , Volume 2 2.5.24 REMAPBASE—Remap Base Address Register 2.5.25 REMAPLIMIT—Remap Limit A dd ress Regis ter B/D/F /T ype: 0 /0/0/PCI Address Offset: .
Datasheet , Volume 2 75 Processo r Configuration Reg isters 2.5.26 TOM—Top of Memory Regis t er This regist er co ntain s the s ize of p hysical m em ory .
Proce ssor Config uration Registers 76 Datasheet , Volume 2 2.5.27 TOUUD—Top of Upper Usable DR A M Regis ter This 64-b it reg ister defi nes t he T op of Up per U sable D RA M. Con figuratio n soft ware m ust se t this v a lue to TO M min us all ME sto len m emory if recla im is disab led.
Datasheet , Volume 2 77 Processo r Configuration Reg isters 2.5.28 BDSM—Base Data of Stolen Memory Register This regist er co ntains t he ba se ad dress of grap hics da ta s tolen DRAM m emo ry .
Proce ssor Config uration Registers 78 Datasheet , Volume 2 2.5.30 G Memory Base Re gister This regist er co ntain s the b ase a ddress of TS EG DR AM m emor y . BIO S d eterm ines th e bas e of T SE G memory which m ust be a t or below G r aphi cs Base of G T T Stolen Me mory (PC I Devic e 0, O ffset B4h, bits 3 1:20).
Datasheet , Volume 2 79 Processo r Configuration Reg isters B/D/F/Typ e: 0/0/0/PCI Address Offset: BC–BFh Reset Va lue: 0010_ 0000h Access: RW-KL , RW-L Size: 32 bits BIOS Op timal Default 00000h Bi.
Proce ssor Config uration Registers 80 Datasheet , Volume 2 2.5.32 ERRSTS—Error Status Register This regist er is used to rep ort variou s erro r condi tions using t he S ERR D MI m essa ging mech ani sm.
Datasheet , Volume 2 81 Processo r Configuration Reg isters 2.5.33 ERRCMD—Error Command Re gister This regist er co ntrols the Ho st Br idge respon ses to various syst em erro rs. Si nce the Host B rid ge do es not have an SERR B si gnal, S ERR me ssag es are pa ssed f rom the proc esso r to the P CH o ver DM I.
Proce ssor Config uration Registers 82 Datasheet , Volume 2 2.5.35 SCICMD—SCI Comma nd Register This regist er ena bles various err ors to gen erate a n SMI DMI s pecia l cycle.
Datasheet , Volume 2 83 Processo r Configuration Reg isters 2.5.37 CAPID0_A—Capabilities A Register This regist er co ntrol of b its in thi s regis ter are onl y requ ired for custo mer visibl e SKU differ entia tion.
Proce ssor Config uration Registers 84 Datasheet , Volume 2 7:4 RO-FW 0h Reserved 3:3 RO 0h Reserved 2:0 RO-FW 000b Uncor e DDR3 Ma ximum Frequenc y C apability (DMFC) This field contr ols wh ich va lues may be written to the Memo ry Freque ncy Select field 6:4 of th e Clocking Configu ration registers (MCHBAR Offset C00h).
Datasheet , Volume 2 85 Processo r Configuration Reg isters 2.6 PCI Device 1 , Funct ion 0 –2 Confi gurat ion Regist ers T ab le 2-8 lists t he re giste rs arrang ed by a ddre ss offse t. Registe r bit d escripti ons are in the se ction s fol lowing the ta ble.
Proce ssor Config uration Registers 86 Datasheet , Volume 2 90–91h MSI_CAPI D Message Signaled Interr upts Capability ID A005h RO 92–93h M C Messa ge Control 0000h RO, RW 94–97h MA M essage Addr.
Datasheet , Volume 2 87 Processo r Configuration Reg isters 2.6.1 VID1—Vendor Iden tification Register This reg iste r combi ned wit h the D evice Iden tificat ion regi ster uniqu ely iden tify a ny PCI dev ice.
Proce ssor Config uration Registers 88 Datasheet , Volume 2 2.6.3 PCICMD1—PCI Comman d Register B/D/F /T ype: 0 /1/0–2/PCI Address Offset: 4– 5h Reset Va lue: 0000h Access: RW, RO Size: 16 bits .
Datasheet , Volume 2 89 Processo r Configuration Reg isters 2 RW 0 b Un core Bus Mast er Enable (BME ) This bit controls the ability of the PEG por t to forward Memory R ead /Wr i te Requests in the u pstream direc tion. 0 = This device is p revented from makin g memory reque sts to its primary bu s.
Proce ssor Config uration Registers 90 Datasheet , Volume 2 2.6.4 PCISTS1—PCI Sta tus Regis ter This regist er re ports the occ urrenc e of e rror co nditions assoc iated w ith p rimary s ide o f the " virtua l" Hos t-PCI Expr ess bridg e embe dded w ithin th e Root po rt.
Datasheet , Volume 2 91 Processo r Configuration Reg isters 8 RW 1C 0b Uncore Mas ter Data Parity Error (PM DPE) This bit is Set by a Requester (P rimary Side for T ype 1 Configuration Space header Fu.
Proce ssor Config uration Registers 92 Datasheet , Volume 2 2.6.5 RID1—Revision Iden tification Register This regist er co ntain s the re visio n numb er of t he p roces sor roo t por t. Thes e bits a re read o nly a nd w rites t o this regis ter h ave no ef fec t.
Datasheet , Volume 2 93 Processo r Configuration Reg isters 2.6.7 CL1—Cache Line Size Register 2.6.8 HDR1—Header Type Regis ter This r egist er iden tifie s the hea de r layout o f the c onfigu ration s pace . No p hysical reg ister ex ists a t thi s locatio n.
Proce ssor Config uration Registers 94 Datasheet , Volume 2 2.6.10 SBUSN1—Secondary Bu s Number Regist er This regist er iden tifies t he b us num ber ass igned to the s econd b us si de of th e "vir tual" bri dge (t hat is , to PCI Ex press-G ).
Datasheet , Volume 2 95 Processo r Configuration Reg isters 2.6.12 IOBASE1—I/O Ba se Address Register This regist er co ntrols the pro cess or to P CI Ex press-G I/O acces s rou ting ba sed o n the follow ing fo rmul a: IO_B ASE addres s I O_LI MIT Only the upper 4 bits are pr ogramm able.
Proce ssor Config uration Registers 96 Datasheet , Volume 2 2.6.14 SSTS1—Secondary Statu s Register SSTS is a 16-bit status reg ister that r eports t he occ urren ce o f error c ondi tions ass ociate d with secon dary side (that i s, PCI E xpress -G si de) of t he "vi rtual" P CI-PCI bri dge em bedde d w ithin the pro cessor .
Datasheet , Volume 2 97 Processo r Configuration Reg isters 2.6.15 MBASE1—Memory Base Ad dress Regis ter This re giste r co ntrols the pr ocess or to PCI E xpre ss-G no n-prefe tchabl e mem ory acce.
Proce ssor Config uration Registers 98 Datasheet , Volume 2 2.6.16 MLIMIT1—Memo r y Limit Address Regist er This re gister cont rols th e proce ssor to PC I Express -G non -prefe tchab le memo ry ac.
Datasheet , Volume 2 99 Processo r Configuration Reg isters 2.6.17 PMBASE1—Prefetchable Me mory Base Address Register This regist er in conj unction with th e co rrespo nding Up per Base Addre ss re.
Proce ssor Config uration Registers 100 Datasheet , Volume 2 2.6.18 PMLIMIT1—Prefetchable Memory Limit Address Regist er This regist er in c onjunc tion with th e co rrespondi ng Up per Limit A ddr .
Datasheet , Volume 2 101 Processo r Configuration Reg isters 2.6.19 PMBASEU1—Prefetchable Memory Base Address Upper Register The fu nctio nality assoc iated with th is regi ster i s pres ent in the PE G de sign imple ment ation .
Proce ssor Config uration Registers 102 Datasheet , Volume 2 2.6.20 PMLIMITU1—Prefetchable Me m ory Limit A ddress Upper Register The fu nctio nality associ ated with this reg iste r is pres ent in the PEG desig n imple ment ation .
Datasheet , Volume 2 103 Processo r Configuration Reg isters 2.6.22 INTRLINE1—Interrupt Line Regist er This regist er co ntains in terru pt l ine routin g informa tio n. The d evice i tself does n ot use this val ue, rath er it is used by d evice d rivers and operatin g system s to d eter mine pri ority an d vector info rmati on.
Proce ssor Config uration Registers 104 Datasheet , Volume 2 2.6.24 BCTRL1—Bridge Control Regis ter This regi ster provi des exten sions to the PCICM D register that a re spe cific to PCI-to-PCI bri dges.
Datasheet , Volume 2 105 Processo r Configuration Reg isters 2 RW 0 b Un core ISA Enab l e ( I SAE N) Needed to exclude legacy reso urce decode to route ISA resource s to legacy decode path. M odifies the re sponse by the root port to an I/O access issued by th e processor th at target ISA I/O addre sses.
Proce ssor Config uration Registers 106 Datasheet , Volume 2 2.6.25 PM_CAPID1—Power Managemen t Capabilities Register B/D/F /T ype: 0 /1/0–2/PCI Address Offset: 80 –83h Reset Va lue: C803_9 001h.
Datasheet , Volume 2 107 Processo r Configuration Reg isters 2.6.26 PM_CS1—Power Manageme nt Control/Status Regis ter B/D/ F/Type: 0/1/0–2/PCI Address Offset: 84 –87h Reset Va lue: 0000_ 0008h A.
Proce ssor Config uration Registers 108 Datasheet , Volume 2 2.6.27 SS_CAPID—Subsys t e m ID and Vendor ID Capabilities Register This capab ility is us ed to uni quely identify the subs ystem where t h e PCI device r e sides .
Datasheet , Volume 2 109 Processo r Configuration Reg isters 2.6.28 SS—Subsystem ID and Su bsystem Vendor ID Register System BIOS can be use d as t he m echani sm f or loadi ng the SSID/S VID valu es. T hese values must be pr eserved t hroug h po wer ma nag ement t ransitio ns an d a h ardware reset .
Proce ssor Config uration Registers 110 Datasheet , Volume 2 2.6.30 MC—Message Control Re gister System s oftware c an m odify bits i n t his register , but the device i s prohibite d fro m doi ng so. If th e devic e wr ites t he sam e m essa ge mu ltiple t imes, o nly o ne of t hose m essa ges is ens ured t o be se rvice d.
Datasheet , Volume 2 111 Processo r Configuration Reg isters 2.6.31 MA—Message Address Register 2.6.32 MD—Message Data R egister 2.6.33 PEG_CAPL—PCI Express-G Capability List Register Enume rates th e PCI Expre ss ca pabili ty stru cture.
Proce ssor Config uration Registers 112 Datasheet , Volume 2 2.6.34 PEG_CAP—PCI Express-G Capabilities Regist er This regist er ind icates PCI Expres s devi ce ca pabili ties. 2.6.35 DCAP—Device Capab ilities Register This regist er ind icates PCI Expres s devi ce ca pabili ties.
Datasheet , Volume 2 113 Processo r Configuration Reg isters 2.6.36 DCTL—Device Con t rol Regis t er This regist er pr ovide s control for PC I Exp ress d evice s peci fic ca pabili ties. The e rror re port ing e nable bits are i n refe ren ce to e rrors detect ed by thi s devic e, not error message s rec eived a cross th e link.
Proce ssor Config uration Registers 114 Datasheet , Volume 2 2.6.37 DSTS—Device Status Registe r Reflects stat us corre spon ding t o con trols in the D evice Contr ol reg ister . The e rro r rep orting bits are in r eferen ce t o errors detecte d by t his device, n ot errors m essa ges recei ved acr oss t he link.
Datasheet , Volume 2 115 Processo r Configuration Reg isters 2.6.38 LCTL—Link Control Register This regist er allow s co ntrol o f PCI Ex pres s link .
Proce ssor Config uration Registers 116 Datasheet , Volume 2 6 RW 0 b Unc ore Common C lock Configuration ( CCC) 0 = Indicates th at this component a nd the component at the opposite end of this Link are operating with asyn chronous referen ce clock.
Datasheet , Volume 2 117 Processo r Configuration Reg isters 2.6.39 LSTS—Link Status Register This regist er ind icates PCI Ex press link status. B/D/ F/Type: 0/1/0–2/PCI Addres s Offset: B2– B3.
Proce ssor Config uration Registers 118 Datasheet , Volume 2 2.6.40 SLOTCAP—Slot Capabilities Register Note: Hot Plug is not s uppor ted on Inte l ® Xeon ® pr ocesso r E3- 1200 fa mily p latfor ms. 9:4 RO- V 0 0h U ncore Negotiate d Link Width (NL W) This field indicates negotia ted link widt h.
Datasheet , Volume 2 119 Processo r Configuration Reg isters 16:15 RW-O 0 0b Un core Slot P ower Limit Scale (SPLS) This field specifies the scal e used for th e Slot Power Limit Value. 00 = 1. 0x 01 = 0. 1x 10 = 0.01x 11 = 0. 001x If this fie ld is written, the l ink sends a Set_Slo t_Power_Limit messa ge.
Proce ssor Config uration Registers 120 Datasheet , Volume 2 2.6.41 SLOTCTL—Slot Cont rol Register Note: Hot Plug is not s uppor ted on Inte l ® Xeon ® pr ocesso r E3- 1200 fa mily p latfor ms.
Datasheet , Volume 2 121 Processo r Configuration Reg isters 7:6 RO 00b Uncore Reserve d for Attention I ndicator Control (A IC) If an Att ention Indicator is imp lemented, writes to t his f ield set the Attention I ndicator to the w ritten state.
Proce ssor Config uration Registers 122 Datasheet , Volume 2 2.6.42 SLOTSTS—Slot Status Register This is fo r PCI Expres s Slot relat ed regi sters .
Datasheet , Volume 2 123 Processo r Configuration Reg isters 3 RW 1C 0b Uncore Presenc e Detect Changed (PD C) A pulse indication that th e inband prese nce detect state h as changed This bit is set when the value r eported in Presen ce Detect State is changed.
Proce ssor Config uration Registers 124 Datasheet , Volume 2 2.6.43 RCTL—Root Contr ol Register This regist er allow s control of PCI Exp ress Root Comple x spec ific p aramet ers.
Datasheet , Volume 2 125 Processo r Configuration Reg isters 2.6.44 LCTL2—Link Contro l 2 Register B/D/ F/Type: 0/1/0–2/PCI Address Offset: D0– D1h Reset Va lue: 0002h Access: RWS, R WS-V Size: .
Proce ssor Config uration Registers 126 Datasheet , Volume 2 6 RWS 0 b Powerg ood Selectable De-emphasis (se lectabledeemp hasis) When the Link is operating at 5GT/s speed, sel ects the level of de- emphasis.
Datasheet , Volume 2 127 Processo r Configuration Reg isters 2.7 PCI Device 1 , Funct ion 0 –2 Exte nded Config uration Reg isters T ab le 2-9 lists t he re giste rs arrang ed by a ddre ss offse t. Registe r bit d escripti ons are in the se ction s fol lowing the ta ble.
Proce ssor Config uration Registers 128 Datasheet , Volume 2 2.7.2 PVCCAP2—Port VC Ca p a bility Register 2 This regist er des cribes the config uration of PC I Expr ess Virt ual Channe ls as sociated wit h this po rt.
Datasheet , Volume 2 129 Processo r Configuration Reg isters 2.7.4 VC0RCAP—VC0 R esourc e Capa bility Register B/D/ F/Type: 0/1/0 –2/MMR Address Offset: 11 0–113h Reset Va lue: 0000_ 0001h Acces.
Proce ssor Config uration Registers 130 Datasheet , Volume 2 2.7.5 VC0RCTL—VC0 Resource Co ntrol Register This regist er co ntrols the res ourc es as sociated w ith PCI E xp ress V irtual Ch annel 0.
Datasheet , Volume 2 131 Processo r Configuration Reg isters 2.7.6 VC0RSTS—VC0 Res ource Status Register This regist er re ports the Virt ual Cha nne l spec ific sta tus.
Proce ssor Config uration Registers 132 Datasheet , Volume 2 2.8 PCI Device 2 Config uration R egist ers T able 2- 10 lists the regi sters arrange d b y addr ess o f fse t. Registe r bi t descri ptio ns a re in the s ection s fol lowing the t able. Tab le 2-10 .
Datasheet , Volume 2 133 Processo r Configuration Reg isters 2.8.1 VID2—Vendor Iden tification Register This regist er , comb ined with th e Devi ce I dentific ation r egis ter , un ique ly identi fies a ny PCI device .
Proce ssor Config uration Registers 134 Datasheet , Volume 2 2.8.3 PCICMD2—PCI Comman d Register This 16- bit re gister pr ovide s basic cont rol ove r the I GD's abi lity t o res pond to P CI cycle s. Th e PCIC MD Regi ster in the IGD disables the IGD PCI co mpliant master acc esses t o ma in me mory .
Datasheet , Volume 2 135 Processo r Configuration Reg isters 2.8.4 PCISTS2—PCI Status Register PCIS TS is a 1 6 -bit status reg ister t ha t repo rts t he oc curren ce o f a P CI comp liant m ast er abo rt and P CI co mpli ant t arget abort. PCISTS a lso i ndicat es the DEV SEL# timing that has been set by t he IG D.
Proce ssor Config uration Registers 136 Datasheet , Volume 2 2.8.5 RID2—Revision Iden tification Register This regis ter c ontai ns the re vision number for Devi ce 2 Fu nctions 0. Thes e bits are read on ly and wri tes to this reg ister have no effect .
Datasheet , Volume 2 137 Processo r Configuration Reg isters 2.8.7 CLS—Cache Line Si ze Register The I GD d oes no t supp ort th is regis ter a s a P CI sl ave. 2.8.8 MTXT2—Master L atency Timer Re gister The I GD d oes no t supp ort th e p rogramma bility o f the ma ste r latenc y time r be cause i t does not p erform bur sts.
Proce ssor Config uration Registers 138 Datasheet , Volume 2 2.8.10 GTTMMADR—Graphics Trans lation Table, Memory Mapped Range Address Register This regist er re quests alloca tion for the comb ined Grap hics T r anslatio n T a ble Mod ifica tion Range and M emor y Mappe d Range .
Datasheet , Volume 2 139 Processo r Configuration Reg isters 2.8.11 GMADR—Graphics Memo ry Range Address Regis ter GM ADR i s the P CI ap erture u sed by soft ware to acc ess tile d GF X surfac es in a linea r fash ion.
Proce ssor Config uration Registers 140 Datasheet , Volume 2 2.8.12 IOBAR—I/O Base Addr ess Register This regist er provides the Base offse t of the I/O registe rs within Device 2 . Bits 1 5:6 are program ma ble all owing the I/O Bas e to be lo cated anyw here in 16- bit I/O Addres s Spa ce.
Datasheet , Volume 2 141 Processo r Configuration Reg isters 2.8.14 SID2—Subsystem Iden tification Register This regist er is u sed to un iquely iden tify the subsys tem w here t he PC I dev ice re sides.
Proce ssor Config uration Registers 142 Datasheet , Volume 2 2.8.17 MINGNT—Minimum Grant Re gister The I ntegrat ed Graphic s D evice ha s no require ment for th e set tings of Lat ency Timers. 2.8.18 MAXLAT—Maximum L a tency Register The I ntegrat ed Graphic s D evice ha s no require ment for th e set tings of Lat ency Timers.
Datasheet , Volume 2 143 Processo r Configuration Reg isters 2.8.19 MSAC—Multi Si z e Aperture Control Register This r egist er det erm ines the s ize o f the graph ics memo ry ape rture i n func tio n 0 an d in the t rusted sp ace.
Proce ssor Config uration Registers 144 Datasheet , Volume 2 2.9 Devi ce 2 I/O Regi sters 2.9.1 INDEX—MMIO Add r e ss Register A 3 2-bit I /O writ e to t his po rt loa ds th e off set of the MM IO re giste r or o ffset into the GTT that need s to be acc essed .
Datasheet , Volume 2 145 Processo r Configuration Reg isters 2.10 PCI Device 6 Con figura tion Reg isters T ab le 2-1 2 l ists the reg isters arranged by addre ss offs et. Register bit de scriptio ns a re in the se ction s fol lowing the ta ble. Ta ble 2-12 .
Proce ssor Config uration Registers 146 Datasheet , Volume 2 2.10.1 VID6—Vendor Identification Regis ter This regis ter , comb ined with t h e D evice Ident ification reg ister , u niqu ely i dent ify any PC I dev ice.
Datasheet , Volume 2 147 Processo r Configuration Reg isters 2.10.2 DID6—Device Identification Regis ter This regist er , comb ined with th e V en dor I dentifi cation regis ter , u niqu ely id entifie s an y PCI device .
Proce ssor Config uration Registers 148 Datasheet , Volume 2 6 RW 0 b Unc ore Parity E rror Response Enable (PER RE) Controls wh ether or not the Mast er Data Parity Error bit in the PCI Status r egister can bet set . 0 = Master Data Parity Error bit in PCI Status registe r can NO T be set.
Datasheet , Volume 2 149 Processo r Configuration Reg isters 2.10.4 PCISTS6—PCI Status Re g i ster This regist er rep orts the occur renc e of e rror condi tions assoc iated with primary sid e of the " virtual" Host-PC I Expr ess b ridge em bedde d w ithin th e Root por t.
Proce ssor Config uration Registers 150 Datasheet , Volume 2 8 RW 1C 0b Uncore Master Data Parity Error (P MDPE) This bit is set by a Requester (Prim ary Side for T ype 1 Configuration S pace header F.
Datasheet , Volume 2 151 Processo r Configuration Reg isters 2.10.5 RID6—Revision Ident ification Register This regist er co ntains t he revi sion n umbe r of t he proc esso r root p or t. Thes e bits are read o nly a nd w rites t o this regis ter ha ve no eff ect.
Proce ssor Config uration Registers 152 Datasheet , Volume 2 2.10.7 CL6—Cache Line Size Register 2.10.8 HDR6—Header Type Regist er This regist er iden tifies the head er layout of the config uration spac e. No physical reg ister ex ists at thi s locatio n .
Datasheet , Volume 2 153 Processo r Configuration Reg isters 2.10.10 SBUSN6—Seco ndary Bus Number Register This re gist er iden tifies t he bus n umbe r assi gned to the se cond bu s sid e of th e "vir tual" bri dge (th at is, to PCI E xp ress-G) .
Proce ssor Config uration Registers 154 Datasheet , Volume 2 2.10.12 IOBASE6—I/O Base Address Register This regist er co ntrols the pro cess or to P CI E xpre ss-G I /O acc ess routin g bas ed o n the foll owing fo rmul a: IO_B ASE a ddress I O_LI MIT Only the upp er 4 bits a re pr ogramm able.
Datasheet , Volume 2 155 Processo r Configuration Reg isters 2.10.14 SSTS6—Second ary Status Register SSTS i s a 16 -bit s tatus reg iste r that report s the occ urrence o f er ror co nditions ass ociate d with second ary side (th at is, PCI Ex press -G s ide) of the "vi rtua l" PCI-P CI brid ge em bedded wi thin th e proc essor .
Proce ssor Config uration Registers 156 Datasheet , Volume 2 2.10.15 MBASE6—Memory Ba se Address Register This re gister cont rols th e proce ssor to PC I Express -G non -prefe tchab le memo ry acce.
Datasheet , Volume 2 157 Processo r Configuration Reg isters 2.10.16 MLIMIT6— Memory Limit Address Register This re giste r co ntrols the pr ocess or to PCI E xpre ss-G no n-prefe tchabl e mem ory a.
Proce ssor Config uration Registers 158 Datasheet , Volume 2 2.10.17 PMBASE6—Prefe t chable M emory Base Address Register This regist er , in c onjunc tion wit h the corres pond ing U pper B ase A d.
Datasheet , Volume 2 159 Processo r Configuration Reg isters 2.10.18 PMLIMIT6—Pr efetchable Memory Limit Add ress Register This re gist er , in con junctio n with t he c orresp onding Uppe r Limi t .
Proce ssor Config uration Registers 160 Datasheet , Volume 2 2.10.19 PMBASEU6—Prefetchable M emory Base Address Upper Register The fu nctio nality associ ated with this reg iste r is pres ent in the PEG desig n imple ment ation .
Datasheet , Volume 2 161 Processo r Configuration Reg isters 2.10.20 PMLIMITU6—Prefe tchable Memory Limit Addres s Upper Register The fu nctio nality assoc iated with th is regi ster i s pres ent in the PE G de sign imple ment ation .
Proce ssor Config uration Registers 162 Datasheet , Volume 2 2.10.22 INTRLINE6 —Interrupt Line Register This regist er co ntains i nterru pt lin e rou ting in forma tion. T he d evice itself do es n ot use this val ue, r ather it is use d by dev ice drivers a nd o perating s yste ms to d eterm ine pri ority an d vecto r inform ation .
Datasheet , Volume 2 163 Processo r Configuration Reg isters 2.10.24 BCTRL6—Br idge Control Register This regi ster provides extensio ns to the PCIC MD regi ster that are spe cific to PCI-t o-PC I brid ges.
Proce ssor Config uration Registers 164 Datasheet , Volume 2 1 RW 0 b Unc ore SERR En able (SERREN) 0 = No forwarding of error messages from secondary side to prima ry side that could result in a n SERR. 1 = ERR_COR, ERR_NONF AT AL, and ERR_ F AT A L messages res ult in SERR message when in dividua l ly enable d by the Root Control r egister .
Datasheet , Volume 2 165 Processo r Configuration Reg isters 2.10.25 PM_CA PI D6—Power M anagement Capabilities Regis t er B/D/F/Typ e: 0/6/0/PCI Address Offset: 80 –83h Reset Va lue: C803 _9001h .
Proce ssor Config uration Registers 166 Datasheet , Volume 2 2.10.26 PM_CS6—Po w er Management Con t rol/Status Regis ter B/D/F/Typ e: 0/6/0/PCI Address Offset: 84 –87h Reset Va lue: 0000_ 0008h A.
Datasheet , Volume 2 167 Processo r Configuration Reg isters 2.10.27 SS_CAPID—Subsy stem ID and Vendor ID Capabilities Register This cap abilit y is us ed to un iquel y identif y the subsy stem where the PCI devic e r eside s.
Proce ssor Config uration Registers 168 Datasheet , Volume 2 2.10.28 SS—Subsystem I D and Subsystem Vendor ID Register System BIOS can b e use d as t he m ech anism fo r loa ding the SS ID/SV ID value s. Thes e values must be pr eserve d th rough p ower m ana gemen t transi tions an d a h ardware reset .
Datasheet , Volume 2 169 Processo r Configuration Reg isters 2.10.30 MC—Messa ge Control Register System so ftware can mo dify bits i n this re gist er , but t he device is prohibit ed from d oing so. If th e devic e wr ites t he same me ssage m ultip le tim es, on ly on e of th ose me ssag es is ass ured to be service d.
Proce ssor Config uration Registers 170 Datasheet , Volume 2 2.10.31 MA—Message Address Regis ter 2.10.32 MD—Message D ata Register 2.10.33 PEG_CAPL—PCI E xpress-G Capability List Register This regist er en umerat es the PCI Expres s cap ability s tructu re.
Datasheet , Volume 2 171 Processo r Configuration Reg isters 2.10.34 PEG_CAP—PCI Express-G Capabilities Regist er This regist er ind icates PCI Ex press devic e capa bilities . 2.10.35 DCAP—Device Capabilities Register This regist er ind icates PCI Ex press devic e capa bilities .
Proce ssor Config uration Registers 172 Datasheet , Volume 2 2.10.36 DCTL—Device Co ntrol Register This regist er pr ovide s contro l for P CI Ex press device spec ific ca pabil ities . The e rror re port ing enab le bits a re in re feren ce t o erro rs det ected b y thi s devic e, no t error mess ages received acros s the li nk.
Datasheet , Volume 2 173 Processo r Configuration Reg isters 2.10.37 DSTS—Devi ce Status Register This regist er r eflects status corr espon ding to cont rols in t he Device C ont rol reg iste r . The e rror re porti ng bi ts are in re ferenc e to er rors detec ted by this device , not errors mess ages received acr oss the link.
Proce ssor Config uration Registers 174 Datasheet , Volume 2 2.10.38 LCTL—Link Cont rol Register This regist er all ows control of PC I Exp ress l ink.
Datasheet , Volume 2 175 Processo r Configuration Reg isters 6 RW 0 b Un core Common C lock Configuration ( CCC) 0 = Indicates that this componen t and the c om pon ent at the opposite en d o f t his Link are operating w ith asynchr onous referen ce clock.
Proce ssor Config uration Registers 176 Datasheet , Volume 2 2.10.39 LSTS—Link Status R egister This regist er in dicates PCI Expres s lin k stat us.
Datasheet , Volume 2 177 Processo r Configuration Reg isters 2.10.40 SLOTCAP—Slot Ca pabilities Register No te: Hot Plug is not s uppor ted on Inte l ® Xeon ® pr ocesso r E3- 1200 fa mily pl atfor ms. 9:4 RO- V 0 0h Uncore Negotiat ed Link Width (NL W) This field indicates negotia ted link width.
Proce ssor Config uration Registers 178 Datasheet , Volume 2 16:15 RW-O 0 0b U ncore Slot Pow er Limit Scale ( SPLS) This field specifies the sc ale used for th e Slot Power Limit V alue. 00 = 1. 0x 01 = 0. 1x 10 = 0. 01x 11 = 0.001x If this fie ld is written, the link sends a Set _Slot_Power_Limit messa ge.
Datasheet , Volume 2 179 Processo r Configuration Reg isters 2.10.41 SLOTCTL—Slo t Cont r ol Regist er No te: Hot Plug is not s uppor ted on Inte l ® Xeon ® pr ocesso r E3- 1200 fa mily pl atfor ms.
Proce ssor Config uration Registers 180 Datasheet , Volume 2 7:6 RO 00b U ncore Reserve d for Attention I ndicator Contr ol (AIC) If an Att ention Indicator is im plemented, writes to this field set t h e Attention I ndicator to the wr itt en s tate.
Datasheet , Volume 2 181 Processo r Configuration Reg isters 2.10.42 SLOTSTS—Slo t Status Register This i s for PCI Expr ess Slot relate d regis ters.
Proce ssor Config uration Registers 182 Datasheet , Volume 2 2.10.43 RCTL—Root Control Register This regist er allow s control of PCI Exp ress Root Comple x spec ific p aramet ers.
Datasheet , Volume 2 183 Processo r Configuration Reg isters 2.11 PCI Device 6 Exten ded C onfigura tion Re gisters T ab le 2-1 3 l ists the reg isters arranged by addre ss offs et. Register bit de scriptio ns a re in the se ction s fol lowing the ta ble.
Proce ssor Config uration Registers 184 Datasheet , Volume 2 2.11.2 PVCCAP2—Port VC Capability Re gister 2 This regist er des cribes the config uration of PC I Expr ess Virt ual Channe ls as sociated wit h this po rt.
Datasheet , Volume 2 185 Processo r Configuration Reg isters 2.11.4 VC0RCAP—VC0 Res ource Capa bility Register B/D/F/Typ e: 0/6/0/MM R Address Offset: 11 0–113h Reset Va lue: 0000_ 0001h Access: R.
Proce ssor Config uration Registers 186 Datasheet , Volume 2 2.11.5 VC0RCTL—VC0 Resource Co ntrol Register This regist er co ntrols the res ourc es as sociated w ith PCI E xp ress V irtual Ch annel 0.
Datasheet , Volume 2 187 Processo r Configuration Reg isters 2.11.6 VC0RSTS—VC0 Resour ce Status Register This regist er re ports the Virt ual Cha nne l spec ific sta tus.
Proce ssor Config uration Registers 188 Datasheet , Volume 2 2.12 DMIB AR Re gisters T able 2- 14 lists the regi sters arrange d b y addr ess o f fse t.
Datasheet , Volume 2 189 Processo r Configuration Reg isters 2.12.1 DMIVCECH—DM I Virtual Channel Enhanced Capabili t y Register This regist er ind icates DMI V irtual C hann el ca pabil it ies .
Proce ssor Config uration Registers 190 Datasheet , Volume 2 2.12.2 DMIPVCCAP1—DMI Port VC Cap ability Register 1 This regist er des cribes the config uration of PC I Expr ess Virt ual Channe ls as sociated wit h this po rt.
Datasheet , Volume 2 191 Processo r Configuration Reg isters 2.12.4 DMIPVCCTL—DMI Port VC C ontrol Register 2.12.5 DMIVC0RCAP—DMI VC0 Resource Capability Register B/D/F/Typ e: 0/0/0/DMIBA R Addres.
Proce ssor Config uration Registers 192 Datasheet , Volume 2 2.12.6 DMIVC0RCTL—DMI VC0 Resource Contr ol Register This regist er co ntrols the res ourc es as sociated w ith PCI E xp ress V irtual Ch annel 0.
Datasheet , Volume 2 193 Processo r Configuration Reg isters 2.12.7 DMIVC0RSTS—DMI V C0 Resource Status Register This regist er re ports the Virt ual Cha nne l spec ific sta tus.
Proce ssor Config uration Registers 194 Datasheet , Volume 2 2.12.9 DMIVC1RCTL—DMI VC1 Resource Contr ol Register This regist er co ntrols the res ourc es as sociated w ith PCI E xp ress V irtual Ch annel 1.
Datasheet , Volume 2 195 Processo r Configuration Reg isters 2.12.10 DMIVC 1RSTS—DMI VC1 Resource Status Re gister This regist er re ports the Virt ual Cha nne l spec ific sta tus.
Proce ssor Config uration Registers 196 Datasheet , Volume 2 2.12.12 DMIVCPRCTL—DMI VCp Resource Control Register This regist er co ntrols the res ourc es as sociated w ith the DMI P rivate Ch annel (V Cp ).
Datasheet , Volume 2 197 Processo r Configuration Reg isters 2.12.13 DMIVCPRS TS—DMI VCp Resource Status Regis ter This regist er re ports the Virt ual Cha nne l spec ific sta tus.
Proce ssor Config uration Registers 198 Datasheet , Volume 2 2.12.14 DMIESD—DMI Element Self Description Register This regist er pr ovides in forma tion a bout th e root co mplex e lem ent co ntainin g this Li nk Dec laration C apab ility .
Datasheet , Volume 2 199 Processo r Configuration Reg isters 2.12.15 DMILE1D—DMI Lin k Entry 1 Description Register This re gist er pr ovides t he firs t par t of a Li n k Entry tha t decla res an intern al lin k to anot her Roo t Compl ex Elem ent.
Proce ssor Config uration Registers 200 Datasheet , Volume 2 2.12.17 DMILE2D—DMI Lin k Entry 2 Description Register This regist er pr ovide s the f irst pa rt of a Link Entry t hat d eclares an int erna l link t o anot her Root C omple x Elem ent . 2.
Datasheet , Volume 2 201 Processo r Configuration Reg isters 2.12.19 LCAP—Link Capabilities Register This regist er ind icates DMI s pecifi c cap abilitie s.
Proce ssor Config uration Registers 202 Datasheet , Volume 2 2.12.20 LCTL—Link Cont rol Register This regist er all ows control of PC I Exp ress l ink.
Datasheet , Volume 2 203 Processo r Configuration Reg isters 2.12.21 LSTS—DMI Lin k Status Register This regist er ind icates DMI s tatus . B/D/F/Typ e: 0/0/0/DMIBA R Address Offset: 8A–8 Bh Reset.
Proce ssor Config uration Registers 204 Datasheet , Volume 2 2.12.22 LCTL2—Link Control 2 Regis ter B/D/F /T ype: 0 /0/0/DMIBAR Address Offset: 98 –99h Reset Va lue: 0002h Acces s: RW S, RWS-V Siz.
Datasheet , Volume 2 205 Processo r Configuration Reg isters 6 RWS 0 b Powerg ood Selec table De-emphasis (se lectabledee mphasis) When the Link is operating at 5 GT/s speed, this bit selects th e level of de -emphasis. Enco dings: 1 = -3.5 dB 0 = -6 dB When t he Lin k is operating a t 2 .
Proce ssor Config uration Registers 206 Datasheet , Volume 2 2.12.23 LSTS2—Link Status 2 Register 2.12.24 AFE_BMUF0—AFE BMU Co nfiguration Function 0 Regis t er 2.
Datasheet , Volume 2 207 Processo r Configuration Reg isters 2.13 MCHB AR Re gisters in Mem ory Cont roller – Cha nnel 0 T ab le 2-1 5 l ists the reg isters arranged by addre ss offs et. Register bit de scriptio ns a re in the se ction s fol lowing the ta ble.
Proce ssor Config uration Registers 208 Datasheet , Volume 2 2.13.2 TC_RAP_C0—Tim ing of DDR Regular Access Parameters Register This regist er pr ovide s the re gular timing pa ra m eter s in D CLK cyc les.
Datasheet , Volume 2 209 Processo r Configuration Reg isters 2.13.4 TC_SRFTP_C0—Self-R efresh Timing Parameters Regist er This regist er pr ovides S elf-refres h timin g param eters .
Proce ssor Config uration Registers 210 Datasheet , Volume 2 2.13.6 ECCERRLOG0_C0—EC C Error Log 0 Register 2.13.7 ECCERRLOG1_C0—EC C Error Log 1 Register B/D/F /T ype: 0 /0/0/MCHBAR M C0 Address .
Datasheet , Volume 2 211 Processo r Configuration Reg isters 2.13.8 TC_RFP_C0—Ref r e sh Parameters Register 2.13.9 TC_RFTP_C0—Re fresh Timing Parameters Register B/D/F/Typ e: 0/0/0/MCHB AR MC0 Ad.
Proce ssor Config uration Registers 212 Datasheet , Volume 2 2.14 MCHBA R R egisters in M emory C ontrolle r – Cha nnel 1 T able 2- 16 lists the regi sters arrange d b y addr ess o f fse t. Registe r bi t descri ptio ns a re in the s ection s fol lowing the t able.
Datasheet , Volume 2 213 Processo r Configuration Reg isters 2.14.2 TC_RAP_C1—Timing of DDR Regular Access Parameters Register This regist er pr ovides the regu lar t iming pa rameters in D CLK cy cles.
Proce ssor Config uration Registers 214 Datasheet , Volume 2 2.14.4 TC_SRFTP_C1—Self - R efresh Timing Parameter s Reg is ter This regist er pr ovide s Se lf -r efresh tim ing parame ters.
Datasheet , Volume 2 215 Processo r Configuration Reg isters 2.14.6 ECCERRLOG0_C1—ECC Error Log 0 Register 2.14.7 ECCERRLOG1_C1—ECC Error Log 1 Register B/D/F/Typ e: 0/0/0/MCHB AR MC1 Address Offs.
Proce ssor Config uration Registers 216 Datasheet , Volume 2 2.14.8 TC_RFP_C1—Refresh P arameters Register 2.14.9 TC_RFTP_C1—Ref r e sh Timing Parameters Regi ster B/D/F /T ype: 0 /0/0/MCHBAR M C1.
Datasheet , Volume 2 217 Processo r Configuration Reg isters 2.15 MCHB AR Re gisters in Mem ory Cont roller – Inte grated M emory Periph eral Hub (IMP H) T ab le 2-1 7 l ists the reg isters arranged by addre ss offs et. Register bit de scriptio ns a re in the se ction s fol lowing the ta ble.
Proce ssor Config uration Registers 218 Datasheet , Volume 2 2.16 MCHBA R R egisters in M emory C ontrolle r – Comm on T able 2- 18 lists the regi sters arrange d b y addr ess o f fse t. Registe r bi t descri ptio ns a re in the s ection s fol lowing the t able.
Datasheet , Volume 2 219 Processo r Configuration Reg isters 2.16.2 MAD_DIMM_ch0—Address Decode Channel 0 Regis ter This re gist er defin es ch annel charact eristics —numbe r o f DIMM s, num ber of ranks, size, ECC , inter leave opti ons, and EC C opt ions .
Proce ssor Config uration Registers 220 Datasheet , Volume 2 2.16.3 MAD_DIMM_ch1—Address Decode Channel 1 Regis t er This regist er defi nes ch annel cha r ac teri stics—nu mber of DI MMs, n umber of ranks, size , ECC , interleav e opti ons, and EC C opt ions .
Datasheet , Volume 2 221 Processo r Configuration Reg isters 2.16.4 PM_SREF_config—Self Re fresh Configuration Register This self refre s h mode c ontro l re gister de fines if an d whe n DD R can go into S R.
Proce ssor Config uration Registers 222 Datasheet , Volume 2 2.17 Memor y Co ntroller M MIO R egiste rs Broa dcast Grou p T able 2- 19 lists the regi sters arrange d b y addr ess o f fse t. Registe r bi t descri ptio ns a re in the s ection s fol lowing the t able.
Datasheet , Volume 2 223 Processo r Configuration Reg isters 2.17.2 ECCERRLOG0—ECC Error Log 0 Register 2.17.3 ECCERRLOG1—ECC Error Log 1 Register B/D/F/Typ e: 0/0/0/MCHB AR_MCBCAST Address Offset.
Proce ssor Config uration Registers 224 Datasheet , Volume 2 2.17.4 PM_CMD_PWR—Power Mana g e ment Command Powe r Register This regist er defi nes the power contri bution of e ach comm and - ACT+P RE, CAS-r ead and CAS w rite.
Datasheet , Volume 2 225 Processo r Configuration Reg isters 2.18 Int egrate d Graph ics VT- d Rem apping E ngin e Regist ers T ab le 2-2 0 l ists the reg isters arranged by addre ss offs et. Register bit de scriptio ns a re in the se ction s fol lowing the ta ble.
Proce ssor Config uration Registers 226 Datasheet , Volume 2 2.18.1 VER_REG—Version Re g i ster This regis ter reports the arch itecture version su pport ed.
Datasheet , Volume 2 227 Processo r Configuration Reg isters 2.18.2 CAP_REG—Capability Regist er This regist er re ports ge neral rem app ing ha rdware c apabi lities.
Proce ssor Config uration Registers 228 Datasheet , Volume 2 23 R O 1 b Un co re Isochrony ( ISOCH) 0 = R e mapping hardw ar e u nit has no criti cal isochronous requeste rs in its scope. 1 = R e mapping hardware unit has one or more cr i tica l i sochronous requeste rs in its scope.
Datasheet , Volume 2 229 Processo r Configuration Reg isters 7 RO 0 b Un core Caching Mode (CM) 0 = Not-present and err oneous entries are not cached in a ny of the rem apping caches. In v a lidations are not required for modific ations to individual not present or invalid entr ies.
Proce ssor Config uration Registers 230 Datasheet , Volume 2 2.18.3 ECAP_REG—Extended Capab ility Register This regist er r eports re ma pping hardw are extende d cap abilit ies.
Datasheet , Volume 2 231 Processo r Configuration Reg isters 1 RO-V 1b Uncore Queued In validation Sup port (QI) 0 = Hardware does Not support queued inv a lidations .
Proce ssor Config uration Registers 232 Datasheet , Volume 2 2.18.4 GCMD_REG—Global Co m m and Register This regist er co ntrols remapp ing h ardwa re. I f mul tiple contr ol fields in t his regi ster nee d to be m o dified, s oftware mu st seria lize th e mo difica tions t hrough multipl e wr ites to t his re gister .
Datasheet , Volume 2 233 Processo r Configuration Reg isters 29 R O 0 b Un core Set Fault Log (SFL) This field is va lid on ly for implementa tions supportin g adv a nced fault logging. Software s ets this field to request hardware to se t/update the fault-log pointe r used by har dw a re.
Proce ssor Config uration Registers 234 Datasheet , Volume 2 25 W O 0 b Un core Interrupt Rema pping Ena ble (IRE) This fiel d is va lid only for implementa tions supporting interrupt remapping .
Datasheet , Volume 2 235 Processo r Configuration Reg isters 2.18.5 GSTS_REG—Global S t a tus Register This regist er re ports ge neral rem ap ping ha rdware s tatu s.
Proce ssor Config uration Registers 236 Datasheet , Volume 2 2.18.6 RTADDR_REG—Root-Entry Table Address Register This reg ister pr ovide s the b ase a ddress of ro ot - entry table .
Datasheet , Volume 2 237 Processo r Configuration Reg isters 2.18.7 CCMD_REG—Conte xt Command Register This regist er man ages cont ext cac he. T he ac t of w riting the u pper mo st byte of t he CCM D_R EG with the IC C fie ld set c ause s the h ardwa re to pe rfo rm the conte xt-cac he invalidat ion.
Proce ssor Config uration Registers 238 Datasheet , Volume 2 60:59 R O-V 1h U ncore Conte xt Actual Invalid ation Granularity (CA IG) Hardware repor ts the granularity a t which an invalidation reques t was processed t hrough the CAIG f ield at th e time of reportin g invalidation complet ion (by clearing the ICC field).
Datasheet , Volume 2 239 Processo r Configuration Reg isters 2.18.8 FSTS_REG—Fault Status Register This regist er ind icates the var ious e rror sta tus.
Proce ssor Config uration Registers 240 Datasheet , Volume 2 1 ROS - V 0 b Powerg ood Primary P ending Fault (P PF) This bit indicates if ther e are one or mo re pending fa ult s log ged in the faul t recording regis ters.
Datasheet , Volume 2 241 Processo r Configuration Reg isters 2.18.9 FECTL_REG—Faul t Event Control Register This regist er spe cifies the fa ult event in terrup t messa ge co ntrol b its.
Proce ssor Config uration Registers 242 Datasheet , Volume 2 2.18.10 FEDATA_REG—Fa ult Event Data Register This regist er spe cifies the in terru pt m essag e data. 2.18.11 FEADDR_REG—Fau lt Event Address Register This regist er spe cifies the in terru pt m essag e addre ss.
Datasheet , Volume 2 243 Processo r Configuration Reg isters 2.18.13 AFLOG_REG—Adva nced Fault Log Regi ster This regist er spe cifies the ba se ad dres s of th e me mory-res iden t fault-log re gion .
Proce ssor Config uration Registers 244 Datasheet , Volume 2 2.18.14 PMEN_REG —Protected Memory Enable Regis te r This regist er ena bles th e DM A -p rotec ted me mory r egio ns set up thro ugh the PLM BASE, PLML IMT , PHM BAS E, PH MLIM IT regi sters .
Datasheet , Volume 2 245 Processo r Configuration Reg isters 2.18.15 PLMBASE_REG—Pr otected Low-Memory Base Re gister This re gist er set s up t he ba se ad dress o f DMA-pr otected low-me mory regio n be low 4 GB.
Proce ssor Config uration Registers 246 Datasheet , Volume 2 2.18.16 PLMLIMIT _REG—Protected Low-Memory Limit Register This regist er set s up t he l imit add res s o f DMA-pro tect ed lo w-memo ry reg ion belo w 4 GB .
Datasheet , Volume 2 247 Processo r Configuration Reg isters 2.18.17 PHMBASE_REG—Pr otected High-Memory Base Register This regist er set s up t he ba se ad dress of D MA-protec ted h igh-m emory reg ion.
Proce ssor Config uration Registers 248 Datasheet , Volume 2 2.18.18 PHMLIMIT_REG —Protected High-Memory Limit Register This regist er set s up t he l imit add res s o f DMA-pro tect ed hi gh-mem ory r egio n.
Datasheet , Volume 2 249 Processo r Configuration Reg isters 2.18.19 IQH_REG—In validation Queue Head Register This regi ster indic ates the inval idation que ue head. This r egis ter is treate d a s Rsvd Z b y imple ment ation s repo rting Qu eued Invalida tio n (QI) a s no t sup porte d in th e Exten ded Capab ility re gist er .
Proce ssor Config uration Registers 250 Datasheet , Volume 2 2.18.21 IQA_REG—Invalida tion Queue Addres s Register This reg ister co nfigures the base addre ss an d size o f the i nvalida tion que ue.
Datasheet , Volume 2 251 Processo r Configuration Reg isters 2.18.23 IE CTL_REG—Invalidation Event Contro l Register This regist er spe cifies the in validatio n even t inter rupt co ntrol b its.
Proce ssor Config uration Registers 252 Datasheet , Volume 2 2.18.24 IEDATA_REG—Inv alidat ion Event Data Register This regist er spe cifies the I nvalidation Even t inte rrupt message da ta.
Datasheet , Volume 2 253 Processo r Configuration Reg isters 2.18.26 IRTA_REG —Interrupt Remapping Table Address Regist er This regist er pr ovide s the b ase a ddress of Inter rupt r ema pping table.
Proce ssor Config uration Registers 254 Datasheet , Volume 2 2.18.27 IVA_REG—I nvalidate Address Register This regist er pr ovides t he DM A add ress w hose corres pond ing IOTL B entry needs to be invalidat ed throu gh t he cor respo nding IOTLB Invalidate regi ster .
Datasheet , Volume 2 255 Processo r Configuration Reg isters 2.18.28 IOTLB_REG—IO TLB Invalidate Register This regis ter inva lida tes the IOTLB. The act of writing the upper byt e of the IOTLB_R EG wit h IVT b it se t causes t he ha rdwar e to pe rform the I O TLB invalidat ion.
Proce ssor Config uration Registers 256 Datasheet , Volume 2 58:57 R O-V 1h U ncore IOTLB Actu al Invalidation G ranularity (IAIG ) Hardware repor ts the granularity a t which an invalidation reques t was processed t hrough this field when report ing inv a lidation completio n (by clearing the IVT field).
Datasheet , Volume 2 257 Processo r Configuration Reg isters 2.18.29 FRCDL_ REG—Fault Recording Low Regis ter This regist er re cords fau lt info rmat ion w hen p rimar y fau lt logging is ac tive. Ha rdwar e rep orts t he num ber and loc ation o f faul t rec ordin g regist ers th rough t he Ca pabili ty reg ister .
Proce ssor Config uration Registers 258 Datasheet , Volume 2 2.18.30 FRCDH_REG—Faul t Recording High Register This regist er r ecords fa ult informat ion w hen primary fault loggin g is a ctive. H ardw are rep orts the numb er an d loc ation of fault re cordi ng r egister s throu gh t he Ca pabi lity reg ister .
Datasheet , Volume 2 259 Processo r Configuration Reg isters 2.18.31 VTPOLICY—DMA Remap E ngine Policy Control Register This regist er co ntain s all the polic y bi ts re lated t o th e DMA re map engi ne.
Proce ssor Config uration Registers 260 Datasheet , Volume 2 2.19 PCU MCHB AR Regis ters T able 2- 21 lists the regi sters arrange d b y addr ess o f fse t.
Datasheet , Volume 2 261 Processo r Configuration Reg isters 2.19.1 MEM_TRML_ESTIM A TION_CONFIG—M emory Thermal Estimation Co nfiguration Register This regist er co ntains c onfig uration rega rdi ng VTS t emper ature es tima tion calc ulation s that are do ne b y PCOD E.
Proce ssor Config uration Registers 262 Datasheet , Volume 2 2.19.2 MEM_TRML_THRESHOLDS_ CONFIG—Memory Thermal Thresholds Configuration Reg i ster This reg ister des cribes th e thres hold s for th e mem ory therm al m anageme nt in t he M C. • The warm thres hold defi nes w hen sel f-refresh is at do uble rate.
Datasheet , Volume 2 263 Processo r Configuration Reg isters 2.19.3 MEM_TRML_STATUS_RE PORT—Memory Thermal Stat us Report Register This regist er re ports the th ermal s tatu s of DRA M.
Proce ssor Config uration Registers 264 Datasheet , Volume 2 2.19.4 MEM_TRML_TEMPER A TURE_REPORT—Me mory Thermal Temperature Repo rt Register This reg ister is used to repo rt t he esti mate d therm al st atus of the memo ry .
Datasheet , Volume 2 265 Processo r Configuration Reg isters 2.19.6 GT_PERF_STATUS—GT P erformance Status Register P-st ate en coding for th e Se condary Power P lane' s curr ent PLL frequ ency and the curre nt V ID.
Proce ssor Config uration Registers 266 Datasheet , Volume 2 2.19.8 SSKPD—Sticky Scratchpad Data Register This reg ister ho lds 64 writab le bits wi th no functio nality b ehin d them .
Datasheet , Volume 2 267 Processo r Configuration Reg isters 13:8 RWS 000000b Powerg ood Self Ref resh Latency Ti m e (WM 1) Number of microsecond s to access mem ory if memory is in Self R efr esh (0.5 us granularit y). 00h = 0 us 01h = 0.5 us 02h = 1 us .
Proce ssor Config uration Registers 268 Datasheet , Volume 2 2.20 PXP EPBAR Regist ers T able 2- 22 lists the regi sters arrange d b y addr ess o f fse t.
Datasheet , Volume 2 269 Processo r Configuration Reg isters 2.21 Def ault PEG/ DMI V T-d R emappin g Eng ine Regis ters T ab le 2-2 3 l ists the reg isters arranged by addre ss offs et. Register bit de scriptio ns a re in the se ction s fol lowing the ta ble.
Proce ssor Config uration Registers 270 Datasheet , Volume 2 2.21.1 VER_REG—Version Re g i ster This regis ter reports the arch itecture version su pport ed.
Datasheet , Volume 2 271 Processo r Configuration Reg isters 2.21.2 CAP_REG—Capability Regist er This regist er re ports ge neral rem app ing ha rdware c apabi lities.
Proce ssor Config uration Registers 272 Datasheet , Volume 2 23 RO 0b Uncore Isochrony ( ISOCH) 0 = Remapping hardware unit has no critical isochronous requeste rs in its scope. 1 = Remapping hardware unit has one or more cr itical isochro nous requesters i n it s scope.
Datasheet , Volume 2 273 Processo r Configuration Reg isters 7 R O 0b Uncore Caching Mode (CM) 0 = Not-p rese nt and erroneo us entries are Not cached in any of the rem apping caches. Invalidatio ns are not requir ed for modifi cations to individual not presen t or invalid entries.
Proce ssor Config uration Registers 274 Datasheet , Volume 2 2.21.3 ECAP_REG—Extended Capab ility Register This regist er r eports re ma pping hardw are extende d cap abilit ies.
Datasheet , Volume 2 275 Processo r Configuration Reg isters 2.21.4 GCMD_REG—Global Co m m and Register This regist er co ntrols remapp ing h ardwa re. If m ultip le cont rol fi elds in t his regi ster need to be mo dified , soft ware mu st seri alize the modifica tions throu gh mult iple write s to th is reg ister .
Proce ssor Config uration Registers 276 Datasheet , Volume 2 30 W O 0 b Un core Set Root Tab le Pointer (SRTP ) Software sets this field to set/update the root - entry table p ointer used by hardware. Th e root-entry table po in ter is specified through the Root-entry T able Address (RT A_R EG) register .
Datasheet , Volume 2 277 Processo r Configuration Reg isters 27 R O 0 b Un core Write Bu ffer Flush (WBF) This bit is va lid on ly for implementa tions requiring write buffer flushing. Software s ets this field to request that hardware flush the Root- Compl ex in t ernal write buffers.
Proce ssor Config uration Registers 278 Datasheet , Volume 2 24 W O 0 b Un core Set Interrup t Remap Table Pointer ( SIRTP) This fiel d is va lid only for implementa tions supporting interrupt- remapping . Software sets this f ield t o se t/update t he inte rrupt rema pping t a ble pointer used b y h ardware.
Datasheet , Volume 2 279 Processo r Configuration Reg isters 2.21.5 GSTS_REG—Global S t a tus Register This regist er re ports ge neral rem ap ping ha rdware s tatu s.
Proce ssor Config uration Registers 280 Datasheet , Volume 2 2.21.6 RTADDR_REG—Root-Entry Table Address Register This reg ister pr ovide s the b ase a ddress of ro ot - entry table .
Datasheet , Volume 2 281 Processo r Configuration Reg isters 2.21.7 CCMD_REG—Conte xt Command Register This regist er man ages cont ext cac he. T he ac t of w riting the u pper mo st byte of t he CCM D_R EG with the IC C fie ld set c ause s the h ardwa re to pe rfo rm the conte xt-cac he invalidat ion.
Proce ssor Config uration Registers 282 Datasheet , Volume 2 60:59 R O-V 0h U ncore Conte xt Actual Invalid ation Granularity (CA IG) Hardware repor ts the granularity a t which an invalidation reques t was processed t hrough the CAIG f ield at th e time of reportin g invalidation complet ion (by clearing the ICC field).
Datasheet , Volume 2 283 Processo r Configuration Reg isters 2.21.8 FSTS_REG—Fault Status Register This regist er ind icates the var ious e rror sta tus.
Proce ssor Config uration Registers 284 Datasheet , Volume 2 1 ROS - V 0 b Powerg ood Primary P ending Fault (P PF) This field indicates if ther e are one or more pending faults logged in the f ault recording regist ers.
Datasheet , Volume 2 285 Processo r Configuration Reg isters 2.21.9 FECTL_REG—Faul t Event Control Register This regist er spe cifies the fa ult event in terrup t messa ge co ntrol b its.
Proce ssor Config uration Registers 286 Datasheet , Volume 2 2.21.10 FEDATA_REG—Fa ult Event Data Register This regist er spe cifies the in terru pt m essag e data. 2.21.11 FEADDR_REG—Fau lt Event Address Register Registe r speci fying the interrupt m es sage addres s.
Datasheet , Volume 2 287 Processo r Configuration Reg isters 2.21.13 AFLOG_REG—Adva nced Fault Log Regi ster This regist er spe cifies the ba se ad dres s of th e me mory-res iden t fault-log re gion .
Proce ssor Config uration Registers 288 Datasheet , Volume 2 2.21.14 PMEN_REG —Protected Memory Enable Regis te r This regist er ena bles th e DM A -p rotec ted me mory r egio ns set up thro ugh the PLM BASE, PLML IMT , PHM BAS E, PH MLIM IT regi sters .
Datasheet , Volume 2 289 Processo r Configuration Reg isters 2.21.15 PLMBASE_REG—Pr otected Low-Memory Base Re gister This re gist er set s up t he ba se ad dress o f DMA-pr otected low-me mory regio n be low 4 GB.
Proce ssor Config uration Registers 290 Datasheet , Volume 2 2.21.16 PLMLIMIT _REG—Protected Low-Memory Limit Register This regist er set s up t he l imit add res s o f DMA-pro tect ed lo w-memo ry reg ion belo w 4 GB .
Datasheet , Volume 2 291 Processo r Configuration Reg isters 2.21.17 PHMBASE_REG—Pr otected High-Memory Base Register This regist er set s up t he ba se ad dress of D MA-protec ted h igh-m emory reg ion.
Proce ssor Config uration Registers 292 Datasheet , Volume 2 2.21.18 PHMLIMIT_REG —Protected High-Memory Limit Register This regist er set s up t he l imit add res s o f DMA-pro tect ed hi gh-mem ory r egio n.
Datasheet , Volume 2 293 Processo r Configuration Reg isters 2.21.19 IQH_REG—In validation Queue Head Register Register indic ating th e invali dation qu eue head . Th is regis ter is treate d as Rs vd Z by imple ment ation s repo rting Qu eued Invalida tio n (QI) a s no t sup porte d in th e Exten ded Capab ility re gist er .
Proce ssor Config uration Registers 294 Datasheet , Volume 2 2.21.21 IQA_REG—Invalida tion Queue Addres s Register This reg ister co nfigures the base addre ss an d size o f the i nvalida tion que ue.
Datasheet , Volume 2 295 Processo r Configuration Reg isters 2.21.23 IE CTL_REG—Invalidation Event Contro l Register This regist er spe cifies the in validatio n even t inter rupt co ntrol b its.
Proce ssor Config uration Registers 296 Datasheet , Volume 2 2.21.24 IEDATA_REG—Inv alidat ion Event Data Register This regist er spe cifies the I nvalidation Even t inte rrupt message da ta.
Datasheet , Volume 2 297 Processo r Configuration Reg isters 2.21.26 IEUADDR_REG—In validation Event Upper Address Register This re gist er spe cifies the I nv a lidat ion E vent interrup t mess age upper a ddr ess.
Proce ssor Config uration Registers 298 Datasheet , Volume 2 2.21.28 IVA_REG—I nvalidate Address Register This regist er pr ovides t he DM A add ress w hose corres pond ing IOTL B entry needs to be invalidat ed throu gh t he cor respo nding IOTLB Invalidate regi ster .
Datasheet , Volume 2 299 Processo r Configuration Reg isters 2.21.29 IOTLB_REG—IO TLB Invalidate Register Register to invalid ate IOTL B. The a ct of w ritin g the u pper b yte o f th e IOTLB_R EG w ith IVT field S et cau ses the ha rdware t o pe rform t he IOTLB invalidatio n.
Proce ssor Config uration Registers 300 Datasheet , Volume 2 § § 58:57 R O-V 0h U ncore IOTLB Actu al Invalidation G ranularity (IAIG ) Hardware repor ts the granularity a t which an invalidation reques t was processed t hrough this field when report ing inv a lidation completio n (by clearing the IVT field).
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