Benutzeranleitung / Produktwartung SPARC64 V des Produzenten Fujitsu
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Fujitsu Limited 4-1-1 Kamik odan ak a Nahah ar a-k u, Ka was aki, 211 -858 8 J apan SP ARC JPS1 Implementation Supplement: Fujitsu SP ARC64 V Fujitsu Limited Release 1.
Release 1. 0, 1 J uly 2002 F . Chapte r 2 Copyright 2002 Sun Microsystems, Inc., 901 San Antonio Road, Palo Alto, California 94303 U.S.A. All rights reserved. Portions of this document ar e protected by copyright 1994 SP ARC International, Inc.
3 SP ARC JPS1 Implementati on Supplement: Fuj itsu SPA RC64 V • Re lease 1.0, 1 J uly 2002.
i F .CHAPTER Contents 1. Ov e r v i e w 1 Navigating the S P ARC64 V Implementation S upplement 1 Fonts and Notatio nal Conventions 1 The SP ARC64 V processor 2 Component Ove rview 4 Instruction Control Unit (IU) 6 Execution Unit (EU) 6 Stor age Uni t (SU) 7 Secondar y Cache and External A ccess Unit (SXU) 8 2.
ii SP ARC JPS1 Implementati on Supplement: Fuj itsu SPA RC64 V • Re lease 1.0, 1 J uly 2002 Floating-Point Defer red-T rap Queue (FQ) 24 IU Defe rred -T rap Q ueue 24 6.
Release 1. 0, 1 J uly 2002 F . Chapter Contents ii i SP ARC JPS1 Implementation-D ependent T raps 39 8. Me mo r y M od e l s 41 Overview 42 SP ARC V9 M em ory Mo del 42 Mode C ontrol 42 Synchronizing Instruction and Data Me mo ry 42 A.
iv SP ARC JPS1 Implemen tation Suppl ement: Fujitsu SPARC64 V • Release 1 .0, 1 July 200 2 D. Form al S pe cifi c atio n o f t he M emo ry M od els 81 E.
Release 1. 0, 1 J uly 2002 F . Cha pter Con tents v Level- 1 Dat a Ca c he (L1D C a ch e) 12 7 Level-2 Unified Cache (L 2 Cache) 127 Cache Coher ency Proto cols 128 Cache Contr ol/Status Instructions .
vi SP ARC JPS1 Implemen tation Suppl ement: Fujitsu SPARC64 V • Release 1 .0, 1 July 200 2 err or_state T ransition Err or 150 Urgent Er ror 150 Restrainable Error 152 Ac t i o n a n d E r ro r C o .
Release 1. 0, 1 J uly 2002 F . Chapter Contents vi i TLB Err or Handling 1 95 Handling of TLB En try Err ors 195 Automatic W ay Reduction of sTLB 196 Handling of Extende d UP A Bus Interface Err or 197 Handlin g of Exte nded UP A Addr ess Bus Err or 197 Handlin g of Extende d UP A Da ta Bus Err or 197 Q.
viii SP ARC JPS1 Implemen tation Su pplement: Fujitsu SPARC64 V • R ele a se 1. 0, 1 July 20 02.
1 F .CHAPTER 1 Overview 1.1 Navigating the SP ARC64 V Implementation Supplement W e suggest tha t you approach thi s Implem entat ion Supple ment SP ARC Joint Prog ramming Specification as fol lows.
2 SP ARC JPS1 Implementati on Supplement: Fuj itsu SPA RC64 V • Release 1. 0, 1 J uly 2002 1.3 The SP ARC64 V pr ocessor The SP AR C64 V processor is a hig h-performance, high-reliability , and high-integrity pr ocessor that fully implemen ts the in struction set arch itectur e that conforms to SP ARC V9, as described in JPS1 Commonal ity .
Release 1. 0, 1 J uly 2002 F . Chapter 1 Overvie w 3 1. Advanced RAS features for caches ■ Str ong cache error pr otection: ■ ECC p rotecti on for D1 (Da ta level 1 ) cache dat a, U2 (u nified level 2) cac he data, and the U2 cache tag. ■ Parity pr otection for I1 (Ins truction level 1) cache data.
4 SP ARC JPS1 Implementati on Supplement: Fuj itsu SPA RC64 V • Release 1. 0, 1 J uly 2002 ■ Asynchr onous dat a error ( ADE ) trap for add itional err ors: ■ Rel axe d in st ruct io n end met h.
Release 1. 0, 1 J uly 2002 F . Chapter 1 Overvie w 5 FIGURE 1-1 SP ARC64 V Major Units Extended UP A Bus UP A interface logic Mov eIn buff er Mov eOut buff er SX- Uni t U2$ U2$ dat a S-Unit int erf ac.
6 SP ARC JPS1 Implementati on Supplement: Fuj itsu SPA RC64 V • Release 1. 0, 1 J uly 2002 1.3.2 Instr uction Contr o l Unit (IU) The IU p redict s the instr uction ex ecution path , fetches ins tru.
Release 1. 0, 1 J uly 2002 F . Chapter 1 Overvie w 7 1.3.4 Storage Unit (SU) The SU handles a ll sourcing and sinking of data for load and store instructions. TA B L E 1 - 3 de scribes the SU major blocks. Interface r egisters Input/output r egisters to other uni ts.
8 SP ARC JPS1 Implementati on Supplement: Fuj itsu SPA RC64 V • Release 1. 0, 1 J uly 2002 1.3.5 Secondary Cache and External Access Unit ( SXU) The SX U contr ols the operation of un ified level-2 caches and t he external d ata access interfac e (extended U P A i nterface).
9 F .CHAPTER 2 Definitions This ch apter def ines concept s unique to the S P ARC6 4 V, the F ujitsu im plementa tion of SP ARC JPS1. For definition of te rms that are comm on to all implementations, please refe r to Chapter 2 of C ommonali ty .
10 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 instruction reti red T erm appl ied to an in struction when all mac hine resources (seri al numbe rs, r ena me d registers) have been reclaimed and ar e availabl e for use by oth er instructi ons.
Release 1. 0, 1 J uly 2002 F . Chapter 2 Definiti ons 11 in pa rallel. When inst ructions are committed , res ults in r enamed reg isters a re posted to the ar chitected r egisters in th e pr oper sequ ence to pr oduce the corr ect pr ogram re sults. scan A me thod us ed to in itializ e all of the mac hine st ate wit hin a ch ip.
12 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02.
13 F .CHAPTER 3 Ar chitectural Overvi ew Please r efer to C hapter 3 in the Commonalit y sectio n of SP ARC Joint Pro gramming Specificatio n ..
14 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02.
15 F .CHAPTER 4 Data Formats Plea se r efer to Chap ter 4, Data Form ats in Commonality ..
16 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02.
17 F .CHAPTER 5 Registe rs The SP ARC64 V processor includes two ty pes of re gisters: general-purpose — tha t is, working, data, c ontro l/status — and A SI r egist ers.
18 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 5.1.7 Floating-Point Stat e Register (FSR) Plea se r efer to S ection 5.1. 7 of Commonality for the description of FSR . The section s below des cribe SP ARC64 V-specific feat ures of the FSR reg i s t e r .
Release 1. 0, 1 J uly 2002 F . Chapter 5 Register s 19 else i f (<F Pop commits wit h IE EE_754_ exce ption >) <set o ne bi t in the CE XC f ield as sup plie d by FPU>; else i f (<F Pop.
20 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 Note – Spurio us set ting of the PSTATE .RED bit by priv ileged softwar e should not be performed, sin ce it will take the SP ARC64 V into RED_state wi thou t the requir ed se quencing.
Release 1. 0, 1 J uly 2002 F . Chapter 5 Register s 21 The Pe rformance Contr ol Register in SP ARC64 V is il lustrated in FIGUR E 5-1 and described in TA B L E 5 - 2 . FIGURE 5-1 SP ARC64 V Perfo rmance Control Reg ister (PCR) (ASR 16) TA B L E 5 - 2 PCR Bit Descrip tion Bit Field Description 47:32 OVF Overfl ow Cle ar/Se t/Stat us.
22 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 Performance Instrumentation Counter (PIC) Register (ASR 17) The PIC reg ister is implemented as desc ribed in SP ARC JPS1 Commonality . Four PIC s ar e implem ented in SP ARC64 V.
Release 1. 0, 1 J uly 2002 F . Chapter 5 Register s 23 Af te r a p ow er- on res et ( POR ), all fie lds of DCUCR , including implementation- depen dent field s, ar e set to 0. Af ter a WDR , XIR , or SIR reset, a ll fields of DCUCR , incl udi ng imp lemen tat ion -d epen den t fie lds, are se t to 0.
24 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 Data W a tchpoint Regist ers No imp leme ntati on-d epend ent fe ature of SP ARC64 V reduce s the reliabi lity of d ata watchp oints (i mpl. dep . #244) . SP ARC64 V employs conservative c heck of P A/V A watchpoint over partial stor e instructi on.
25 F .CHAPTER 6 Instru ctions This chapt er presents SP ARC64 V impl e mentati on-spe cifi c instruct ion deta ils a nd the pr ocessor pipeline information in the se subsection s: ■ Instruct ion Exe.
26 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 1. If a memory operation y r esolves to a volatile memory addr ess ( location[y] ), SP ARC64 V w ill not speculatively prefetch location[y] for any reason; location[y] will be fe tched or stor ed to only wh en operation y is co mmitable .
Release 1. 0, 1 J uly 2002 F . Chapter 6 Instructions 27 6.1.3 Syncing Instr uctions SP ARC64 V has in structions, call ed syncing inst ructions, t hat stop executi on for the number of cycles it t akes to clea r the pipel ine and to synchr onize the pr ocessor .
28 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 6.2 Instr uction Formats and Fields Instruction s are encoded in five ma jor 32-bit formats and seve ral minor form ats. Plea se r efer to Sec tion 6. 2 of Commonalit y for illustrations of four m ajor formats.
Release 1. 0, 1 J uly 2002 F . Chapter 6 Instructions 29 Since size = 00 is n ot IMPD EP2B and sin ce size = 1 1 assu med quad operatio n s bu t is not implem ented in SP ARC64 V, the instruct ion with size = 00 or 1 1 generat es an illegal_instruction exception in SP ARC6 4 V.
30 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 SP ARC64 V impleme nts JMPL and CALL re turn pre diction har dware in a form of special s tack, call ed the Return Addr ess Stack (RAS ).
Release 1. 0, 1 J uly 2002 F . Chapter 6 Instructions 31 6.4 Pr ocessor P ipeline The pipeline of SP ARC64 V consists of fiftee n stages, shown in FIGURE 6-2. Each stage is r eferenc ed by one or two lett ers as follows: 6.4.1 Instr uction Fetch Stages ■ IA (Instr uction Addr ess genera tion) — Calcula te fetch ta rget addr ess.
32 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 FIGURE 6-2 SP ARC64 V Pipeline IA IT IM IB IR D P B X Ts Ms Bs Rs U W E Ps BRHIS iTL B Instruction Buff er R.
Release 1. 0, 1 J uly 2002 F . Chapter 6 Instructions 33 6.4.2 Issue Stages ■ E (Entry) — Instruct ions are passed from fetch st ages. ■ D (Decode) — Assig n resour ces and di spatch t o r eserv ation stat ion (RS.) SP ARC64 V is an out -of-or der execut ion CPU.
34 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 Execution Stages for Cache Access Memory ac cess req uests ar e passed to the cache access pipeline afte r the target address is calcul ated.
35 F .CHAPTER 7 Tr a p s Plea se r efer to Chap ter 7 o f Commonality . Section numbe rs in this chap ter corr espond to those in C hapter 7 of Commonal ity .
36 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 7.1.1 RED_state R E D _ s t a t e Tr a p Ta b l e The RED_st ate trap vector is located at an im pleme ntation-dep endent add ress re fe rre d t o a s RS TVad dr .
Release 1. 0, 1 J uly 2002 F . Chapter 7 T r aps 37 Although th e standard beh avior of the CPU upon an en try into error _state is to interna lly gener ate a w atchdog_reset (WDR), the CPU option ally stays halte d upon an entry to error_state dependin g on a se tting i n the OPS R re gist er (imp l.
38 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 7.3 T rap Contr ol Plea se r efer to Sec tion 7. 3 of Commonalit y . 7.3.1 PIL Contr ol SP ARC64 V re ceives exter nal int errupts fr om the UP A interc onnect.
Release 1. 0, 1 J uly 2002 F . Chapter 7 T r aps 39 7.4.4 Details of Supported T raps Plea se r efer to S ection 7.4. 4 in Commonality . SP ARC64 V Implementation-Specific T raps SP ARC64 V supports t he followin g impleme ntation-specifi c trap type : ■ async_data_error 7.
40 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 ■ Uncorr ectable errors in the interna l ar chitectur e regist ers (general r egisters – gr , floating-p.
41 F .CHAPTER 8 Memory Models The SP ARC V9 ar chitectur e is a model that spec ifies the behavior obs ervable by softwar e on SP ARC V9 s ystems. Ther efore, access to mem ory can be implem ented in .
42 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 8.1 Overview Note – Th e wor ds “ hardware memory model ” denote th e underlyi ng har dwar e memory model s as differ entiated fr om the “ SP ARC V9 me mory mode l , ” which is the memory model the progr ammer select s in PSTAT E.
Release 1. 0, 1 J uly 2002 F . Chapter 8 Memor y Models 43 corr esponding locations in all instructi on caches; r e fer ences to any inst ruction cache cause corr esponding modified data to be flushed and corresponding unmodified data to be invalidated fr om all data caches.
44 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02.
F .APPENDIX 45 A Instr uction Defi nitions: SP ARC64 V Extensions This appe ndix describes t he SP A RC64 V-s pecific im plementation of the instruct ions in Appendix A of Commonali ty . If an instruction is not describe d in t his appendix, then no S P ARC6 4 V implementat ion-dependen cy applies .
46 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 4. A description of the featur es, r estrictions, and exception-causing conditions. 5. A list of e xceptions tha t can occur as a conseque nce of atte mpting to execute the inst ruc tion( s).
Release 1. 0, 1 J uly 2002 F . Chapter A Instruction Defi nitions: SP A RC64 V Extensions 47 A.4 Block Load and Stor e Instr uctions (VIS I) The followin g notes summariz e behavior of b lock load/stor e instr uctions in SP ARC64 V.
48 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 4. The block stor e with commit instr uction always store s the operand in main storage and inv alidates the l ine in the L1D cache if it is pre sent.
Release 1. 0, 1 J uly 2002 F . Chapter A Instruction Defi nitions: SP A RC64 V Extensions 49 A.12 Call and Link SP ARC64 V cle ars the u pper 32 bits of th e PC va lue in r[15 ] when PSTATE.AM is set (impl. dep. #125). T he value wri tten into r[15] is visible to the instr uction in th e delay slot.
50 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 A.24.1 Floating -Point Multiply-Add/Subtract SP ARC64 V uses I MPDEP2B opcode space to encode the Floating- Point Multiply Add/Subtract ins tructions. † 11 is reserved for quad.
Release 1. 0, 1 J uly 2002 F . Chapter A Instruction Defi nitions: SP A RC64 V Extensions 51 Descri ption The Floating-point Multi ply-Add instruction s multiply th e registe rs specified by the rs1 f.
52 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 det ects any co ndit ions for an unfinished_FP op trap, the Floating- point Multip ly-Add/ Subtract instr uction genera tes the unfinished_FP op exception. In this case, none of rd , cexc , or aexc are mod ified.
Release 1. 0, 1 J uly 2002 F . Chapter A Instruction Defi nitions: SP A RC64 V Extensions 53 Programming Note – The M ultiply Add/Subtract instructions a re e ncoded in the SP ARC V9 IMPDEP2 opcode sp ace, an d they are speci fic to the SP ARC64 V impl ementati on.
54 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 A.30 Load Quadwor d, Atomic [Physical] The Load Qu adword A SIs in this s ection are specific to SP ARC64 V, as an e xtension to SP ARC JPS1 .
Release 1. 0, 1 J uly 2002 F . Chapter A Instruction Defi nitions: SP A RC64 V Extensions 55 ■ TTE.NFO = 0 ■ TTE.CP = 1 ■ TTE.CV = 0 ■ TTE.E = 0 ■ TTE.P = 1 ■ TTE.W = 0 Note – TTE .IE depends on the endianness of the ASI. When the ASI is 034 16 , TTE.
56 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 Descri ption The me mory barrier instruct ion, MEMBAR , has two complement ary functions: to expres s order con strai nts betw een me mory reference s and to provide e xpli cit c ontro l of memory-r eferen ce completion.
Release 1. 0, 1 J uly 2002 F . Chapter A Instruction Defi nitions: SP A RC64 V Extensions 57 A.42 Partial Stor e (VIS I) Plea se r efer A. 42 in Commonal ity for general details. W atchpoint exceptions on p artial stor e instr uctions occur cons ervatively on SP ARC64 V .
58 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 TA B L E A - 7 describes prefetch variants implemented in SP ARC64 V. A.51 Read State Register In SP ARC64 V, an RD PCR instructio n will generate a privileged_action exception if PSTATE.
Release 1. 0, 1 J uly 2002 F . Chapter A Instruction Defi nitions: SP A RC64 V Extensions 59 A.70 W rite State Register In SP ARC64 V, a WRPC R instruction will cause a privileged_action exception if PSTATE.PRIV =0 a n d PCR.PRIV =1 . I f PSTATE .PRIV =0 a n d PCR.
60 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02.
F .APPENDIX 61 B IEEE Std 754-1985 Requir em ents for SP ARC V9 The IEEE Std 754-1 985 floating-point standard contains a number of implementation depe nden cies . Please see App endix B of Commonality for choices for these imple mentation depen dencies, to ensur e that SP ARC V9 implementati ons ar e as consist ent as possible.
62 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 SP ARC64 V floating-point hardw are has i ts specific range of com putation.
Release 1.0, 1 J u ly 2002 F . Chapter B IEEE Std 754-1 985 Requirements f o r SP ARC V9 63 Implem entation No te – Detecting the exact b oundary conditions r equires a lar ge amount of har dware.
64 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 Pessimistic Zer o If a condition i n TA B L E B - 3 is true , SP ARC64 V genera tes the r esult as a pess imist ic zer o, meanin g that the r esult is a denorma lized mini mum or a zer o, depending on the rounding mode ( FSR.
Release 1.0, 1 J u ly 2002 F . Chapter B IEEE Std 754-1 985 Requirements f o r SP ARC V9 65 Pessimistic Overflow If a condition i n TA B L E B - 4 is true , SP ARC64 V regar ds the operation as having an overflow condition. B.6.2 Operation Under FSR.NS = 1 When FSR.
66 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 summarizes the behavi or of SP ARC6 4 V floating-point har dwar e depending on FSR.NS . Note – The re sult an d behavi or of SP ARC64 V of the sha ded colum n in the tab les T a ble B-5 and T able B-6 conform t o IEEE754-1985 s t andard.
Release 1.0, 1 J u ly 2002 F . Chapter B IEEE Std 754-1 985 Requirements f o r SP ARC V9 67 TA B L E B - 6 de scribe s how SP ARC64 V beh aves whe n FSR.
68 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02.
F .APPENDIX 69 C Implementation De pendencies This ap pendix summarizes implementation dependencies. In SP ARC V9 and SP ARC JPS1, the nota tion “ IMPL. DEP . # nn : ” iden tifies the defini tion of an implem entation dependen cy; the nota tion “ (impl.
70 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 C.2 Har dwar e Characteristics Pleas e refer to Se cti on C.2 o f Commonality . C.3 Implem entatio n Dependen cy Categories Pleas e refer to Se cti on C.3 o f Commonality .
Release 1. 0, 1 J uly 2002 F . Chapter C Implementati on Dependen cies 71 9 RDASR / WRASR privi l eged status See A.50 and A.70 in Commonality for detail s of implementation-dependent RDASR / WRASR in structions. — 10 – 12 Reserved. 13 VER . impl VER.
72 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 32 Deferred traps SP ARC64 V signals a deferred trap in a few of its severe error conditions.
Release 1. 0, 1 J uly 2002 F . Chapter C Implementati on Dependen cies 73 42 FLUSH ins truction SP ARC64 V implements the FLUSH ins truction in ha rdware. — 43 Reserved. 44 Data access FPU trap The destination r egister(s) are unchanged if an access error occurs.
74 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 106 IMPDEP n in struction s SP ARC64 V uses the IMPDEP2 opcode for the Multi ply Add/Subtract instruct io n s. SP ARC64 V al so c on fo rm s t o Su n ’ s spec ification for VIS -1 and VIS-2.
Release 1. 0, 1 J uly 2002 F . Chapter C Implementati on Dependen cies 75 11 9 Unim plemented values f or PSTATE.MM W r iting 11 2 into PSTATE.MM causes the machine to u se the TSO memory model. However , the e ncoding 1 1 2 should not be used, si nce futur e versions of SP ARC64 V may use this encoding f or a new memory model.
76 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 206 SHUTDOWN in struction In priv ileged mod e the SHUTDOWN instr uction execut es as a NOP in SP ARC64 V .
Release 1. 0, 1 J uly 2002 F . Chapter C Implementati on Dependen cies 77 218 async_d ata_err or async_data_erro r trap is implemente d in SP ARC64 V , using tt =4 0 16 .
78 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 227 TSB number of entries SP ARC64 V supports a maximum of 16 million entries in the common TSB and a maximum of 32 m illion lines the Split TSB.
Release 1. 0, 1 J uly 2002 F . Chapter C Implementati on Dependen cies 79 240 DCU Cont rol Register bits 47:41 SP ARC64 V uses bit 41 for WEAK_SPCA , wh ich enable s/disabl es memo ry access in spec ulative pat hs. 23 241 Address Masking and DSFAR SP ARC64 V writes zer oes to the more signifi cant 32 bits of DSFAR .
80 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 252 DCUCR.DC (D ata Cache Enable) SP ARC64 V does not imp lement DCUCR.DC . 24 253 DCUCR.IC (Instruction Cache Enabl e) SP ARC64 V does not implement DCUCR.IC .
F .APPENDIX 81 D Formal Specification of the M emory Models Pleas e refer to Appen dix D of Common ality ..
82 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02.
F .APPENDIX 83 E Opcode Maps Please r efer to Appendix E in Commonality . TA B L E E - 1 lists th e opcode map for the SP ARC64 V IMPDE P2 in stru ction .
84 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02.
F .APPENDIX 85 F Memory Management Unit The Me mory Ma nagement Unit ( MMU) architec ture of SP ARC64 V c onfo rms to the MMU ar chitectur e defined in Appendix F of Commonality bu t with some model depen d e ncy . See Appe ndix F in Commonality for the basi c definiti ons of the SP ARC64 V MMU.
86 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 The micro-TLBs ar e coherent to main TLBs and are not visible to softwar e, with the excep tion of TLB multip le hit detec t ion. Har dware maint ains the cons istency between micro-TLBs and main TLBs.
Release 1. 0, 1 J uly 2002 F . Chapter F Memor y Management Uni t 87 The ph ysical addr ess lengt h to be passed to the UP A interfac e is 41 bits or 43 bits , as desi gnated in the ASI_UPA_CO NFIG.AM fiel d. When t he 41-bi t PA is specified in ASI_ UPA_ CONF IG.
88 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 F .3.3 TSB Organization IMPL. D EP . # 227 : The maxim um number of en tries in a T SB is imple mentation dependen t in JPS1. See impl. dep. #22 8 for the limitat ion of TSB_ size in TSB re g is t e r s.
Release 1. 0, 1 J uly 2002 F . Chapter F Memor y Management Uni t 89 8K_POINTER = TSB_Extension[63:1 4+N] 0 (VA[21+N:13] ⊕ TSB_Hash) 0000 64K_POINTER = TSB_Extension[63:14+N] 1 (VA[24+N:16] ⊕ TSB_.
90 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 ■ X1: The contents of the contex t field of the D-MMU T ag Access Registe r ar e undefined after a data_access_exception . ■ X2: I-SFS R is updated according to i ts update policy described in Section F .
Release 1. 0, 1 J uly 2002 F . Chapter F Memor y Management Uni t 91 ■ An fDTLB entry parity err or is detected in a fDTLB lookup for an inst ruction operand acce ss.
92 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 F .10 Internal Registers and ASI operations F .10.1 Accessing MMU Registers IMPL. D EP . # 233 : Wh eth er th e TSB_Hash field is implem ented in I/D Primary/S econdary/Nucleu s TSB Exten sion Register is implementa tion dependent in JPS1.
Release 1. 0, 1 J uly 2002 F . Chapter F Memor y Management Uni t 93 F .10.4 I/D TLB Data In, Data Access, and T ag Read Registe rs IMPL . DEP . #234 : The r eplacement algorithm of a TLB ent ry is impleme ntation dependent in JP S1.
94 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 For fTLB, SP A RC64 V implements a pseudo-LR U. For sTLB, LRU is used. IMPL. D EP . #235 : The MMU TLB data access address assignment and the purpose of the ad dr ess ar e implementat ion depe ndent in JP S1.
Release 1. 0, 1 J uly 2002 F . Chapter F Memor y Management Uni t 95 The MMU TLB data access address assignment and the purpose of the address on SP ARC64 V are shown in TA B L E F - 4 . TA B L E F - 4 MM U TLB Data Access Addr ess Assignment V A Bi t Field Description 17:16 TLB# T LB to be accessed: fTLB or sTLB i s designated as follows.
96 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 FIGURE F-2 Index n umber of set associ ative TLBs I/D MMU TLB T ag Access Register On an ASI stor e to the TLB Data Access or Data In Register , SP ARC64 V verifies the consiste ncy betwee n the T ag Access Regis ter and the data t o be writte n.
Release 1. 0, 1 J uly 2002 F . Chapter F Memor y Management Uni t 97 I/D TSB Base Registers IMPL . DEP . #236 : The width of the TSB_ Size field in the TSB Ba se Register is impl ementati on dependent; the per mitted ra nge is fr om 2 to 6 bi ts. The least signif icant bit of TSB_Size is alway s at bit 0 of the TSB Base R egister .
98 SP ARC JPS1 Implementati on Supplement: Fuji tsu SPARC64 V • Release 1.0, 1 July 20 02 The specifica tion of bits 24:0 in the SP ARC64 V SFSR conforms to the specification defined in Section F .10.9 in Commonalit y . Bits 63:25 in SP ARC64 V SFSR are impl ementati on dependent.
Release 1. 0, 1 J uly 2002 F . Chapter F Memor y Management Uni t 99 TA B L E F - 6 des cribes the field encoding for ISFSR.FT . Data <15> TM R/W T ranslation mis s. When TM = 1, it signifi es an occurrenc e of a mITLB miss u pon an i ns tru ct io n re fe ren ce.
100 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 ISFSR is updated either up on a occurrenc e of a fast_instruction_access_MMU_mi ss , an instruction_access_exception , or an instruction_acces s_error trap.
Release 1. 0, 1 J uly 2002 F . Chapter F Memor y Management Unit 101 Data <46> MK R/W Marked UE . On SP ARC64 V, all uncorrectable err ors are reported as marked, so this bit i s always set whenev er DSFSR.UE =1 . See Sec tion P .2.4 for detail s.
102 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 TA B L E F - 9 defines the encod ing of the FT <6:0 > field. Data CT <1:0> R/ W Context type. Saves the context attribute for the refe rence that invo kes an exception.
Release 1. 0, 1 J uly 2002 F . Chapter F Memor y Management Unit 103 Multiple b its of DSFSR.FT ma y be set by a trap as long as the cause of the trap match es mu ltipl y in TA B L E F - 9 .
104 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 F .1 1 MMU Bypass On SP ARC64 V, two addition al ASIs are supporte d as DMMU byp ass acces ses: ASI_ATO.
Release 1. 0, 1 J uly 2002 F . Chapter F Memor y Management Unit 105 F .1 1.10 TLB Replacement Policy Automatic TLB Replacement Rule On an automatic repla cement wri te to the TLB, the MMU picks the e ntry to wr ite accor ding to the following rul es: 1.
106 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 ■ sTLB entry updat e data: ■ New sTLB entry da t a is designated in stxa data. ■ New sTLB entry tag is designated in the I/D TLB T ag Access Regis ter .
F .APPENDIX 107 G Assembly Language Syntax Pleas e refer to Appen dix G of Comm onality ..
108 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002.
F .APPENDIX 109 H Softwar e Considerations Pleas e refer to Appen dix H of Commonality ..
110 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002.
F .APPENDIX 111 I Extending the SP ARC V9 Ar chitectur e Pleas e r efe r to Appen dix I of Commonalit y ..
112 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002.
F .APPENDIX 113 J Changes fr om SP ARC V8 to SP ARC V9 Pleas e r efe r to Appendi x K of Commonalit y ..
114 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002.
F .APPENDIX 115 K Pr ogramming with the Memory Models Please refer to App endix J of Commonality ..
116 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002.
F .APPENDIX 117 L Addr ess Space Id entifiers Every loa d or stor e address in a SP ARC V9 processor has an 8-b it Address Spac e Ident ifier (ASI) appended to t he V A .
118 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 45 16 ASI_DCU_CON TROL _REG ( ASI_DCUCR )R W 0 0 2 2 45 16 ASI_MEMORY_ CONTROL_R EG RW 0 8 9 2 46 16 .
Release 1. 0, 1 J uly 2002 F . Chapter L Address Space Identi fiers 11 9 L.3.2 Special Me mory Access ASIs Please refer to Sectio n L.3.3 in Commonality . In addition to the ASIs described in Commonalit y , SP ARC64 V supports th e ASIs described below .
120 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 ASI 4F 16 ( ASI_SCRA TCH_REGx ) SP ARC64 V provid es eight of 64-bit r egisters that can be used temporary storage f or supervisor soft ware.
Release 1. 0, 1 J uly 2002 F . Chapter L Address Space Identi fiers 12 1 n = 2 (4-byte alignment): LDDF_ mem_address_not _aligned exc eption is generated. n ≤ 1 ( ≤ 2-b yte alignment ): mem _address_not_a ligned excepti on is generate d. 2. If the memory addr ess is correctly aligned, SP ARC64 V generates a data_a ccess_e xception wi th AFSR.
122 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 3. Wh en th e LBSY on the SB is change d, LBSY change i nformation is br oadcast to all CPUs in t he SB. Each CPU r eceives the cha nge information and updates its copy .
Release 1. 0, 1 J uly 2002 F . Chapter L Address Space Identi fiers 12 3 BSTW Control Register ( ASI_C_BSTW0 , ASI_C_BSTW1 ) The BSTW con trol r egi ster desi gnates wh ich bit in LB SY is written thr ough ASI_BSTW x .
124 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 Last Barrier Sy nchr onizatio n Status R ead ( ASI_LBSYR0 , ASI_LBSYR1 ) ASI_LBSYRx i s a read interface to th e copy of LB SY . A write to ASI_LB SYRx is ignor ed.
F .APPENDIX 125 M Cache Or ganization This appe ndix describes SP ARC64 V cache or ganization in t he following sect ions: ■ Cach e T ypes on page 125 ■ Cache Coher ency Pr otocols on page 128 ■ Cache Contr ol/Status Instructions o n p a g e 1 2 8 M.
126 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 M.1.1 Level-1 Instruction Cache (L1I Cache) T ABLE M -1 shows the characterist ics of a level -1 instructio n cache. Although an L1 I cache is VIPT , TTE.
Release 1. 0, 1 J uly 2002 F . Chapter M Cache Organizat ion 127 M.1.2 Leve l-1 Data Cache (L 1D Ca che) The level-1 da ta cache is a writeback ca che. Its charac teristics ar e shown in TA B L E M - 2 . Although L1D ca che is VIPT , TTE.CV is ineffect ive since S P ARC64 V has unaliasing features in har dware.
128 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 M.2 Cache Coh er enc y Pr ot ocols The CPU uses the UP A MOE SI cache- cohere nce pr otocol; thes e let.
Release 1. 0, 1 J uly 2002 F . Chapter M Cache Organizat ion 129 1. The opc ode of the instructions shou ld be ldda , ldxa , lddfa , s tda , stxa , or stdfa . Otherwise, a data_a ccess_exceptio n exc epti on wi th D-SFSR.FT =0 8 16 (Invalid ASI) is generated.
130 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 M.3.2 L evel-2 Cache Control Register ( ASI_L2_CTRL ) ASI_L2 _CTRL is a contr ol register for L2 training, inte rface, and size configuration. It is illu strated below and describ ed in TA B L E M - 6 .
Release 1. 0, 1 J uly 2002 F . Chapter M Cache Organizat ion 131 ASI_L2_DIAG _TAG_REA D works in concert with ASI_L2_DI AG_TAG_R EAD_REG . A read to ASI_L2_D IAG_TAG_ READ ret urns 0, with t he side ef fect of setti ng the tag to AS I_L2_DIAG_TA G_READ_RE G0-6 .
132 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002.
F .APPENDIX 133 N Interr upt Handling Interrup t handling in S P ARC64 V is descri bed in these sections: ■ Interrupt Dispatch on page 133 ■ Interrupt Receive on page 135 ■ Inte rrupt-R elated ASR Regi sters o n p a g e 1 3 6 N.
134 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 read ASI_I NTR_DISP A TCH_ST A TUS Error (begin atomi c sequen ce) PST A TE.
Release 1. 0, 1 J uly 2002 F . Chapter N Interrupt Handli ng 135 N.2 Interrupt Receive When an in terrupt packet is r eceived, ei ght interr upt data r egisters ar e updated with the as sociated i ncomi n g data an d the B USY bi t in th e ASI_INT R_RECEIVE re gi s t e r i s set.
136 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 N.3 Interr upt Glo bal Registers Plea se r efer to Sec tion N.3. of Commonality . N.4 Interr upt-Re lated ASR Registers Plea se re fer to Sec tion N.4 o f Commona lity f or deta ils of t hese regi sters.
F .APPENDIX 137 O Reset, RED_state, and err or_state The appendix contains the se sections: ■ Reset T ypes on page 137 ■ RED_s tate a nd error_ state o n p a g e 1 3 9 ■ Proce ssor State af ter Reset and in RED_state o n p ag e 1 4 1 O.
138 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 3. The UP A_RESET_L p in is deassert ed. The p rocess or enters RED_state with TT = 1 trap to RSTVad dr + 20 16 and starts the instruction execu tion. O.1.
Release 1. 0, 1 J uly 2002 F . Chapter O Rese t, RED_state , and erro r_state 13 9 O.2 RED_state and err o r_state FIGURE O- 1 illustrates the pr ocessor state transit ion diagram.
140 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 O.2.1 RED_state Once the p rocess or enters RED_state for any r eason except when a power -on r eset (P.
Release 1. 0, 1 J uly 2002 F . Chapter O Rese t, RED_state , and erro r_state 14 1 O.2.3 CPU Fatal Err or state The pr ocessor enters C PU fatal err or state when a fatal error is detected on the pr ocessor .
142 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 TLE CLE 0/ C opied from CLE 0/ Unc hanged Copied from CL E Unchanged TBA <63:15> Unkno wn/Unchang.
Release 1. 0, 1 J uly 2002 F . Chapter O Rese t, RED_state , and erro r_state 14 3 TA B L E O - 2 ASR State after Rese t and in RED_st ate A S RN a m e P O R 1 1.Hard POR occurs w hen power is cycled. Values are unknown following hard POR. Soft POR occurs when UPA_RESET_L is asserted.
144 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 4A 00 UPA_CONFI G WB_S WRI_S INT_S UC_S AM MCAP CLK_MODE SCIQ1 SCIQ0 UPC_CAP2 MID UPC_CAP 000/Unc hange.
Release 1. 0, 1 J uly 2002 F . Chapter O Rese t, RED_state , and erro r_state 14 5 58 20 DMMU_SFAR Unknown/Unchanged Unchanged 58 28 DMMU_TSB_ BASE Unknown/Unchanged Uncha nged 58 30 DMMU_TAG_ ACCESS .
146 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 O.3.1 Operating Status Register ( O PSR ) OPSR is the control r egister in the CPU that is scanned in during the har dware power -on rese t sequence befor e the CP U starts running.
Release 1. 0, 1 J uly 2002 F . Chapter O Rese t, RED_state , and erro r_state 14 7 O.3.2 Har dwar e Power- On Reset Sequence T o be de fined later . O.
148 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002.
F .APPENDIX 149 P Err o r Hand ling This appe ndix describes pr ocessor behavior to a pr ogrammer writing operating system, firmware, and recovery code for SP ARC64 V.
150 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 When the CPU detects the fatal err or , the CPU enters F A T AL error _state and r eports the fatal err or occurrence to the sy stem contr oller . The system contr oller trans fers the entir e system state to the F A T AL state and st ops the syst em.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 151 ■ Otherwise, an err or exception is generated and the damaged instructi on is exec uted a s when A SI_ERROR _CONTROL .WEAK_ED =0 i s s e t . The thr ee types of instruction -obstructing err ors are described below .
152 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 When the re sour ce with the error is used, the program can not contin ue exec uti on, o r the er ror_ state transi tion error or the fatal e rr or is dete cted.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 153 ■ Degrad ation SP ARC64 V can isol ate an in ternal har dwar e re sour ce that g enerates fre quent err ors and con tinue pr ocessing with out deleterio us ef fect on softwar e during pr ogram executi on.
154 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 P .2.2 Summary of Actions Upon Err or Detection T ABL E P-2 summa riz es what ha ppen s when an erro r is dete cted .
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 155 Action upon the err or det ection 1. CPU enters CPU fatal state. 2. CPU informs the s ystem of fatal error occurrence. 3. T he F A T AL rese t ( whi ch is a form of POR reset) is issued to th e whole system.
156 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 tt ( trap type) 1 ( RE D_state )2 ( RED_state ) ADE : 40 16 DA E : 32 16 IAE : 0A 16 63 16 Tr a p p r i o r i t y 1 1 ADE — 2 DA E — 12 IAE — 3 32 End-met hod of trapped instruction Aband oned Ab andone d.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 157 P .2.3 Extent of Automatic Sour ce Data Corr ection for Corr ectable Err or Upon detect ion of the followin g correct able err ors ( CE ), the CP U corr ects the i nput data a nd uses the corr ected data ; however , the sour ce data with the CE is not corr ected au tomaticall y .
158 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 ■ When a har dwar e unit first de tects an uncorr ected err or in the cacheab le data, t he hardware .
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 159 The ERROR_ MARK_ID (14 bits wide) identifies the err or sour ce. The har dware unit that d etects the erro r pr ovides the err or sour ce_ID and s ets the ERROR_MARK_ID valu e. The format of ERROR_MAR K_ID <13: 0> is defined in T A BLE P-5 .
160 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 Dif fer ence Between Err or Marking on SP ARC64 IV and SP ARC64 V T ABL E P-7 lists t he dif fer ences betw een err or marking on SP ARC64 IV and SPAR C64 V.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 161 P. 2 . 5 ASI_EI DR The ASI_EI DR re gister d esigna tes the sou r ce ID in th e ERROR_MA RK_ID of the CP U.
162 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 1 WEAK_ED RW W eak Error Detecti on. Contr ols whether the detecti on of I_UGE and DA E is suppressed: When WEAK _ED = 0 , error de tection is not suppress ed.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 163 P .3 Fatal Err or and e rror_sta te Tr a n s i t i o n E r r o r P. 3 . 1 ASI_ST CHG_ERR OR_INFO The ASI _STCHG_ ERRO R_INF O registe r stor es detected F A T AL error and error_ state transition err or information, for access by OBP (Open Boot PROM) software.
164 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 P .3.2 Fatal Err or T ypes ■ FE_UP A_ADDR_UNCORRECTED_ ER ROR — An uncorr ected err or in the addre.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 165 ■ Ideal specification (not implemente d) The EE_OTH ER bit is specified in ASI_STCHG_ERROR _INFO bi t 14. Wh en hardwa re dete cts error_ state transiti on err ors other than those des cribed above, it se ts ASI_S TCHG_ERR OR_INFO.
166 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 22 IAUG_CRE R U ncorr ectab le error in any of the following: (IA) ASI_EID R (IA) ASI_PA_ WATCH_POI NT .
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 167 15 AUG_SDC R S ystem data corruption. Indicate s the occurrence of the follow ing system data corru pt ion: Small data corruption: Data in the c acheable a rea wi th an unpr edictabl e address is destro yed.
168 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 P. 4 . 2 A c t i o n o f async_data_error ( ADE ) T rap The sing le- ADE trap and the mult iple- AD E trap ar e generated upon the conditions defined in T ABLE P -2 o n page 154.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 169 The following actions ar e executed in this order: a. State transition if ( TL = MAXT L ), th e CPU en ters er ror_st ate and abandons the ADE trap; else if (CP U is in exec ution state & & ( TL = MAXT L − 1)), then the CPU enters RED_state .
170 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 Err ors in r egisters oth er than those listed ab ove and a ny err ors in the T LB entry re ma i n . b. Update of ASI _UGESR , as shown in T ABLE P- 13 . c.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 171 T ABL E P-14 defi nes each instruc tion end- metho d af ter an ADE trap . P .4.4 Expected Softwar e Handling of ADE Tr a p The expec ted softwar e handling of an ADE trap is described by the pseudo C code below .
172 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 void expected_software_handling_of_ADE_trap() { /* Only %r0-%r7 can be used from here to Point#1 because the register window control registers may not have valid value until Point#1.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 173 causes the data_access_error trap when its tag matches at the DTLB reference for address translation. */ } if (ASI_UGESR.IUG_ITLB == 1) { execute demap_all for ITLB; /* A locked fITLB entry with uncorrectable error is not removed by this operation.
174 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 P .7 Restrainabl e Err ors This secti on describ es the registers — ASI_ASY NC_F AULT _STATUS , ASI_AS YNC_F AULT _ADDR_D 1 , and ASI_ ASYNC_ FAULT _ADDR_ U2 — that def ine th e r estrainable err ors and explains how softwar e handles these err ors.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 175 ■ If the P rio_U2 column for the err or shown in the table r ow is bla nk, the er ror is ne ve r re co rde d i nt o ASI_AFAR_U2 . ■ Otherwise, the Prio_U2 column for the err or shown in th e table r ow indicat es the ASI_ AFAR_ U2 r ecord ing priority , as follows.
176 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 3 UE_DST_BETO RW1C Di srupting stor e UP A bus error or timeo ut.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 177 P .7.2 ASI_ASYNC_F AUL T_ADDR_D1 T ABL E P-16 describe s the f ields of the ASI_ASYNC_FAUL T_ADDR_D1 reg iste r . [1] R egister nam e: ASI_ASYNC_FAUL T_ADDR_D1 ( ASI_ AFAR_D1 ) [2] A SI: 4D 16 [3] V A: 00 16 [4] Er r or checking: Parity [5] F orma t & f unction: S ee T ABLE P- 16 .
178 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 P .7.3 ASI_ASYNC_F AUL T_ADDR_U2 The ASI_AS YNC_FAULT_AD DR_U2 r egist er is described in T ABLE P- 17 .
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 179 P. 7 . 4 E x p e c t e d So ftwar e Handling of Restrainable Err ors Err or recor ding and information is e xpected for all r estrainable err ors . The expec t ed softw are recove ry from each type of each r estrainable err or is described below .
180 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 b. W rite the U2 cach e line with the CE detection to memory eithe r by using t he ASI_L2 _CTRL .U2_ FLUSH f a c i l i t y o r b y d i s pl a c e m e n t f l u s h .
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 181 P .8 Handling of Internal Register Erro rs This section describes err or handling for the following: ■ Most regi sters ■ ASR registers ■ ASI registers P .
182 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 P .8.2 ASR Error Handling The terminolog y used in T ABL E P-19 is defined as follows: T ABL E P-19 shows the h andling of ASR errors.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 183 P .8.3 ASI Reg ister Err or Handling The terminolog y used in T ABLE P -20 is defined as follows: 5 PC R Parity Always IUG_PST A TE AD E tr.
184 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 Error D etect Condition Always Error is al ways checked. AU G always Error i s checked when ( ASI_ERROR_CONTROL .UGE_HAND LER = 0) && ( ASI_ERROR_CON TROL.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 185 Error T y pe error_s tate error _state transition err or . (I) AUG _ xxxx The err or is indica ted by ASI_ UGESR.IAUG _ xxxx = 1, and the err or class is autonomous ur gent error . I(A) UG_ xxxx Th e error is in dicated by ASI_UGESR.
186 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 T ABL E P-20 shows the han dling of ASI register errors.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 187 58 16 30 16 DMMU_ TAG_ACCESS RW P a r i t y LDXA #D IUG_TSB P W (W otherD ) 58 16 38 16 DMMU_ VA_WATCHPO INT RW P a r i t y E n a b l e d L.
188 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 SP ARC64 V Implementation and the Id eal Specification In the table on page 183 (defining termi nology .
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 189 When a pa rity err or is detected in a D1 cache ta g entry or in a D1 cache tag cop y entry , har dwar e automati cally corr ects the e rror b y copying t he corr ect ta g entry fr om the othe r copy of the tag entry .
190 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 P .9.2 Handling of an I1 Cache Data Err or I1 ca che data is prote cted by parity att ached t o every doub lewor d. When a pa rity err or is detected in I1 cache d ata during a n instruction f etch, har dwar e executes t he following sequence: 1.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 191 Marked Uncorr ectable Err or in D1 Cache Data When a marke d uncorrect able error ( UE ) in D1 cache data is detected during the D1 cache line writeback to the U2 cache, the D1 cache data and its ECC are written to the target U2 cac he da ta and i ts EC C with out mo difi cati on.
192 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 P .9.4 Handling of a U2 Cache Data Err or U2 cache dat a is prote cted by 2-bit error det ection and 1-bi t error correction ECC, attached to every doublewor d.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 193 doublewor d an d its ECC in the r ead data and those in the source U2 cache line ar e changed to marked UE data. The r estrainable e rror ASI_AFSR. UE_RA W _L2$INSD is detected. Implem entation No te – SP ARC64 V detects ASI _AFSR.
194 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 2. Othe rwise: ■ All ent ries in I1 c ache way W a re inva lidated and the way W will nev er be re fi l l e d . ■ The r e strainable err or AS I_AFSR.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 195 2. Othe rwise: ■ All ent ries in availa ble U2 cache w ays, including way W , are inv alidated to retain system cons istenc y . ■ W ay W becomes unavai lable and is never refilled. ■ The r e strainable err or AS I_AFSR.
196 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 When a pa rity err or is detected in an ITLB entry when an LDXA instruction att empts to read ASI_ITLB_D ATA_ACCE SS or ASI_I TLB_TAG_ACCE SS , h a rdw are automatic ally demaps t he entry and an instruction urge nt err or is indicated in ASI_UGESR.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 197 sTLB W ay Redu ction When a w ay reduct ion condition is r ecognized for the sTLB w a y W ( W = 0 o r 1 ) , har dwar e executes the foll owing way r eduction pr ocedur es: 1.
198 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 ■ Raw (unmar ked) uncorr ectable err or (multibit err or) ■ Mark ed u ncor rectab l e er ror Corr e.
Release 1. 0, 1 J uly 2002 F . Chapt er P Error Handling 199 ■ Incom ing noncachea ble data fetched by an instruction fetch . When a UE is detected in su ch data, an instruction_access_error with marked UE i s d et ec te d at the time t he fe tche d inst ruc tion is ex ecute d.
200 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002.
F .APPENDIX 201 Q Performance Instrumentation This appendix desc ribes and specifies performance monitors that have be en impleme nted in the SP A RC64 V pr ocessor .
202 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 /* clear pi cs wit hou t alte ring sl /s u valu es */ pic_in it = 0x0; pcr = rd_pc r(); pcr.ul ro = 0x1; /* don’t ch an ge su/ sl on write */ pcr.ov f = 0 x0; /* c lear ov erfl ow b its als o */ pcr.
Release 1. 0, 1 J uly 2002 F . Chapter Q P erfo rmance Instrumentation 203 for(i= 0; i<=p cr .nc; i+ +) { /* ass ume r est of pcr data has been p rese rved */ pcr.sc = i; wr_pcr (pcr) ; pic = rd_pi c(); picl[ i] = pic.picl ; picu[ i] = pic.picu ; } Q.
204 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 Q.2.1 Instr uction Statistics Instruct ion statistics counters can be monitor ed by any SU or SL of any PIC . ● Performance Monitor Cycle Count (cycle_counts) Coun ts the cycl es whe n th e perfo rman ce mo nito r is en abl ed.
Release 1. 0, 1 J uly 2002 F . Chapter Q P erfo rmance Instrumentation 205 ● Instruction Count ( instruction_coun ts) Counts the number of committ ed instructions . For user or system mode counts, this coun ter is exa ct. Combined w ith the cycle_counts , it provi des instr uctions per cycle.
206 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 ● Pr efetch Instruction Count (pr efetch_instructions) Counts t he committed pr efetch inst ructions. Q.2.2 T rap-Related Statistics ● All T raps Count (trap_ all) Counts a ll trap events.
Release 1. 0, 1 J uly 2002 F . Chapter Q P erfo rmance Instrumentation 207 ● Softwar e Instructi on T rap (trap_trap_i nst) Counts the occurren ces of Tcc instructi ons. ● Instruction MMU Mis s T rap (trap_IMMU_ miss) Counts the occurren ces of f a st_instruction_access_M MU_miss .
208 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 Q.2.4 Cache Event Counters ● I1 Cache Miss C ount (if_r_i u_r eq_mi_go) Counts the occurren ces of I1 cache m isses. ● D1 Cache Mi ss Count (op_r_iu_ req_ mi_go) Counts the occurren ces of D1 cache mis ses.
Release 1. 0, 1 J uly 2002 F . Chapter Q P erfo rmance Instrumentation 209 ● L2 Cache Miss Coun t by Demand Access (sx_ miss_count_d m) Counts the occurren ces of L2 cache miss by demand access.
210 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 Q.2.5 UP A Event Counters UP A event counte rs count t he number of S_REQ _ xxx re que st s rec ei v ed by a C PU in a given tim e. ● INV Recei ve Count ( sr eq_ bi_coun t) Coun ts the numb er of S_ INV_ REQ packets r eceived.
Release 1. 0, 1 J uly 2002 F . Chapter Q P erfo rmance Instrumentation 211 Q.2.6 Miscellaneous Counters ● Barrier -Assist ASI Read Count (asi_ rd _bar) Counts the num ber of rea d accesses to the barr ier- assist ASI r egisters.
212 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002.
F .APPENDIX 213 R UP A Pr ogrammer ’ s Model This chapter describes the prog rammers model of the UP A interface of t he SP ARC64 V. The r egisters fo r the UP A interf ace and th e access me thod for those registers are described.
214 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 R.2 UP A PortID Register The UP A PortID Reg ister i s a standard read-only register th at accessi ble by a sl ave read from another UP A port. This registe r i s located at word address 00 16 in the slave physical addr ess of the UP A port.
Release 1. 0, 1 J uly 2002 F . Chapter R UP A Progr ammer ’ s Model 215 R.3 UP A Config Register The UP A Config Regist er is an implement ation-spe cific ASI r ead-only regi ster . This r egist er is access ible in the A SI 4A 16 space from the ho st processor and c annot be accessed for a UP A slav e read.
216 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 58:57 WRI_S Specify the size of maximum outstanding WRI packet as fo llows . 00 2 :1 01 2 :2 10 2 :4 11 2 :8 56:55 INT_S Specify the size of maximum outstanding INT packet as fo llows .
Release 1. 0, 1 J uly 2002 F . Chapter R UP A Progr ammer ’ s Model 217 29:23 PCON Pro cessor Configurati on. Separated i nto PCON <6:4> an d PCON <3:0>. PCON <6:4> ( UPA_CONFI G <29:27>) rep resent s the size of class 1 r equest queue in the System Contr oller (SC).
218 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002.
F .APPENDIX 219 S Summary of Dif fer ences between SP ARC64 V and UltraSP ARC-III The f oll owing tabl e sum mar izes differenc es b etwee n SP ARC 64 V and Ultr aSP ARC-I II ISAs .
220 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 Floating- poi n t subnormal handling I n ge ne r al , S P A R C 6 4 V d o e s n o t handle most subnormal operands an d re sul ts in h ard w are . H ow eve r , its han dling differs from t hat of Ultr aSP ARC-III.
Release 1. 0, 1 J uly 2002 F . Chapter S Summar y of Diff erences between SP ARC64 V and UltraSP ARC-III 22 1 Err or status ASI 4C 16 /08 16 ( ASI _UGESR ): S P AR C6 4 V i mp l e m e n t s a n e r r o r status regi ster to in dicate wher e an err o r was dete cted.
222 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002.
223 F .CHAPTER Bibliography Genera l Refer ences Pleas e refer to Bibliography in Commonality ..
224 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002.
225 F .CHAPTER Index A A_UGE categories152 err o r dete ction action15 5 err or det ection mask154 specific at ion of15 1 addr ess mask (AM) field of PST A TE r egister49 , 53 addr ess space id entifi.
226 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 ASI_ C_B STW01 23 ASI_ C_B STW11 23 ASI_C_LBSTWBUS Y123 ASI_C_LBSYR0 122 ASI_C_LBSYR1 122 ASI_DCU_CONTR.
Release 1. 0, 1 J uly 2002 F . Chapter Inde x 227 ASI_INTR_ W133 , 13 4 ASI_ ITLB_D A T A_ACCES S196 ASI_ITLB_T A G_ACCESS1 96 ASI_L2_CTRL1 30 ASI_L2_ DIAG_T AG 131 ASI_L2_DIAG_ T AG_READ_RE G131 ASI_.
228 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 compare and swa p37 B barrie r assist121 ASI r ead/write accesses, counti ng211 parallel18 7 , 188 bloc.
Release 1. 0, 1 J uly 2002 F . Chapter Inde x 229 level-2 char acterist ics125 contro l reg iste r130 tag r ead130 unified12 7 use2 snooping1 40 synchr onizing42 unified char acterist ics127 desc rip .
230 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 err or det ection mask154 reporting 151 data cacheable doub lewo rd err or ma rki ng 158 error marking1.
Release 1. 0, 1 J uly 2002 F . Chapter Inde x 231 dispatc h (instru ction)9 disr up ti ng traps17 , 37 distrib ution nonsp eculat ive10 speculati ve11 DMMU access bypas sing 104 disabled91 internal r .
232 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 ECC_error exception46 , 153 , 155 , 180 ee_ops r 164 ee_sec ond_w atch_d og_timeou t 164 ee_sir_ in_max.
Release 1. 0, 1 J uly 2002 F . Chapter Inde x 233 privi leged_a ction 79 statis tic s mo nit ori ng206 – 207 unfinish ed_FP op 62 , 65 execute_state140 executed, defi nition9 execution EU (exec utio.
234 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 FMADD s instr uction50 FMSUB ins tr u cti o n3 0 , 45 FMSUBd instr uction50 FMSUBs instr uction50 FNMAD.
Release 1. 0, 1 J uly 2002 F . Chapter Inde x 235 IMMU internal r egister (ASI_MCNTL)92 re gisters ac cessed92 Sync hron ous F ault Sta tus R eg ist e r97 IMMU_DEMAP r egis ter 186 IMMU_SFSR r egis te.
236 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 imp lem ent ati on -de pen den t ( I MPD EP2 )3 0 imp lem ent ati on -de pen den t ( I MPD EP n )49 , 5.
Release 1. 0, 1 J uly 2002 F . Chapter Inde x 237 JMPL instruct ion29 , 53 JPS1_TSB P mode93 JT AG command91 , 16 4 , 189 L LBSY cont r ol reg ist er1 22 LDD ins truction37 LDDA instr uc tio n3 7 , 54.
238 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 stor e or der (STO)75 TSO41 , 42 MEMOR Y_CONTROL re gister186 mmask field56 MMU disabled91 event counti.
Release 1. 0, 1 J uly 2002 F . Chapter Inde x 239 partial or dering, spec ification56 partial st ore i nstruction UP A transact ion5 7 watchpoin t exc ept ions5 7 partial st ore i nstructions1 20 part.
240 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 PRIMAR Y_CONTEXT register186 privilege d reg isters19 privi leged_a ction exception20 , 79 , 90 , 103 ,.
Release 1. 0, 1 J uly 2002 F . Chapter Inde x 241 clock-tick (TICK)73 curr ent window pointe r (CWP) 75 Data Cache Unit Control (DCUCR)23 LBSY cont r ol122 other w indows (OTHER WIN)75 privilege d19 r.
242 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 scan definition 11 ring 11 sDTLB77 , 85 , 90 SECONDAR Y_CONTEXT register186 SERIA L_ID r egister186 SET.
Release 1. 0, 1 J uly 2002 F . Chapter Inde x 243 T T ag Access Regi ster96 T cc ins truc tion, coun ting2 07 TICK r egister19 , 73 TICK _CO MP ARE r e gis ter 183 TL r egister138 , 140 TLB CP field1 .
244 SP ARC JPS1 Implem entati on Su p ple ment: Fujitsu SPARC64 V • Release 1. 0, 1 Ju ly 2002 way r eduction194 uDTLB10 , 85 , 90 UE_R A W_D 1$ INSD error19 1 UE_RA W_L2$FILL erro r192 uITLB10 , 85.
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