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MCF5221 1 ColdFire ® Integrated Microcontroller Reference Manual Devices Supported: MCF52210 MCF52211 MCF52212 MCF52213 Document Number : MCF52211RM Re v .
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MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor i Chapter 1 Overview 1.1 MCF5221 1 Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor ii 2.14 Pulse-W idth Modulator Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 1 2.15 Debug Support Signals .
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor iii 5.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 Memory Map/Register Description .
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor iv Chapter 8 Power Management 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor v 10.6.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Chapter 11 Real-Time Clock 1 1.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor vi 13.4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor vii 15.5 OTG and Host Mode Oper ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-33 15.6 Host Mode Operation Examples .
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor viii 18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.2 External Signal Description .
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor ix 21.4 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.5 Signal Description .
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor x 22.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2.1 DMA T i mer Mode Registers (DTMR n ) .
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor xi 24.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.2 External Signal Description .
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor xii 25.3.7 Clock Synchronization and Ar bitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.3.8 Handshaking and Clock S tretching .
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor xiii Chapter 27 Pulse-Width Modula tion (PWM) Module 27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor xiv 28.6.2 Concurrent BDM and Processor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-41 28.7 Processor Status, Debug Data De finition .
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-1 Chapter 1 Overview This chapter provides an overview of the major features and functional components of the MCF5221 1 family of microcontrollers.
Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-2 F re escale Semiconductor 1.1 MCF52211 F amily Configurations T able 1-1.
Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-3 1.2 Bloc k Diagram The superset device in the MCF 5221 1 family comes in a 100-lead l eaded quad flat package (LQFP). Figure 1-1 shows a top-level block diagram of the MCF5221 1.
Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-4 F re escale Semiconductor 1.2 Features The MCF5221 1 family includes the following features: • V ersion 2 ColdF.
Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-5 — Up to 16-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access.
Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-6 F re escale Semiconductor — 12-bit resolution — Minimum 1.125 μ s conversion time — Simultaneous sampling .
Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-7 — Maintains system time-of-day clock — Provides stopwatch and alarm interrupt funct.
Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-8 F re escale Semiconductor – Power -on reset (POR) – External – Software – W atchdog – Loss of clock / l.
Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-9 real-time tracing capability is provided on 100-lead packages. This allo ws the processor and system to be debugged at full speed without the need for costly in-circuit emulators.
Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-10 F re escale Semiconductor 1.2.4 On-Chip Memories 1.2.4.1 SRAM The dual-ported SRAM module provides a general-pur pose 8- or 16-Kbyte me mory block that the ColdFire core can access in a single cycle.
Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-11 1.2.7 U ARTs The MCF5221 1 has three full-duplex UAR T s that function independently . Th e three UAR T s can be clocked by the system bus clock, eliminating the need for an external clock source.
Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-12 F re escale Semiconductor register (TCR n ). Each of these timers can be configured for input capture or reference (output) compare mode. T i mer events may optionally cause interrupt requests or DMA transfers.
Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 1-13 1.2.17 Bac kup W atchdog Timer The backup watchdog timer is an independent 16-b it timer that, like the so ftware watchdog timer , facilitates recovery from runaway code.
Overview MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 1-14 F re escale Semiconductor 1.2.22 GPIO Nearly all pins on the MCF5221 1 have general purpo se I/O capability and are grouped into 8-bit ports. Some ports do not use all eight bits.
Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 2-1 Chapter 2 Signal Descriptions 2.
Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-2 F re escale Semiconductor Figure 2-1. Bloc k Diagram wit h Signal Interfaces 2.
Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semiconductor 2-3 T able 2-1. Pin Functions b y Primary and Alternate Purpose Pin Group Primary.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-4 F reescale Semiconductor Signal Descriptions Interrupts IRQ7 — — G P I O L o w F A S T — 9 5C 45 8 IRQ6 — — GPIO.
Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semiconductor 2-5 QSPI QSPI_DIN/ EZPD — URXD1 GPIO PDSR[2] PSRR[2] — 16 F 3 12 QSPI_DOUT /E.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-6 F reescale Semiconductor Signal Descriptions U ART 1 UCTS1 SYNCA URXD2 GPIO PD SR[15] PSRR[15] — 98 C3 61 URTS1 SYNCB UT.
Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semiconductor 2-7.
Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-8 F re escale Semiconductor 2.4 Reset Signals Ta b l e 2 - 2 describes signals that are used to re set the chip or as a reset indication.
Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 2-9 2.7 External Interrupt Signals Ta b l e 2 - 6 describes the external interrupt signals. 2.8 Queued Serial P eripheral Interface (QSPI) Ta b l e 2 - 7 describes the QSPI signals.
Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-10 F re escale Semiconductor 2.9 I 2 C I/O Signals Ta b l e 2 - 8 describes the I 2 C serial interface module signals. 2.10 U AR T Module Signals Ta b l e 2 - 9 describes the UAR T module signals.
Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 2-11 2.12 ADC Signals T able 2-11 describes the signals of the analog-to-digital converter . 2.13 General Purpose Timer Signals T able 2-12 describes the genera l purpose timer signals.
Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-12 F re escale Semiconductor T est Data Inp ut TDI Serial input f or test inst r uctions and data. TDI is samp led on the rising edge of TC LK. I T est Data Output TDO Ser ial output for test inst r uctions and data.
Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 2-13 2.16 EzP or t Signal Descriptions Table 2-15 contains a list of EzPort external signals 2.17 P ower and Gr ound Pins The pins described in T able 2-16 provide system power a nd ground to the chip.
Signal Descriptions MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 2-14 F re escale Semiconductor.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-1 Chapter 3 ColdFire Core 3.1 Intr oduction This section describes the organiza tion of the V ersion 2 (V2) ColdFire ® processor core and an overview of the program-visible registers.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-2 F re escale Semiconductor instruction, fetches the required operands and then executes the required function.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-3 The supervisor-programming model is intended to be used only by syst em control software to implement restricted operating system functi ons, I/O control, and memory management.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-4 F re escale Semiconductor 3.2.1 Data Registers (D0–D7) D0–D7 data registers ar e for bit (1-bit), byte (8-bit ), word (16-bit) and longwor d (32-bit) operations; they can also be used as index registers.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-5 hardware uses one 32-bit register as the active A7 and the other as OTHER_A7.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-6 F re escale Semiconductor 3.2.5 Pr ogram Counter (PC) The PC contains the currently exec uting instruction address.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-7 not implemented by ColdFire processo rs. They are assumed to be zero, forcing the table to be aligned on a 1 MByte boundary . Figure 3-7.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-8 F re escale Semiconductor 3.3 Functional Description 3.3.1 V ersion 2 ColdFire Micr oarchitecture From the block diagram in Figure 3-1 , the non-Harvard architecture of th e processor is readily apparent.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-9 Figure 3-10. V ersio n 2 ColdFire Proc essor Operand Execut ion Pipeline Diagram The instruction fetch pipeline prefet ches instructions from local memory using a two-stage structure.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-10 F re escale Semiconductor For simple register-to-register inst ructions , the first stage of the OEP perfor.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-11 Figure 3-12. V2 OEP Embed ded-Load P ar t 1 Figure 3-13.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-12 F re escale Semiconductor For read-modify-write instructions, the pipeline ef fectively combines an em bedded-load with a store operation for a three-cycle execution time.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-13 Figure 3-15. V2 OEP Pipe line Execution T emplates 3.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-14 F re escale Semiconductor Ta b l e 3 - 4 summarizes the instructions a dded to revision ISA_A to form revision ISA_A+. For more details see the ColdFir e Family Programmer ’ s Refer ence Manual .
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-15 fixed-length stack frame for all exceptions.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-16 F re escale Semiconductor All ColdFire processors inhibit interrupt sampling dur ing the first instruction of all exception handlers.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-17 • The 8-bit vector number , vector[7 :0], defines the exception type a nd is calculated by the processor for all internal faults and represents the value supplied by the interrupt controller in case of an interrupt.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-18 F re escale Semiconductor execution until all previous operations, including all pending write operations, are complete. If any previous write terminates with an access error , it is guaranteed to be reported on the NOP instruction.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-19 In the original M68000 ISA definition, lines A and F were effe ctively reserved for user -defined operations (line A) and co-processor instructions (line F).
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-20 F re escale Semiconductor 3. The processor then generates a trace exception. The PC in the exce ptio n stack frame points to the instruction after the stop, and the SR reflects the value loaded in the previous step.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-21 3.3.4.11 TRAP Instruction Exception The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing system calls.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-22 F re escale Semiconductor ColdFire processors load hardware configurati on information into the D0 and D1 general-purpose registers after system reset. The hardware configuration information is loaded immediately after the reset-in signal is negated.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-23 Information loaded into D1 defines the local memory hardware configuration as shown in the figure below . 11 MMU MMU present. This bit signals if the optional vir tual memo r y management uni t (MMU) is present in processor core.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-24 F re escale Semiconductor T able 3-10. D1 Hard ware Configuration Informat ion Field Description Field Description 31–30 CLSZ Cache line size. This field is fix e d to a he x value of 0x0 indicating a 16-byte cache line size .
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-25 3.3.5 Instruction Execution Timing This section presents p roce ssor in struction execution times in terms of processor -core clock cycles.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-26 F re escale Semiconductor 3.3.5.2 MO VE Instruction Execution Times T able 3-12 lists execution times for MOVE.{B,W} instructions; T able 3-13 lists timings for MOVE.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-27 3.3.5.3 Standard One Operand Instruction Execution Times (d8,A y ,Xi*SF) 3(1/0) 3 (1/1) 3(1/1) 3(1/1) — — — xxx.w 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — — xxx.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-28 F re escale Semiconductor 3.3.5.4 Standard T wo Operand Instruction Execution Times T able 3-15. T wo Opera nd Instruction Execution Times Opcode <EA> Effective Address Rn (An) (An)+ -(An) (d16,An) (d16,PC) (d8,An,Xn*SF) (d8,PC,Xn*SF) xxx.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-29 3.3.5.5 Miscellaneous Instruction Execution Times REMS.L <ea>,Dx ≤ 35(0/0) ≤ 38(1/0) ≤ 38(1/0) ≤ 38(1/0) ≤ 38( 1/0) — — — REMU .
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-30 F re escale Semiconductor 3.3.5.6 MA C Instruction Execution Times W D E B U G < e a > —5 ( 2 / 0 )— —5 ( 2 / 0 ) — — — 1 The n is the number of registers mov ed b y the MO VEM opcode.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 3-31 3.3.5.7 Branch Instruction Execution Times Table 3-18. General Branch Instruction Execu tion Times Opcode <EA> Effecti ve Address Rn (An) (An)+ -(An) (d16,An ) (d16,PC) (d8,An,Xi*SF) (d8,PC,Xi*SF) xxx.
ColdFire Core MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 3-32 F re escale Semiconductor.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-1 Chapter 4 Multipl y-Accumu late Unit (MA C) 4.1 Intr oduction This chapter describes the functiona lity , microarchitecture, and performance of th e multiply-a ccumulate (MAC) unit in the ColdFire family of processors.
Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-2 F re escale Semiconductor cycles than comparable non-MAC architectures.
Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-3 BDM: 0x804 (MA CSR) Access: Supervisor read/wr ite BDM read/writ.
Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-4 F re escale Semiconductor Ta b l e 4 - 3 summarizes the interaction of th e MACSR[S/U,F/I,R/T] control bits.
Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-5 if extension word, bit [5] = 1, the MASK bit, then if <ea>.
Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-6 F re escale Semiconductor 4.3 Functional Description The MAC speeds execution of ColdFire integer -mu ltiply instructions (MULS and MULU) and provides additional functionality for multiply-a ccumulate ope rations.
Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-7 4.3.1 Fractional Operation Mode This section describes behavior when the fr actional mode is used (MACSR[F/I] is set).
Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-8 F re escale Semiconductor int macsr; } macState; The following assembly language r outine shows the proper sequence for a correct MAC state save.
Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-9 4.3.3 MA C Instruction Execution Times The instruction execution time s for the MAC can be found in Section 3.3.5.6, “MAC Instruction Execution Ti m e s ” .
Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-10 F re escale Semiconductor treated as a sticky flag, mea ning after set, it remains set until the accumu lator or the MACSR is directly loaded.
Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-11 else result[31:0] = 0x7fff_ffff } /* scale product before combi.
Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-12 F re escale Semiconductor break; case 1: case 3: /* signed fractionals */ if (MACSR.
Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 4-13 if (MACSR.OMC == 0 || MACSR.
Multiply-Accumulate Unit (MA C) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 4-14 F re escale Semiconductor then {if (inst == MSAC) then result[31:0] = acc[31:0] - product[3 1:0] else result[31:0] = acc[31:0] + product[3 1:0] } /* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 5-1 Chapter 5 Static RAM (SRAM) 5.1 Intr oduction This chapter describes the on-chip static RAM (SRAM) implementation, including general operations, configuration, and initializ ation.
Static RAM (SRAM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 5-2 F re escale Semiconductor 5.2.1 SRAM Base Address Regi ster (RAMB AR) The configuration information in the SRAM base-addr ess register (RAMBAR) c ontrols the operation of the SRAM module.
Static RAM (SRAM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 5-3 5.3 Initialization/Application Inf ormation After a hardware reset, the SRAM module contents are undefined. The valid bit of the RAMBAR is cleared, disabling the proces sor port into the memory .
Static RAM (SRAM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 5-4 F re escale Semiconductor 2. Read the source data and write it to the SR AM. V arious instructions support this function, including memory-to-memory move instru ctions, or the MOVEM opcode.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-1 Chapter 6 Cloc k Module 6.1 Intr oduction The clock module allows the device to be configured for one of several clocking methods.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-2 F re escale Semiconductor next POR. If the relaxation oscillator was already selected as the system clock’ s source and is subsequently selected as the timer ’ s input source, the system and the timer can use the oscillator as the source.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-3 In stop mode, all system cl ocks are disabled. There are several opt ions for enabling or disabling the PLL or crystal oscillator in stop mode, compromising be tween stop mode current and wakeup recovery time.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-4 F re escale Semiconductor Figure 6-1. Cloc k Module Bloc k Diagram EXTAL CLKMOD1 CLKSRC PLL Low Power Divider.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-5 6.6 Signal Descriptions The clock module signals are summarized in Ta b l e 6 - 2 and a brief description follows. For more detailed information, refer to Chapter 2, “Signal Description s.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-6 F re escale Semiconductor 6.6.5 RST O The RSTO pin is asserted by one of the following: • Internal system reset signal • FRCRSTOUT bit in the reset cont rol statu s register (RCR); see Section 10.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-7 6.7.1.1 Synthesiz er Contr ol Register (SYNCR) IPSBAR Offset: 0x12_0000 (SYNC R) Ac.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-8 F re escale Semiconductor 14–12 MFD Multiplication F actor Divider . Contain the bina ry value of the divider in the PLL feedback loop . The MFD[2:0] value is the multiplication f actor appl ied to the re ference frequency .
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-9 6.7.1.2 Synthesiz er Status Register (SYNSR) The SYNSR is a read-only register th at can be read at any time. W rit ing to the SYNSR has no ef fect and terminates the cycle normally .
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-10 F re escale Semiconductor T able 6-6. SYNSR Field Descriptions Field Description 7 EXT OSC Indicates if an e.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-11 6.7.1.3 Relaxation Oscillator Control Register (ROCR) The ROCR is used to trim the frequency of the on-chip oscillator .
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-12 F re escale Semiconductor 6.7.1.5 Clock Contr ol High Register (CCHR) The CCHR sets the pre-division fact or , which divides down the PLL input clock by 1 (CCH R[2:0] = 000) to 8 (CCHR[2:0] =1 1 1 ).
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-13 6.7.1.7 Oscillator C ontr ol High Register (OCHR) The OCHR is used to enable and configure the relaxation oscillator .
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-14 F re escale Semiconductor 6.7.1.8 Oscillator C ontr ol Low Register (OCLR) The OCLR is used to enable and configure the external oscillator .
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-15 6.7.1.9 Real-Time C loc k Control Register (R TCCR) The R TCCR is used to conf igure the R TC oscillator . T able 6-13. OCLR Field Descriptions Field Description 7 OSCEN Externa l Oscillator Enable bit.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-16 F re escale Semiconductor 6.7.1.10 Backup W atchdog Time r Contr ol Register (BWCR) The BWCR is used to configure the interaction between the clock module and the Backup W atchdog T i mer module (see Chapter 7, “Backup W atchdog T imer (BWT) Module ”).
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-17 6.8 Functional Description This section provides a functional description of the clock module. 6.8.1 System Cloc k Modes The system clock source and P LL mode (enabled/disabled) are determined during reset (see T able 10-5 ).
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-18 F re escale Semiconductor In PLL mode, the PLL operates in self-clocked mode (SCM) during reset until the input reference clock to the PLL begins operating within the limits given in the elec trical specifications.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-19 Figure 6-12. Crystal Oscillator Example 6.8.4.1 Phase and Freq uency Detector (PFD) The PFD is a dual-latch ph ase-frequency detector .
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-20 F re escale Semiconductor 6.8.4.3 V oltage Control Output (VCO) The voltage across the loop filter co ntrols the frequency of the VCO output.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-21 Figure 6-13. Loc k Detect Sequence 6.8.4.6 PLL Loss of Lock Conditions After the PLL acquires lock after rese t, the LOCK and LOCKS flags are se t.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-22 F re escale Semiconductor 6.8.4.8 Loss of Clock Detection The LOCEN bit in the SYNCR enables the loss of clock detection circuit to moni tor the input clocks to the phase and frequency detector ( PFD).
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-23 6.8.4.11 Loss of Clock in Stop Mode T able 6-19 shows the resulting actions for a loss of clock in stop mode wh en the device is being clocked by the various clocking methods.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-24 F re escale Semiconductor NRM 0 0 0 Off On 1 Lose lock No lock regain Unstab le NRM 0–>‘LK 0–>1 ‘LC Block LOCKS until lock regained Lose reference clock or no f .
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-25 NRM 1 0 0 Off On 0 Lose lock, f .
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-26 F re escale Semiconductor NRM 1 1 0 On On 0 — — NRM ‘LK 1 ‘LC Lose clock RESET — — — Reset imm.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 6-27 SCM 1 0 0 On On 1 — — SCM 0 0 1 Lose reference clock SCM Note: PLL = PLL enabled dur ing ST OP mode. PLL = On when STPMD[1:0] = 00 or 01 OSC = oscillator enabled during STOP mode.
Clock Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 6-28 F re escale Semiconductor.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 7-1 Chapter 7 Bac kup W atchdog Timer (BWT) Module 7.1 Intr oduction The Backup W atchdog T imer (BWT) module is used to he lp software recover from runaway code.
Backup W atchdog Timer (BWT ) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 7-2 F re escale Semiconductor 7.1.2.1 W ait Mode The functionality of the BWT in W ait mode depends on the value of WCR[W AIT]. When WCR[W AIT]=1, the BWT stops wh en the device enters W ait mode .
Backup W atchdog Timer (BWT) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 7-3 7.2.2 Register Descriptions 7.2.2.1 Backup W atchdog Time r Control Register (WCR) The WCR, shown in Figure 7-2 , configures the operation of the BWT .
Backup W atchdog Timer (BWT ) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 7-4 F re escale Semiconductor 7.2.2.2 Backup W atchdog Timer Modulus Register (WMR) The WMR, shown in Figure 7-3 , contains the value (modulus) that is loaded into the BWT count register (WCNTR) when the BWT is serviced.
Backup W atchdog Timer (BWT) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 7-5 7.2.2.4 Backup W atchdog Time r Service Register (WSR) The WSR is shown in Figure 7-5 , and is used to instruct the BWT to reset its internal counter to the value in WMR[WM].
Backup W atchdog Timer (BWT ) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 7-6 F re escale Semiconductor 7.3 Functional Description When the BWT is properly enabled, it loads the value in WMR[WM] into WCNTR[WC] and begins to decrement WCNTR[WC].
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-1 Chapter 8 P o wer Management 8.1 Intr oduction This chapter explains the low- power operation of the MCF5221 1. 8.1.1 Features The following features support low-power operation.
P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-2 F re escale Semiconductor 8.2.1 P eripheral P ower Mana g ement Register s (PPMRH, PPMRL) The PPMRH and .
Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-3 T able 8-2. PPMRH Field Descriptions Field Description 31–12 Res erved, should be cl eared.
P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-4 F re escale Semiconductor 8.2.1.1 Peripheral P ower Management Register Low (PPMRL) IPSBAR Offset: 0x001.
Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-5 8.2.2 Low-P ower Interrupt Contr ol R egister (LPICR) Implementatio.
P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-6 F re escale Semiconductor The following is the sequence of operations needed to enable this functionality: 1.
Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-7 8.2.3 P eripheral P ower Mana gement Set Register (PPMRS) The PPMRS.
P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-8 F re escale Semiconductor 8.2.4 P eripheral P ower Mana ge ment Clear Register (PPMRC) The PPMRC registe.
Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-9 8.3 IPS Bus Timeout Monitor The IPS controller implements a bus timeout monito r to ensure that every IPS bus cycle is properly terminated within a programmed period of time.
P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-10 F re escale Semiconductor the cycle with an error termination. At reset, the I PSBMT is enabled with a maximum timeout value. See Figure 8-7 and Ta b l e 8 - 9 for the IPSBMT definition.
Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-11 A wakeup event is required to exit a low-power mode and return to run mode.
P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-12 F re escale Semiconductor further details). A peripheral may be disabled at any time and rema ins disabled during any low-power mode of operation. 8.4.2 P eripheral Behavior in Lo w-P ower Modes 8.
Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-13 8.4.2.6 I 2 C Module When the I 2 C Module is enabled by the setti.
P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-14 F re escale Semiconductor 8.4.2.10 I/O P or ts The I/O ports are unaf f ected by entr y into a low-power mode. These pi ns may impact low-power current draw if they are configured as out puts and are sourcing current to an ex ternal load.
Po w e r M a n a g e m e n t MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 8-15 8.4.2.15 Programmab le Interrupt Timers (PIT0–PIT1) In stop mode (or in doze mode, if so programmed), the programmabl e interrupt timer (PIT) ce ases operation, and freezes at the current value.
P ower Management MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 8-16 F re escale Semiconductor I 2 C Module Enabled Y es 2 Enabled Y es 2 Stopped N o QSPI Enabled Y es 2 En.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 9-1 Chapter 9 Chip Configuration Module (CCM) 9.1 Intr oduction This chapter describes the various ope rating configurations of the device. It also pr ovides a description of signals used by the CCM and a programming model.
Chip Configuration Module (CCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 9-2 F re escale Semiconductor 9.2.1 RCON The serial flash programming mode is entered by asserting the RCON pin (with the TEST pin negated) as the chip comes out of reset.
Chip Configuration Modu le (CCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 9-3 9.3.2 Memory Map 9.3.3 Register Descriptions The following section describes the CCM registers. 9.3.3.1 Chip Configuration Register (CCR) T able 9-3.
Chip Configuration Module (CCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 9-4 F re escale Semiconductor 9.3.3.2 Reset C onfiguration Register (RCON) At reset, RCON determines the defa ult operation of certain chip functi ons.
Chip Configuration Modu le (CCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 9-5 T able 9-6. CIR Field Description Field Description 15–6 PIN P ar t identification number . Contain s a uni que identification number f or the device .
Chip Configuration Module (CCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 9-6 F re escale Semiconductor.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 10-1 Chapter 10 Reset Contr oller Module 10.1 Intr oduction The reset controller is provided to de termine the cause of reset, ass ert the appropriate reset signals to the system, and keep a history of what caused the reset.
Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 10-2 F re escale Semiconductor Figure 10-1. Reset Contr oller Bloc k Diagram 10.4 Signals T able 10-1 provides a summary of the reset controller signal properties.
Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 10-3 See T able 10-2 for the memory map and the following para graphs for a description of the registers.
Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 10-4 F re escale Semiconductor 10.5.2 Reset Status Register (RSR) The RSR contains a status bit for ev ery reset source.
Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 10-5 10.6 Functional Description 10.6.1 Reset Sources T able 10-5 defines the sources of reset and the signals driven by the reset controller .
Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 10-6 F re escale Semiconductor Internal byte, word, or longword writes are guarant eed to complete without data corruption when a synchronous reset occurs.
Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 10-7 10.6.2 Reset Contr ol Flow The reset logic contro l flow is shown in Figure 10-4 .
Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 10-8 F re escale Semiconductor Figure 10-4. Re set Control Flow RSTI PIN OR WD TIMEOUT OR SW RESE T? L.
Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 10-9 10.6.2.1 Synchr onous Reset Requests In this discussion, the refe rences in parentheses refer to the state numbers in Figure 10-4 .
Reset Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 10-10 F reescale Semiconductor If a loss-of-clock or loss-of-loc k condition is detected during the 512 cycle wait, the reset sequence continues after a PLL lock (9, 9A).
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-1 Chapter 11 Real-Time Cloc k 11.1 Intr oduction This section discusses how to operate and progra.
Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-2 F re escale Semiconductor 11.1.3 Modes of Operation The incoming 1 Hz signal is used to increment the seconds, minutes, hours, and days TOD counters.
Memory Map/Register Definition MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-3 11.2.1.1 R TC Hours and Minutes Counter Register (HOURMIN) The real-time clock hours a nd minutes counter regist er (HOURMIN) is used to program the hours and minutes for the TO D clock.
Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-4 F re escale Semiconductor 11.2.1.2 R TC Seconds Counter Register (SECONDS) The real-time clock seconds regist er (SECONDS) is used to program the seconds for the T OD clock.
Memory Map/Register Definition MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-5 11.2.1.3 R TC Hours and Minutes Alarm Register (ALRM_HM) The real-time clock hours a nd minutes alarm (ALRM_HM) register is used to configure the hours and minutes setting for the alarm.
Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-6 F re escale Semiconductor 11.2.1.4 R TC Seconds A larm Register (ALRM_SEC) The real-time clock seconds alarm (ALRM_SEC) register is used to configure th e seconds setting for the alarm.
Memory Map/Register Definition MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-7 11.2.1.5 RTC Contr ol Register (RTCCTL) The real-time clock control (R TCCTL) register is used to enable the real-time clock module and specify the reference frequency info rmation for the prescaler .
Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-8 F re escale Semiconductor 11.2.1.6 R TC Interrup t Status Register (R TCISR) The real-time clock interrupt status register (R TCISR) indicates the status of the various real-time clock interrupts.
Memory Map/Register Definition MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-9 11.2.1.7 RTC Interrupt En able Register (R TCIENR) The real-time clock interrupt enable register (R TCIENR) is used to en able/disable the various real-time clock interrupts.
Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-10 F reescale Semiconductor 11.2.1.8 R TC Stopwatch Minutes Register (STPWCH) The stopwatch minutes (STPWCH) re gister contains the current stopwatch countdown value.
Memory Map/Register Definition MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-11 11.2.1.9 R TC Days Counter Register (D A YS) The real-time clock days c ounter register (DA Y S) is used to progr am the day for the TO D clock.
Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-12 F reescale Semiconductor 11.2.1.10 RTC Da y Alarm Register (A LRM_D A Y) The real-time clock day alar m (ALRM_DA Y) register is used to conf igure the day for the alarm.
Functional Description MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-13 Figure 11-13. R TC General Oscillator Count Lo wer Register (RTCGOCL) 11.3 Functional Description The R TC uses a supplied 1 Hz signal to increment the seconds, minutes , hours, and days T OD counters.
Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-14 F reescale Semiconductor Interrupts signal when each of the four counters incr ements, and can be used to indicate when a counter rolls over . For example, each tick of the seconds counter caus es the 1HZ interrupt flag to be set.
Initialization/Applicatio n Information MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 11-15 Figure 11-14. Flow Cha r t of RT C Operation 11.4.2 Code Example for Initializing the Real-Time Cloc k Figure 1 1-15 shows sample code for initializing the R TC.
Real-Time Clock MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 11-16 F reescale Semiconductor.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-1 Chapter 12 System Contr ol Module (SCM) 12.1 Intr oduction This section details the functionali.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-2 F re escale Semiconductor • System access control unit (SACU) programming model — Master privilege registe r (MPR) — Peripheral access control registers (P ACRs) — Grouped peripheral access contro l registers (GP ACR0, GP ACR1) 12.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-3 12.5 Register Descriptions 12.5.1 Internal P eripheral System Base Address Register (IPSB AR) The IPSBAR specifies the base address for the 1-Gbyte memory space associated with the on-chip peripherals.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-4 F re escale Semiconductor NO TE Accessing reserved IPSBAR memory sp ace could result in an unterminated bus cycle that causes the core to hang. Only a hard reset allows the core to recover from this state.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-5 known as a ping-pong scheme) may load data into one portion of the dual-ported SRAM while the processor is manipulating data in another portion of the SRAM.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-6 F re escale Semiconductor • The back door enable bit, RAMBAR [BDE], is cleared at reset, di sabling the module access to the SRAM. NO TE The RAMBAR default value of 0x0000_0000 is invalid.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-7 12.5.4 Core W atchdog Contr ol Register (CWCR) The core watchdog timer prevents system lockup if the software becomes trapped in a loop with no controlled exit.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-8 F re escale Semiconductor 12.5.5 Core W atchdog Service Register (CWSR) The software watchdog service sequence must be performed using the CWSR as a data register to prevent a CWT time-out.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-9 12.6 Internal Bus Arbitration The internal bus arbitration is perf .
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-10 F reescale Semiconductor • There are two arbitration algorith ms: fixed and round-robin. Fixed ar bitration sets the next-state arbitration pointer to the highest priority requester .
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-11 • Master 2 (M2): 4-channel DMA • Master 0 (M0): V2 ColdFire Co.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-12 F reescale Semiconductor The initial state of the master priorities is M2 > M0. System software should guarantee that the programmed M n _PR TY fields are unique, otherwise the hardware defaults to the initial-state priorities.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-13 • User operand write Instruction fetch accesses are associ ated with the execute attribute.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-14 F reescale Semiconductor 12.7.3.1 Master Privile ge R egi ster (MPR ) The MPR specifies the access privilege level associated with each bus master in the platform.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-15 IPSBAR Offset: 0x0024 + Offset (P ACR n ) Access: read/write 76543210 R LOCK1 A CCESS_CTRL1 LOCK0 ACCESS_CTRL0 W R e s e t : 00000000 Figure 12-9.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-16 F reescale Semiconductor At reset, these on-chip modules are configured to have only supervisor read/write access capabilities.
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 12-17 At reset, these on-chip modules are configured to have only supervisor read/write access capabilities. Bit encodings for the ACCESS_CTRL fi eld in the GP ACR are shown in T able 12-14 .
System Control Module (SCM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 12-18 F reescale Semiconductor T able 12-15. GP A CR Address Space Regist er Space Protected (IPSB.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-1 Chapter 13 General Purpose I/O Module 13.1 Intr oduction Many of the pins associated with the external interface may be us ed for several diff erent functions.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-2 F re escale Semiconductor 13.2 Overview The MCF5221 1 ports module controls the confi guration.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-3 T able 13-1. Register s in the MCF52211 P orts Address Space Address 1 1 The register address is the sum of the IPSBAR address and the value in this column.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-4 F re escale Semiconductor 13.6 Register Descriptions 13.6.1 P or t Output Data Registers (POR T n ) The PORT n registers store the data to be driven on the corresponding port n pins when the pins are configured for digital output.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-5 13.6.2 P or t Data Direction Reg ister s (DDR n) The DDR n registers control the direction of the port n pin drivers when the pins are configured for digital I/O.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-6 F re escale Semiconductor Setting any bit in a DDR n register configures the corresponding port n pin as an output. Clearing any bit in a DDR n register configures the corresponding pin as an input.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-7 13.6.3 P or t Pin Data/Set Data Register s (PORT n P/SET n ) The PORT n P/SET n registers reflect the current pin states and control the sett ing of output pins when the pin is configured for digital I/O.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-8 F re escale Semiconductor IPSBAR Offsets: 0x10_003E (PORTT AP/SETT A) 0x10_003F (PORTTCP/SETTC.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-9 13.6.4 P or t Clear Output Data Registers (CLR n ) Writing 0s to a CLR n register clears the corr esponding bits in the PORT n register.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-10 F reescale Semiconductor 13.6.5 Pin Assignment Register s All pin assignment registers are read/write. Refer to Table 2-1 for the different functi ons assignable to each pin.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-11 13.6.5.1 Dual-Function Pi n Assignment Registers The dual function pin assignment regist ers allow each pin controlled by each register bit to be configured for the primary function or the GPIO fu nction.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-12 F reescale Semiconductor IPSBAR Offset: 0x10_006C (PQSP AR) Access: User read/write 15 14 13 .
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-13 13.6.5.3 P or t NQ Pin Assign ment Register (PNQP AR) The port NQ pin assignment register (PNQPAR) contains quad-function (for IRQ1 ) and dual-function pin assignment controls.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-14 F reescale Semiconductor IPSBAR Offset: 0x10_0078 (PSRR ) Access: User read/write 31 30 29 28.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 13-15 13.6.6.2 Pin Drive Strength Register (PDSR ) The pin drive strength register is read/write. Each bit resets to logic 0 in single chip mode (MCF52211 default) and logic 1 in EzPort and FA ST mode.
General Purpose I/O Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 13-16 F reescale Semiconductor.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-1 Chapter 14 Interrupt Contr oller Module This section details the functionality for the MCF5221 1 interrupt controller .
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-2 F re escale Semiconductor fetched data provides an index into the exception vector table, which contains 256 addresses, each pointing to the beginning of a specific exception service r outine.
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-3 The level and priority is fully pr ogrammable for all sources except inte rrupt sources 1–7. Interrupt source 1–7 (from the Edge Port module) are fixed at th e corresponding level’ s midpoi nt priority .
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-4 F re escale Semiconductor if interrupt source 8 is active and acknowledged, then Vector n umber = 72 if interrupt source 9 is active and acknowledged, then Vector n umber = 73 .
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-5 14.3 Register Descriptions The interrupt controller registers are described in the following sections.
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-6 F re escale Semiconductor 14.3.1 Interrupt P e nding Regist ers (IPRH n , IPRL n ) The IPRH n.
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-7 14.3.2 Interrupt Mask Register (IMRH n , IMRL n ) The IMRH n and IM.
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-8 F re escale Semiconductor NO TE A spurious interrupt may oc cur if an interrupt source is bei.
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-9 request, 0 = negate request) in the appropriate INTFRC n register . The assertion of an interrupt request via the INTFRC n register is not affected by the interrupt mask register .
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-10 F reescale Semiconductor 14.3.4 Interrupt Request Level Register (IRLR n ) This 7-bit regist.
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-11 14.3.6 Interrupt Contr ol Registers (ICR nx ) Each ICR nx , where x = 1, 2,..., 63, specifies the interrupt level (1–7) and the priority within the level (0–7).
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-12 F reescale Semiconductor IPSBAR Offsets: See T able 14-2 f or register offsets (ICR nx ) Acc.
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-13 14.3.6.1 Interrupt Sources T able 14-13 lists the interrupt sources fo r each interrupt request line.
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-14 F reescale Semiconductor 29 Not used (Reser v ed) 30 Not used (Reser v ed) 31 Not used (Rese.
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-15 14.3.7 Software and Level m IA CK Registers (SWIA CK n , L m IA CK.
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-16 F reescale Semiconductor 14.3.8 Global Level m IA CK Registers (GL m IA CK) In addition to the soft ware IACK registers ( Section 14.
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 14-17 2. The processor executes a ST OP instruction which places it in stop mode.
Interrupt Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 14-18 F reescale Semiconductor.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-1 Chapter 15 Univer sal Serial Bus, O TG Capable Contr oller NO TE Portions of Chapter 15, “Universal Serial Bus, OTG Capable Controller,” relating to the EHCI specification are Copyright © Intel Corporation 1999-2001.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-2 F re escale Semiconductor USB software provides a uniform vi ew of the system for all applica tion software, hiding implementation details making application software more portable.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-3 15.1.2 USB On-The-Go USB (Universal Serial Bus) is a popular standard for connecting peripherals and portable consumer electronic devices such as digital cameras and hand-held comput ers to host PCs.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-4 F re escale Semiconductor 15.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-5 Figure 15-3.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-6 F re escale Semiconductor BDT . The BDT must be located on a 512-byte boundary in system memory . Al l enabled TX and RX endpoint BD entries are indexed into the BDT to al low easy access via the US B-FS or ColdFire Core.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-7 Figure 15-5.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-8 F re escale Semiconductor 15.3.5 USB T ransaction When the USB-FS transmits or receives data, it co mputes the BDT address using the address generation shown in T able 2.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-9 because it is assumed that a second attempt will be que ued and succeed in the future.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-10 F reescale Semiconductor The following sections provide details about the registers in the USB OTG memory map.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-11 15.4.1.2 P eripheral ID Comple ment Register (ID_COMP) The Peripheral ID Complement Register reads back th e complement of the Peripheral ID Register .
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-12 F reescale Semiconductor 15.4.1.3 P eripheral Revision Register (REV) This register contains the re vision number of the USB Module.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-13 15.4.1.5 O TG Interrupt Status Reg ister (O TG_INT_ST A T) The OTG Interrupt S tatus Register records changes of the ID sense a nd VBUS signals.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-14 F reescale Semiconductor 15.4.1.6 O TG Interrupt Cont rol Register (O TG_INT_EN) The OTG Interrupt Control Register enables the corr esponding interrupt status bits defined in the OTG Interrupt Status Register .
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-15 15.4.1.7 Interrupt Status Register (O TG_ST A T) The Interrupt Status Register displa ys the actual value from the external comparator outputs of the ID pin and VBUS.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-16 F reescale Semiconductor 15.4.1.8 O TG C ontr ol Register (O T G_CTRL) The OTG Control Register controls the operation of VBUS and Data Line termination resistors.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-17 15.4.1.9 Interrupt Status Register (INT_ST A T) The Interrupt S tatus Register contai ns bits for each of the interrupt sources within the USB Module.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-18 F reescale Semiconductor 15.4.1.10 Interrupt Enable Register (INT_ENB) The Interrupt Enable Register cont ains enable bits for each of the interrupt sources within the USB Module.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-19 15.4.1.11 Error Interrupt Status Register (ERR_ST A T) The Error Interrupt S tatus Register contains enable bits for each of the error sources within the USB Module.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-20 F reescale Semiconductor 15.4.1.12 Error Interrupt Enab le Register (ERR_ENB) The Error Interrupt Enable Register c ontains enable bits for each of th e error interrupt sources within the USB Module.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-21 15.4.1.13 Status Register (ST A T) The S tatus Register reports the transaction status within the USB Module.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-22 F reescale Semiconductor 15.4.1.14 Control Register (CTL) The Control Register provides va rious control and configuration information for the USB Module.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-23 15.4.1.15 Address Register (ADDR) The Address Register holds the unique USB address that the USB Module decodes when in Peripheral mode (HOST_MODE_EN=0).
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-24 F reescale Semiconductor 15.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-25 15.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-26 F reescale Semiconductor 15.4.1.18 T oken Register (T OKEN) The T oken Register is used to perform USB tran sactions when in host mode (HOST_MODE_EN=1).
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-27 15.4.1.19 SOF Threshold Register (SOF _THLD) The SOF Threshold Register is used only in Hosts mode (HOST_MODE_EN=1).
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-28 F reescale Semiconductor 15.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-29 15.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-30 F reescale Semiconductor 5 Reser ved 4 EP_CTL_DIS This bit, when set, d isab les contro l (SETUP) transf er s. When cleared, control tr ansfers are enab led.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-31 15.4.1.23 USB Control Register (USB_CTRL) IPSBAR Offset: 0x1C_0100 (USB_CTRL) Access: User read/wr ite 76543210 R SUSP PDE ———— CLK_SRC W R e s e t : 01000011 Figure 15-30.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-32 F reescale Semiconductor 15.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-33 15.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-34 F reescale Semiconductor Host mode is intended for use in handheld-portable de vices to allow easy connect ion to simple HID class devices such as printers and keyboards.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-35 T o complete a control transaction to a connected device: 1. Complete all steps discover a connected device 2.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-36 F reescale Semiconductor T o send a Full speed bulk data transfer to a target device: 1. Complete all steps discover a connected device and to configure a conn ected device.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-37 Figure 15-33. Dual Role A Device Flo w Diagram T able 15-38. Stat e Descriptions f or Figure 15-33 State Action Respons e A_IDLE If ID Interrupt.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-38 F reescale Semiconductor 15.7.2 O TG Dual Role B Devi ce Operation A device is considered a B device if it connected to the bus with a USB T ype B cable or a USB T ype Mini B cable.
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 15-39 15.7.3 P ower The USB-FS core is a fully synchronous static design. The power used by the de sign is dependant on the application usage of the core .
Universal Serial Bus, O TG Capable Controller MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 15-40 F reescale Semiconductor 15.7.4 USB Suspend State USB bus powered devices are required to respond to a 3ms lack of activity on th e USB bus by going into a suspend state.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 16-1 Chapter 16 Edge P or t Module (EPORT) 16.1 Intr oduction The edge port module (EPOR T) has se ven external interrupt pins, IRQ7 –IRQ1 .
Edge Port Module (EPORT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 16-2 F re escale Semiconductor 16.2 Low-P o wer Mode Operation This section describes the operati on of the EPOR T module in low-power modes. For more information on low-power modes, see Chapter 8, “Power Management”.
Edge Port Module (EPORT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 16-3 16.4.1 EPOR T Pin Assign ment Register (EPP AR) The EPOR T pin assignment register (EPP AR) controls the function of each pin individually .
Edge Port Module (EPORT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 16-4 F re escale Semiconductor 16.4.2 EPORT Data Dire ction Register (EPDDR) The EPOR T data direction register (EPDDR) controls the direction of each one of the pins individually .
Edge Port Module (EPORT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 16-5 16.4.4 Edge P or t Data Register (EPDR) The EPOR T data register (EPDR) holds the data to be driven to the pins.
Edge Port Module (EPORT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 16-6 F re escale Semiconductor 16.4.6 Edge P or t Flag Register (EPFR) The EPOR T flag register (EPFR) indi vidually latches EPOR T edge events.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-1 Chapter 17 DMA Contr oller Module 17.1 Intr oduction This chapter describes the direct memory access (DMA) controller modul e. It provides an overview of the module and describes in detail its si gnals and registers.
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-2 F re escale Semiconductor Figure 17-1. DMA Signal Dia gram NOTE Throughout this chapter , the terms exte rnal request and DREQ are used to refer to a DMA request from one of the on-chip UAR TS, DMA timers.
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-3 17.2 DMA T ransf er Over vie w The DMA module can data within system memory (including memory and pe ripheral devices) with minimal processor intervention, greatly improvi ng overall system perfo rmance.
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-4 F re escale Semiconductor 17.3.1 DMA Request Contr ol (DMAREQC) The DMAREQC register provides a so ftware-controlled connection matrix for DMA requests.
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-5 17.3.2 Source Address Register s (SAR n ) SAR n , shown in Figure 17-4 , contains the address from which the DMA controller requests data.
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-6 F re escale Semiconductor 17.3.4 Byte Count Registers (BCR n ) and DMA Status Re gisters (DSR n ) T.
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-7 IPSBAR Offsets: See Figure 17-6 (DSR n ) Access: read/write 76543210 R 0 CE BES BED 0 REQ BSY DONE W R e s e t : 00000000 Figure 17-7.
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-8 F re escale Semiconductor 17.3.5 DMA Contr ol Registers (DCR n ) The DMA control registers (DCR n ) are described in Figure 17-8 and T able 17-4 .
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-9 27–25 BWC Bandwidth control. Indicates the n umber of b ytes in a bloc k transf er . When the byte count reaches a multiple of the BWC value , the DMA releases the bus.
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-10 F reescale Semiconductor 15–12 SMOD Source address modulo. Defines the size of the source data circular buf fer used by the DMA Controlle r . If enabled (SMOD is non-zero), the b uffer base address is locate d on a boundary of the buffer size.
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-11 17.4 Functional Description In the following discussion, the te rm DMA request implies that DCR n [ST AR T] or DCR n [EEXT] is set, followed by assertion of an internal or external DMA request.
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-12 F reescale Semiconductor Source and destination address registers (SAR n and DAR n ) can be programmed in the DCR n to increment at the completion of a successful transfer .
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-13 17.4.3 Channel Initialization and Startup Before a block transfer starts, channel registers must be initia lized with information describing configuration, request-generation method, and the data block.
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-14 F reescale Semiconductor As soon as the channel has been initialize d, it is started by wr iting a one to DCR n [ST AR T] or a peripheral DMA request, depending on the status of DCR n [EEXT].
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 17-15 If BWC equals 000, the request si gnal remains asserted until BCR n reaches zero. DMA has priority over the core. In this scheme, the arbiter can al ways force the DMA to relinquish the bus.
DMA Controller Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 17-16 F reescale Semiconductor.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-1 Chapter 18 ColdFire Flash Module (CFM) 18.1 Intr oduction 18.1.1 Overview The ColdFire Flash Module (CFM) is a non-volatile memory (NVM) modul e for integration with a CPU.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-2 F re escale Semiconductor Figure 18-1. CFM Bloc k Diagram 18.
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-3 • Protection scheme to preven t acciden tal program or erase of .
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-4 F re escale Semiconductor 18.3.2 Flash Base Address Register (FLASHB AR) The configuration information in the flash base addr ess register (FLASHBAR) controls the operation of the flash module.
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-5 NO TE Flash accesses (reads/writes) by a bus master other than the.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-6 F re escale Semiconductor The CFM contains a set of control and status registers locat ed at the regi ster base address as defined by the system level configuration.
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-7 18.3.3 Register Descriptions 18.3.3.1 CFMMCR — CFM Module Con figuration Register The CFMMCR register is used to configure and c ontrol the operation of the internal bus interface.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-8 F re escale Semiconductor 18.3.3.2 CFMCLKD — CFM C loc k Divider Register The CFMCLKD register is used to control the period of the clock used for time d events in program and erase algorithms.
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-9 All CFMCLKD register bits are readable, while bi ts [6:0] write once and bit 7 is not writable.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-10 F reescale Semiconductor The CFMSEC register is loaded from the flash c onfiguration field in the flash block at offset 0x0414 during the reset sequence, indicated by F in Figure 18-6 .
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-11 T o change the flash memory protect ion on a temporary basi s, the CFMPROT register should be written after the LOCK bit in the CFMMCR register has been cleared.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-12 F reescale Semiconductor 18.3.3.5 CFMSA CC — CFM Supervisor Access Reg ister The CFMSACC register is used to control supervisor/user access to the flash memory.
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-13 18.3.3.6 CFMD A CC — CFM Data Access Register The CFMDACC register is used to control data/instruction access to the flash memory.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-14 F reescale Semiconductor CFMUST A T register bits CBEIF , PVIOL, ACCERR, an d BLANK are readable a nd writable while CCIF is readable but not writable, and remain ing bits read 0 and are not writable.
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-15 18.3.3.8 CFMCMD — CFM Command R egister The CFMCMD register is th e flash command register.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-16 F reescale Semiconductor 18.3.3.9 CFMCLKSEL — CFM Clock Select Register The CFMCLKSEL register reflects th e factory setting for read access la tency from the system bus to the flash block.
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-17 18.4.2 Flash Normal Mode In flash normal mode, the user can access the CFM registers and the CFM flash memory (see Section 18.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-18 F reescale Semiconductor Therefore, the clock to the flas h block timing control, FCLK, is: .
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-19 buffered command waits for the active command to be completed before being launched. The CCIF flag in the CFMUST A T register set upon completio n of all active and buffered commands.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-20 F reescale Semiconductor check operation (CCIF=1), the BLANK flag sets in the CFMUST A T register if the entire flash memory is erased.
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-21 P age Erase V erify The page erase verify operation ve rifies all memory addresses in a flash logical page are erased.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-22 F reescale Semiconductor Figure 18-15. Example Pa ge Erase V erify Command Flow Program The operation programs a previously erased address in the flash memory using an embedded algorithm.
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-23 An example flow to execute the program operati on is shown in Figure 18-16 . The program command write sequence is as follows: 1.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-24 F reescale Semiconductor Figure 18-16. Example Pr ogram Command Flow P age Erase The page erase operation eras es all memor y addresses in a flash logi cal page using an embedded algorithm.
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-25 An example flow to execute the page erase operati on is shown in Figure 18-17 . The page erase command write sequence is as follows: 1.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-26 F reescale Semiconductor Figure 18-17. Example Pa ge Erase Command Flow Mass Erase The mass erase operation erases all flash me mory addresses using an embedded algorithm.
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-27 An example flow to execute the mass erase command is shown in Figure 18-18 . The mass erase command write sequence is as follows: 1.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-28 F reescale Semiconductor Figure 18-18. Example Mas s Erase Command Flow Write: Register CFMC.
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-29 18.4.2.3.5 Flash Normal Mo de Illegal Operations The ACCERR flag .
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-30 F reescale Semiconductor If a command is not active (CCIF=1) when the MC U enters stop mode, the ACCERR flag does not set.
ColdFire Flash Modul e (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 18-31 18.4.3.2 Blank Check A secured CFM can be unsecur ed by verifying that the entire flash me mory is erased. If required, the mass erase command can be executed on the flash memory.
ColdFire Flash Module (CFM) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 18-32 F reescale Semiconductor.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 19-1 Chapter 19 EzP or t EzPort is a serial flash programming interface that allows the flas h memor.
EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 19-2 F re escale Semiconductor Figure 19-1 is a block diagram of the EzPort. Figure 19-1. EzP or t Bloc k Diagram 19.3 External Signal Description 19.3.1 Overview Table 19-1 contains a list of Ez Port external signals.
EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 19-3 EZPCK.The maximum frequency of the EzPort clock is half the system clock frequency for all commands except when executing the read da ta command.
EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 19-4 F re escale Semiconductor 19.4.1 Command Descriptions 19.4.1.1 Write Enable The W rite Enable command sets the write enable regist er bit in the status regi ster.
EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 19-5 19.4.1.4 Write Configuration Register The W rite Configuration Command updates the flash cont roller ’ s clock configurat ion register.
EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 19-6 F re escale Semiconductor 19.4.1.5 Read Data The Read Data command returns data from the flash memory , starting at the address specified in the command word.
EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 19-7 19.4.1.8 Sector Erase The Sector Erase command erases the contents of a 2-Kb yte space of flash memory. The 3-byte address sent after the command byte can be a ny address within the space to erase.
EzP ort MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 19-8 F re escale Semiconductor 19.6 Initialization/Application Information Prior to issuing any program or eras e commands, the clock configuration register must be written to set the flash state machine clock (FCL K).
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 20-1 Chapter 20 Pr ogrammable Interrupt Timer s (PIT0–PIT1) 20.1 Intr oduction This chapter describes the opera tion of the two programmable in terrupt timer modules: PIT0–PIT1.
Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 20-2 F re escale Semiconductor NO TE The low-power interrupt control regist er (LPICR) in the system control module specifies the interrupt level at or above which the device can be brought out of a low-power mode.
Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 20-3 20.2.1 PIT Control and St atus Register (PCSR n ) The PCSR n registers configure the corresponding timer ’ s operation.
Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 20-4 F re escale Semiconductor 20.2.2 PIT Modulus Register (PMR n ) The 16-bit read/write PMR n contains the timer modulus value loaded into the PIT counter when the count reaches 0x0000 and the PCSR n [RLD] bit is set .
Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 20-5 20.2.3 PIT Count Register (PCNTR n ) The 16-bit, read-only PCNTR n contains the counter value. Reading the 16-bit counter wi th two 8-bit reads is not guaranteed coherent.
Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 20-6 F re escale Semiconductor Figure 20-5. Counter Reloading from the Modulus Latc h 20.3.2 Free-Running Timer Operation This mode of operation is selected when the PCSR n [RLD] bit is clear .
Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 20-7 The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests.
Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 20-8 F re escale Semiconductor.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-1 Chapter 21 General Purpose Timer Module (GPT) 21.1 Intr oduction This device has one 4-channel gene ral purpose timer module (GP T). It c onsists of a 16-bit counter driven by a 7-stage programmable prescaler .
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-2 F re escale Semiconductor 21.3 Block Dia gram Figure 21-1.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-3 21.4 Low-P o wer Mode Operation This subsection describes the operation of the ge neral purpose time module in low-power modes and halted mode of operation.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-4 F re escale Semiconductor 21.5.3 SYNC n The SYNC n pin is for synchronization of th e timer counter . It can be used to synchronize the counter with externally-timed or clocked events.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-5 21.6.1 GPT Input Capture/Output Compare Select Register (GPTIOS) 0x1A_0017 GPT Channel 3 Register Low (GPTC3L) 2 8 21.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-6 F re escale Semiconductor 21.6.2 GPT Compare Force Register (GPCFORC) NO TE A successful channel 3 output compar e overrides any compare on channels 2:0.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-7 21.6.4 GPT Output Compare 3 Data Register (GPT OC3D) NO TE A successful channel 3 output compare overrides any channel 2:0 compares.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-8 F re escale Semiconductor 21.6.6 GPT System Control Register 1 (GPTSCR1) T able 21-8. GPTCNT Field Descriptions Field Description 15–0 CNTR Read-only field that provides the current count of the timer coun ter .
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-9 Figure 21-8.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-10 F reescale Semiconductor 21.6.9 GPT Contr ol Register 2 (GPTCTL2) 21.6.10 GPT Interrupt Enable Register (GPTIE) T able 21-11. GPTCL1 Field Descriptions Field Description 7–0 OMx/OLx Output mode/o utput le vel.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-11 21.6.11 GPT System Contr ol Register 2 (GPTSCR2) T able 21-13. GPTIE Field Descriptions Field Description 7–4 Reserved, should be clea red.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-12 F reescale Semiconductor 21.6.12 GPT Flag Register 1 (GPTFLG1) 21.6.13 GPT Flag Register 2 (GPTFLG2) 2–0 PR Prescaler bits. Select the prescaler divisor f or the GPT counter .
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-13 Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is se t, an y access to the GPT coun ter registers clears GPT flag register 2.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-14 F reescale Semiconductor 21.6.16 Pulse Accumulator Fla g Register (GPTP AFLG) T able 21-18. GPTP A CTL Field Descriptions Field Description 7 Reser ved, should be cleared.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-15 NO TE When the fast flag clear all enable bit (GP TSCR1[TFFCA]) is set, any access to the pulse accumulator counter registers clears all the flags in GP TP AFLG .
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-16 F reescale Semiconductor 21.6.18 GPT P or t Data Register (GPTPOR T) 21.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-17 21.7.1 Prescaler The prescaler divides the module cl ock by 1 or 16. The PR[2:0] bits in GP TSCR2 select the prescaler divisor .
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-18 F reescale Semiconductor 21.7.4 Pulse Accum ulator The pulse accumulator (P A) is a 16-bit counter that can operate in two modes: 1. Event counter mode: counts edge s of selected polarity on the pulse accumulator input pin, P AI 2.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-19 The P A counter register (GP TP ACNT) reflects the number of pulses from the divide-by-64 clock since the last reset.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-20 F reescale Semiconductor T able 21-23. GPT Settings and Pin Functions GPTEN DDR 1 1 When DDR sets the pin as input (0), reading the data regi ster re turns the state of the pin.
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 21-21 21.8 Reset Reset initializes the GP T registers to a known startup state as described in Section 21.6, “Memory Map and Registers .
General Purpose Timer Module (GPT) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 21-22 F reescale Semiconductor 21.9.3 Pulse Accum ulator Input (P AIF) P AIF is set when the selected edge is detected at the P AI pin. In event counter mode, the event edge sets P AIF .
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 22-1 Chapter 22 DMA Timer s (DTIM0–DTIM3) 22.1 Intr oduction This chapter describes the configuration and operation of the four direct memory access (DMA) timer modules (DTIM0, DTIM1, DTIM2, and DTIM3).
DMA Timers (DTIM0–DTIM3) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 22-2 F re escale Semiconductor Figure 22-1 is a block diagram of one of the four identical timer modules.
DMA Timer s (DTIM0–DTIM3 ) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 22-3 22.2.1 DMA Timer Mode Registers (DTMR n ) DTMRs, shown in Figure 22-2 , program the prescaler and various timer modes.
DMA Timers (DTIM0–DTIM3) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 22-4 F re escale Semiconductor 22.2.2 DMA Timer Extended Mode Registers (DTXMR n ) The DTXMR n register programs DMA request a nd increment modes for the timers.
DMA Timer s (DTIM0–DTIM3 ) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 22-5 22.2.3 DMA Timer Event Registers (DTER n ) DTER n , shown in Figure 22-4 , reports capture or refere nce events by setting DTER n [CAP] or DTER n [REF].
DMA Timers (DTIM0–DTIM3) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 22-6 F re escale Semiconductor 22.2.4 DMA Timer Reference Registers (DTRR n ) Each DTRR n , shown i.
DMA Timer s (DTIM0–DTIM3 ) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 22-7 22.2.5 DMA Timer Capture Registers (DTCR n ) Each DTCR n latches the corresponding DTCN n value during a capture operation when an edge occurs on DTIN n , as programmed in DTMR n .
DMA Timers (DTIM0–DTIM3) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 22-8 F re escale Semiconductor 22.3 Functional Description 22.3.1 Prescaler The prescaler clock input is selected from the internal bus clock (f sys divided by 1 or 16) or from the corresponding timer input, DTIN n .
DMA Timer s (DTIM0–DTIM3 ) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 22-9 22.4 Initialization/Application Information The general-purpose ti.
DMA Timers (DTIM0–DTIM3) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 22-10 F reescale Semiconductor move.l #0x0000,D0;writing to the timer counter with any move.l DO,TCN0 ;value resets it to zero move.l #0xAFAF,DO ;set the timer0 refer ence to be move.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-1 Chapter 23 Queued Serial P eripheral Interface (QSPI) 23.1 Intr oduction This chapter describes the queued serial peripheral inte rface (QSPI) module.
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-2 F re escale Semiconductor 23.1.2 Overview The queued serial peripheral interface module provides a serial periphe ral interface with queued transfer capability .
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-3 23.3 Memory Map/Register Definition T able 23-2 is the QSPI register memory map. Reading reserved locations returns zeros.
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-4 F re escale Semiconductor T able 23-3. QMR Field Descriptions Field Description 15 MSTR Master mode enable. 0 Reser ved, do not use.
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-5 Figure 23-3 shows an example of a QSPI clocking and data transfer . Figure 23-3. QSPI Cloc king and Data T ransfer Example 23.
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-6 F re escale Semiconductor 23.3.3 QSPI Wrap Register (QWR) The QSPI wrap register provides halt transfer control, wraparound settings, and queue pointer locations.
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-7 23.3.5 QSPI Address Register (QAR) The QAR is used to specify the locatio n in the QSPI RAM that read and write ope rations affect.
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-8 F re escale Semiconductor 23.3.6 QSPI Data Register (QDR) The QDR is used to access QSPI RAM indirectly . The CPU read s and writes all data from and to the QSPI RAM through this register .
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-9 NO TE The command RAM is accessed only us ing the most significant byte of QDR and indirect addre ssing based on QAR[ADDR].
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-10 F reescale Semiconductor The RAM is organized so that 1 byte of command cont rol data, 1 word of transmit data, and 1 word of receive data comprise 1 of the 16 queue entries (0x0–0xF).
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-11 23.4.1 QSPI RAM The QSPI contains an 80-byte block of static RAM that can be accesse d by the user and the QSPI.
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-12 F reescale Semiconductor stored in the least significant bits of the RAM. Unus ed bits in a receive queue entry are set to zero upon completion of the i ndividual queue entry .
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-13 The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following expression: Eqn.
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-14 F reescale Semiconductor where QDL YR[DTL] has a range of 1–255. A zero value for DTL causes a delay-af ter-transfer value of 8192/f sys .
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 23-15 QIR[SPIFE] is set. QIR[SPIF ] is not automatically rese t. If interrupt driven QSPI service is used, the service routine must clear QIR[SPIF] to abort the current reques t.
Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 23-16 F reescale Semiconductor.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-1 Chapter 24 U AR T Modules 24.1 Intr oduction This chapter describes the use of the three univers al asynchronous receiver/t ransmitters (UAR T s) and includes programming examples.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-2 F re escale Semiconductor NOTE The DTIN n pin can clock UAR T n .
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-3 24.2 External Signal Description T able 24-1 briefly describes th e UAR T module signals. Figure 24-2 shows a signal configuration for a UAR T/RS-232 interface.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-4 F re escale Semiconductor T able 2 4-2. U A RT Module Memory Map IPSBAR Offset Register Width (bit) Access.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-5 24.3.1 U ART Mode Register s 1 (UMR1 n ) The UMR1 n registers control configuration.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-6 F re escale Semiconductor 24.3.2 U AR T Mode Register 2 (UMR2 n ) The UMR2 n registers control UAR T module configuration. UMR2 n can be read or written when the mode register pointer points to it, wh ich occurs after any access to UMR1 n .
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-7 24.3.3 U ART Status Register s (USR n ) The USR n registers, shown in Figure 24-5 , show the status of the transmit ter , the receiver , and the FIFO.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-8 F re escale Semiconductor IPSBAR Offset: 0x00_0204 (USR0) 0x00_0244 (USR1) 0x00_0284 (USR2) Access: User read-only 76543210 R RB FE PE OE TXEMP TXRD Y FFULL RXRD Y W R e s e t : 00000000 Figure 24-5.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-9 24.3.4 U AR T Clock Select Register s (UCSR n ) The UCSRs select an external clock on the DTIN input (divided by 1 or 16) or a prescaled internal bus clock as the clocking source for th e transmitter and receiver .
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-10 F reescale Semiconductor T able 24-7 describes UCR n fields and commands. Examples in Section 24.4.2, “T ransmitter and Receiver Operating Modes ,” show how these commands are used.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-11 24.3.6 U ART Receive Buff ers (URB n ) The receive buffers (shown in Figure 24-8 ) contain one serial shift regi ster and three receiver holding registers, which act as a FIFO.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-12 F reescale Semiconductor 24.3.7 U AR T T ransmit Buffers (UTB n ) The transmit buffers consist of th e transmitter holding register and th e transmitter shift register .
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-13 24.3.9 U AR T A uxiliary Control Register (U A CR n ) The UACRs control the input enable.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-14 F reescale Semiconductor NOTE T rue status is pr ov ided in the UISR n regardless of UIMR n settings.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-15 24.3.11 U AR T Baud Rate Ge nerator Registers (UBG1 n /UBG2 n ) The UBG1 n registers hold the MSB, and the UBG2 n registers hold the LSB of the preload value.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-16 F reescale Semiconductor 24.3.13 U AR T Output P or t Command Registers (UOP1 n /UOP0 n ) The UR TS n output can be asserted by writing a 1 to UOP1 n [R TS] and negated by writing a 1 to UOP0 n [R TS].
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-17 24.4.1.1 Pro grammable Divider As Figure 24-17 shows, the UAR T n transmitter and receiver can us e the following clock sources: • An external clock signal on the DTIN n pin.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-18 F reescale Semiconductor Using a 66-MHz internal bus clock and letting baud rate equal 9600, then Eqn. 24-2 Therefore, UBG1 n equals 0x00 and UBG2 n equals 0xD6.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-19 optional parity bit, and the programmed number of st op bits. The lsb is sent first. Data is shifted from the transmitter output on the falling edge of the clock source.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-20 F reescale Semiconductor Figure 24-19. T ransmitter Timin g Diagram 24.4.2.2 Receiver The receiver is enabled through its UCR n , as described in Section 24.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-21 framing error , overrun error, and received break conditions set the respective PE, FE, OE, and RB error and break flags in the USR n at the received character bounda ry .
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-22 F reescale Semiconductor programming the ERR bit in the UAR T’ s mode re gister (U MR1 n ), status is provided in character or block modes. USR n [RXRDY] is set when at least one character is availa ble to be read by the CPU.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-23 24.4.3.1 A utomatic Echo Mode In automatic echo mode, shown in Figure 24-21 , the UAR T automatically rese nds received data bit by bit.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-24 F reescale Semiconductor Figure 24-2 3. Remote Loopbac k 24.4.4 Multidrop Mode Setting UMR1 n [PM] programs the UAR T to ope rate in a wake-up mode for multidrop or multiprocessor applications.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-25 Figure 24-24. Mult idrop Mode Timing Diagr am A character sent from the master st ation consists of a start bit, a programmed number of data bits, an address/data (A/D) bit flag, and a programmed number of stop bits.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-26 F reescale Semiconductor 24.4.5 Bus Operation This section describes bus operati on during read, write, and interrupt acknowledge cycles to the UAR T module.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-27 3. Unmask appropriate bits in the core’ s st atus register (SR) to enable interrupts.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-28 F reescale Semiconductor T o configure the UAR T for DMA requests: 1. Initialize the DMAREQC in the SCM to map th e desired UAR T DMA requests to the desired DMA channels.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-29 b) If preferred, program operation of transmitter ready-to-send (TXR TS). c) If preferred, program operation of clear-to-send (TXCTS bit).
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-30 F reescale Semiconductor Figure 24-25. U ART Mode Pr ogramming Flowc har t (Sheet 2 of 5) CHCHK CHCHK Pla.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-31 Figure 24-25. U ART Mode Pr ogramming Flowc har t (Sheet 3 of 5) A B B FRCHK Ha.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-32 F reescale Semiconductor Figure 24-25. U ART Mode Pr ogramming Flowc har t (Sheet 4 of 5) Wa s IRQ Caused.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 24-33 Figure 24-25. U ART Mode Pr ogramming Flowc har t (Sheet 5 of 5) OUTCH Is T ran.
U A RT Modules MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 24-34 F reescale Semiconductor.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-1 Chapter 25 I 2 C Interface 25.1 Intr oduction This chapter describes the I 2 C module, clock synchronization, and I 2 C programming model registers.
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-2 F re escale Semiconductor 25.1.1 Block Diagram Figure 25-1 is a block diagram of the I 2 C module. Figure 25-1. I 2 C Module Bloc k Diagram Figure 25-1 shows the I 2 C registers, described in Section 25.
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-3 The interface operates up to 100 Kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of the internal bus cloc k divided by 20, with reduced bus loading.
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-4 F re escale Semiconductor 25.2.1 I 2 C Address Register s (I2ADR n ) The I2ADR n hold the address the I 2 C responds to when addressed as a sl ave.
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-5 25.2.3 I 2 C Contr ol Registers (I2CR n ) The I2CR n enable the I 2 C modules and the I 2 C interrupts. They also contai n bits that govern operation as a slave or a master .
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-6 F re escale Semiconductor IPSBAR Offset: 0x0308 (I2CR0) 0x0388 (I2CR1) Access: User read/write 76543210 R IEN IIEN MST A MTX TXAK RST A 0 0 W R e s e t : 00000000 Figure 25-4.
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-7 25.2.4 I 2 C Status Registers (I2SR n ) The I2SR n contain bits that indicate tr ansaction direction and status.
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-8 F re escale Semiconductor 25.2.5 I 2 C Data I/O Register s (I2DR n ) In master -receive mode, reading the I2DR n s allows a read to occur and for the next data byte to be received.
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-9 Figure 25-7. I 2 C St andard Comm unication Pr otocol 25.3.2 Slave Address T ransmission The master sends the slave address in the first byte after the ST AR T signa l ( B).
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-10 F reescale Semiconductor 25.3.4 Ac knowledge The transmitter releases the SDA line high during the acknowle dge clock pulse as shown in Figure 25-9 .
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-11 Figure 25 -10. Repeat ed ST ART V arious combinations of read/w rite formats are then possible: • The first example in Figure 25-1 1 is the case of master -transmitter transmitting to slave-receiver .
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-12 F reescale Semiconductor 25.3.7 Clock Sync hr onization and Arbitration I 2 C is a true multi-master bus that allows more than one ma ster connected to it.
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-13 25.3.8 Handshaking and Clock Stretching The clock synchronization m echanism can acts as a handshake in da ta transfers. Slave devices can hold SCL low after completing one byte transfer.
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-14 F reescale Semiconductor may need to wait until the I2C is busy after writing the calli ng address to the I2DR before proceeding with the following instructions.
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 25-15 For a master receiver to terminate a data transf er , it must inform the sl ave transmitter by not acknowledging the last data byte.
I 2 C Interface MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 25-16 F reescale Semiconductor Figure 25-14. Flow-Chart of T ypical I 2 C Interrupt Routine Clear Master Mode?.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-1 Chapter 26 Analog-to-Digital Con verter (ADC) 26.1 Intr oduction The analog-to-digital converter (ADC) consists of tw o separate and complete ADCs, each with their own sample and hold circuits.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-2 F re escale Semiconductor 26.3 Block Dia gram The ADC function, shown in Figure 26-1.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-3 26.4.1 Control 1 Register (CTRL1) The CTRL1 register , shown in Figure 26-2 , is used to configure and control the ADC module.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-4 F re escale Semiconductor 12 SYNC0 Synchronization 0 Enable bit. When this bit is set, a co nv ersion may be initiated by asser ting a positive edge on the SYNC0 input.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-5 26.4.2 Control 2 Register (CTRL2) The structure of the CTRL2 register depends on whether the ADC is operating in sequential or parallel mode (see Section 26.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-6 F re escale Semiconductor 26.4.2.2 CTRL2 Under Pa rallel Scan Modes When the ADC operates in a parallel scan mode, the CTRL2 register is used to control the operation of converter B.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-7 12 SYNC1 Synchronization 1 Enable bit. In parallel-scan modes when SIMUL T equaling 0, setti ng SYNC1 allows a conv ersion to b e initiated by asser ting a positive edge on the SYNC1 input.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-8 F re escale Semiconductor 26.4.3 Zero Cr ossing Co ntrol Register (ADZCC) The ADC ze.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-9 SAMPLE4-7 should only contain binary values between 100 and 1 1 1. No dama ge occurs if this constraint is violated, but results are undefined.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-10 F reescale Semiconductor 26.4.5 Sample Disable Re gister (ADSDIS) This register is an exte nsion to the ADLST1and ADLST2, providing the ability to enab le only the desired samples programmed in the SAMPLE0–S AMPLE7.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-11 26.4.6 Status Register (ADST A T) This register provides the curren t status of the ADC module. RDY n bits are cleared by reading their corresponding result (ADRSL T n ) registers.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-12 F reescale Semiconductor T able 26-11. ADST A T Field Descriptions Field Description 15 CIP0 Conv ersion in Progress 0 bit. This bit indicates whe n a scan is in progress.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-13 26.4.7 Limit Status Register (ADLST A T) The ADC limit statu.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-14 F reescale Semiconductor 26.4.8 Zer o Crossing Stat us Register (ADZCST A T) The ADC zero crossing status (ADZCST A T) register latches in the result of a sign comparison between the current and previous sample.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-15 Negative results (SEXT = 1) are alwa ys presented in twos-complement fo rmat. If an application requires that the result be always positive, the corresponding of fset register (ADOFS n) must be set to 0x0.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-16 F reescale Semiconductor IPSBAR Offsets: 0x19_0022 (ADLLMT0) o x19_0024 (ADLLMT1) 0.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-17 26.4.11 Offset Register s (ADOFS n ) The values in the of fs et regis ters (ADOFS n ) are subtracted from the raw ADC values, and the results are stored in the ADRSL T n registers.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-18 F reescale Semiconductor 5. Current mode • Normal current mode is used to power the converters at cloc k rates above 100 kHz. • S tandby current mode uses less power and is engaged only when the ADC clock is at 100 kHz.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-19 10 PSTS0 Conv er ter A P ower Status bit. This bit is asser ted i mmediately after PD0 is set. It is deasser ted PUDELA Y ADC clock cycles after PD0 is c leared if APD is 0.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-20 F reescale Semiconductor 26.4.13 V olta g e Ref erence Register (CAL) In earlier series, this register supported ADC calibration and had a di fferent name.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-21 26.5 Functional Description The ADC’ s conversion process is in itiated by a sync signal from one of two input pins (SYNCx) or by writing 1 to a ST AR T n bit.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-22 F reescale Semiconductor Parallel scan can be simultaneous or non-simultaneous.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-23 Optional interrupts can be generated at the end of a scan sequence.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-24 F reescale Semiconductor Figure 26-20. Input Select Mux P arallel, Single Ended The two 1-of-4 select muxes can be set f or the appropr iate input line.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-25 26.5.2 ADC Sample Con version The ADC consists of a cyclic, algor ithmic architecture using two recu rsive sub-ranging sections (RSD#1 and RSD#2), shown in Figure 26-21 .
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-26 F reescale Semiconductor 26.5.2.1 Single- Ended Samples The ADC module performs a ratio metric conversion.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-27 Figure 26-22. T ypical Connections f or Differen tial Measurements 26.5.3 ADC Data Pr ocessing As shown in Figure 26-23 , the raw result of the ADC conversion proc ess is sent to an adder for offset correction.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-28 F reescale Semiconductor Figure 26-2 3. Result Register Dat a Manipulation 26.5.4 Sequential vs. P arallel Sampling All scan modes make use of the 8 SAMPLE slots in the ADLST1 and AD LST2 registers.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-29 bit is 1, when the SYNC0 i nput goes high. A scan ends when the first disabled sample slot is encountered in the SDIS register .
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-30 F reescale Semiconductor completion of the previous scan. In loop parallel scan modes, both converter s restart together if SIMUL T equals 1 and restart independe ntly if SIMUL T equals 0.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-31 T able 26-21. ADC Scan Modes Scan Mode Description Once sequential Up on ST AR T or an enabled sync signal, samples are ta ken one at a time star ting with SAMPLE0 until a first disa bled sample is encountered.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-32 F reescale Semiconductor 26.5.7 Interrupt Sour ces Figure 26-24 illustrates how five interrupt sources are combined into three entries in the interrupt vector table.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-33 PUDELA Y ADC clock cycles execute at the start of all scans while th e ADC engages the conversion clock and the ADC powers up, stabil izing in the standby current mode.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-34 F reescale Semiconductor When starting up in normal mode, fi rst set PUDELA Y to the lar ge power-up value. Next, clear the PD0 and or PD1 bits to power - up the required converters.
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-35 26.5.9.2 Description of Clock Operation As shown in Figure 26-25 , the conversion clock is the primary s ource for the ADC clock and is always selected as the ADC clock when conversions are in process.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-36 F reescale Semiconductor standby power mode requires an 8 MHz oscillator clock from th e relaxation oscillator , crystal oscillator , or external oscillator .
Analog-to-Digital Converter (ADC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 26-37 Figure 26-27.
Analog-to-Digital Co n verter (A DC) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 26-38 F reescale Semiconductor V REFH is as noise-free as possibl e. Any noise residing on the V REFH voltage is directly transferred to the digital result.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-1 Chapter 27 Pulse-Width Modulation (PWM) Module 27.1 Intr oduction This chapter describes the configuration and operati on of the pulse-width modul ation (PWM) module.
Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-2 F re escale Semiconductor Main features include the following: • Double-buffered pe.
Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-3 27.2.1 PWM Enable Register (PWME) Each PWM channel has an enable bit (PWME n ) to start its waveform output.
Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-4 F re escale Semiconductor 27.2.2 PWM P olarity Register (PWMPOL) The starting polarity of each PWM channel waveform is determined by the associated PWMPOL[PPOL n ] bit.
Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-5 27.2.4 PWM Prescale Clock Select Register (PWMPRCLK) The PWMPRCLK register selects the prescale clock source fo r clocks A and B indepe ndently .
Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-6 F re escale Semiconductor 27.2.5 PWM Center Align En able Register (PWMCAE) The PWMCAE register contains eight control bits for the selection of center -aligned outputs or left-aligned outputs for each PWM channel.
Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-7 27.2.6 PWM Contr ol Register (PWMCTL) The PWMCTL register provides various control of the PWM module. Change the CON n(n+1) bits only when both corresponding channels are disabled.
Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-8 F re escale Semiconductor 27.2.7 PWM Scale A Register (PWMSCLA) PWMSCLA is the programmable scale value used in sc aling clock A to generate clock SA.
Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-9 27.2.8 PWM Scale B Register (PWMSCLB) PWMSCLB is the programmable scale value used in sc aling clock B to generate clock SB.
Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-10 F reescale Semiconductor (PWME n =0), the PWMCNT n register does not count. When a channel is enabled (PWME n =1), the associated PWM counter starts at the count in the PWMCNT n register .
Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-11 27.2.11 PWM Channel Duty Register s (PWMDTY n ) The PWM duty registers determine the duty cycle of the associated PWM channel.
Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-12 F reescale Semiconductor 27.2.12 PWM Shutdo wn Register (PWMSDN) The PWM shutdown register provi des emergency shutdown functiona lity of the PW M module.
Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-13 27.3 Functional Description 27.3.1 PWM Clock Select There are four available clocks—clock A, B, SA (s caled A), and SB (s caled B) —all based on the internal bus clock.
Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-14 F reescale Semiconductor Figure 27-1 4.
Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-15 27.3.1.2 Scaled Clock (SA or SB) The scaled A (SA) and scaled B (SB) clocks use clock A and B respectively as inputs, divide it further with a user programmable value, then di vide this by 2.
Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-16 F reescale Semiconductor Figure 27-15. PWM Timer Channel Bloc k Diagram 27.3.2.1 PWM Enable Each PWM channel has an enable bit (PWME n ) to start its waveform output.
Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-17 and/or period values to be latched. In addition, because the co unter is readable, it is possible to know where the count is with respect to th e duty value, and software can be used to make adjustments .
Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-18 F reescale Semiconductor 27.3.2.5 Left-Aligned Outputs The PWM timer provides the choice of two types of outputs: le ft- or center -aligned.
Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-19 Figure 27-17.
Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-20 F reescale Semiconductor Eqn. 27-10 27.
Pulse-Width Modulation ( PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 27-21 Figure 27-20. PWM 1 6-Bit Mode Left- or center -aligned out put mode can be used in concatenated mode and is controlled by the low order CAE n bit.
Pulse-Width Modulation (PWM) Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 27-22 F reescale Semiconductor T able 27-16.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-1 Chapter 28 Deb ug Module 28.1 Intr oduction This chapter describes the revision B+ enhanced hardware debug module. 28.1.1 Block Diagram The debug module is shown in Figure 28-1 .
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-2 F re escale Semiconductor The first version 2 ColdFire core devices implemented the original de bug architecture, now called revision A.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-3 28.3 Real-Time T race Support Real-time trace, which defines the dynamic execution pa th and is also known as instruction trace, is a fundamental debug function.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-4 F re escale Semiconductor Execution speed is affected only when both storage elements contain valid data to be dumped to the DDA T A port. The core stalls until one FIFO entry is available.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-5 28.3.1 Begin Execution of T aken Branc h (PST = 0x5) PST is 0x5 when a taken branch is executed. For some opcodes, a branch tar get address may be displayed on DDA T A depending on the CSR settings.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-6 F re escale Semiconductor 28.4 Memory Map/Register Definition In addition to the existing BDM comm ands tha.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-7 NO TE Debug control registers can be written by the external development system or the CPU through the WDEBUG instru ction.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-8 F re escale Semiconductor DRc[4:0]: 0x00 (CSR) Access: Super visor write-o nly BDM read/write 31 30 29 28 2.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-9 15 MAP F orce processor references in emulator mode. 0 Al l emulator-mode ref erences are mapped into super visor code and data spaces.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-10 F reescale Semiconductor 28.4.3 BDM Address Attrib ute Register (B AAR) The BAAR register defines the address space fo r memory-referencing BDM commands.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-11 setting of the trigger definition re gister (TDR). AA TR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and through the BDM port using the WDMREG command.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-12 F reescale Semiconductor 28.4.5 T rig ge r Definition Register (TDR) The TDR configures the operation of the hard ware breakpoint logic corresponding with the ABHR/ABLR/AA TR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the debug module.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-13 DRc[4:0]: 0x07 (TD R) Access: Super visor write-only BDM write -only Second Lev e.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-14 F reescale Semiconductor 20–18 L2EA Enable Le vel 2 Address Breakpoint. Setting an L2EA bit enables the corresponding address breakpoint. Clear ing all three bits disables the breakpoint.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-15 28.4.6 Pr ogram Counter Breakpoint /Mask Registers (PBR0–3, PBMR) The PBR n registers define an instruction address for use as part of the trigger .
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-16 F reescale Semiconductor contents of the breakpoint registers are compared with the processo r ’ s program counter register when TDR is configured appropriately .
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-17 28.4.7 Address Breakpoint Registers (ABLR, ABHR) The ABLR and ABHR define regions in the processor ’ s data address space that can act as part of the trigger .
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-18 F reescale Semiconductor 28.4.8 Data Breakpoint and Mask Registers (DBR, DBMR) The data breakpoint register (DBR), specify data patterns used as part of the trigger in to debug mode.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-19 28.5 Backgr ound Debug Mode (BDM) The ColdFire family implements a low-level system debugger in th e microprocessor in a dedicated hardware module.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-20 F reescale Semiconductor 3. The execution of a HAL T instruction immediately suspends execution. Attempting to execute HAL T in user mode while CSR[UHE] is cleared generates a privilege violation exception.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-21 Figure 28-13 . Maximum BDM Serial Interf ace Timing DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled, along with DSI, on the rising edge of PSTCLK.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-22 F reescale Semiconductor 28.5.2.2 Transmit P acket Format The basic transmit packet consists of 16 data bits and 1 reserved bit. 28.5.3 BDM Command Set T able 28-20 summarizes the BDM command set.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-23 Freescale reserves unassigned comm and opcodes. All unused command fo rmats within any revision level perform a NOP and return the illegal command respo nse .
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-24 F reescale Semiconductor 28.5.3.1 ColdFire BDM Command Format All ColdFire family BDM commands include a 16-bit operation word followed by an optional set of one or more extension words.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-25 28.5.3.2 Command Sequence Diagrams The command sequence diagram in Figure 28-17 shows serial bus traf fic for commands. Each bubble represents a 17-bit bus transfer .
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-26 F reescale Semiconductor • Results are returned in the two serial transfer cycles after the memory access completes.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-27 28.5.3.3.2 Write A/D Register ( WAREG / WDREG ) The operand longword data is written to the specified addr ess or data register . A wr ite alters all 32 register bits.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-28 F reescale Semiconductor Command/Result Formats: Command Sequence: Figure 28-23. READ Command Sequence Operand Data: The only operand is the longw ord address of the requested location.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-29 28.5.3.3.4 Write Me mor y Location ( WRITE ) W rite data to the memory location specified by the longword address. BAAR [TT ,TM] defines address space.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-30 F reescale Semiconductor Command Sequence: Figure 28-25. WRITE Command Sequen ce Operand Data: This two-operand inst ruction requires a longword abso lute address that specifies a location the data operand is written.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-31 NO TE DUMP does not check for a valid address; it is a valid command only when preceded by NOP , READ , or another DUMP command. Otherwise, an illegal command response is returned.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-32 F reescale Semiconductor Result Data: Requested data is returned as a wo rd or longword. Byte data is returned in the least-significant byte of a wo rd result.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-33 Command Sequence: Figure 28-29. FIL L Command Sequence Operand Data: A single opera nd is data to be writte n to the memory location.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-34 F reescale Semiconductor Operand Data: None Result Data: The command-complete response ( 0xFFFF) is returned during the next shift operation. 28.5.3.3.8 No Operation ( NOP ) NOP performs no operation and may be us ed as a null command where required.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-35 Command Sequence: Figure 28-35. SYNC _ PC Command Sequence Operand Data: None Result Data: Command complete status (0xFFFF) is returned when the register write is complete.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-36 F reescale Semiconductor Command Sequence: Figure 28-37. RCREG Command Sequence Operand Data: The only operand is the 32-bi t Rc control register select field.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-37 else A7 = User Stack Pointer OTHER_A7 = Supervisor Stack Point er The BDM programming model supports reads and writes to A7 and OTHER_A7 directly .
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-38 F reescale Semiconductor 28.5.3.3.13 Read Deb ug Module Register ( RD MR E G ) Read the selected de bug module register and return the 32-bit result. The only va lid register selection for the RDMREG command is CSR (DRc = 0x00).
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-39 Command Format: T able 28-4 shows the definition of the DRc write encoding. Command Sequence: Figure 28-43. WDMREG Command Sequence Operand Data: Longword data is written into the specified debug register .
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-40 F reescale Semiconductor The breakpoint status is also posted in the CSR. CS R[BST A T] is cleared by a CSR read when a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoi nt is not enabled.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-41 When debug interrupt operati ons complete, the R TE instruction execut es and the processor exits emulator mode.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-42 F reescale Semiconductor NO TE Breakpoint registers must be carefully configured in a de velopment system if the processor is executing.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-43 T able 28-25. PST/DD A T A Specificat ion for User -Mode Instructions Instruction Opera nd Syntax PST/DD A T A add.l <ea>y ,Dx PST = 0x1, {PST = 0xB, DD = source operand} add.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-44 F reescale Semiconductor divu.w <ea>y ,Dx PST = 0x1, {PST = 0x9, DD = source operand} eor .l Dy ,<ea>x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB , DD = destination} eori.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-45 or .l Dy ,<ea>x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} ori.l #<data>,Dx PST = 0x1 pea.l <ea>y PST = 0x1, {PST = 0xB , DD = desti nation operand} pulse PST = 0x4 rems.
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-46 F reescale Semiconductor T able 28-26 shows the PST/DDA T A specification fo r multiply-accumulat e instructions. 1 During nor mal exception processing, the PST output is driven to a 0xC indicating the e xception pr ocessing state.
Debug Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 28-47 28.7.2 Supervisor Instruction Set The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown below .
Debu g Module MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 28-48 F reescale Semiconductor Figure 28-44. Recommended BDM Connector 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 29-1 Chapter 29 IEEE 1149.1 T est Access P or t (JT A G) 29.1 Intr oduction The Joint T est Action Group (JT AG) is a dedicated user -accessible test logic compliant with the IEEE 1 149.
IEEE 1149.1 T est Acc ess P ort (JT AG) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 29-2 F re escale Semiconductor 29.1.2 Features The basic features of the JT AG module .
IEEE 1149.1 T est Access Port (JT A G) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 29-3 When one module is selected, the inputs into the ot her module are disabled or forced to a known logic level, as shown in T able 29-3 , to disable the corresponding module.
IEEE 1149.1 T est Acc ess P ort (JT AG) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 29-4 F re escale Semiconductor 29.2.5 T est Reset/Development Seri al Clock (TRST /DSC.
IEEE 1149.1 T est Access Port (JT A G) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 29-5 29.3.3 Bypass Register The bypass register is a single-bit shift register path from TDI to TDO when the BYP ASS instruction is selected.
IEEE 1149.1 T est Acc ess P ort (JT AG) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 29-6 F re escale Semiconductor The boundary scan register cont ains bits for bonded-out and non bonded-out signals, excluding JT AG signals, analog signals, power supplies, comp liance enable pins, and clock signals.
IEEE 1149.1 T est Access Port (JT A G) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 29-7 Figure 29-4. T AP Contr oller State Machine Fl ow 29.4.3 JT A G Instructions T able 29-5 describes public and private instructions.
IEEE 1149.1 T est Acc ess P ort (JT AG) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 29-8 F re escale Semiconductor 29.4.3.1 IDCODE Instruction The IDCODE instruction selects the 32-bit IDCODE register for connection as a shift path between the TDI and TDO pin.
IEEE 1149.1 T est Access Port (JT A G) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor 29-9 and held in the boundary scan update registers. EXTEST can also confi gure the direction of bidirectional pins and establish high-impedance st ates on some pins.
IEEE 1149.1 T est Acc ess P ort (JT AG) MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 29-10 F reescale Semiconductor to a single bit (the bypass register ) while conducting an EXTEST type of instruction through the boundary scan register .
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-1 Appendix A Register Memory Map Quic k Reference Ta b l e A - 1 summarizes the address, name, and byte assi gnment for registers within the MCF5221 1 CPU space.
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-2 F re escale Semiconductor T able A-2.
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-3 IPSBAR + 0x18_0000 Reser ved 64K IPSBAR + 0x19_0000 ADC 64K .
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-4 F re escale Semiconductor IPSBAR + 0x0031 Grouped P eri pheral Access Control Register.
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-5 IPSBAR + 0x021C (Read) Reserved 8 U ART Baud Rate Generator .
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-6 F re escale Semiconductor IPSBAR + 0x0288 (Read) Reser ved 8 (Write ) U ART Command Re.
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-7 I 2 C1 Reg isters IPSBAR + 0x0300 I 2 C Address Register 1 I.
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-8 F re escale Semiconductor IPSBAR + 0x0480 DMA Timer Mode Register 2 DTMR2 16 IPSBAR + .
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-9 IPSBAR + 0x0C4C Interrupt Control Register 0-12 ICR012 8 IPS.
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-10 F re escale Semiconductor IPSBAR + 0x0C6D Interrupt Control Register 0-45 ICR045 8 IP.
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-11 IPSBAR + 0x0FFC Global Lev el 6 Interr upt Acknowledge Regi.
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-12 F re escale Semiconductor IPSBAR + 0x10_001E Reser ved — 8 IPSBAR + 0x10_001F Reser.
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-13 IPSBAR + 0x10_003C P or t QS Pin Da ta/Set Data Register PO.
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-14 F re escale Semiconductor IPSBAR + 0x10_0058 P or t TD Clear Outp ut Data Register CL.
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-15 Reset Control, Chip Configur ation, and Po wer Manag ement .
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-16 F re escale Semiconductor Programmable Interrupt Timer 0 Registers IPSBAR + 0x15_0000.
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-17 IPSBAR + 0x1A_0009 GPT Control Register 1 GPTCTL1 8 IPSBAR .
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-18 F re escale Semiconductor IPSBAR + 0x1B_0014 PWM Channel P eriod Register 0 PWMPER0 8.
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor A-19 IPSBAR + 0x1C_0098 Address Register ADDR 8 IPSBAR + 0x1C_0 .
Register Memory Map Quick Reference MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 A-20 F re escale Semiconductor IPSBAR + 0x1D_0008 CFM Security Register CFMSEC 32 IPSBAR +.
MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 F reescale Semicondu ctor B-1 Appendix B Re vision Histor y This appendix describes corrections to the MCF5221 1 Refer ence Manual . For convenience, the corrections are grouped by revision.
Revision History MCF52211 ColdFire® Integr ated Microcontroller Reference Manual, Rev . 2 B-2 F re escale Semiconductor B.2 Changes between Rev . 0 and Rev . 1 T able 2. MCF52211RM Re v . 0 to Re v . 1 Changes Location Description Throughout • Formattin g, la yout, spelling, and grammar corrections.
Ein wichtiger Punkt beim Kauf des Geräts Freescale Semiconductor ColdFire MCF52210 (oder sogar vor seinem Kauf) ist das durchlesen seiner Bedienungsanleitung. Dies sollten wir wegen ein paar einfacher Gründe machen:
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