Benutzeranleitung / Produktwartung RX-8564LC des Produzenten Epson
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RM0403-3-E01 Application Manua l Real Time Clock Module RX-8564LC Model Product Number RX- 8564LC Q418564C0 xxxx00.
N O T I C E • The material is subject to change without notice. • Any part of this material may not be reproduced or duplicated in any form or any means without the written permission of EP SON TO YOCOM. • The information, applied circuit, program, usage etc.
RX − 8564 LC CONTENTS 1. Overv iew ................................................................................................................... 1 2. Block diagram ...............................................................................
RX − 8564 LC Page − 1 ETM12E-01 Low pow er consumption / Small size thin model p ackage I 2 C-Bus Interface Real Time Clock Module RX − − − − 8564 LC • Built in frequency adjusted 32.768 kHz crystal unit. • Interface type : 400 kHz two-w ire I 2 C-bus interface • W ide operating voltage range : 1.
RX − 8564 LC Page − 2 ETM12E-01 3. Terminal description 3.1. T er m inal connect ions RX − 8564 LC 1. N.C . 12. N.C . 2. N.C . 11 . C L K O E 3. N.C . 10. V DD 4. N.C . 9. CLK OUT 5. / IN T 8 . SC L 6. G ND # 1 # 6 # 12 # 7 7. SDA VSOJ − 12pin 3.
RX − 8564 LC Page − 3 ETM12E-01 4. External Dimensions / Marking Layout 4.1. External Dim ensions RX − 8564 LC ( VSOJ − 12pin ) • E x t e r n a l d i m e n s i o n s • Recommended soldering pattern Unit : m m ( 0.4 ) 2.8 ± 0.2 2.77 0.8 1.
RX − 8564 LC Page − 4 ETM12E-01 5. Absolut e Maximum Ratings GND = 0 V Parame ter Symbol Condition Rating Unit Supply Voltage V DD Between V DD and GND − 0.5 to +6.5 V Supply Voltage I DD V DD pin − 50 to 50 mA Input Voltage V I Input pin GND − 0.
RX − 8564 LC Page − 5 ETM12E-01 8. Electrical Characteristics 8.1. DC charact er ist ics * Unless otherwise specified, G ND = 0 V , V DD = 1.8 V to 5.
RX − 8564 LC Page − 6 ETM12E-01 8.2. AC electr ical char act er istics * Unless otherwise specified, G ND = 0 V , V DD = 1.8 V to 5.5 V , Ta = − 40 ° C to +85 ° C Item Symbol Condition Min . Typ . Max . Unit SCL clock frequency f SCL 400 kHz Start condition set-up time t SU; STA 0.
RX − 8564 LC Page − 7 ETM12E-01 9. Reference data (1) Example of frequency and temperature characteristics -150 -100 -50 0 -50 0 50 100 Temperat ure [ ° C] Frequency ∆ f T × 10 -6 θ T = +25 ° C Typ. α = -0.035 × 10 -6 T y p . [ Fi n din g the f r eq uen c y st abi li ty ] 1.
RX − 8564 LC Page − 8 ETM12E-01 10. External connection ex ample device SCL SDA GND V DD Master V DD SCL SDA t r R = C BUS Pull up Registor 8564 SCL SDA GND V DD SLAVE ADRS = 1010001 I C-BUS 2 I C.
RX − 8564 LC Page − 9 ETM12E-01 1 1. Application notes 1) Notes on h andli ng This modu le us es a C- M O S IC t o r ealiz e low p ower c onsu m pt ion.
RX − 8564 LC Page − 10 ETM12E-01 12. Overv iew of Functions and Description of Registers 12.1. Overview of Functions 1) Clock f unctions This function is used to set and read out month, day , hour , date, minute, second, and year (last two digit s) data.
RX − 8564 LC Page − 11 ETM12E-01 12.2. Reg ister table Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 not e 00 Control 1 TEST 0 STOP 0 TEST 0 0 0 ∗ 3 , ∗ 4 01 Control 2 0.
RX − 8564 LC Page − 12 ETM12E-01 13. Description of Functions 13.1. Descript ion of registers 13.1.1. Control register 1 ( Reg − 00 [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2.
RX − 8564 LC Page − 13 ETM12E-01 13.1.2. Control register 2 ( Reg − 01 [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 Control 2 0 × 0 TI / TP AF TF AIE TIE • This register is used to monitor various interrupt ev ent settings and the conditions under which v arious interrupt- related events occur.
RX − 8564 LC Page − 14 ETM12E-01 13.1.3. Clock counter ( Reg − 02 [h] to 04 [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02 Seconds VL 40 20 10 8 4 2 1 03 M inutes × 40 20 10 8 4 2 1 04 Hours × × 20 10 8 4 2 1 • The clock counter counts seconds, minutes, and hours.
RX − 8564 LC Page − 15 ETM12E-01 13.1.4. Calendar counter ( Reg − 05 [h] , 07 [h] , 08 [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05 Da ys × × 20 10 8 4 2 1 07 .
RX − 8564 LC Page − 16 ETM12E-01 13.1.6. Alarm registers ( Reg − 09 [h] to 0C [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 09 Minute Alarm AE 40 20 10 8 4 2 1 0A Ho.
RX − 8564 LC Page − 17 ETM12E-01 13.1.9. CLKOUT output register (Reg - 0D [h]) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0D CLKOUT frequency FE × × × × × FD1 FD0 • This register is used to control clock output via the C LKOUT output pin.
RX − 8564 LC Page − 18 ETM12E-01 13.2. Fixed-cycle Timer I nt er rupt Function The fix ed-cycle timer interrupt function generates an interrupt event periodically at any fix ed cycle set betw een 244.
RX − 8564 LC Page − 19 ETM12E-01 3) Overview of fix ed-cycle timer interrupt function (1) Changing the T E (T imer Enable) bit value from "0" to "1" starts operation of the fix ed-cycle timer interrupt function.
RX − 8564 LC Page − 20 ETM12E-01 13.2.2. Related registers for function of timer interrupts. Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 Control 2 0 × 0 TI / TP AF TF .
RX − 8564 LC Page − 21 ETM12E-01 3) Down counter for fix ed-cycle timer ( T imer Register ) This register is used to set the default (preset) v alue for the counter.
RX − 8564 LC Page − 22 ETM12E-01 6) TIE bit ( T imer Interrupt Enable ) This bit is used to control output of interrupt signals from the /INT pin when a fix ed-cycle timer interrupt event has occurred. W hen a "1" is written to this bit, occurrence of an interrupt ev ent causes a low-lev el interrupt signal to be output from /INT pin.
RX − 8564 LC Page − 23 ETM12E-01 13.2.4. Diagram of fixed-cy cle timer interrupt function 13.2.4.1. Operation ex ample of level interrupt mode ( TI / TP = " 0 " ) • After an interrupt event has occurred, this function operates only once.
RX − 8564 LC Page − 24 ETM12E-01 13.2.4.2. Operation ex ample of repeated interrupt mode ( TI / TP = " 1 " ) • After an interrupt event has occurred, ex ecution of the operation is automatically repeated continuously.
RX − 8564 LC Page − 25 ETM12E-01 13.3. Alarm I nt errupt Function The alarm interrupt generation function generates interrupt event s for alarm settings such as date, day , hour , and minute settings.
RX − 8564 LC Page − 26 ETM12E-01 13.3.2. Alarm interrupt function registers Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 Control 2 0 × 0 TI / TP AF TF AIE TIE 03 Minute.
RX − 8564 LC Page − 27 ETM12E-01 3) AIE bit ( Alarm Interrupt Enable ) This bit is used to control interrupt signal output from the /INT pin when an alarm interrupt event has occurred. W riting "1" to this bit causes a low- level interrupt signal to be output from the /INT pin w hen an interrupt event occurs.
RX − 8564 LC Page − 28 ETM12E-01 13.4. /I NT "L" Interrupt O ut put W hen Interrupt Funct ion O per at es 1) Setting interrupt events to occur in response to /IN T "L" interrup.
RX − 8564 LC Page − 29 ETM12E-01 13.5. Flow Charts • The flow chart s shown below are intended as ex amples only . ∗ These ex amples are wr itten to be easily understood, and therefore they may not be as efficient as the actual processing.
RX − 8564 LC Page − 30 ETM12E-01 3) Example of pr ocessing to recover from back up mode ∗ 1) Ch ec k t he V L bi t (V oltage Low F l ag ). ∗ 2) W hen t he V L bi t = " 1", it m a y be d ue t o an erro r dur ing back up (clock dat a o r register se t tings may have be e n lost, due to a v oltage dr op , etc.
RX − 8564 LC Page − 31 ETM12E-01 6) Example of t imer interrupt f unction setting T o ne xt pr ocess Se t timer interrupt func tion TE ← " 0 " • Zero -clear the TE b it to stop t he timer interrupt function.
RX − 8564 LC Page − 32 ETM12E-01 13.6. Reading / W riting Data via the I 2 C Bus In terface 13.6.1. Overview of I2C-BUS The I 2 C bus supports bi-directional communications via tw o signal lines: the SDA (data) line and SCL (clock) line.
RX − 8564 LC Page − 33 ETM12E-01 13.6.3. S tarting and stopping I2C bus communications SCL ST AR T condition SDA 1 s ( M ax . ) Repeated ST ART(R EST ART) condition STOP condition [ S ] [ Sr ] [ P.
RX − 8564 LC Page − 34 ETM12E-01 13.6.4. Data transfers and acknow ledge responses during I2C-BUS communications 1) Data transfers Data transfers are performed in 8-bit (1 byte) units once the STAR T condition has occurred. There is no limit on the amount (bytes) of data that are transferred betw een the START condition and STOP condition.
RX − 8564 LC Page − 35 ETM12E-01 13.6.6. I 2 C bus protocol In the following sequence descriptions, it is assumed that the CPU is the master and the [ 8564 ] is the slave.
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