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NS9215 Hardware Reference 90000847_C R elease date: 10 April 2008.
©2008 Digi International Inc. P rinted in the United States of America. All rights reserved. Digi, Digi International, the Digi logo, a Digi Inte rnational Company , Connec tCore, NET+, NET+O S an d NET+W orks are trademarks or registered trademarks of Digi International, Inc.
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5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 1: Pinout (265) ..................................................... 2 7 The Legend .........
6 Hardware Reference NS9215 GPIO Configuration Register #15 ......... ..................................... ....... 63 GPIO Configuration Register #16 ......... ..................................... ....... 64 GPIO Configuration Register #17 .........
. . . . . www .digiembedded.com 7 ICache and DCache beha vior .................. ..................................... ... 90 R2: Translation Table Base register ......................... ................................ 91 Register format ...........
8 Hardware Reference NS9215 Access instructions ........................................ ............................ 103 Register format ............................. ..................................... ......103 Performing a fast context switch ..
. . . . . www .digiembedded.com 9 MMU faults and CPU aborts ................................................. ................ 119 Alignment fault checking ........ ............................. ....................... 119 Fault Address and Fault Status registers .
10 Hardware Reference NS9215 High speed bus system ............................. ....... ....... ........ ....... ...... 138 High-speed bus arbiters ............................ ................................... 138 How the bus arbiter works .......
. . . . . www .digiembedded.com 11 AHB Error Detect Status 2 .............. ............................. ....................... 160 AHB Error Monitoring Configur ation register ..................... ....................... 161 Timer Master Control register .
12 Hardware Reference NS9215 Low-power SDRAM partial array refresh ..................................... ......204 Memory map .......................... .................................... ..................... 205 Power-on reset memory map .........
. . . . . www .digiembedded.com 13 222 Memory banks constructed from 16- or 32-bit memory devices ................ 223 Dynamic memory controller ................... ..................................... ........ 225 Write protection .......... .......
14 Hardware Reference NS9215 Static Memory Write Delay 0–3 registers ...................... ............................ 257 StaticMemory Turn Round Dela y 0–3 registers ............... ............................ 258 Chapter 6: Ethernet Communication Module .
. . . . . www .digiembedded.com 15 Writing to other registers ............... ..................................... ........ 276 Ethernet Control and Status registers .............. ..................................... . 2 77 Register address filter .
16 Hardware Reference NS9215 Transmit statistics counters address map ............................ ............. 307 Transmit byte counter (A060 06E0 ) ................................................. 307 Transmit packet counter (A060 06E4) .........
. . . . . www .digiembedded.com 17 Multicast Low Address Filter Register #6 ......................................... . 3 28 Multicast Low Address Filter Register #7 ......................................... . 3 28 Multicast High Address Filter Register #0 .
18 Hardware Reference NS9215 Buffer length ... ....... ........ ....... ....... ........ ....... ....... ........ ....... ...... 340 Destination address [pointer] ...... ....... ........ ....... ....... ........ ....... ...... 340 Status .............
. . . . . www .digiembedded.com 19 Last (L) bit ....................................... ..................................... . 3 58 Full (F) bit ........... ............................. ..................................... . 3 58 Decryption .......
20 Hardware Reference NS9215 [Module] DMA RX Contro l ........... .................................... ..................... 375 [Module] DMA RX Buffer Descri ptor Pointer ........... ............................. ......376 [Module] RX Interrupt Configuration register .
. . . . . www .digiembedded.com 21 UART FIFO Control register ............. ............................. ....................... 409 UART Line Control register ................................... .............................. 409 UART Modem Control register .
22 Hardware Reference NS9215 SPI module structure . .............................. ................................... 434 SPI controller .......... ..................................... ............................. ......434 Simple parallel/serial data conversion .
. . . . . www .digiembedded.com 23 Register bit assignment .. ..................................... ....................... 451 Master Address register ........................ ....... ........ ....... ....... ........ ....... . 452 Register ...... ..
24 Hardware Reference NS9215 ADC Configuration register ....................... ........ ....... ....... ........ ............. 475 ADC Clock Configuration register . .................................... ..................... 477 ADC Output Registers 0-7 .
. . . . . www .digiembedded.com 25 Clock timing ............... ....... ........ ....... ....... ........ ....... ....... ........ ....... . 511 System PLL reference clock timing................... .............................. 511 Chapter 17: Packaging .
26 Hardware Reference NS9215.
27 Pinout (265) CHAPTER 1 T he NS9215 offers a connection to a 10/100 Ethernet network, as well as a glueless connection to SDRAM, PC 100 DI MM, flash, EEPROM, and SRAM memories, and an external bus expansion module.
PINOUT (265) Memory bus interface 28 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . PINOUT (265) Memory bus interface www .digiembedded.com 29 M1 addr[0] U I/O 4 Address bus, PLL NR[0] L1 data[31] U I/O 4 Data bus K2 data[30] U I/O 4 Data bus K1 data[29] U I/O 4 Data bus J1.
PINOUT (265) Ethernet interface MAC 30 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . PINOUT (265) General purpose I/O (GPIO) www .digiembedded.com 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PINOUT (265) General purpose I/O (GPIO) 32 Hardware Reference NS9215 Note: All GPIOs except 12 and 16 to 31 are rese t to mode 3, input. GPIO 12 is reset to mode 2, reset_done.
. . . . . PINOUT (265) General purpose I/O (GPIO) www .digiembedded.com 33 G17 gpio[8] U I/O 2 0 DCD / TX C UART C 1 Ext DMA Done Ch 1 2 Ext Time r Event Out Ch 8 3 gpio[8] 4 SPI EN (dup) G15 gpio[9] .
PINOUT (265) General purpose I/O (GPIO) 34 Hardware Reference NS9215 D3 gpio[16] U I/O 4 0 data[0] 1 DCD UART B 2 Ext Int Ch 0 (dup) 3 gpio[16] B2 gpio[17] U I/O 4 0 data[1] 1C T S U A R T B 2 Ext Int.
. . . . . PINOUT (265) General purpose I/O (GPIO) www .digiembedded.com 35 F4 gpio[26] U I/O 4 0 data[10] 1D S R U A R T D 2 PIC_1_GEN_IO[0](I/O) 3 gpio[26] F3 gpio[27] U I/O 4 0 data[11] 1R X D U A R.
PINOUT (265) General purpose I/O (GPIO) 36 Hardware Reference NS9215 D17 gpio[36] U I/O 2 0 Ethernet MII RX DV 1 PIC_0_GEN_IO[4](I/O)(dup) 2 Reserve d 3 gpio[36] C17 gpio[37] U I/O 2 0 Ethernet MII R .
. . . . . PINOUT (265) General purpose I/O (GPIO) www .digiembedded.com 37 D12 gpio[46] U I/O 2 0 Ethernet M II TXD[2] 1 PIC_1_GEN_IO[6](I/O)(dup) 2 Reserved 3 gpio[46] A16 gpio[47] U I/O 2 0 Ethernet.
PINOUT (265) General purpose I/O (GPIO) 38 Hardware Reference NS9215 J4 gpio [56] U I/O 2 0 RTS/RS485 Control UART B (dup) 1 PIC_0_BUS_1[13](I/O) 2 PIC_1_BUS_1[13](I/O) 3 gpio[56] K3 gpio[ 57] U I /O .
. . . . . PINOUT (265) General purpose I/O (GPIO) www .digiembedded.com 39 N8 gpi o[66] U I/O 2 0 TXD UART D (dup) 1 PIC_0_BUS_1[23](I/O) 2 PIC_1_BUS_1[23](I/O) 3 gpio[66] P9 gpio[67] U I/O 2 0 PIC_0 .
PINOUT (265) General purpose I/O (GPIO) 40 Hardware Reference NS9215 T15 gpio [76] U I/O 2 0 PIC_0_CTL_IO[0](I/O) 1 PIC_1_CTL_IO[0](I/O) 2 Ext Timer Event in Ch 2 3 gpio[76] T16 gpio [77] U I/O 2 0 PIC_0_CTL_IO[1](I/O) 1 PIC_1_CTL_IO[1](I/O) 2 Ext Timer Event in Ch 3 3 gpio[77] R14 gp io[78] U I.
. . . . . PINOUT (265) General purpose I/O (GPIO) www .digiembedded.com 41 K13 g pio[ 86] U I/ O 2 0 PIC_0_BUS_0[6 ](I/O) 1 PIC_1_BUS_0[6](I/O) 2 Ext Time r Event Out Ch 2 3 gpio[86] K16 g pio[ 87] U .
PINOUT (265) General purpose I/O (GPIO) 42 Hardware Reference NS9215 C16 gp io[96] U I/O 2 0 PIC_0_BUS_1[0](I/O) 1 PIC_1_BUS_1[0](I/O) 2 PIC_0_CAN_RXD(I)(dup) 3 gpio[96] B16 gp io[97] U I/O 2 0 PIC_0_.
. . . . . PINOUT (265) System clock www .digiembedded.com 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PINOUT (265) System clock 44 Hardware Reference NS9215 System clock drawing.
. . . . . PINOUT (265) System mode www .digiembedded.com 45 R TC clock and battery backup drawing Note: If R TC battery backup is not used, th e following connection changes c an be made. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PINOUT (265) System mode 46 Hardware Reference NS9215 sys_mode_2 sys_mode_1 sys_mode_0 Description 0 0 0 manufacturing test 0 0 1 manufacturing test 0 1 0 manufacturing test 0 1 1 normal operation, bo.
. . . . . PINOUT (265) System r eset www .digiembedded.com 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PINOUT (265) JT AG T est 48 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . PINOUT (265) ADC www .digiembedded.com 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PINOUT (265) POR and battery-backed logic 50 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POR and battery-backed logic The POR will generate keep reset_out_n low between 75ms and 300ms after 3.
. . . . . PINOUT (265) Power and gr ound www .digiembedded.com 51 If the R TC feature is not used, the inputs must be terminated as shown below . If the R TC feature is used, see RTC cloc k and battery backup drawing on page 45. . . . . . . . . . . . .
PINOUT (265) Power and gr ound 52 Hardware Reference NS9215.
53 I/O Control Module CHAPTER 2 T he NS9215 ASIC contains 1 08 pins that are designated as general purpose I/O (GPIO). The first 16 GPIO can be configured to serve one of five functions. The remaining GPIO can be conf igured to serve one of four functions.
I/O CONTROL MODULE Contr ol and Sta tus registers 54 Hardware Reference NS9215 A090_200C GPIO Configuration Register #3 R/W 0x18181810 A090_2010 GPIO Configuration Register #4 R/W 0x00000000 A090_2014.
. . . . . I/O CONTROL MODULE GPIO Configuration r egisters www .digiembedded.com 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O CONTROL MODULE GPIO Configuration r egisters 56 Hardware Reference NS9215 GPIO Configuration Registe r #0 Address: A090_2000 GPIO Configuration Registe r #1 Address: A090_2004 1 3 1 2 1 1 1 0 9876.
. . . . . I/O CONTROL MODULE GPIO Configuration r egisters www .digiembedded.com 57 GPIO Configuration Register #2 Address: A090_2008 GPIO Configuration Register #3 Address: A090_200C 1 3 1 2 1 1 1 0 .
I/O CONTROL MODULE GPIO Configuration r egisters 58 Hardware Reference NS9215 GPIO Configuration Registe r #4 Address: A090_2010 GPIO Configuration Registe r #5 Address: A090_2014 1 3 1 2 1 1 1 0 9876.
. . . . . I/O CONTROL MODULE GPIO Configuration r egisters www .digiembedded.com 59 GPIO Configuration Register #6 Address: A090_2018 GPIO Configuration Register #7 Address: A090_201C 1 3 1 2 1 1 1 0 .
I/O CONTROL MODULE GPIO Configuration r egisters 60 Hardware Reference NS9215 GPIO Configuration Registe r #8 Address: A090_2020 GPIO Configuration Registe r #9 Address: A090_2024 1 3 1 2 1 1 1 0 9876.
. . . . . I/O CONTROL MODULE GPIO Configuration r egisters www .digiembedded.com 61 GPIO Configuration Register #10 Address: A090_2028 GPIO Configuration Register #1 1 Address: A090_202C 1 3 1 2 1 1 1.
I/O CONTROL MODULE GPIO Configuration r egisters 62 Hardware Reference NS9215 GPIO Configuration Registe r #12 Address: A090_2030 GPIO Configuration Registe r #13 Address: A090_2034 1 3 1 2 1 1 1 0 98.
. . . . . I/O CONTROL MODULE GPIO Configuration r egisters www .digiembedded.com 63 GPIO Configuration Register #14 Address: A090_2038 GPIO Configuration Register #15 Address: A090_203C 1 3 1 2 1 1 1 .
I/O CONTROL MODULE GPIO Configuration r egisters 64 Hardware Reference NS9215 GPIO Configuration Registe r #16 Address: A090_2040 GPIO Configuration Registe r #17 Address: A090_2044 1 3 1 2 1 1 1 0 98.
. . . . . I/O CONTROL MODULE GPIO Configuration r egisters www .digiembedded.com 65 GPIO Configuration Register #18 Address: A090_2048 GPIO Configuration Register #19 Address: A090_204C 1 3 1 2 1 1 1 .
I/O CONTROL MODULE GPIO Configuration r egisters 66 Hardware Reference NS9215 GPIO Configuration Registe r #20 Address: A090_2050 GPIO Configuration Registe r #21 Address: A090_2054 1 3 1 2 1 1 1 0 98.
. . . . . I/O CONTROL MODULE GPIO Configuration r egisters www .digiembedded.com 67 GPIO Configuration Register #22 Address: A090_2058 GPIO Configuration Register #23 Address: A090_205C 1 3 1 2 1 1 1 .
I/O CONTROL MODULE GPIO Configuration r egisters 68 Hardware Reference NS9215 GPIO Configuration Registe r #24 Address: A090_2060 GPIO Configuration Registe r #25 Address : A090_2064 1 3 1 2 1 1 1 0 9.
. . . . . I/O CONTROL MODULE GPIO Configuration r egisters www .digiembedded.com 69 GPIO Configuration Register #26 Address: A090_2068 1 3 1 2 1 1 1 0 9876543210 15 14 31 29 28 27 26 25 24 23 22 21 20.
I/O CONTROL MODULE GPIO Contr ol re gisters 70 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . I/O CONTROL MODULE GPIO Contr ol r egisters www .digiembedded.com 71 GPIO Control Register #1 Address: A090_2070 D25 R/W GPIO25 0 GPIO[25] con trol bit D26 R/W GPIO26 0 GPIO[26] con trol bit.
I/O CONTROL MODULE GPIO Contr ol re gisters 72 Hardware Reference NS9215 GPIO Control Registe r #2 Address: A090_2074 D22 R/W GPIO54 0 GPIO[54] control bit D23 R/W GPIO55 0 GPIO[55] control bit D24 R/.
. . . . . I/O CONTROL MODULE GPIO Contr ol r egisters www .digiembedded.com 73 GPIO Control Register #3 Address: A090_2078 D19 R/W GPIO83 0 GPIO[83] con trol bit D20 R/W GPIO84 0 GPIO[84] con trol bit.
I/O CONTROL MODULE GPIO S tatus registers 74 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . I/O CONTROL MODULE GPIO S tatus r egisters www .digiembedded.com 75 GPIO S tatus Register #2 Address: A090_2084 D26 R GPIO58 Undefined GPIO[58] status bit D27 R GPIO59 Undefined GPIO[59] sta.
I/O CONTROL MODULE Memory Bus Configuration r egister 76 Hardware Reference NS9215 GPIO S tatus Registe r #3 Address: A090_2088 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . I/O CONTROL MODULE Memory Bus Confi guration r egister www .digiembedded.com 77 Bit(s) Access Mnemonic Reset Description D02:00 R/W CS0 0x4 Controls which system memory chip select is routed.
I/O CONTROL MODULE Memory Bus Configuration r egister 78 Hardware Reference NS9215 D14:12 R/W CS4 0x6 Controls which sy stem memory chip select is routed to CS4 000 dy_cs_0 001 dy_cs_1 010 dy_cs_2 011.
. . . . . I/O CONTROL MODULE Memory Bus Confi guration r egister www .digiembedded.com 79 D25 R/W APUDIS 0x0 Address bus pullup control (Applicable only to ad dress associated with hardware strapping).
I/O CONTROL MODULE Memory Bus Configuration r egister 80 Hardware Reference NS9215.
81 W orking with the CPU CHAPTER 3 T his processor core is based on the ARM926EJ-S proces sor . The ARM926EJ-S processor belongs to the ARM9 family of general-purpose microprocessors. The ARM926EJ- S processo r is tar geted at mult i- tasking applications in which full memory management, high performance, low di e size, and low power are important.
W ORKING WITH THE CPU Instruction sets 82 Hardware Reference NS9215 Arm926EJ-S process block diagram This drawing shows the ma in bloc ks in the ARM926EJ-S processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . W O RKING WITH THE CPU System contr ol pr oce ssor (CP15) r egisters www .digiembedded.com 83 Java inst ruction set In Java state, the processor core executes a majority of Java bytecodes naturally . Bytecodes are decoded in two states, compar ed to a single deco de stage when in ARM/Thumb mode.
W ORKING WITH THE CPU System contr ol pro cessor (CP15) r egisters 84 Hardware Reference NS9215 Figure 1: CP15 MRC and MCR bit pattern The mnemonics for these instructions are: MCR{cond} p15,opcode _1.
. . . . . W O RKING WITH THE CPU System contr ol pr oce ssor (CP15) r egisters www .digiembedded.com 85 Note: In all cases, reading from or writing any data values to any CP15 registers, including those fields specified as UNPREDICT ABLE, SHOULD BE ONE, or SHOULD BE ZERO, does not cause any physic al damage to the chip.
W ORKING WITH THE CPU R0: ID code and cache type status registers 86 Hardware Reference NS9215 The B bit is set to 0 at reset if the BIGENDINIT signal is low , and set to 1 if the BIGENDINIT signal is high. . . . . . . . . . . . . . . . . . . . . .
. . . . . W O RKING WITH THE CPU R0: ID code and cache type status registers www .digiembedded.com 87 Y ou can access the cache type register by reading CP15 register R0 with the opcode_2 field set to 1.
W ORKING WITH THE CPU R1: Contr ol r egister 88 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . R1: Control register R egister R1 is the control register for the ARM926 EJ-S processor .
. . . . . W O RKING WITH THE CPU R1: Contr ol r egister www .digiembedded.com 89 Control r egister Bit functionality 1 31 19 16 15 12 11 1 0 9 8 7 3 0 2 18 17 1 4 13 6 S B Z SBZ S B O S B O L 4 R R VI SBZ RS B SBO CA M Bits Name Function [31:19] N/A Reserved: When read, returns an UNPREDICT ABLE value.
W ORKING WITH THE CPU R1: Contr ol r egister 90 Hardware Reference NS9215 ICache and DCache behavior The M, C, I, and RR bits directly affect ICache and DCache behavior , as shown: If either the DCache or ICache is disab led, the contents of that cache are not accessed.
. . . . . W O RKING WITH THE CPU R2: T ranslation T able Base r egister www .digiembedded.com 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W ORKING WITH THE CPU R4 r egister 92 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . R4 register Accessing (reading or writing) this register causes UN PREDICT ABLE behavior .
. . . . . W O RKING WITH THE CPU R6: Fault Addr ess r egister www .digiembedded.com 93 S tat us and domain fields This table shows th e en codings used for the status field i n the Fault Sta tus register , and indicates whethe r the domain field contains val id information.
W ORKING WITH THE CPU R7:Cache Operations r egister 94 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . R7:Cache Operations register R egister R7 controls the cache s and write buffer .
. . . . . W O RKING WITH THE CPU R7:Cache Operations r egister www .digiembedded.com 95 Cache oper ation functions This table lists the cache operation functi ons and associated data and instruction formats for R7. Drain write buffer Act s as an explicit me mory barrier.
W ORKING WITH THE CPU R7:Cache Operations r egister 96 Hardware Reference NS9215 Modified vi rtual address format (MV A) This is the modified virtual addr ess format for Rd for the CP15 R7 MCR operations. The tag, set, and word fields de fin e th e MV A.
. . . . . W O RKING WITH THE CPU R8:TLB Operations r egister www .digiembedded.com 97 Note: The test and clean DCache instruction MRC p15, 0, r15, c7, c10, 3 is a special encoding that uses r15 as a destination operand. The PC is not changed by using this instruction, however .
W ORKING WITH THE CPU R9: Cache Lockdown r egister 98 Hardware Reference NS9215 The invalidate TLB operation s invalidate all the unpreserved entries in the TLB. The invalidate TLB sing le entry operations invalidate any TLB entry corresponding to the modified virtual address given in Rd , regardless of its preserved state.
. . . . . W O RKING WITH THE CPU R9: Cache Lockdown r egister www .digiembedded.com 99 Instruction or data lockdown reg i s t er The first four bits of this register determ ine the L bit for the associated cache way .
W ORKING WITH THE CPU R9: Cache Lockdown r egister 100 Hardware Reference NS9215 Lockdow n cache: Specific loading of addresses into a cache-way Use this procedure to lockdown cache.
. . . . . W O RKING WITH THE CPU R10:TLB Lockdown r egister www .digiembedded.com 101 8 Wr i t e <C Rm>==0 to Cache Lockdown register (R9), setting L==1 for bit i and restoring all other bits to the values they had be fore the lockdown routine was started.
W ORKING WITH THE CPU R1 1 and R12 r egisters 102 Hardware Reference NS9215 Programming instructio ns Use these instructions to prog ram the TLB Lockdown register: The victim automatically increments after any table walk that results in an entry being written into the lo ckdown part of the TLB.
. . . . . W O RKING WITH THE CPU R13:Pr ocess ID r egister www .digiembedded.com 103 Use the P rocess ID regist er to det ermine th e process that is currently running.
W ORKING WITH THE CPU R14 r egister 104 Hardware Reference NS9215 A1, A2, and A3 are the three instructio ns following the fast context switch . Context ID reg is te r The Context ID register provides a mechan ism that allows real-time trace tools to identify the cu rrently execut ing proc ess in multi -tasking environments.
. . . . . W O RKING WITH THE CPU DSP www .digiembedded.com 105 Software emulation within the ARM- optimized JVM, which addresses the remaining 20% of the Java byte codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W ORKING WITH THE CPU MemoryManagement Unit (MMU) 106 Hardware Reference NS9215 Invalidate entire TLB using R8: TLB Operations register (see “R8:TLB Operations register” on page 97). Invalidate TLB ent r y sel ec t ed by MV A, using R8: TLB Operations register (see “R8:TLB Operations register” on page 97).
. . . . . W O RKING WITH THE CPU MemoryManagement Unit (MMU) www .digiembedded.com 107 MMU program accessible registers This table shows the CP15 registers that are used in conjunction with page table descriptors stored in memory to determine MMU operation.
W ORKING WITH THE CPU MemoryManagement Unit (MMU) 108 Hardware Reference NS9215 The MMU table-walking hardware adds entries to the TLB. The translation information that comprises both the ad dress translation data and the access permission data resides in a tra nslation table located in ph ys ical memory .
. . . . . W O RKING WITH THE CPU MemoryManagement Unit (MMU) www .digiembedded.com 109 Ta b l e w a l k process First-level fetch Bits [31:14] of the TTB register are concat enated with bits [31:20] of the MV A to produce a 30-bit address.
W ORKING WITH THE CPU MemoryManagement Unit (MMU) 11 0 Hardware Refere nce NS9215 First-level fetch concatenation and address This address selects a 4-byte translation tabl e entry .
. . . . . W O RKING WITH THE CPU MemoryManagement Unit (MMU) www .digiembedded.com 111 First-level descriptor bit assignments: Priority encoding of fault status First-level descriptor bit assignments: Interpr eting first level descriptor bits [1:0] Section descriptor A section descriptor provides the base address of a 1 MB block of memory .
W ORKING WITH THE CPU MemoryManagement Unit (MMU) 11 2 Hardware Refere nce NS9215 Section descriptor bit descript ion Coarse page tabl e descriptor A coarse page table descriptor provides the base address of a page table that contains second-lev el descriptors for eith er large page or small page accesses.
. . . . . W O RKING WITH THE CPU MemoryManagement Unit (MMU) www .digiembedded.com 11 3 page tables have 1024 entries, splitting th e 1 MB that the table describes into 1 KB blocks. The next two sections show the format of a fine pa ge table descript or and define the fine page table descriptor bit assignments.
W ORKING WITH THE CPU MemoryManagement Unit (MMU) 11 4 Hardware Refere nce NS9215 Second-level descriptor The base address of the page table to be used is determined by the descriptor returned (if any) from a first-level fetch — either a coarse page table descriptor or a fine page table descriptor .
. . . . . W O RKING WITH THE CPU MemoryManagement Unit (MMU) www .digiembedded.com 11 5 A tiny page descriptor provides the ba se address of a 1 KB block of memory . Coarse page tables provide base addresse s for either small or large pages. Large page descriptors must be repe ated in 16 consecutive entri es.
W ORKING WITH THE CPU MemoryManagement Unit (MMU) 11 6 Hardware Refere nce NS9215 Tr a n s l a t i o n sequence for large pa ge re fere nce s Because the upper four b its of the page in dex and low-or.
. . . . . W O RKING WITH THE CPU MemoryManagement Unit (MMU) www .digiembedded.com 11 7 T ranslating sequence for small page refer ences If a small page descriptor is included in a fine page table, the up per two bits of the page index and low-order two bits of the fi ne page table index overlap .
W ORKING WITH THE CPU MemoryManagement Unit (MMU) 11 8 Hardware Refere nce NS9215 Tr a n s l a t i o n sequence for tiny pa ge re fere nce s P age translation involves one additional st ep beyond that of a section translation. The first-level d escriptor is the fine pa ge table descriptor; th is points to the first- level descriptor .
. . . . . W O RKING WITH THE CPU MMU faults and CPU aborts www .digiembedded.com 11 9 When you use subpage permissions and the page entry has to be invalida ted, you must invalidate all four subpages separately . . . . . . . . . . . . . . . . . . . . .
W ORKING WITH THE CPU MMU faults and CPU aborts 120 Hardware Reference NS9215 register . If an access violation simultaneously generates more than one source of abort, the aborts are encoded in the priority shown in the priority encoding table. The Fault Address register is not updated by faul ts caused by instruction prefetches.
. . . . . W O RKING WITH THE CPU Domain a ccess contr ol www .digiembedded.com 121 Compatibility issues T o enable code to be ported easily to future architectures, it is recommended that no reliance is made on external abort behavior . The Instruction Fault Status register is intended for de bugging purposes only .
W ORKING WITH THE CPU Fault checkin g sequence 122 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . W O RKING WITH THE CPU Fault checking sequence www .digiembedded.com 123 The conditions that gener ate each of the faults are di scu ssed in the following sections.
W ORKING WITH THE CPU Fault checkin g sequence 124 Hardware Reference NS9215 Note: If an access generates an alignment fa ult, the access sequen ce aborts without reference to other permission checks. T r anslation faults There are two types of translation fault: section and page.
. . . . . W O RKING WITH THE CPU External aborts www .digiembedded.com 125 interpreted in the same way as for a section (see “Interpreting access permission bits” on page 121). The only di fference is that the fa ult generated is a pag e permission fault.
W ORKING WITH THE CPU TLB stru ctur e 126 Hardware Reference NS9215 Car e mu st be tak en i f the tra nsl ated addr ess differs from the untranslated address, because several instructions followin g the enabling of the MMU mig ht have been prefetched with MMU off ( VA = M VA = P A ).
. . . . . W O RKING WITH THE CPU Caches and write buffer www .digiembedded.com 127 about the structure, replacement algorith m, or persistence of entries in the set-associative part — specifically: Any entry written into the set-asso ciat ive part of the TLB can be removed at any time.
W ORKING WITH THE CPU Caches and write buffer 128 Hardware Reference NS9215 The caches use pseudo-random or round- robin replacement, selected by the RR bit in R1: Control register .
. . . . . W O RKING WITH THE CPU Caches and write buffer www .digiembedded.com 129 ICache I and M bit settings This table gives the I and M bit settings for the ICache, and the associated behavior . ICache page table C bit settings This table shows the page table C bit setti ngs for the ICache (R1 I bit = M bit = 1) .
W ORKING WITH THE CPU Cache MV A and Set/W ay formats 130 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . W O RKING WITH THE CPU Cache MV A and Set/W ay formats www .digiembedded.com 131 Generic, virtually indexed, virtually addressed cache 0 0 1 2 3 4 5 6 7 n TAG 1 2 3 012 m m m m Hit Read data.
W ORKING WITH THE CPU Cache MV A and Set/W ay formats 132 Hardware Reference NS9215 ARM926EJ-S cache format ARM926EJ-S cache associativity The following points apply to th e AR M926EJ-S cache associativity: The group of tags of the same index defines a set.
. . . . . W O RKING WITH THE CPU Noncachable instruction fetches www .digiembedded.com 133 In this figure: A = log 2 associativity For example, with a 4-way cache A = 2: S = log 2 NSETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W ORKING WITH THE CPU Noncachable instruction fetches 134 Hardware Reference NS9215 AHB behavior If instruction prefetching is disabled, al l instruc tion fetches appear on the AHB interface as single, nonseq ue ntial fetches.
. . . . . W O RKING WITH THE CPU Noncachable instruction fetches www .digiembedded.com 135 recommended that either a nonbuffered store ( STR ) or a noncached load ( LDR ) be used to trigger external synchronization. 4 Invalidate the cache. The ICache must be invalidated to remove any stale copies of instructions that are no longer valid.
W ORKING WITH THE CPU Noncachable instruction fetches 136 Hardware Reference NS9215.
137 System Control Module CHAPTER 4 T he System Control Module config ures an d oversees system operations for the processor , and defines both the AMBA Hi gh-speed Bus (AHB) arbiter system and system memory address space.
SYSTEM CONTROL MODULE System bus arbiter 138 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE System bus arbiter www .digiembedded.com 139 2 The arbiter stops evaluating the BRR until a bus grant is issued for the previous evaluation cycle.
SYSTEM CONTROL MODULE System bus arbiter 140 Hardware Reference NS9215 If the bus is granted to a defaul t ma ster and cont inues to be in the ID LE state longer than a specified period of time, an AHB bus arbiter timeout is generated. An AH B bus arbit er time out can be config ure d to interrup t the CPU or to reset the chip.
. . . . . SYSTEM CONTROL MODULE Addr ess decoding www .digiembedded.com 141 BRC1[23:16] = 8’b1_0_00_0000 chann el disabled BRC1[15:8] = 8’b1_0_00_0000 channel disabled BRC1[7:0] = 8’b1_0_00_0000.
SYSTEM CONTROL MODULE Pr ogrammable timers 142 Hardware Reference NS9215 This table shows the hmaster[3:0] assignments for the processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE General purpose timers/counters www .digiembedded.com 143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE Basic PWM function 144 Hardware Reference NS9215 Interrupt enable Concatenate to up-stream timer/co unter; that is, use up-stream timer/counter’ s overflow/under flow o.
. . . . . SYSTEM CONTROL MODULE Enhanced PWM function www .digiembedded.com 145 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE How the quadratur e de coder/counter works 146 Hardware Reference NS9215 A quadrature decoder/counter module performs these task s at real time speed and interrupts th e CP U at th e pre de t ermin ed conditions. . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE How the quadratur e decoder/cou nter works www .digiembedded.com 147 Monitors h ow far the encoder has moved The counter keeps a running count of how far the encoder has moved. The decoder increments a 32-bit counter when a state change is found in the positive direction.
SYSTEM CONTROL MODULE Interrupt contr oller 148 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt controller The interrupt system is a simple two-tier priority scheme.
. . . . . SYSTEM CONTROL MODULE Interrupt contr oller www .digiembedded.com 149 IRQ characteristics The IRQ interrupt s are enabled by the respective enabling bits.
SYSTEM CONTROL MODULE Interrupt contr oller 150 Hardware Reference NS9215 The interrupt sources are assigned as shown: Interrupt ID Interrupt source 0 Watchdog Timer 1 AHB Bus Error 2 Ext DMA 3 CPU Wa.
. . . . . SYSTEM CONTROL MODULE V ector ed interrupt contr oller (VIC) flow www .digiembedded.com 151 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE Bootstrap initialization 152 Hardware Reference NS9215 PLL configuration and control system block diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE Bootstrap initialization www .digiembedded.com 153 Pin name Configuration bits gpio_a[3] Endian configuration 0 Little endian 1B i g e n d i a n gpio_ a[2] Boot mode 0 .
SYSTEM CONTROL MODULE System configur ation r egisters 154 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE System configur ation r egisters www .digiembedded.com 155 A090 0074 Timer 9 Read and Capture register A090 0078 Timer 6 High register A090 007C Timer 7 High register A.
SYSTEM CONTROL MODULE System configur ation r egisters 156 Hardware Reference NS9215 A090 00F8 Interrupt Vector Address Register Level 13 A090 00FC Interrupt Vector Address Register Level 14 A090 0100.
. . . . . SYSTEM CONTROL MODULE System configur ation r egisters www .digiembedded.com 157 A090 017C C lock Configuration register A090 0180 Module Reset register A090 0184 Miscellaneous Syst em Confi.
SYSTEM CONTROL MODULE General Arbiter Contr ol r egister 158 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE AHB Err or Detect S tatus 1 www .digiembedded.com 159 Channel allocation This is how the channels are a ssigned in the four registers: Register Register bit assignment This table shows the bit definition for each channel, using data bits [07:00] as the example.
SYSTEM CONTROL MODULE AHB Error Detect S tatus 2 160 Hardware Reference NS9215 The AHB Error Detect Status 1 register records the haddr[31:0] value present when any AHB error is found. Note that this value is not reset on powerup but is reset when the AHB Erro r Interrupt Clear bit is set in the AHB Error Monitoring Configuration register (*).
. . . . . SYSTEM CONTROL MODULE AHB Err or Monitoring C onfiguration r egister www .digiembedded.com 161 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE T imer Master Control r egister 162 Hardware Reference NS9215 Registe r Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE T imer Master Contr ol r egister www .digiembedded.com 163 Register bit assignment Bits Access Mnemonic Reset Description D31:22 N/A Reserved N/A N/A D21 R/W T9RSE 0x0 .
SYSTEM CONTROL MODULE T imer 0–4 Contr ol re gisters 164 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE T imer 0–4 Control r egisters www .digiembedded.com 165 Register Register bit assignment 1 3 1 2 1 1 1 0 98765432 15 14 31 29 28 27 26 25 24 23 22 21 20 19 1 8 30 TCS.
SYSTEM CONTROL MODULE T imer 5 Control r egister 166 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE T imer 5 Control r egister www .digiembedded.com 167 Register bit assignment Bits Access Mnemonic Reset Description D31:19 N/A Reserved N/A N/A D18 R/W Rel mode 0x0 Reload mode Initializes the timer and the reload value at terminal count.
SYSTEM CONTROL MODULE T imer 6–9 Contr ol re gisters 168 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE T imer 6–9 Control r egisters www .digiembedded.com 169 Register Register bit assignment 1 3 1 2 1 1 1 0 9876543210 15 14 31 2 9 28 27 26 25 24 23 22 21 20 19 18 17 1.
SYSTEM CONTROL MODULE T imer 6–9 High r egisters 170 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE T imer 6–9 Low r egisters www .digiembedded.com 171 Register Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE T imer 6–9 High and Low S tep r e gisters 172 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE T imer 0-9 Reload Count and Compar e register www .digiembedded.com 173 Register Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE T imer 0-9 Read and Captur e r egister 174 Hardware Reference NS9215 Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE Interrupt V ector Addr ess Register Level 31–0 www .digiembedded.com 175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE ISADDR r egister 176 Hardware Reference NS9215 Registe r bit assignment This is how the bits are assigned in each register , using data bits [07:00] as the example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE Interrupt S tatus Active www .digiembedded.com 177 Register Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE Interrupt S tatus Raw 178 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE Softwar e W atchdog T i mer www .digiembedded.com 179 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE Clock Configuration r e gister 180 Hardware Reference NS9215 Registe r Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE Clock Configur ation r e gister www .digiembedded.com 181 Register bit assignment Bits Access Mnemonic Reset Description D31:29 R/W CSC 0x000 Clock scale control 000 Full speed (149.9136/74.9568) 001 Divide by 2 (74.9568/37.
SYSTEM CONTROL MODULE Module Reset register 182 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE Module Reset r egister www .digiembedded.com 183 The Module R e set register resets each module on the AHB bus. Register Register bit assignment 13 12 11 10 9 8 7 6 5 4.
SYSTEM CONTROL MODULE Miscellaneous System Configuration and S tatus r egister 184 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE Miscellaneous System Confi guration and S tatus r egister www .digiembedded.com 185 Register bit assignment Bits Access Mnemonic Reset Description D31:24 R REV 0x0 Revision Indicates the hardware iden tification and revision of the processor chip.
SYSTEM CONTROL MODULE PLL Configuration r egister 186 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Configuration register Address: A090 0188 The PLL Configuration regist er configures the PLL.
. . . . . SYSTEM CONTROL MODULE Active Interrupt Leve l ID S tatus r egister www .digiembedded.com 187 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE Power Management 188 Hardware Reference NS9215 Registe r bit assignment Bits Access Mnemonic Reset Description D31 R/W Slp en 0x0 Deprecated Chip sl eep enable This control bit is provided for backwards compatibility with softwa re written for the NS9750 and NS9360 processors, and should not be used by new software.
. . . . . SYSTEM CONTROL MODULE Power Management www .digiembedded.com 189 D20 R/W WakeIntClr 0x0 CPU wake interrupt clear Write a 1, followed by a 0 to clear the CPU wake interrupt.
SYSTEM CONTROL MODULE AHB Bus Activit y Status 190 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE System Memory Chip Select 1 Dyna mic Memory Base and Mask registers www .digiembedded.com 191 These control registers set the base and mask for system memory chip select 0, with a minimum size of 4 K. The powerup default settings produce a memory ran ge of 0x0000 0000 — 0x0FFF FFFF .
SYSTEM CONTROL MODULE System Memory Chip Sele ct 2 Dynamic Memory Ba se and Mask registers 192 Hardware Reference NS9215 Registe rs Registe r bit assignment System Memory Chip Select 2 Dynamic Memory Base and . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE System Memory Chip Select 3 Dyna mic Memory Base and Mask r egisters www .digiembedded.com 193 Registers Register bit assignment System Memory Chip Select 3 Dynamic Memory Base and . . . . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE System Memory Chip Se lect 0 S tatic Memory Base and Mask registers 194 Hardware Reference NS9215 Registe rs Registe r bit assignment System Memory Chip Select 0 Static Memory Base and Mask . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE System Memory Chip Select 1 S tat ic Memo ry Base and Mask r egisters www .digiembedded.com 195 Registers Register bit assignment System Memory Chip Select 1 Static Memory Base and Mask . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE System Memory Chip Se lect 2 S tatic Memory Base and Mask registers 196 Hardware Reference NS9215 Registe rs Registe r bit assignment System Memory Chip Select 2 Static Memory Base and Mask . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE System Memory Chip Select 3 S tat ic Memo ry Base and Mask r egisters www .digiembedded.com 197 Registers Register bit assignment System Memory Chip Select 3 Static Memory Base and Mask . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE Gen ID register 198 Hardware Reference NS9215 Registe rs Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE External Interrupt 0–3 Contr ol r egister www .digiembedded.com 199 Register Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM CONTROL MODULE RTC Module Contr ol re gister 200 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SYSTEM CONTROL MODULE RTC Module Contr ol register www .digiembedded.com 201 D03 R Rdy int 0x0 RTC clock ready interrupt status 0 RTC clock ready interrupt not asserted 1 RTC clock ready interrupt asserted Note: The R TC clock ready and R TC module interrupts are ORed together to the int er- rupt controller .
SYSTEM CONTROL MODULE RTC Module Contr ol re gister 202 Hardware Reference NS9215.
203 Memory Controller CHAPTER 5 T he Multiport Memory Controller is an AMBA-compliant system-on-chip (SoC) peripheral that connects t o the Adva nced High-performance Bus (AHB). The remainder of this chapter refe rs to this controller as the memory controller .
MEMORY CONTROLLER Low-power operation 204 Hardware Reference NS9215 P o wer- saving modes that dynamically control SDRAM clk_en . Dynamic memory self-refresh mode su pported by a power management unit (PMU) interface or by software.
. . . . . MEMORY CONTROLLER Memory map www .digiembedded.com 205 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory map The memory controller provides hardware support for booting from external nonvolatile memory .
MEMORY CONTROLLER Memory map 206 Hardware Reference NS9215 2 When the power-on reset ( reset_n ) goes inactive, the processor starts booting from 0x00000000 in memory . 3 The software programs the optimum delay values in the flash memory so the boot code can run at full spee d.
. . . . . MEMORY CONTROLLER S tatic memory contr oller www .digiembedded.com 207 2 When the power-on reset ( reset_n ) goes inactive, the processor starts booting from 0x00000000 in memory . 3 The software programs the optimum delay values in fl ash memory so the boot code can run at f ull speed.
MEMORY CONTROLLER S tatic memory controller 208 Hardware Reference NS9215 Notes: Buffering enables th e transaction order to be rearranged to improve memory performance. If the transaction order is important, the buffers must be disabled. Extended wait an d page mode cannot be en abled at the same t ime.
. . . . . MEMORY CONTROLLER S tatic memory initialization www .digiembedded.com 209 time critical services, such a s interru pt latency and low latency devices; for example, video controllers. Memory mapped peripherals Some systems use external peripherals that can be accessed using the static memory interface.
MEMORY CONTROLLER S tatic memory read contr ol 210 Hardware Reference NS9215 “Static Memory Ext ended W ait register” on page 247 (StaticExtende dW ait) The number of cy cl es in which an AMBA.
. . . . . MEMORY CONTROLLER S tatic memory read: T iming and parameters www .digiembedded.com 21 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY CONTROLLER S tatic memory read : T iming and parameters 212 Hardware Reference NS9215 External memory read transfer with two output enable delay states This diagram shows an external memory read transfer with two output enable delay states ( WA I T O E N = 2 ).
. . . . . MEMORY CONTROLLER S tatic memory read: T iming and parameters www .digiembedded.com 213 Burst of zer o wait states with fixed length This diagram shows a burst of zero wait state reads with the length specified.
MEMORY CONTROLLER Asynchr onous page mode r ead 214 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . MEMORY CONTROLLER Asynchr onous page mode r e ad: T iming and parameters www .digiembedded.com 215 External memory 32-bit burst read from 8-bit memory This diagram shows a 32-bit read from an 8-bit page mode ROM device, causing four burst reads to be performed.
MEMORY CONTROLLER St a t i c m e m o r y write control 216 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . MEMORY CONTROLLER S tatic memory W rite: T iming and parameters www .digiembedded.com 217 External memory write transfer with two wait states This diagram shows a single external memo ry write transfer with two wait states ( WA I T W R = 2 ).
MEMORY CONTROLLER S tatic memory W rite: T iming and parameters 218 Hardware Reference NS9215 T wo external memory write transfers with zero wait states This diagram shows two external memory write transfers with zero wait states ( WA I T W R = 0 ).
. . . . . MEMORY CONTROLLER Bus turnar ound www .digiembedded.com 219 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY CONTROLLER Bus turnar ound: T iming and parameters 220 Hardware Reference NS9215 Write fo llowed by a rea d with no turnaround This diagram shows a zero wait write foll owed by a zero wait read with default turnaround betwee n the transfers of one cycle.
. . . . . MEMORY CONTROLLER Byte lane contr ol www .digiembedded.com 221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY CONTROLLER Addr ess connectivity 222 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . MEMORY CONTROLLER Addr ess connectivity www .digiembedded.com 223 Memory banks constructed from 16-or 32-bit memory devices For memory banks constructed from 16- or 32-bit memory device s, it is important that the byte lane sele ct (PB) bit is se t to 1 within the respective memory bank control register .
MEMORY CONTROLLER Addr ess connectivity 224 Hardware Reference NS9215 datat[ 31:0] data[31 :0] data[3 1:16] data[15:0] data[3 1:24] data[2 3:16] data[15:8] data[7:0] Q[31:0] 2Mx32 ROM 64Kx16 SRAM 128K.
. . . . . MEMORY CONTROLLER Dynamic memory controller www .digiembedded.com 225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY CONTROLLER SDRAM Initialization 226 Hardware Reference NS9215 10 Set the SDRAMInit value in the Dynamic Control register to 01 — Issue SDRAM Mode command. 11 P rogram the SDRAM memory 10-bit mode register . Th e mode register enables these parameters to be programmed: A read transaction from the SDRAM me mory programs the mode register .
. . . . . MEMORY CONTROLLER SDRAM Initialization www .digiembedded.com 227 Left-shift value table: 32-bit wide data bus SDRAM (BRC) Left-shift value table: 16-bit wide data bus SDRAM (RBC) 256M 1 x 8 .
MEMORY CONTROLLER SDRAM addr ess and data bus interconnect 228 Hardware Reference NS9215 Left-shift value table: 16-bit wide data bus SDRAM (BRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . MEMORY CONTROLLER SDRAM addr ess and data bus interconnect www .digiembedded.com 229 32-bit wide configuration addr[14] A12* A12 A12 addr[15] addr[16] addr[17] addr[18] addr[19] addr[20] add.
MEMORY CONTROLLER Registers 230 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers Registe r map All configuration registers must be access ed as 32-bit words and as single accesses only .
. . . . . MEMORY CONTROLLER Registers www .digiembedded.com 231 A070 0044 DynamictWR Dynamic Memory Write Recovery Time (t WR , t DPL , t RWL , t RDL ) A070 0048 DynamictRC Dynamic Memory Active to Ac.
MEMORY CONTROLLER Contr ol register 232 Hardware Reference NS9215 Reset values R eset values will be n oted in the description column of each regis ter table, rather than as a separate column. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . MEMORY CONTROLLER Contr ol r egister www .digiembedded.com 233 Register bit assignment Bits Access Mnemonic Description D31:03 N/A Reserved N/A (do not modify) D02 R/W LPM Low-power mode 0 Normal mode (rese t value on reset_n) 1 Low-power mode Indicates normal or low-power mode.
MEMORY CONTROLLER S tatus register 234 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status register Address: A070 0004 The Status register provides memo ry controller status information.
. . . . . MEMORY CONTROLLER Dynamic Memory Contr ol register www .digiembedded.com 235 Register Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY CONTROLLER Dynamic Memory Refr esh T i mer r egister 236 Hardware Reference NS9215 Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . MEMORY CONTROLLER Dynamic Memory Read C onfiguration r egister www .digiembedded.com 237 The Dynamic Memory R efresh T imer register configures dynamic memory operat ion. It is recommended that this register be modified during system initialization, or when there are no current or outstandin g transactions.
MEMORY CONTROLLER Dynamic Memory Pr echarge Command Period r egister 238 Hardware Reference NS9215 Registe r Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . MEMORY CONTROLLER Dynamic Memory Active to Pr echarge Command Period r egister www .digiembedded.com 239 Register bit assignment Dynamic Memory Active to Precharge Command Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY CONTROLLER Dynamic Me mory Self-r efre sh Exit T ime r egister 240 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . MEMORY CONTROLLER Dynamic Memory Data-in to Ac tive Command T ime r egister www .digiembedded.com 241 Register Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY CONTROLLER Dynamic Memory W rite Re covery T ime register 242 Hardware Reference NS9215 Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . MEMORY CONTROLLER Dynamic Memory Active to Active Command Pe riod r egister www .digiembedded.com 243 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY CONTROLLER Dynamic Memory Exit Self-r efresh r egister 244 Hardware Reference NS9215 Note: The Dynamic Memory Auto R efresh P e riod register is used for all four dynamic memory chip selects. Th e worst case va lue for al l chip selects must be programmed.
. . . . . MEMORY CONTROLLER Dynamic Memory Acti ve Bank A to Active Bank B T ime register www .digiembedded.com 245 Register Register bit assignment Dynamic Memory Active Bank A to Active Bank B Time . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY CONTROLLER Dynamic Memory Load Mode r egister to Active Command T ime r egister 246 Hardware Reference NS9215 Registe r bit assignment Dynamic Memory Load Mode re gister to Active Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . MEMORY CONTROLLER S tatic Memory Exte nded W ait r egister www .digiembedded.com 247 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY CONTROLLER Dynamic Memory Configuration 0–3 r egisters 248 Hardware Reference NS9215 Use the Dynamic Memory Configuration 0–3 registers to program the configuration information for the relevant dynamic me mory chip select. These registers are usually modified on ly during system initialization.
. . . . . MEMORY CONTROLLER Dynamic Memory Confi guration 0–3 r e gisters www .digiembedded.com 249 Address mapping for the Dynamic Memory Configuration registers The next table shows address mapping fo r the Dynamic Memory Configuration 0-3 registers.
MEMORY CONTROLLER Dynamic Memory RAS and CAS Delay 0–3 r egisters 250 Hardware Reference NS9215 Chip select and memory devices A chip select can be connected to a single memory device; in this situation, the chip select data bus width is the same as th e device width.
. . . . . MEMORY CONTROLLER S taticMemory Confi guration 0–3 r egisters www .digiembedded.com 251 The Dynamic Memory RAS and CAS Delay 0–3 registers allow you to program the RAS and CAS latencies for the relevant dynami c memory .
MEMORY CONTROLLER S taticMemory Configuration 0–3 r egisters 252 Hardware Reference NS9215 Registe r Registe r bit assignment 1 3 1 2 1 1 1 0 9876543210 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 .
. . . . . MEMORY CONTROLLER S taticMemory Confi guration 0–3 r egisters www .digiembedded.com 253 D07 R/W PB Byt e lane state 0 For reads, all bits in byte_lane[3:0] are high. For writes, the respective active bits in byte_lane[3:0] are low (reset value for chip select 0, 2, and 3 on reset_n ).
MEMORY CONTROLLER S taticMemory W rite Enabl e Delay 0–3 r egisters 254 Hardware Reference NS9215 Note: Synchronous burst mode memory devices are not supp orted. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . MEMORY CONTROLLER S tatic Memory Output E nable Delay 0–3 r egisters www .digiembedded.com 255 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY CONTROLLER S tatic Memory Read Delay 0–3 registers 256 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . MEMORY CONTROLLER S tatic Memory W rite Delay 0–3 r egisters www .digiembedded.com 257 modified during sys tem initialization, or when there a re no current or outstanding transactions. W ait until the memory contro ller is idle, then enter low-power or disabled mode.
MEMORY CONTROLLER S taticMemory T urn Round Delay 0–3 r egisters 258 Hardware Reference NS9215 Registe r Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . MEMORY CONTROLLER S taticMemory T urn R ound Delay 0–3 r egisters www .digiembedded.com 259 Register bit assignment T o prevent bus contention on the extern al memory databus, the W AITTURN field controls the nu mber of bus turnaround cy cles added between static memory read and write accesses.
MEMORY CONTROLLER S taticMemory T urn Round Delay 0–3 r egisters 260 Hardware Reference NS9215.
. . . . . ETHERNET COMMUNICATION MODULE www .digiembedded.com 261 Ethernet Communication Module CHAPTER 6 T he Ethernet Communication module co nsists of an Ethernet Media Access Controller (MAC) and Ethernet front-end modu le.
ETHERNET COMMUNICATION MODULE Ethernet MAC 262 Hardware Reference NS9215 Ethernet communications module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE Ethernet MAC www .digiembedded.com 263 MAC module block diagram MAC module features Feature Description MAC Core 10/100 megabit Media Access Controller Performs the CSMA/CD function.
ETHERNET COMMUNICATION MODULE S tation addr ess logic (SAL) 264 Hardware Reference NS9215 PHY interface mappings This table shows how th e different PHY interfac es are mapped to the e xternal IO. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE S tatistics module www .digiembedded.com 265 module. The filtering option s, listed next, are programmed in the Station Address Filter register (see page 301).
ETHERNET COMMUNICATION MODULE Ethernet fr ont-end module 266 Hardware Reference NS9215 The counters support a clear on read capability that is enable d when AUTOZ is set to 1 in the Ethernet General Control R egister #2. . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE Receive packet pr ocessor www .digiembedded.com 267 The 2K byte RX_FIFO allows the entire Ethernet frame to be buffered while the receive byte count is analyzed.
ETHERNET COMMUNICATION MODULE Receive packet pr ocessor 268 Hardware Reference NS9215 T ransferring a frame to system memory The RX _RD logic manages the transfer of a frame in the RX_FIFO to system memory . The transfer is enabled by setting the ERXDMA (enable receive DMA) bi t in Ethernet General Control Register #1.
. . . . . ETHERNET COMMUNICATION MODULE T ransmit packet processor www .digiembedded.com 269 Receive buf fer descriptor field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE T ransmit packet processor 270 Hardware Reference NS9215 reside in different buffers in s ystem memo ry , several buffer desc riptors can be used to transfer the f rame. T r ansmit buffer descriptor f ormat All buffer descriptors (that is, up to 64) are found in a local TX buffer descriptor RAM.
. . . . . ETHERNET COMMUNICATION MODULE T ransmit packet processor www .digiembedded.com 271 T ransmitting a frame Setting the EXTDMA (enable transmit DMA) bit in Ethernet General Contr ol R egister #1 starts the transfer of transmit frames from the system memory to the TX_FIFO.
ETHERNET COMMUNICATION MODULE T ransmit packet processor 272 Hardware Reference NS9215 The TX_WR logic examines the stat us received from the MAC after it has transmitted the frame.
. . . . . ETHERNET COMMUNICATION MODULE Ethernet slave interface www .digiembedded.com 273 – A packet consisting of multiple, linked buffer descriptors does not have the F bit set in any of the non-first buffer descriptors.
ETHERNET COMMUNICATION MODULE Resets 274 Hardware Reference NS9215 St a t u s b i t s The status bits for all interrupts are avai lable in the Ethernet Interrupt Status register , and the associated enables are av ailable in the Ether net Interrupt Enable register .
. . . . . ETHERNET COMMUNICATION MODULE Multicast addr ess filtering www .digiembedded.com 275 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE Clock synchr onization 276 Hardware Reference NS9215 Multicast add r ess filtering example 2 T o accept multicast pac kets with de stination addresses in the range of 0x0.
. . . . . ETHERNET COMMUNICATION MODULE Ethernet Contr ol and S tatus r egisters www .digiembedded.com 277 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE Ethernet Contr ol and S tatus r egisters 278 Hardware Reference NS9215 A060 0A0C RXDPTR RX_D Buffer Descriptor Pointer register A060 0A10 EINTR Ethernet In terrupt Status.
. . . . . ETHERNET COMMUNICATION MODULE Ethernet General Contr ol Register #1 www .digiembedded.com 279 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE Ethernet General Contr ol Register #1 280 Hardware Reference NS9215 Registe r bit assignment Bits Access Mnemonic Reset Description D31 R/W ERX 0 Enable RX packet processing 0 Reset RX 1E n a b l e R X Used as a soft reset for th e RX.
. . . . . ETHERNET COMMUNICATION MODULE Ethernet General Contr ol Register #1 www .digiembedded.com 281 D22 R/W ETXDMA 0 Enable tran smit DMA 0 Disable transmit DMA data request (use to stall transmit.
ETHERNET COMMUNICATION MODULE Ethernet General Contr ol Register #2 282 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE Ethernet General S tatus r egister www .digiembedded.com 283 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE Ethernet T ransmit S tatus register 284 Hardware Reference NS9215 Registe r Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE Ethernet T ransmit S tatus r egister www .digiembedded.com 285 Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Reserved N/A N/A D15 R TXOK 0x0 Frame transmitted OK When set, indicates that the frame has been delivered to and emptied from the transm it FIFO without problems.
ETHERNET COMMUNICATION MODULE Ethernet Receive S tatus register 286 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE Ethernet Receive S tatus r egister www .digiembedded.com 287 Register Register bit assignment 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 2.
ETHERNET COMMUNICATION MODULE MAC Configuration Register #1 288 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE MAC Configuration Register #2 www .digiembedded.com 289 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE MAC Configuration Register #2 290 Hardware Reference NS9215 D09 R/W LONGP 0 Long p reamble enforcemen t 0 Allows any length preamble (as defined in the 802.3u standard). 1 The MAC allows only receive frames that contain preamble fields less than 12 bytes in length.
. . . . . ETHERNET COMMUNICATION MODULE Back-to-Back In ter-Packet -Gap r egister www .digiembedded.com 291 P AD operation table for transmit frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE Non Back-to-Back Inte r -Packet-Gap r egister 292 Hardware Reference NS9215 Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE Collision W indow/R etry r egister www .digiembedded.com 293 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE Maximum Frame r egister 294 Hardware Reference NS9215 Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE MII Management Conf iguration r egister www .digiembedded.com 295 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE MII Management Command r egister 296 Hardware Reference NS9215 Clocks field settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE MII Management Addr ess r egister www .digiembedded.com 297 Register Register bit assignment Note: If both SCAN and READ are set, SCAN takes precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE MII Management W rite Data register 298 Hardware Reference NS9215 Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE MII Management Indicators r egister www .digiembedded.com 299 Register Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE S tation Address registers 300 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE S tation Addr ess Filter r egister www .digiembedded.com 301 Register bit assignments for all three r egisters Note: Octet #6 is the first byte of a frame re ceived from the MAC. Octet #1 is the last byte of the st ation ad dress received from the MAC.
ETHERNET COMMUNICATION MODULE RegisterHash T ables 302 Hardware Reference NS9215 Registe r Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE S tatistics r egisters www .digiembedded.com 303 HT2 Address: A060 0508 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE S tatistics r egist ers 304 Hardware Reference NS9215 Receive statistics counters address map Receive byte counter (A060 069C) Incremented by the byte count of frames received with 0 to 1518 byte s, including those in bad packets, excluding fr aming bits but including FCS bytes.
. . . . . ETHERNET COMMUNICATION MODULE S tatistics r egisters www .digiembedded.com 305 Receive FCS error counter (A060 06A4) Incremented for each frame received with a length of 64 to 1518 b ytes, and containing a frame check sequ ence (FCS) e rror .
ETHERNET COMMUNICATION MODULE S tatistics r egist ers 306 Hardware Reference NS9215 Receive alignment error counter (A060 06BC) Incremented for each received frame, fr om 64 to 1518 bytes, that contains an invalid FCS and has dribble bits (that is, is not an integral number of bytes).
. . . . . ETHERNET COMMUNICATION MODULE S tatistics r egisters www .digiembedded.com 307 Receive jabber counter (A060 06D8) Incremented for frames received that ex ceed 1518 bytes (non-V LAN) or 1522 bytes (VLAN) and contain an invali d FCS, including alignment e rrors.
ETHERNET COMMUNICATION MODULE S tatistics r egist ers 308 Hardware Reference NS9215 T ransmit pack et counter (A060 06E4) Incremented for each transmitted pack et (including bad packets, excessive deferred packets, excessive collision packets , late collision packets, and all unicast, broadcast, and multicast packets).
. . . . . ETHERNET COMMUNICATION MODULE S tatistics r egisters www .digiembedded.com 309 T ransmit multiple collision packet counter (A060 0700) Incremented for each frame t ransmitted th at expe rienced 2 –15 collisi ons (includin g any late collisions) during transmission.
ETHERNET COMMUNICATION MODULE S tatistics r egist ers 310 Hardware Reference NS9215 T ransmit oversize frame counter (A060 072 4) Incremented for each transmitted frame that exceeds 1518 b ytes (NON_V LAN) or 1532 bytes (VLAN) and contain s a valid FCS.
. . . . . ETHERNET COMMUNICATION MODULE S tatistics r egisters www .digiembedded.com 31 1 Register Register bit assignment Carry Regist er 2 Address: A060 0734 C1 RMC C1 RBC C1RXP C1 RXC C1 RXU C1RAL .
ETHERNET COMMUNICATION MODULE S tatistics r egist ers 312 Hardware Reference NS9215 Registe r Registe r bit assignment Carry Register 1 Mask register Address: A060 0738 C2 TBY C2 TPK C2TBC C2TMC Rsvd .
. . . . . ETHERNET COMMUNICATION MODULE S tatistics r egisters www .digiembedded.com 313 Register Register bit assignment M1 RMC M1 RBC M1RXP M1 RXC M1 RXU M1RAL Not used M1 RCD M1 RCS M1 RUN M1 ROV M.
ETHERNET COMMUNICATION MODULE S tatistics r egist ers 314 Hardware Reference NS9215 Carry Register 2 Mask register Address: A060 073C Registe r Registe r bit assignment M2 TBY M2 TPK M2TBC M2 TMC Not .
. . . . . ETHERNET COMMUNICATION MODULE RX_A Buffer Descript or Pointer r egister www .digiembedded.com 315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE RX_C Buffer Descript or Pointer register 316 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE Ethernet Interrupt S tatus r egister www .digiembedded.com 317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE Ethernet Interrupt S tatus re gister 318 Hardware Reference NS9215 D21 R/C RXDONEB 0 Assigned to RX interrupt. Complete receive frame stor ed in pool B of system memory. D20 R/C RXDONEC 0 Assigned to RX interrupt. Complete receive frame stor ed in pool C of system memory.
. . . . . ETHERNET COMMUNICATION MODULE Ethernet Interrupt Enable r egister www .digiembedded.com 319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE TX Buffer Descript or Pointer register 320 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE T ransmit Recover Buffer De scriptor Pointer register www .digiembedded.com 321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE TX S tall Buffer De scriptor Pointer register 322 Hardware Reference NS9215 Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE RX_A Buffer Descri ptor Poin ter Offset r egister www .digiembedded.com 323 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE RX_B Buffer Descriptor Pointer Offse t r egister 324 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE RX_D Buffer Desc ri ptor Poin ter Offset r egister www .digiembedded.com 325 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE RX Free Buffer register 326 Hardware Reference NS9215 Registe r Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE Multicast Addr ess Filter r egisters www .digiembedded.com 327 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE Multicast Addr ess Filter r egisters 328 Hardware Reference NS9215 Multicas t Low Address Filter Registe r #6 Address: A060 0A58 Multicas t Low Address Filter Registe r #.
. . . . . ETHERNET COMMUNICATION MODULE Multicast Address Mask r egisters www .digiembedded.com 329 Multicast High Address Fi lter Register #6 Address: A060 0A78 Multicast High Address Fi lter Register #7 Address: A060 0A7C . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE Multicast Addr ess Mask registers 330 Hardware Reference NS9215 Multicas t Low Address Mask Registe r #4 Address: A060 0A90 Multicas t Low Address Mask Registe r #5 Addre.
. . . . . ETHERNET COMMUNICATION MODULE Multicast Addr ess Fi lter Enable r egister www .digiembedded.com 331 Multicast High Address Mask Register #5 Address: A060 0AB4 Multicast High Address Mask Register #6 Address: A060 0AB8 Multicast High Address Mask Register #7 Address: A060 0ABC .
ETHERNET COMMUNICATION MODULE TX Buffer De scriptor RAM 332 Hardware Reference NS9215 Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE RX FIFO RAM www .digiembedded.com 333 Offset+4 Offset+8 Offset+C See “T ransmit buffer descriptor format” on page 270, for more information about the fields in Offset+C. . . . . . . . . . . . . . . . . . . .
ETHERNET COMMUNICATION MODULE Sample hash table code 334 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . ETHERNET COMMUNICATION MODULE Sample hash table code www .digiembedded.com 335 (*MERCUR Y_EFE).ht2.b its.da ta = SW AP32(hash_table[1]); (*MERCUR Y_EFE).
ETHERNET COMMUNICATION MODULE Sample hash table code 336 Hardware Reference NS9215 /* * * Function: void set_hash_bit (BYTE *table, int bit) * * Description: * * This routine sets the appropriate bit in the hash table.
. . . . . ETHERNET COMMUNICATION MODULE Sample hash table code www .digiembedded.com 337 * * Return V alues: * * bit position to set in hash table * */ #define POL YNOMIAL 0x4c11db6L static int calcul.
ETHERNET COMMUNICATION MODULE Sample hash table code 338 Hardware Reference NS9215 bp = rotate (bp, RIGHT , 1); } } // CRC calculation done. The 6-bit result resides in bit // locations 28:23 result =.
. . . . . EXTERNAL DMA DMA transfers www .digiembedded.com 339 External DMA CHAPTER 6 T he external DMA interface provides two external channe ls for external peripheral support. Each DM A channel moves dat a from the source address to the destination address.
EXTERNAL DMA DMA buffer descriptor 340 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA buffer descriptor All DMA channels use a buffer descriptor .
. . . . . EXTERNAL DMA Descriptor li st pr ocessing www .digiembedded.com 341 Note: Optimal performanc e is achieved when the destination address is aligned on a word boundary .
EXTERNAL DMA Peripheral DMA r ead access 342 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . EXTERNAL DMA Peripheral DMA write access www .digiembedded.com 343 Peripheral DMA single read access Peripheral DMA burst read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXTERNAL DMA Peripheral REQ and DONE signaling 344 Hardware Reference NS9215 Determin ing the width of PDEN Use the memory controller’ s Static Memory W rite Delay register and Static Memory W rite Enab le Delay register to determine the width of the PDEN assertion.
. . . . . EXTERNAL DMA St a t i c R A M c h i p s e lect configuration www .digiembedded.com 345 DONE signal The external peripheral can terminat e the DMA transfer at any time by asserting th e DONE signal . The peripheral must also deassert the REQ signal when it asserts the DONE signal.
EXTERNAL DMA Contr ol and Sta tus registers 346 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . EXTERNAL DMA DMA Contr ol r egister www .digiembedded.com 347 Register Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXTERNAL DMA D M A C o n t ro l re g i s t e r 348 Hardware Reference NS9215 Registe r bit assignment Bit(s) Access Mnemonic Reset Description D31 R/W CE 0 Ch anne l enab le Enables and disables DMA operations as required.
. . . . . EXTERNAL DMA DMA Contr ol r egister www .digiembedded.com 349 D22:21 R/W DB 0 Destination burst Defines the AHB maximum burst size allowed when writing to the destination. Note that the destination must have e nough space, as defined by this register se tting, before asserting REQ.
EXTERNAL DMA DMA S tatus and Interr upt Enable r egister 350 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . EXTERNAL DMA DMA St atus and Interr upt Enable r egister www .digiembedded.com 351 Register bit assignment Bit(s) Access Mnemonic Reset Description D31 R/W1C NCIP 0 Normal completion interrupt pending Set when a buffer descriptor has been closed.
EXTERNAL DMA DMA Peripheral Chip Select register 352 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . EXTERNAL DMA DMA Peripheral Chip Select r egister www .digiembedded.com 353 Register bit assignment Bit(s) Access Mnemonic Reset Definition D31:02 R/W Not used 0 This field must always be set to 0.
EXTERNAL DMA DMA Peripheral Chip Select register 354 Hardware Reference NS9215.
. . . . . AES DATA ENCRYPTION/DECRYPTION MODULE www .digiembedded.com 355 AES Data Encryption/Decryption Module CHAPTER 6 T he AES data encryption/decryption modu le provides IPSec-compatible network security to processor-based systems.
AES DATA ENCRYPTION/DECRYPTION MODULE AES DMA buffer descriptor 356 Hardware Reference NS9215 Block diagram Data blocks The AES module works on 128-b it blocks of data. This table shows the perform ance per each 128-bit b lock, depending on the ke y size: .
. . . . . AES DATA ENCRYPTION/DECRYPTION MODULE AES DMA buffer descriptor www .digiembedded.com 357 AES buffer descriptor diagram Field definitions follow . Source addr ess [pointer] The source address pointer identifies the st arting location of the source data.
AES DATA ENCRYPTION/DECRYPTION MODULE AES DMA buffer descriptor 358 Hardware Reference NS9215 AES op code Indicates the contents of the data buff er associated with this descriptor: 000 Non-AES memory.
. . . . . AES DATA ENCRYPTION/DECRYPTION MODULE Decryption www .digiembedded.com 359 The DMA channel does not try a transfer wh en the F bit is clear .
AES DATA ENCRYPTION/DECRYPTION MODULE CBC, CFB, OFB, and CTR pr ocessing 360 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . AES DATA ENCRYPTION/DECRYPTION MODULE CCM mode www .digiembedded.com 361 For encryption, software must set up th is buffer descriptor sequence: K ey , Nonce, additional dat a (op tional), data (used to compute the authentication code), data (used to perform the actual encryption).
AES DATA ENCRYPTION/DECRYPTION MODULE CCM mode 362 Hardware Reference NS9215.
363 I/O Hub Module CHAPTER 9 T he I/O hub provides access to the low sp eed ports on the processor through one master port on the AHB bus. The low speed ports include four UAR T ports, one SPI port, one I 2 C port, 2 multi-function controlled ports, and one a nalog-to-digital (A/D) port.
I/O HUB MOD ULE DMA contr oller 364 Hardware Reference NS9215 31 March 2008 Block diagram AHB slave interface The CPU has access to the control and stat us registers in the DMA controller , the peripheral device s, and th e GP IO con figuration. . . .
. . . . . I/O HUB MODULE DMA contr oller www .digiembedded.com 365 Buffer descriptors The pe ripheral buffer data is held in buffe rs in external memory , linked together using buffer descriptors. The buffer desc riptors are 16 bytes in length and are located contiguou sly in external memory .
I/O HUB MOD ULE DMA contr oller 366 Hardware Reference NS9215 31 March 2008 For transmit channels. CPU sets the F bit after the data is written to a buffer .
. . . . . I/O HUB MODULE T ransmit DMA example www .digiembedded.com 367 HDLC SPI Not applicable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O HUB MOD ULE Contr ol and status register addr ess maps 368 Hardware Reference NS9215 31 March 2008 2 V erifies that the data buffer is valid by making sure the F bit is set to 1.
. . . . . I/O HUB MODULE Contr ol and status re gister addr ess maps www .digiembedded.com 369 Note: R egisters 9000_0000 – 9000_7FFF and registers 9000_80 00 – 9000_FFFF are reserved.
I/O HUB MOD ULE Contr ol and status register addr ess maps 370 Hardware Reference NS9215 31 March 2008 UAR T C register address map UAR T D register address map 0x9001_8030 – 0x9001_8FFF Reserved 0x.
. . . . . I/O HUB MODULE Contr ol and status re gister addr ess maps www .digiembedded.com 371 SPI register address map AD register address map Reserved R egisters 9004_0000 – 9004_7FFF and 9004_8000 – 9004_FFFF are reserved. I 2 C register address map Reserved R egisters 9005_8000 – 9005_FFFF are reserv ed.
I/O HUB MOD ULE [Module] Interrupt and FIFO S tatus register 372 Hardware Reference NS9215 31 March 2008 RT C r e g i s t e r address map IO Hardware Assist register address map (0) IO Hardware Assist register address map (1) IO register address map (0) IO register address map (1) .
. . . . . I/O HUB MODULE [Module] Interrupt and FIFO S tatus register www .digiembedded.com 373 Register Register bit assignment 1 3 1 2 1 1 1 0 98765432 10 15 14 31 29 28 27 26 25 24 23 22 21 20 1 9 .
I/O HUB MOD ULE [Module] Interrupt and FIFO S tatus register 374 Hardware Reference NS9215 31 March 2008 D26 R/W* RXFO FIP 0x0 RX FIFO ove rflow interrupt pendin g Set when the RX FIFO finds a n overflow condition.
. . . . . I/O HUB MODULE [Module] DMA RX Contr ol www .digiembedded.com 375 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O HUB MOD ULE [Module] DMA RX Buffer Descriptor Pointer 376 Hardware Reference NS9215 31 March 2008 Registe r Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . I/O HUB MODULE [Module] RX Interrupt Configuration register www .digiembedded.com 377 Register Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O HUB MOD ULE [Module] Dir ect Mode RX Status FIFO 378 Hardware Reference NS9215 31 March 2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . I/O HUB MODULE [Module] Dir ect Mode RX Data FIFO www .digiembedded.com 379 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O HUB MOD ULE [Module] DMA TX Contr ol 380 Hardware Reference NS9215 31 March 2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . I/O HUB MODULE [Module] DMA TX Buffer Descriptor Pointer www .digiembedded.com 381 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O HUB MOD ULE [Module] Dir ect Mode TX Data FIFO 382 Hardware Reference NS9215 31 March 2008 Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . I/O HUB MODULE [Module] Dir ect Mode TX Data Last FIFO www .digiembedded.com 383 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O HUB MOD ULE [Module] Dir ect Mode TX Data Last FIFO 384 Hardware Reference NS9215 31 March 2008.
. . . . . SERIAL CONTROL MODULE: UAR T www .digiembedded.com 385 Serial Control Module: UAR T CHAPTER 10 T he processor ASIC supports four independent univ ersal async hronous receiver/transmitter (UART) channels (A through D). Each channel support s several modes, conditions, and formats.
SERIAL CONTROL MODULE: UAR T Normal mode operation 386 Hardware Reference NS9215 UAR T module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: UAR T Baud rate generator www .digiembedded.com 387 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: UAR T Har dwar e- based flow control 388 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: UAR T ARM wakeup on cha racter recog nition www .digiembedded.com 389 character completes, regard less of any flow control me chanism that might stall normal data transmission. Use the Force T ransmit Character Contro l register to program this operation.
SERIAL CONTROL MODULE: UAR T W rapper Control an d Status r egisters 390 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: UAR T W rapper Configur ation r egister www .digiembedded.com 391 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: UAR T W rapper Configuration r egister 392 Hardware Reference NS9215 D17 R/W RXFLUSH 0 Resets the cont ents of the 64-byte RXFIFO. Write a 1, then a 0 to reset the FIFO. D16 R/W TXFLUSH N/A Resets the cont ents of the 64-byte TX FIFO.
. . . . . SERIAL CONTROL MODULE: UAR T Interrupt E nable r egister www .digiembedded.com 393 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: UAR T Interrupt Enable r egister 394 Hardware Reference NS9215 D19 R/W OF LOW 0 Enable overflow error Enables interrupt generati on if the 4-character FIFO in the UART overflows. Note: This should not happen in a pro perly configured system.
. . . . . SERIAL CONTROL MODULE: UAR T Interrupt S tatus r egister www .digiembedded.com 395 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: UAR T Interrupt S tatus register 396 Hardware Reference NS9215 Registe r Registe r bit assignment 1 3 1 2 1 1 1 0 9876543210 15 14 31 29 28 27 26 25 24 2 3 22 21 20 19 18 17 16 .
. . . . . SERIAL CONTROL MODULE: UAR T Interrupt S tatus r egister www .digiembedded.com 397 D11 R/W1TC MATCH3 0 Character match3 Indicates th at a receive character match has occurred against the Receive Match Register 3.
SERIAL CONTROL MODULE: UAR T Receive Character GAP Contr ol r egister 398 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: UAR T Receive Bu ffer GAP Contr ol r egister www .digiembedded.com 399 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: UAR T Receive Character-Based Flow Contr ol register 400 Hardware Reference NS9215 The R eceive Character Match Control registers con figu r e th e rec ei ve character match control logic . Each UAR T module has five R eceive Character Match Control registers.
. . . . . SERIAL CONTROL MODULE: UAR T Receive Character-Based Flow Contr ol register www .digiembedded.com 401 Caution: Be aware that if multiple matches oc cu r , an XOFF assertion will supersede an XON assertion.
SERIAL CONTROL MODULE: UAR T For ce T ransmit Character Control r egister 402 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: UAR T ARM W akeup Contr ol register www .digiembedded.com 403 Register Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: UAR T T ransmit Byte Count 404 Hardware Reference NS9215 Registe r Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: UAR T UART Receive Bu ff er www .digiembedded.com 405 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: UAR T UART Baud Rate Divisor LSB 406 Hardware Reference NS9215 Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: UAR T UART Interrupt Enable r egister www .digiembedded.com 407 Register Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: UAR T UART Interrupt Identif ication r egister 408 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: UAR T UART FIFO Contr ol register www .digiembedded.com 409 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: UAR T UART Line Contr ol r egister 410 Hardware Reference NS9215 Registe r Registe r bit assignment 1 3 1 2 1 1 1 0 9876543210 15 14 31 29 28 27 26 25 24 23 22 21 2 0 19 18 17 1.
. . . . . SERIAL CONTROL MODULE: UAR T UART Modem Contr ol r egister www .digiembedded.com 41 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: UAR T UART Modem S tatus register 412 Hardware Reference NS9215 Registe r Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: UAR T UART Modem S t atus r egister www .digiembedded.com 413 Register Register bit assignment 1 3 1 2 1 1 1 0 987654 3210 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18.
SERIAL CONTROL MODULE: UAR T UART Modem S tatus register 414 Hardware Reference NS9215.
. . . . . SERIAL CONTROL MODULE: HDLC Receive and trans mit operations www .digiembedded.com 415 Serial Control Module: HDLC CHAPTER 1 1 T he HDLC module allows f ull-duplex synchronous communication. Both the receiver and transmitter can se lect either an intern al or external clock.
SERIAL CONTROL MODULE: HDLC Clocking 416 Hardware Reference NS9215 Receive operation In the receiver , each byte is marke d with status to indicate end-of-frame, short frame, and CRC error . The receiver automatical ly synchronizes on flag bytes, and presets the CRC checker accordingly .
. . . . . SERIAL CONTROL MODULE: HDLC Data encoding www .digiembedded.com 417 between the opening and closing flags, except for the inserted zeroes, to the receiver data buffer . Last byte bit pattern table . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: HDLC Digital phase-locked-loop (D PLL) operation: Encoding 418 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: HDLC DPLL operation: Adjustme nt ranges and output clocks www .digiembedded.com 419 DPLL-tracked bit cell boundaries The DPLL counter normally counts by 16 but if a transition occurs earlier or later than expected, the count is modified during the next co un t cycle.
SERIAL CONTROL MODULE: HDLC DPLL operation: Adjustme nt ranges and output clocks 420 Hardware Reference NS9215 NRZ and NRZI encoding With NRZ and NRZI encoding, all tra nsitions occur on bit-cell bou ndaries and th e data should be sampled in the middle of the bit cell.
. . . . . SERIAL CONTROL MODULE: HDLC Normal mode operation www .digiembedded.com 421 only uses the clock transitions to track the bit-cell boundaries, by ignoring all transitions occurring outside a window around the center of the bit-cell. The window is half a bit-cell wide.
SERIAL CONTROL MODULE: HDLC W rapper and HDLC Contr ol and Status r egisters 422 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: HDLC W rapper Configur ation r egister www .digiembedded.com 423 Register Register bit assignment 1 3 1 2 1 1 1 0 9876543210 15 14 31 29 28 27 26 25 24 23 22 21 20 19 .
SERIAL CONTROL MODULE: HDLC Interrupt Enable r egister 424 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: HDLC Interrupt S tatus r egister www .digiembedded.com 425 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: HDLC Interrupt S tatus register 426 Hardware Reference NS9215 Registe r Registe r bit assignment 1 3 1 2 1 1 1 0 9876543210 15 14 31 29 28 27 26 25 24 2 3 22 21 20 19 18 17 16 3.
. . . . . SERIAL CONTROL MODULE: HDLC HDLC Data Register 1 www .digiembedded.com 427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: HDLC HDLC Data r egister 3 428 Hardware Reference NS9215 Registe r Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: HDLC HDLC Contr ol Register 1 www .digiembedded.com 429 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: HDLC HDLC Clock Divider Low 430 Hardware Reference NS9215 Registe r Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: HDLC HDLC Clock Divider High www .digiembedded.com 431 Use the HDLC CLock Divider Low register to set bits 07:00 of the clock divider . This is the equation for the HDLC clock rate: Register Register bit assignment . .
SERIAL CONTROL MODULE: HDLC HDLC Clock Divider High 432 Hardware Reference NS9215 Registe r bit assignment Bits Access Mnemonic Reset Description D31:08 R Not used 0 Write this field to 0. D07 R/W EN 0 Clock enable Must be set when the internal clock is used.
. . . . . SERIAL CONTROL MODULE: SPI www .digiembedded.com 433 Serial Control Module: SPI CHAPTER 12 T he processor ASIC contains a s ingle high speed, four-wire, serial peripheral interface (SPI) module.
SERIAL CONTROL MODULE: SPI SPI contr oller 434 Hardware Reference NS9215 SPI module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: SPI SPI clocking modes www .digiembedded.com 435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI clocking modes There are four SPI cloc king modes.
SERIAL CONTROL MODULE: SPI SPI clock generation 436 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI clock generation The reference clock for the SPI module is the system PLL output.
. . . . . SERIAL CONTROL MODULE: SPI System boot-over -SPI operation www .digiembedded.com 437 Av a i l a b l e strapping options EEPROM/FLASH header The boot-over-SPI hardware re quires several p ieces of us er-supplied information to complete the boot operatio n.
SERIAL CONTROL MODULE: SPI System boot-over-S PI operation 438 Hardware Reference NS9215 Tim e to completion The boot-over-SPI operation is performed in two steps. In the first step, the hardware fetches the 16-byte header . The data rate for this step is about 375 Kbps an d completes in less than 0.
. . . . . SERIAL CONTROL MODULE: SPI SPI Contr ol and S tatus r egisters www .digiembedded.com 439 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: SPI Clock Generation r egister 440 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . SERIAL CONTROL MODULE: SPI Interrupt E nable r egister www .digiembedded.com 441 Use this register to define the data rate of the interface. This register must be programmed in thr ee steps. Failure to follow these steps can result in unpredictable beha vior of the SPI module.
SERIAL CONTROL MODULE: SPI Interrupt S tatus register 442 Hardware Reference NS9215 Use the Interrupt Enable registe r to enable interrupt generation on specific event s. Enable the interrupt by writing a 1 to the appropriat e bit field(s). Registe r Registe r bit assignment T .
. . . . . SERIAL CONTROL MODULE: SPI SPI timing characteristics www .digiembedded.com 443 Register Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONTROL MODULE: SPI SPI timing characteristics 444 Hardware Reference NS9215 Notes: 1 The unit clock refers to the SPI master clock. 2 The SPI master inter face clock duty cycle is alwa ys at least 52/48. The numbers shown here are for a 40 Mhz clock rate.
. . . . . SERIAL CONTROL MODULE: SPI SPI timing characteristics www .digiembedded.com 445 2 The numbers shown here are for a 7.5 Mhz SPI slave interface clock rate. 3 The numbers shown here are for a 300 Mh z PLL output frequency . This value must be proportionally increased wi th a PLL output frequency decrease.
SERIAL CONTROL MODULE: SPI SPI timing characteristics 446 Hardware Reference NS9215.
. . . . . I2C MASTER/SLAVE INTERFACE Physical I2C bus www .digiembedded.com 447 I2C Master/Slave Interface CHAPTER 13 T he I2C master/slave interface provides an interface betw een the ARM CPU and the I2C bus. The I2C master/slave interface basically is a parallel-to-serial an d serial-to-parallel converter .
I2C MASTER/SLAVE INTERFACE I2C external addr esses 448 Hardware Reference NS9215 serial clock. Serial clock modula tion can be controlled by both the transmitter and rec eiver , based in their hosts’ se rvice speed .
. . . . . I2C MASTER/SLAVE INTERFACE I2C command interface www .digiembedded.com 449 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C MASTER/SLAVE INTERFACE I2C r egisters 450 Hardware Reference NS9215 bus owner , the transaction goes through. If the module loses bus arbitration, an M_ARBIT_LOST interrupt is generated to the ho s t processor and the command must be reissued. . .
. . . . . I2C MASTER/SLAVE INTERFACE S tatus Receive Data r egister www .digiembedded.com 451 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C MASTER/SLAVE INTERFACE Master Addr ess register 452 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . I2C MASTER/SLAVE INTERFACE Slave Addr ess r egister www .digiembedded.com 453 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C MASTER/SLAVE INTERFACE Configuration r egister 454 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . I2C MASTER/SLAVE INTERFACE Interrupt Codes www .digiembedded.com 455 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C MASTER/SLAVE INTERFACE Softwar e driver 456 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . I2C MASTER/SLAVE INTERFACE Flow charts www .digiembedded.com 457 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C MASTER/SLAVE INTERFACE Flow charts 458 Hardware Reference NS9215 Slave module (normal mod e, 16- bit) Note: ST A TUS_REG and RX_DA T A_REG are read simultaneously .
459 Real T ime Clock Module CHAPTER 14 T he R eal Time Clock (RTC) module tracks the time of the day to an accuracy of 10 milliseconds and provides cale ndar fu nctionality that tracks day , month, and year .
REAL TIME CLOCK MODULE RTC configuration and status r egisters 460 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . REAL TIME CLOCK MODULE 12/24 Hour r egister www .digiembedded.com 461 Register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REAL TIME CLOCK MODULE Ti m e re g i s t e r 462 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . REAL TIME CLOCK MODULE Calendar r egister www .digiembedded.com 463 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REAL TIME CLOCK MODULE T ime Alarm register 464 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Alarm register Address: 9006 0010 The T ime Alarm register sets the time alarm.
. . . . . REAL TIME CLOCK MODULE Calendar Alarm r egister www .digiembedded.com 465 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calendar Alarm register Address: 9006 0014 The Calendar Alarm register sets the ca lendar alarm.
REAL TIME CLOCK MODULE Event Flags register 466 Hardware Reference NS9215 Registe r Registe r bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . REAL TIME CLOCK MODULE Event Flags r egister www .digiembedded.com 467 Register Register bit assignment 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 1 9 18 17 16 30.
REAL TIME CLOCK MODULE Interrupt Enable r egister 468 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . REAL TIME CLOCK MODULE Interrupt Disable r egister www .digiembedded.com 469 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REAL TIME CLOCK MODULE Interrupt Enable S tatus r egister 470 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . REAL TIME CLOCK MODULE General S tatus register www .digiembedded.com 471 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REAL TIME CLOCK MODULE General S tatus register 472 Hardware Reference NS9215.
473 Analog-to-Digital Converter (ADC) Module CHAPTER 15 T he NS9215 ASIC supports a 12-bit succe ssive approximation analog-to-digital converter (ADC). T o maximize flexibility , an input pin is provided to apply an external reference voltage, which defines the full scale input range.
ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE ADC DMA pr ocedure 474 Hardware Reference NS9215 ADC control block The ADC control block provides access betwe en the CPU and the ADC module. The ADC clock and control signals are generate d in this block. The ADC module output can be either DMA ’d to memory or read directly by the CPU.
. . . . . ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE ADC contr ol and status registers www .digiembedded.com 475 2 Set up the ADC DMA control registers and buffer descriptors (UART channel D). 3 R e set the ADC module by writing a 0 th en a 1 to bit 8 in the Module R eset register at address A090 0180.
ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE ADC Configuration r e gister 476 Hardware Reference NS9215 Registe r Registe r bit assignment 1 3 1 2 1 1 1 0 9876543210 15 14 31 29 28 27 26 25 24 23 22 21 20.
. . . . . ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE ADC Clock Confi guration r egister www .digiembedded.com 477 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE ADC Output Registers 0-7 478 Hardware Reference NS9215 Registe r Registe r bit assignment 1 3 1 2 1 1 1 0 9876543210 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Not u s e d DOUT Not u s ed Bit(s) Access Mnemonic Reset Description D31:12 R/W Not used 0 This fiel d must be written to 0.
. . . . . TIMI NG Electric al charac teristics www .digiembedded.com 479 Ti m i n g CHAPTER 16 T his chapter provides the electrical spec ifications, or timing, integral to the operation of the processor . T iming in cludes information about DC and AC characteristics, output rise and fall timi ng, and crystal oscillator specifications.
TIM I NG Electrical characte ristics 480 Hardware Reference NS9215 Recommended operating conditions R ecommended operating condit ions specify voltage and temperature ranges over which a circuit’ s correct logic func tion is guaranteed. The specified DC el ec trical characteristics are satisfied over these ranges.
. . . . . TIMI NG DC electric al characteristic s www .digiembedded.com 481 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIM I NG Reset and edge sensitive input timing r equir ements 482 Hardware Reference NS9215 Ouputs All electrical out puts are 3.3V interface. DC electrical outputs are provided b elow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . TIMI NG Reset and edge se nsitive input tim ing r equirements www .digiembedded.com 483 If an external device driving the reset or edge sensitive input on a Digi processor cannot meet the 500ns maximu m rise and fall time requirement, the signal must be buffered with a Schmitt trigger device.
TIM I NG Memory T iming 484 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Timing All AC characteristics are measured with 35pF , unless otherwise noted.
. . . . . TIMI NG Memory T iming www .digiembedded.com 485 SDRAM burst read (16-bit) Notes: 1 This is the bank and RAS address. 2 This is the CAS address.
TIM I NG Memory T iming 486 Hardware Reference NS9215 SDRAM burst read (16 bit), CAS latency = 3 Notes: 1 This is the bank and RAS address. 2 This is the CAS address.
. . . . . TIMI NG Memory T iming www .digiembedded.com 487 SDRAM burst write (16 bit) Notes: 1 This is the bank and RAS address. 2 This is the CAS address.
TIM I NG Memory T iming 488 Hardware Reference NS9215 SDRAM burst read (32 bit) Notes: 1 This is the bank and RAS address. 2 This is the CAS address. pr ec h g a c t i v e re ad c a s l at da ta -A da.
. . . . . TIMI NG Memory T iming www .digiembedded.com 489 SDRAM burst read (32 bit), CAS latency = 3 Notes: 1 This is the bank and RAS address. 2 This is the CAS address.
TIM I NG Memory T iming 490 Hardware Reference NS9215 SDRAM burst write (32-bit) Notes: 1 This is the bank and RAS address. 2 This is the CAS address. prec hg a ct i v e w r d-A dat a-B dat a-C dat a .
. . . . . TIMI NG Memory T iming www .digiembedded.com 491 SDRAM load mode M4 M9 M8 M7 M5 SD L dM d td op c od e clk_o ut dy _ c s _n< 3 :0> * ra s_n ca s_ n we _ n ad dr <1 1: 0>.
TIM I NG Memory T iming 492 Hardware Reference NS9215 SDRAM refresh mode M9 M8 M7 M6 M6 M6 M6 clk_ o ut dy _ c s 0_ n dy _ c s 1_ n dy _ c s 2_ n dy _ c s 3_ n ra s_n ca s_ n we _n.
. . . . . TIMI NG Memory T iming www .digiembedded.com 493 Clock enable timing M1 3 M1 4 M3 cl k_ e n a b l e . td cl k_ o ut cl k_ e n < 3 :0 > S DRA M cycl e.
TIM I NG Memory T iming 494 Hardware Reference NS9215 V alues in SRAM timing diagrams The next table describes the values sh own in the SRAM timing diagrams. Notes: 1 The (CPU clock out / 2) signal is for reference only . 2 Only one of the four dy_cs_n signals is used.
. . . . . TIMI NG Memory T iming www .digiembedded.com 495 static_rd_0wt.mif S tat ic RAM r ead cycles with 0 wait states WTRD = 1 WOEN = 0 If the PB field is set to 1, all four by te_lane signals will go low for 32-bit, 16- bit, and 8-bit read cycles.
TIM I NG Memory T iming 496 Hardware Reference NS9215 St a t i c R A M asynchronous page mode r ead, WTPG = 1 WTPG = 1 WTRD = 2 If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-bit, and 8-bit read cycles.
. . . . . TIMI NG Memory T iming www .digiembedded.com 497 S tat ic RAM r ead cycle with configurable wait states WTRD = from 1 to 15 WOEN = from 0 to 15 If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-bit, and 8-bi t read cycles.
TIM I NG Memory T iming 498 Hardware Reference NS9215 St a t i c R A M sequential write cycles WTWR = 0 WWEN = 0 During a 32-bit transfer , all four byte_lane signals will go low . During a 16-bit transfer , two byte_lane signals will go low .
. . . . . TIMI NG Memory T iming www .digiembedded.com 499 S tatic RAM write cycle WTWR = 0 WWEN = 0 During a 32-bit transfer , all four byte_lane signals will go low . During a 16-bit transfer , two by te_lane signals will go low . During an 8-bit transfer , only on e byte_lane signal will go low .
TIM I NG Memory T iming 500 Hardware Reference NS9215 S tatic write cycle with configurable wait states WTWR = from 0 to 15 WWEN = from 0 to 15 The WTWR field determines th e length on the write cycle. During a 32-bit transfer , all four byte_lane signals will go low .
. . . . . TIMI NG Memory T iming www .digiembedded.com 501 Slow peripheral acknowledge timing The table below describes the values show n in the slow peripheral ackn owle dge timing diagrams.
TIM I NG Memory T iming 502 Hardware Reference NS9215 Slow peripheral acknowledge r ead Slow peripheral acknowledge write M3 2 M2 6 M1 7 M1 8 M1 9 M2 0 M3 1 M2 7 M2 8 M2 3 M2 4 M2 9 M3 0 0n s 50 ns 10.
. . . . . TIMI NG Memory T iming www .digiembedded.com 503 Ethernet timing All AC characteristics are measured with 10pF , unless otherwise noted. The table below describes the values sh own in the Ethernet timing diagrams. Notes: 1 Minimum specificatio n is for fastest AHB bus clock of 88.
TIM I NG Memory T iming 504 Hardware Reference NS9215 I 2 C timing All AC characteristics are measured with 10pF , unless otherwise noted. The table below describes th e value s shown in the I 2 C timing diagram. Standard Mode Fast Mode Parm Description Min Max Min Max Unit C1 iic_sda to iic_scl START hold time 4.
. . . . . TIMI NG Memory T iming www .digiembedded.com 505 SPI Timing All AC characteristics are measured with 10pF , unless otherwise noted. The next table describes the values shown in the LCD timing diagrams.
TIM I NG Memory T iming 506 Hardware Reference NS9215 Notes: 1 Active level of SPI enable is inverted (that is, 1) if the CSPOL bit in Serial Channel Control Register B is set to a 1. Note that in SPI slave mode, only a valu e of 0 (low enable) is valid; the SPI slave is fixed to an active low chip select.
. . . . . TIMI NG Memory T iming www .digiembedded.com 507 SPI master mode 0 and 1: 2-byte transfer Note: SPI data can be reversed such that LSB is first. Use the BITORDER bit in Serial Channel B/A/C/D Control Register A. SPI master mode2 and 3: 2-byte transfer Note: SPI data can be reversed such that LSB is first.
TIM I NG Memory T iming 508 Hardware Reference NS9215 SPI slave mode 0 and 1: 2-byte transfer Note: SPI data can be reversed such that LSB is first. Use the BITORDER bit in Serial Channel B/A/C/D Control Register A. SPI slave mode 2 and 3: 2-byte transfer Note: SPI data can be reversed such that LSB is first.
. . . . . TIMI NG Reset and har dware strap ping timing www .digiembedded.com 509 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIM I NG JT AG timing 510 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG ti ming All AC characteristics are measured with 10pF , unless otherwise noted.
. . . . . TIMI NG Clock timing www .digiembedded.com 51 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock timing All AC characteristics are measured with 10pF , unless otherwise noted.
TIM I NG Clock timing 512 Hardware Reference NS9215.
513 Packaging CHAPTER 17 B elow is the processor package, 265 LF-XBGA. Diagrams that f ollow show the processor dimensions: top, bottom, and side views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PACKAGING Pr ocessor Dimensions 514 Hardware Reference NS9215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . PACKAGING Pr ocessor Dimensions www .digiembedded.com 515.
PACKAGING Pr ocessor Dimensions 516 Hardware Reference NS9215.
517 Change log CHAPTER 18 T he following changes were made since the last revision of this document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ein wichtiger Punkt beim Kauf des Geräts Digi NS9215 (oder sogar vor seinem Kauf) ist das durchlesen seiner Bedienungsanleitung. Dies sollten wir wegen ein paar einfacher Gründe machen:
Wenn Sie Digi NS9215 noch nicht gekauft haben, ist jetzt ein guter Moment, um sich mit den grundliegenden Daten des Produkts bekannt zu machen. Schauen Sie zuerst die ersten Seiten der Anleitung durch, die Sie oben finden. Dort finden Sie die wichtigsten technischen Daten für Digi NS9215 - auf diese Weise prüfen Sie, ob das Gerät Ihren Wünschen entspricht. Wenn Sie tiefer in die Benutzeranleitung von Digi NS9215 reinschauen, lernen Sie alle zugänglichen Produktfunktionen kennen, sowie erhalten Informationen über die Nutzung. Die Informationen, die Sie über Digi NS9215 erhalten, werden Ihnen bestimmt bei der Kaufentscheidung helfen.
Wenn Sie aber schon Digi NS9215 besitzen, und noch keine Gelegenheit dazu hatten, die Bedienungsanleitung zu lesen, sollten Sie es aufgrund der oben beschriebenen Gründe machen. Sie erfahren dann, ob Sie die zugänglichen Funktionen richtig genutzt haben, aber auch, ob Sie keine Fehler begangen haben, die den Nutzungszeitraum von Digi NS9215 verkürzen könnten.
Jedoch ist die eine der wichtigsten Rollen, die eine Bedienungsanleitung für den Nutzer spielt, die Hilfe bei der Lösung von Problemen mit Digi NS9215. Sie finden dort fast immer Troubleshooting, also die am häufigsten auftauchenden Störungen und Mängel bei Digi NS9215 gemeinsam mit Hinweisen bezüglich der Arten ihrer Lösung. Sogar wenn es Ihnen nicht gelingen sollte das Problem alleine zu bewältigen, die Anleitung zeigt Ihnen die weitere Vorgehensweise – den Kontakt zur Kundenberatung oder dem naheliegenden Service.
