Benutzeranleitung / Produktwartung ISR 37000 CPLD des Produzenten Cypress Semiconductor
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5V , 3.3V , ISR™ High-Performance CPLDs Ultra37000 CPLD Family Cypress Semiconductor Corpora tion • 3901 North First S treet • San Jose , CA 95134 • 408-943-26 00 Document #: 38-03007 Rev .
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 2 of 64 Selection Guide 5.0V Selec tion Guide General Informa tion Device Macrocells Dedicated Input s I/O Pins Speed (t PD )S p e e d ( f MAX ) CY37032 32 5 32 6 200 CY37064 64 5 32/64 6 200 CY37128 128 5 64/128 6.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 3 of 64 Architecture Overview of Ultra37000 Family Programmable Interc onnect Matrix The PIM consists of a completely global routing matrix for signals from I/O pins and feedbacks from th e logic blocks.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 4 of 64 Low-Power Option Each logic block can operate in high-speed mode for critical path performance, or in low-power mode for power con ser- vation. The logic block mode is set by the user on a logic blo ck by logic block basis.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 5 of 64 The buried macrocell also suppor ts input register capability . The buried macrocell can b e configured to act as an inp ut register (D-type or latch) whos e input comes from the I/O pin associated with the neighboring macr ocel l.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 6 of 64 Clocking Each I/O and buried macrocell has access to four synch ronous clocks (CLK0, CLK1, CLK2 and CLK3) as wel l as an asynchronous product term clock PTCLK. Each inp ut macrocell has access to all four synchronous clocks.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 7 of 64 JT AG and PCI St andards PCI Compliance 5V operation of the Ultra37000 is full y compliant with the PCI Local Bus S pe cification published by the PCI S pecial Interest Group. The 3.3V products meet all PC I requirements except for the output 3.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 8 of 64 The third programming option for Ultra37000 devices is to utilize the embedded controll er or processor that already exists in the system.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 9 of 64 Logic Block Diagrams CY37032/CY37032V LOGIC BLOCK B LOGIC BLOCK A 36 16 36 16 Input Clock/ Input 16 I/Os 16 I/Os I/O 0 − I/O 15 I/O .
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 10 of 64 Logic Block Diagrams (continued) TDI TCK TMS TDO JT AG T ap Controller CY37128/CY37128V PIM INPUT MACROCELL CLOCK INPUTS 4 4 36 16 16.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 1 1 of 64 Logic Block Diagrams (continued) CY37256/CY37256V LOGIC BLOCK G LOGIC BLOCK H LOGIC BLOCK I LOGIC BLOCK J LOGIC BLOCK L LOGIC BLOCK .
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 12 of 64 Logic Block Diagrams (continued) CY37384/CY37384V LOGIC BLOCK AH LOGIC BLOCK AI LOGIC BLOCK BD LOGIC BLOCK BE LOGIC BLOCK BG LOGIC BL.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 13 of 64 Logic Block Diagrams (continued) CY37512/CY37512V LOGIC BLOCK AG LOGIC BLOCK AH LOGIC BLOCK BI LOGIC BLOCK BJ LOGIC BLOCK BL LOGIC BL.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 14 of 64 5.0V Device Characteristics Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emp erature ............. .............. ......
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 15 of 64 3.3V Device Characteristics Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature .. ................. .............. –65 ° C to +150 ° C Ambient T emperature with Power Applied .
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 16 of 64 Induct ance [5] Parameter Description T est Con ditions 44- Lead TQFP 44- Lead PLCC 44- Lead CLCC 84- Lead PLCC 84- Lead CLCC 100- Lead TQFP 160- Lead TQFP 208- Lead PQFP Unit L Max imum Pin Induct ance V IN = 3.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 17 of 64 Parameter [1 1] V X Ou tput W aveform—Measurement L evel t ER(–) 1.5V t ER(+) 2.6V t EA(+) 1.5V t EA(–) V the (d) T est Waveforms V OH V X 0.5V V OL V X 0.5V V X V OH 0.5V V X V OL 0.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 18 of 64 Product T erm Clocki ng Parameters t COPT [13, 14, 15] Product T erm Clock or Latch Enable (PTCLK) to Output ns t SPT Set-Up T ime fr.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 19 of 64 Switching Characteristics Over the Operating Range [12] Parameter 200 MHz 16 7 MHz 154 MHz 143 MHz 125 MHz 100 MHz 83 MHz 66 MHz Unit Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 20 of 64 t RO [13, 14, 15] 12 13 13 14 15 18 21 26 ns t PW 8 8 8 8 10 12 15 20 ns t PR [13] 10 10 10 10 12 14 17 22 ns t PO [13, 14, 15] 12 13 13 14 15 18 21 26 ns User Option Parameters t LP 2.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 21 of 64 Registered Output wi th Product Term Clocking In put Going Through the Ar ray Registered Outpu t with Product Te rm Clocking Input Co.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 22 of 64 Registered Input Clock to Clock Latched Input Switching W aveforms (continued) t IS REGISTERED INPUT INPUT REGISTER CLOCK t ICO COMBI.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 23 of 64 Latched Inpu t and Output Asynchronous Rese t Asynchronous Prese t Output Enable/Disabl e Switching W aveforms (continued) t ICS LATC.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 24 of 64 Power Consumption T ypical 5.0V Power Consumption CY37032 CY37064 0 10 20 30 40 50 60 0 50 100 150 200 250 Fr equency ( M Hz) Icc (mA) Hi gh S peed Low P ower The typical pattern is a 16-bit up counter , per logic block, with outputs disabl ed.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 25 of 64 CY37128 CY37192 T ypical 5.0V Power Consumption (continu ed) 0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160 180 Fr equency ( M H z) Icc (mA) Low P ower Hi gh Speed The typical pattern is a 16-bit up counter , per logic block, with outputs disabled.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 26 of 64 CY37256 CY37384 T ypical 5.0V Power Consumption (continu ed) 0 50 100 150 200 250 300 0 20 40 60 80 100 120 140 160 180 Fr equency ( M H z) Icc (mA) Low P ower Hi gh Speed The typical pattern is a 16-bit up counter , per logic block, with outputs disabled.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 27 of 64 CY37512 T ypical 5.0V Power Consumption (continu ed) 0 100 200 300 400 500 600 0 20 40 60 80 100 120 140 160 Fr equency ( M H z) Icc (mA) Low P ower Hi gh S pe ed The typical pattern is a 16-bit up co unter , per logic block, with output s disabled.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 28 of 64 CY37064V CY37128V T ypical 3.3V Power Consumption (continu ed) 0 5 10 15 20 25 30 35 40 45 0 20 40 60 80 100 120 140 Fr equency ( MH z) Icc (mA) Low Pow er Hi gh Speed The typical patter n is a 16-bit up counter , per logic block, with outputs disabled.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 29 of 64 CY37192V CY37256V T ypical 3.3V Power Consumption (continu ed) 0 20 40 60 80 100 120 0 20 40 60 80 100 120 Fr equency ( M H z) Icc (mA) Low P ow er Hi g h Sp e e d The typical pattern is a 16-bit up counter , per logic block, with outputs disabled.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 30 of 64 CY37384V CY37512V T ypical 3.3V Power Consumption (continu ed) 0 20 40 60 80 100 120 140 160 180 200 0 1 02 03 04 05 0 6 07 08 09 0 Fr equency (MH z) Icc (mA) Low P ow er Hi gh Speed The typical pattern is a 16-bit up counter , per logic block, with outputs disabled.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 31 of 64 Pin Configurations [20] 44-pin TQFP (A44) Top View I/O 2 GND V CCO I/O 3 I/O 4 I/O 1 I/O 0 I/O 29 I/O 30 I/O 31 I/O 28 I/O 27 /TDI I/.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 32 of 64 Note: 20. For 3.3V versions (Ultra37000V), V CCO = V CC . Note: 21. This pin is a N/C, but Cypress recommends that you connect it to V CC to ensure future compatibility .
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 33 of 64 Pin Configurations [20] (continued) Top View 100-lead TQFP (A100) 100 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 34 of 64 Pin Configurations [20] (continued) 100-ball Fine-Pitch BGA (B B100) for CY37064V To p V i e w 100-ball Fine-Pitch BGA (B B100) for C.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 35 of 64 Pin Configurations [20] (continued) I/O 77 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 10.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 36 of 64 Pin Configurations [20] (continued) I/O 72 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 10.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 37 of 64 Pin Configurations [20] (continued) I/O 152 I/O 154 I/O 153 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 .
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 38 of 64 Pin Configurations [20] (continued) 292-Ball PBGA (BG292) T op View 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 9 2 0 AG N D I / O.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 39 of 64 Pin Configurations [20] (continued) 256-Ball Fine-Pitch BGA (BB256) T op View 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 A GND GND I/O 26 .
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 40 of 64 Pin Configurations [20] (continued) 388-Lead PBGA (BG388) To p V i e w 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 .
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 41 of 64 Pin Configurations [20] (continued) 400-Ball Fine-Pitch BGA (BB400) T op View A GND GND NC I/O 17 I/O 16 I/O 14 I/O 29 V CC I/O 11 GN.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 42 of 64 Ordering Information 5.0V Ordering Information Macrocells Spee d (MHz) Ordering Code Package Name Package T ype Operating Range 32 20.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 43 of 64 64 154 CY37064P44-154AC A44 44-Lead Thin Quad Flat Pack Commercial CY37064P44-154JC J67 44-Lead Plastic Lea ded Chip Carrier CY37064P.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 44 of 64 128 167 CY37128P84 -167JC J83 84-Lead Plastic Leaded Chip Carrier Commercial CY37128P84-167JXC J83 84-L ead Lead Free Plastic Leaded .
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 45 of 64 256 154 CY372 56P160-154AC A160 160-Lead Thin Quad Flat Pack Commercial CY37256P160-154AXC A160 160-Lead Lead Free Thin Quad Flat Pac.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 46 of 64 512 125 CY37512P20 8-125NC N208 208-Lead Pl asti c Quad Flat Pack Commercial CY37512P256-125BGC BG292 292-Ball Plastic Ball Gri d Arr.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 47 of 64 64 143 CY37064VP44-143AC A44 44-Lea d Thin Quad Flatpack Commercial CY37064VP44-143AXC A44 4 4-Lead Lead Free Thin Quad Flatpack CY37.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 48 of 64 256 100 CY37256VP160-100AC A1 60 160-Lead Thin Quad Flat Pack Commercial CY37256VP160-100AXC A1 60 160-Lead Lead Free Thin Quad Flat .
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 49 of 64 Package Diagrams 51-85064- * B 44-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack A44 51-85003- * A 44-Lead Lead (Pb)-Free Plastic Le.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 50 of 64 Package Diagrams (continued) 44-Lead Ceramic Leaded Chip Car rier Y67 51-80014 -** [+] Feedback.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 51 of 64 Package Diagrams (continued) 48-Ball (7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch) Thin BGA BA48D 51-85109-*C 51-85006- * A 84-Lead Lead (Pb.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 52 of 64 Package Diagrams (continued) 84-Lead Ceramic Leaded Chip C arrier Y84 51-80095- * A [+] Feedback.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 53 of 64 Package Diagrams (continued) 51-85048- * B 100-Lead Lead (Pb)-Free Thin Plastic Quad F lat Pack (TQFP) A100 [+] Feedback.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 54 of 64 Package Diagrams (continued) 100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100 51-85107-*B [+] Feedback.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 55 of 64 Package Diagrams (continued) 51-85049-* B 160-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack (24 x 24 x 1.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 56 of 64 Package Diagrams (continued) SEATING PLANE DIMENSION IN MM (INCH) 2.79(.110) 2.03(.080) 0.500(.020) 0.050(.002) (.020 ±.008) 0.51 ±0.20 (.006 ±.001) 0.15 ±0.02 TYP. 0.300(.012) TYP.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 57 of 64 Package Diagrams (continued) 208-Lead Plastic Qu ad Flatpack N208 51-85069-*B [+] Feedback.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 58 of 64 Package Diagrams (continued) SEATING PLANE DIMENSIONS IN MM (INCH) 0.500(.020) 0.050(.002) 3.94(.155) 3.43(.135) (.006 ±.001) 0.15 ±0.02 (.020 ±.008) 0.51 ±0.20 (1.229 ±.010) 31.22 ±0.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 59 of 64 Package Diagrams (continued) BOTTOM VIEW TOP VIEW 1 0 987654 32 1 A B C D E F G H J K PIN 1 CORNER PIN 1 CORNER 0.20(4X) Ø 0 . 2 5MCAB Ø0.05 M C Ø0.45±0.05(256X)-CPLD DEVICES (37K & 39K) 0.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 60 of 64 Package Diagrams (continued) 292-Ball Plastic Ball Grid Array PBGA (27 x 27 x 2.33 mm) BG292 51-85097-*B [+] Feedback.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 61 of 64 Package Diagrams (continued) 51-85103-*C 388-Ball Plastic Ball Grid Array PBGA (35 x 35 x 2.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 62 of 64 © Cypress Semi conductor Corpora tion, 2005. The i nformation cont ained here in is subject to ch ange withou t notice. Cypress S emic onductor Corporation assu mes no responsibility for the use of any circuitry o ther than circui try embodied i n a Cypress prod uct.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 63 of 64 Addendum 3.3V Operating Range (CY37064VP100-143AC, CY37064 VP100-143BBC , CY37064VP44-1 43AC, CY37064VP48-143B AC) Range Ambient T emperature [2] Jun ction T emp erature V CC Commercial 0°C to +70°C 0°C to +90°C 3.
Ultra37000 CPLD Family Document #: 38-03007 Rev . *E Page 64 of 64 Document History Page Document Title: Ultra37000 CPLD Family 5V , 3.3V , ISR™ High-Performanc e CPLDs Document Number: 38-03007 REV .
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