Benutzeranleitung / Produktwartung CY7C68033 des Produzenten Cypress Semiconductor
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EZ-USB NX2LP-Flex™ Flexible USB NAND Flash Controller CY7C68033/CY7C68034 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-04247 Rev . *D Revised September 21, 2006 CY7C68033/CY7C68034 Silicon Features • Certified compliant for Bus- or Self-powered USB 2.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 2 of 33 Default NAND Firmware Features Because the NX2LP-Flex™ is intended for NAND Flash-based USB mass storage appli cations, a default firm.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 3 of 33 Figure 1. Example DVB Block Diagram Figure 2. Example G PS Block Di agram The “Reference De signs” sectio n of the Cypress we b site provides additional tools fo r typical USB 2.0 applications.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 4 of 33 Buses The NX2LP-Flex features an 8- or 16-bit ‘F IFO’ bidirectional data bus, multiplexed on I/O por t s B and D. The default firmware image implements an 8-bit data bus in GPIF Master mode.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 5 of 33 Figure 4. NX2LP-Flex Enumeration Sequenc e Normal Operation Mode In Normal Operation Mode, th e NX2LP-Flex b ehaves as a USB 2.0 Mass S torage Class NAND Flash controller . This includes all typical USB device states (powered, configured, etc.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 6 of 33 If Autovectoring is enabl ed (A V2EN = 1 in the INTSET -U P register), the NX2LP-Flex su bstitutes its INT2VEC byte.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 7 of 33 If Autovectoring is enabl ed (A V4EN = 1 in the INTSET -U P register), the NX2LP-Flex su bstitutes its INT4VEC byte.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 8 of 33 Wak eu p P i n s The 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 9 of 33 Endpoint RAM Size • 3 × 64 bytes (Endpoints 0 and 1) • 8 × 512 bytes (Endpoints 2, 4, 6, 8) Organization • EP0 — Bidirectional.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 10 of 33 Default High-Speed Alterna te Settings External FIFO Interface Architecture The NX2LP-Flex slave FIFO ar chitecture has ei ght 512-byte.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 1 1 of 33 the default NAND firmwa re image implements an 8-bit data bus and up to 8 chi p enable pins on the GPIF ports, it is recom- mended that designs ba sed upon the d efault firmware image use an 8-bit data bus as well.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 12 of 33 Pin Assignment s Figure 9 and Figure 10 identify al l signals for the 56-pin NX2LP-Flex package. Three modes of operation are available for the NX2LP-Flex: Port mode, GPIF Master mode, and Slave FIFO mode.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 13 of 33 Figure 10. CY7C68033/CY7C6 8034 56-pin QFN Pin Assignment CY7C68033/CY7C68034 56-pin QFN 28 27 26 25 24 23 22 21 20 19 18 17 16 15 43 4.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 14 of 33 T able 8. NX2LP-F lex Pin Descriptions [6] 56 QFN Pin Number Default Pin Name NAND Firmware Usage Pin Ty p e Default Stat e Descriptio n 9 DMINUS N/A I/O/Z Z USB D– Signal . Connect to the USB D– signal.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 15 of 33 13 GPIO8 GPIO8 I/O/Z I GPIO8: is a bidirectional IO port pin. 14 R eserved# N/A Input N/A Reserv ed . Connect to ground. 15 SCL N/A OD Z Clock for the I 2 C interface. Connect to VCC wi th a 2.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 16 of 33 39 P A6 or PKTEND GPIO0 (Input) I/O/Z I (P A6) Multiplexed p in whose function is sel ected by the IFCONF IG[1:0] bits.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 17 of 33 46 PD1 or FD[9] CE1# I/O /Z I (PD1) Multiplexed pin whose functio n is selected by th e IFCONFIG[1:0] and EPxFIFOCFG .0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus. CE1# is a NAND chip enable output signal.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 18 of 33 Register Summary NX2LP-Flex register bit definitions are de scribed in the EZ-USB TRM in greater detail. Some registers that are listed h ere and in the TRM do not apply to the NX2LP-Flex.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 19 of 33 E629 1 ECCRESET ECC Reset x x x x x x x x 00000000 W E62A 1 ECC1B0 ECC1 Byte 0 Addr ess LINE15 LINE14 LINE13 LINE12 LINE1 1 LINE10 LINE.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 20 of 33 E65B 1 NAKIRQ [8] End point Ping -NAK/IBN Interrupt Request EP8 EP6 EP4 EP2 EP1 EP0 0 IBN xxxxxx0x bbbbbbrb E65C 1 USBIE USB Int Ena bl.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 21 of 33 E69E 2 reserv ed E6A0 1 EP0CS End point 0 Contr ol and Sta t us HSNAK 0 0 0 0 0 BUSY ST ALL 10000000 bbbbbbrb E6A1 1 EP1OUTCS End point.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 22 of 33 E6CD 1 FLOWSTBPERIO D Master-S trobe Half-Per iod D7 D6 D5 D4 D3 D2 D1 D0 00000010 RW E6CE 1 GPIFTCB3 [7] GPIF T r an sact io n Count B.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 23 of 33 83 1 DPH0 Data Pointer 0 H A15 A14 A13 A12 A1 1 A10 A9 A8 00 000000 RW 84 1 DPL1 [9] Data Pointer 1 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 .
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 24 of 33 Absolute Maximum Ratings S torage T emperature .............. .............. ...... –65°C to +150°C Ambient T emperature with Powe r Supplied ...... 0°C to +70°C Supply V oltage to Ground Potential .
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 25 of 33 DC Characteristics USB T ran sceiver USB 2.0-compliant in full- and high-speed modes. AC Electrical Characteristics USB T ran sceiver USB 2.0-compliant in full- and high-speed modes. T able 10.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 26 of 33 Slave FIFO Asynchr onous Read Figure 1 1. Slave FIFO Asynch ronous Read T iming Diagram [13] Slave FIFO Asynch ronous W rite Figure 12. Slave FIFO Asynch ron ous Write Timing Diagram [13] T able 1 1.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 27 of 33 Slave FIFO Asynchr onous Packet End Strobe Figure 13. Slave FI FO Asynchronous Packet End Strobe Timing Diagram [9] Slave FIFO Output Enable Figure 14. Slave FIFO Outpu t Enable Timing Diagram [13] Slave FIFO Address to Flags/Data Figure 15.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 28 of 33 Slave FIFO Asynch ro no us Addre ss Figure 16. Slave FI FO Asynchrono us Address Timing Diagram [13] Sequence Diagram Sequence Diagram of a Single and Burst Asynchronous Read Figure 17. Slave FIFO Asynch ro nous Read Sequence and Timing Diagram [13] Figure 18.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 29 of 33 Figure 17 diagrams the timing relationship of the SLA VE FIFO signals during an asynchronous F IFO read. It shows a single read followed by a burst read. • At t = 0 the FIFO address is stable and the SLCS signal i s asserted.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 30 of 33 Ordering Information T able 17.Ordering Inform ation Ordering Code Description Silicon for b attery-powered a pplications CY7C68034-56L.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 31 of 33 PCB Layout Recommendations [16] The following recommendati ons should be followed to ensure reliable high-performance operation: • At least a four-layer impedance controlled boards is recom- mended to maintain signal quality .
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 32 of 33 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce.
CY7C68033/CY7C68034 Document #: 001-04247 Rev . *D Page 33 of 33 Document History Page Document Title: CY7C68033/CY7C 68034 EZ-USB NX2LP-Fle x™ Flex ible USB NAND Flash Controller Document #: 001-04247 Rev .
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