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FuturePlus® Systems Corporation DDR2 DIMM HIGH SPEED PROBE FS2334 Users Manual For use with Agilent T ec hnologies Logic Analyzers Revision 1.1 F uturePlus is a trademark of FuturePlus Systems Corp o.
2 How to reach us....................................................................................................................... 4 Product Warranty ...............................................................................................
3 Overview ....................................................................................................................... ................. 18 State Analysis Operation – Read a nd Writes above 667MT/s .......................................
4 How to reach us For Technical Support: FuturePlus Systems Corporation 36 Olde English Road Bedford NH 03110 TEL: 603-471-2734 FAX: 603-471-2738 On the web http://www.futureplus.com For Sales and Marketing Support: FuturePlus Systems Corporation TEL: 719-278-3540 FAX: 719-278-9586 On the web http://www.
5 Product W arranty Due to wide variety of possible custo m er targe t implementations, the FS2334 DDR2 DIMM probe has a 30 day acceptan ce period by the customer from the date of receipt. If the customer does not conta ct Fu turePlus Systems within 30 days of the receipt of the product it will be said that the customer has accepted the product.
6 Software License Agreement IMPORTANT - Please read this license agreeme nt carefully before opening the media envelope. Rights in the software are offer ed only on the condition t hat the customer agrees to all terms and conditions of the license agreement.
7 Introductio n Thank you for purchasing the FuturePlus Systems FS 2334 DDR2 DIMM Interposer Logic Analyzer Probe. We think you will find the FS2334, alon g with your Agilent Technologies Logic Analyz er, a valuable tool for helping to characterize and deb ug your DDR2-based systems.
8 FS2334 Probe Description The FS2334 DDR2 Probe allows you to perform timing analysi s me asu rements on DDR2 DIMM busses. It also provides a Protocol Decoder with the cap ability of providing State analysis of both Read and Write activi ty is provided by using the dual sam ple mode feature available on the 169xx.
9 Signal Assignme nts on Probe Pod s The overlap in the bit ranges (for DQxx) signals bet ween pods occurs because the bits are assigned to pods in the orde r that they appear physically on the DDR2 DIMM connector, which is not strictly in logical bit order.
10 FS2334 Frontside layout FS2334 Backside layout Test Points There are several test point on the board. The first set of test points are used to select which signals g o to the Clk inp ut and the D15 input of Header 2. The shipping configur ation for the FS2334 is to have S0 wired to the Clk input, which is TP3 wired to TP2.
11 Connecting to y our Tar get System To connect the probe to the DDR2 bus, sele ct an avai lable DDR2 slot. Remove the DDR2 DIMM module, if present. Install the DDR2 DIMM module into the 240 pi n connector on the top of the FS2334 probe. Install the DDR2 probe/DIMM into the target system.
12 Recommended Logic Analy zer Card Req uirements and Co nfiguration file s 169xx Analyzer Type Timing Analysis State Analysis 667MT/s or slower 16753/4/5/6, 16950 FS234_2 3 cards configured as one module, one timing machine FS234_5 4 cards configured as one logic analyzer state machine.
13 Logic Analyzer card configurations – Note : These are all for unbuffered DI MM probing FS234_1 2 machine, 7 Card 800MT/s Read and Write configurati on file Write – Command machi n e 4 cards in slots A – D (B = Master).
14 Software Requirements Setting up the 1 69xx A nalyzer A CD containing the 16900 software is in clud ed in the FS1136 package. The CD contains a setup file that will automatically install the conf iguration files and protocol decoder onto a PC containi ng the 169 00 oper ating system or onto a 16900 a nalyzer itself.
15 Offline Analy sis Offline analysis allows a user to be able to analyze a trace offline at a PC so it fre es up the analyzer for another person to use the analyzer to captu re data.
16 After the decoder has loaded, select Pre f eren ce s from the overview screen and set the preferences to their correct value in order to decode the trace prope rly. The protocol decoders, FS1136 and FS1117, requi re 4 param eters to be entered by the user in order to decode valid states.
17 TimingZoom Analysis The TimingZoom feature of the 1690x logic analyzer allows for efficient timing analysi s of all the signals on the DDR2 DIMM bus. Please refer to the “Setting up the 16900 Analyz er” section of this manual on the use of the general purpose probe feature to de termine how to attach the logic analyzer to the probe.
18 State Analysis Overview There are several choices for State mod e analysis using the FS2334 DDR2 p robe depending on the speed of the data bu s being probed and the numb er of logic a nalyzer cards available to the user.
19 State Analys is Operatio n – Read and Write at 667 MT/s or slower State mode capture is performed by using both ed ge s of CK0. This double probing of each signal is handled internally by the Ag ilent Logic Analyzer using the Dual Sa mple mode feature.
20 The process for setting sampling positio ns at spee ds of 8 00MT/s: This procedure requires the probe user to capture TimingZoom traces an d use the markers to determine the correct sampling posi tion s.
21 State analysis calibration pro cedure This process is in large pa rt the same for both use in the 7 card Read and Write configuration at 800MT/s and for the 4 card configurat ions. Differen ces are noted. 1) Start a memory test program that creat es a good mixture of read s and writes in a single TimingZoom trace.
22 4) Repeat this procedure using the next rising edg e of Write – Command:CK2_TZ and the corresponding data b urst cycle (it will be right next to the burst cycle you just looked at).
23 label to be set to the same value. Then you can drag the blue sample position b ar back to the right to place it in the position you measured in step 5. The sample position is indicated on the scale at the top of the display as well as on the side under the “Sampling Position” column.
24 Adjusting the sam pling po sitio ns with controlled stimulu s This is a special case re qui ring special stimulus of the DDR2 DIMM bus. Thi s may involve the use of a special memory test card from .
25 signal edges change relati ve to the Data Strobes (clock input) and this will be close the valid eye openings for all the Data si gnals. Run Auto Sample Position Setup and/or Auto Threshold as requi red to establish correct Threshold setting s, valid eye openings, and sample position s for the se signals.
26 State Display The following figure shows a typic a l DDR2 screen display. B e ca us e th e analyzer may sample data on both edges of the clo ck (FS1117) there are going to be some st ates that have no commands or data associated with them.
27 DDR2 Protocol Checking and Performance T ool (FS1 140) The FS1140 DDR2 Protocol Checking and Performance Tool is a separate VBA-based application that provides a detailed analysis of a 16900 format logi c analy zer trace file, captured with an FS2334 DDR2 Interpo ser pro be.
28 Setting up the F S1140 DDR2 Tool The FS1140 DDR2 tool has to be set-up with the DDR2 bus para meters being used on the target system in order to insure proper de code of the c aptured logic analyzer trace file. Selecting the “Set- up” button from the window provides a form for this information.
29 Functional and Performanc e Analy sis – NOTE : The Fun ctional Perf ormanc e portion of this softwar e will NOT work with 2 FRAME configur ations This window tab provides t he ability to initiate the analysis of a tra c e file in either on or off-line mode using the “Start Analysis” butt on.
30 Export This function takes the data captu red and exports it in .csv format to a location the user selects. Repetitive Run This function allows the user to set-up the tool to trigger the logic analyzer a p redefined number of times and capture data incrementa lly on each run.
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32 Appendix FS2334 Signal to Logic Analy zer Conne ctor a nd Channe l Mapping The following table shows how the FS2 334 DDR2 Probe conn ects DDR2 DIMM signal s to the logic analyzer pods and chan nel s.
33 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name 20K ohm to Ground 49 50 Ground Ground 51 52 D11 A5 20K ohm to Groun.
34 Header 2 - Command Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground.
35 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 NC3 20K ohm to Ground 61 62 Ground Ground 63 64 D1.
36 Header 3 - Write Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground 7.
37 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 DQ13 20K ohm to Ground 61 62 Ground Ground 63 64 D.
38 Header 4 - Write Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground 7.
39 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 DQ22 20K ohm to Ground 61 62 Ground Ground 63 64 D.
40 Header 5 - Write Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground 7.
41 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 CB0 20K ohm to Ground 61 62 Ground Ground 63 64 D1.
42 Header 14 – ECC bits only this head er is not in any config file Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name .
43 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name 20K ohm to Ground 57 58 Ground Ground 59 60 D13 No connection 20K o.
44 Header 6 – Write Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground.
45 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name 20K ohm to Ground 57 58 Ground Ground 59 60 D13 DQ45 20K ohm to Gro.
46 Header 7 -Write Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground 7 .
47 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name 20K ohm to Ground 57 58 Ground Ground 59 60 D13 DQ50 20K ohm to Gro.
48 Header 8 - Write Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground Ground 3 4 NC NC 5 6 NC Ground 7.
49 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name 20K ohm to Ground 57 58 Ground Ground 59 60 D13 SDA 20K ohm to Grou.
50 Header 12 – Read – Duplicates - only data signals Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 1 2 Gr.
51 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 DQ13 20K ohm to Ground 61 62 Ground Ground 63 64 D.
52 Header 10 - Read Duplicates - only data signals Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground G.
53 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 DQ22 20K ohm to Ground 61 62 Ground Ground 63 64 D.
54 Header 11 – Read Duplicates - only data signals Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground.
55 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 CB0 20K ohm to Ground 61 62 Ground Ground 63 64 D1.
56 Header 9 – Read Duplicates - only data signals Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground .
57 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 DQ45 20K ohm to Ground 61 62 Ground Ground 63 64 D.
58 Header 13 – Read Duplicates - only data signals Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground.
59 Logic A nalyzer channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyzer channel number Signal name/Logical Signal Name Ground 59 60 D13 DQ50 20K ohm to Ground 61 62 Ground Ground 63 64 D.
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