Benutzeranleitung / Produktwartung 01664-97005 des Produzenten Agilent Technologies
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Servic e Guide Publicati o n numbe r 01 66 4-9700 5 Secon d editi on , Janu ary 2 000 For Safe ty informatio n, W arrant ies, and Reg ulato ry informati on, see the pages at t he e nd of the bo ok. Copyri ght Agil ent Technolo gie s 198 7–200 0 All Right s Re served.
Agi len t Te chn olog ies 1 6 6 4 A Log ic Ana lyze r The Agile nt Techn ologies 1664A is a 50-MHz State/500 - MHz Timing Logic Analy zer. Features Some of th e main featur es of the 1664A Logic A nalyzer i s as foll ows: • 32 data chann els and 2 clock/ data ch annel s • 3.
The A gile n t T echnol ogies 166 4A Logi c An a l yzer iii.
In This Book This book is the service guide for the 1 664 A Logic Analyz ers and is divided into eight chapters. Chapter 1 contains i nformation ab out the logic anal y zer and i ncludes accesso ries, specificati ons and characte ristics, and eq uipment re q uired fo r servicing.
Table of Contents 1 Genera l Information Accessori es 1–2 Specificatio ns 1– 3 Characteristics 1–3 Supplemental Characterist ics 1–4 Recommende d Test Equipme nt 1–8 2 Preparing for Use To i.
To tes t the multiple-clo ck, multip le-edge, state acqu isition 1–34 Set up t he equipm ent 1 –34 Set up t he logic analyzer 1–35 Connect t he logi c analyzer 1–37 Verify the test signal 1–.
To remove and replace t he Main Circuit board 6– 7 To remove and replace t he switch act uator ass embly 6–8 To remove and replace the rear panel assembly 6–9 To remove and replace t he front pa.
Cont ents viii.
1 Accessori es 1-2 Specificatio ns 1-3 Characteristics 1 -3 Supplemental Characterist ics 1-4 Recommende d Test Equipme nt 1-8 Gene ral Information.
Gen eral Info rmation This chap ter lists the accessories , the spe cifications and characteris tics, and the reco mmende d te st e quipmen t. Access ories The fo llowing acce ss ories are supplied wi th the 1 664A Lo gic Analyz ers.
Specification s The spe cifications are the performance st andards against which t he pro duct i s tested. Maximum State Spee d 50 MH z Minimum St ate Clock Pulse Width * 3.5 ns Minimum Mast er to Maste r Clock Tim e * 20.0 ns Minimum G li tch W idth* 3.
Supplem ental Characteristics Probe s Input Resis tance 100 k Ω , ± 2% Input Capacitance ~ 8 pF Minimum Vol tage Swing 500 m V , peak -to-peak Threshold Range ± 6.0 V, adjustab le in 50 -mV increments State Anal ys is State/ Clock Qualifi ers 6 Time Tag Reso lution * 8 ns or 0 .
Measuremen t and Displ ay F u nctio ns Display ed Wavefo r ms 24 lines max imum, with scrolling across 96 waveforms . Measuremen t Func tions Run /Stop Fun ctio ns Run starts acquisit ion of dat a in specifi ed trace mo de.
Marke r Functions Time I nterval The X and O marke rs measure the t ime int erval between a point o n a timing waveform and t he trigge r, two po ints o n the same timing waveform, t wo po ints o n different waveforms , or two state s (ti me taggi ng on).
Produc t Reg ulations Safety IEC 348 UL 12 44 CSA Standard C22.2 No.231 ( Series M-89) EMC This pro duct meets t he requirement of the European Communiti es (EC) E MC D irective 8 9/336/ EEC. Em issions EN 55011/ CSIPR 11 ( ISM, Group1 ,Class A equi pment) SABS RAA Act No.
Recom mended Test Equipment Equipme nt Requi red Equip ment Criti cal Spe cifica t ion s Recommend ed Model /Par t Use * Pulse Gene r ator 100 M H z, 3 .
2 To inspect the logic anal yzer 2-2 Ferrit es 2-3 To apply po wer 2-4 To operat e the user int erface 2-4 To s et the line volt age 2- 4 To degauss the display 2-5 To clean t he logic analyzer 2 -5 T.
Pre pari ng For Use This chap ter gives you instr uctions for prep aring the logic analy zer for u se. Powe r Requ irements The logic analyzer requi res a power source of either 115 Vac or 230 Vac, –22 % to +10 %, single p hase , 48 to 6 6 Hz, 2 00 W atts maximum p ower.
Ferrites Ferrit es are include d in the 1 664A access ory pouch fo r the lo gic analyz er cable . Whe n properly instal led, the ferrites re duce RFI emissi ons from the log ic analyzer.
To apply power CA UTION El ectrosta ti c dis charge can damage electroni c com ponents. Use grounded wriststra p s and mats when performi ng any s ervice to the logic analy zer. 1 Check that the lin e vo ltage sele ctor, located on the rear pane l , i s on the corre ct sett ing an d the c o rrect fuse is i nstalled.
1 Tur n the power switch to the Off positio n, then remov e the p owe r cor d from the instru men t. 2 Re move th e fu se module by carefull y pry ing at the to p cen ter of the fuse modu le until you can grasp it an d pull it out by hand .
2– 6.
3 To perform the self- te sts 3-3 To make the test connect ors 3-6 To t est t he t hreshold accuracy 3-8 To t est t he glitch capture 3-17 To t est t he single- clock, s ingle-edge , state acquisit io.
Testi ng Perfo rmance This chapter te lls you how to test the perfo rmance of the logic an alyzer again st the specificati o ns listed in chapter 1. To ensure the logic analyzer is operatin g as specifie d, yo u perform software tests (self-tes ts) and ma nual performance tests on the analyzer.
To per form the self-te sts The self-tests verify the correct oper ation of the logic analyzer . Self-tes ts can be performed all at once or one at a time. While te s tin g th e perfor m ance o f the logic analyzer, run the self-tests all at once. 1 Disco nnect all in p ut s , in s e rt th e bo ot disk , the n turn on th e po wer sw itch.
7 Select the Pri nter/Co ntro ller fie ld next to Sy s PV, then sel ect System Test in the pop-up me nu then p ress the Sel ect key . 8 Install a f ormatted di sk that is not write p rotected i nto the disk drive . If the 1664A has the RS-232C opti on ( 020) , co nnect an RS- 232C loo pback conne ctor onto the RS-23 2C p ort.
11 Select the Disp lay Test. A white grid pattern is displayed. These display screens are not normall y used, but can be used to adjust the dis play. Refer to chapter 4, "Calib rating and Adjust ing" for display adjustment s. a Select Continue and the screen changes to full bri ght.
To make the te st conne ctors The test conne ctors connect the logi c analyzer to the test equipment. Mater i als Required Descript ion Recommende d Part Qty BNC ( f ) Con nector Agilent 12 50-103 2 5.
2 Build o ne t est connector using a BNC connecto r and a 17-b y-2 sec tion of B erg strip . a Solder a jumpe r wi re to a ll pins on one si de of the Berg stri p. b Solder a jumpe r wire to all pins on the other s ide of the Berg strip. c Solder t he cente r of the BNC connec tor to the cent er pin of one row on the Berg s trip.
To test the thre shold a ccuracy Tes ting the thres ho ld accuracy verifie s the perfor m ance of the followi n g specificatio n: • Clock and data c h annel thresho ld a ccuracy . These instru ction s includ e d etaile d step s for testing the threshold s ettin gs of pod 1.
Set up the logic analyzer 1 Press the Config k ey. Assign a l l pod fields to Mach i ne 1 . To assign the p od fiel ds, selec t the p od field s , then select Machin e 1 in the pop-up men u. 2 In the Anal yzer 1 bo x , selec t the Ty pe fiel d . Sele ct Timing in the pop-up menu.
Test the TTL threshold 1 Press the For mat key. Sel ect the field to t he rig ht of Pod 1 , the n selec t TTL in t he po p- up me nu . 2 On the functio n ge nerator fro nt panel, en t e r 1. 647 V ± 1 mV D C offset. Use the mul timeter t o ver ify the voltage.
4 Using the Modify up arro w on the fun ction gen erator, incr ease offset v oltage in 1-mV incre ments un til all acti vity indic ators for pod 1 show th e cha n n els at a logi c high. Record t he fun ction gen erator v olta ge in the performan ce test r ecord.
Test t he ECL threshold 1 Select the fiel d to the ri ght of P od 1, th e n sele ct E C L in the pop - up menu. 2 On the functio n ge nerator fro nt panel, en t er − 1.160 V ± 1 mV DC offset. Use the mul timeter t o ver ify the voltage. The activit y indicato rs for pod 1 should show all data channel s and the J -clock channel at a logic hi gh.
Tes t t h e − User t h reshold 1 Mov e th e cu rsor to the fie ld to the r ight o f Po d 1. Type –6.0 0 , th en u se th e left a n d rig ht cursor c o ntro l key s to high light V. Press th e Sel ect key . 2 On the functio n ge nerator fro nt panel, en t er − 5.
Test t h e + Us e r thr eshold 1 Mov e th e cu rsor to the fie ld to the r ight o f Po d 1. Type +6.00, then use t he left and rig ht cursor c o ntro l key s to high light V. Press th e Sel ect key . 2 On the functio n ge nerator fro nt panel, en t er +6.
Test t he 0 V Us er threshold 1 Mov e th e cu rsor to the fie ld to the righ t of Po d 1 . Type 0, then pre ss the Selec t key. 2 On the functio n ge nerator fro nt panel, en t er +0.10 2 V ± 1 mV DC of f set. Use the mul timeter t o ver ify the voltage.
Te st th e nex t pod 1 Using the 17-by-2 test conne ctor and p r obe tip assemb l y, conne ct th e data and cl o ck chann els of p o d 2 to the outp ut of the fun ction gen erator. 2 Star t w ith "Test the TTL threshold" on p age 3−1 0, su bstituting po d 2 for pod 1.
To tes t the g litch c apture Tes ting the glitch captu re verifies the performan ce of the followin g spe cification: • Min imum d etectable gli tch.
3 Se t u p the osc illoscop e. Osc i llosco pe Setup Time Base Display Delta V Delta T Time/Div: 1.00 ns/div mode: avg V marker s on T mark ers on delay: 1 7.
Connect the Lo gic An a lyzer to the Puls e Generat or Testi ng Combina t ion s To Agil e nt 81 31A Channel 1 Output To 81 31A Channel 1 Outpu t To 81 31A Channel 2 Outpu t To 81 31A Channel 2 Outpu t.
Test the glitch capture on the connected channels 1 Set u p the Format menu. a Pres s the Fo rm at key. b Select the f ield to the right of the pod, then selec t ECL in the pop-up menu. Use the arrow keys to access pods not shown on the s creen (select the Pods field and push Select).
3 Set u p the Trigger menu. a Pres s the Tri gger key . b Select Modify Tri gger, then Clear Trigger, then s elect Al l in the pop- up menus. 4 Using th e Preci sion Edg e Find in the Delta T menu o f th e oscil loscope , ve rify that the p ulse w idths o f the pul se g enerator chan nels 1 and 2 a re 3.
6 On the logi c ana lyzer, pr ess the Run key . The displ ay sho uld be similar to the figure be low. 7 On the pul s e gene rator, e n a b le Chan nel 1 and C h a nnel 2 COMP (with the L ED on). 8 On the logi c ana lyzer, pr ess the Run key . The displ ay sho uld be similar to the figure below.
To tes t the si ng l e-cloc k, s ingle -edg e, sta te ac quis itio n Tes tin g th e s ing le-clock, sing le-edge, s tate acquisi tion verifi es the per formance of the following specificati on s : • Minimum master to master clock t ime. • Maximum state acqu isition spee d .
3 Se t u p the osc illoscop e. Osc i llosco pe Setup Time Base Display Delta V Delta T Time/Div: 1.00 ns/div avg V marker s on T marker s on # of avg : 16 marker 1 pos ition: Chan 1 start on: Pos Edg e 1 screen: dua l marker 2 position: Cha n 1 s top on: Neg E dge 1 Channel C hannel 1 Channe l 2 Di spl ay on o n Probe At ten 20.
2 Set u p the Format menu. a Pres s the For mat key. Sele ct Stat e Acqui sition Mode, then sel ect Full Channel/4 K Memory/ 50MHz . b Select the f ield to the rig ht of each pod, then s elect ECL in t he pop-up menu. 3 Set u p the Trigger menu. a Pres s the Tri gger key .
Connect the logic analyzer 1 Using the 6 -by-2 test con nec tors, con nec t the logi c ana lyzer cl oc k an d data ch annel s listed in the follow ing t able to th e pu lse gen erato r. Install a BNC cable betwe en the pulse genera t or c h annel 2 o utput a n d th e 6x2 test con n e ctor with the lo gic a nalyzer clo ck l ead s .
c Pres s the Tri gger key . Ma ke sure pattern term a is "A". If not, se lect the field next to "a" under the label Lab1. Type "A", then press t he Select key. Ve r ify the test signal 1 Check the clock pul se wid t h. Usin g the osci lloscope, verify that the clock pu lse wi dth is 3.
c In the osci l losc ope Mea sure m enu, se lect Measure Chan 2 , t hen selec t Pe riod. I f the period i s more than or equal to 2 0.00 0 ns, go to step 4. I f the period i s les s than 20.000 ns but greate r than 19.75 ns , go t o ste p 3. d In the osci l losc ope Time base menu, add 10 ns to the delay.
Check the setup/h old comb ination 1 Select the lo gic anal yzer setup /h old time. a In the l ogic a naly zer F orm at me nu, sel ect M aster Clock. b Select the Se tup/Hold field, then s elect the setup/ hold com bination to be tested for all pods. The firs t ti me through this tes t , use the top combinat ion in the f ollowi ng tabl e.
c Adjust the puls e generator channel 1 Delay, then s elect P recision Edge Find in th e oscil loscope Delta T menu. Repeat this s tep unti l the pul ses a re ali gned ac cording to the s etup time of t he setup/hol d combi nation selec ted, +0. 0 ps or − 10 0 ps.
5 Note: This ste p is o nly d one the fi rst time through the test, to create a C ompare file. For su bsequ e n t runs, go to step 6. Use th e fo llowi ng to cr eate a Co mpare file: a Pres s Run. The dis play should show a checkerboard patte rn of alternati ng A s and 5s.
10 Using th e Delay m ode of th e pu lse gen erator cha n nel 1, position the pu lses acc ording t o th e setup / hold comb ination sel ected, + 0 . 0 ps or − 10 0 ps. a In the osci l losc ope Delt a V m enu, set the Marker 1 Pos i t ion to Chan 1, then set Marker 1 at − 1 .
12 Press the b lue shi f t ke y, then p ress the Run key. If 2 - 4 ac qu isiti ons are o btaine d without th e "Stop Condition S atisfied" message appeari ng, then the test pass es. Press Stop to halt the a cqu isition . R ecord the Pass or Fa i l resu lts in t he performa nce test record.
To test the mul tiple-c l ock, multipl e-edg e, sta te a cqui s ition Tes ting the multipl e-clock, multiple - e dge , state acquisitio n verifies the performan ce of th e foll owin g s pecifi cations: • Minimum master to master clock t ime. • Maximum state acqu isition spee d .
3 Se t u p the osc illoscop e. Osc i llosco pe Setup Time Base Display Delta V Delta T Time/Div: 1.00 ns/div avg V marker s on T marker s on # of avg : 16 marker 1 pos ition: Chan 1 start on: Pos Edg e 1 screen : du al mark er 2 posit ion: Chan 1 stop on : Ne g E dge 1 Channel C hannel 1 Channe l 2 Di spl ay on o n Probe At ten 20.
2 Set u p the Format menu. a Pres s the For mat key. Sele ct Stat e Acqui sition Mode, then sel ect Full Channel/4 K Memory/ 50MHz . b Sel ect t he fiel d to the rig ht of each Pod field, then s elect ECL. 3 Set u p the Trigger menu. a Pres s t he Tri gger key .
Connect the logic analyzer 1 Using the 6 -by-2 test con nec tors, con nec t the logi c ana lyzer cl oc k an d data ch annel s listed in the follow i ng t a ble to th e pu lse gen erato r. Install a BNC cable betwee n the pulse genera t or c h annel 2 o utput a n d th e 6x2 test con n e ctor with the lo gic a nalyzer clo ck l ead s .
c Pres s the Tri gger key . Ma ke sure pattern term a is "A". If not, se lect the field next to "a" unde r the label Lab1. Type "A" the n press the Sel ect ke y . Ve r ify the test signal 1 Check the clock pul se wid t h.
c In the osci l losc ope Mea sure m enu, se lect Measure Chan 2 , t hen selec t Pe riod. I f the period i s more than or equal to 2 0.00 0 ns, go to step 4. I f the period i s les s than 20.000 ns but greate r than 19.75 ns , go to s tep 3. d In the osci l losc ope Time base menu, add 10 ns to the Delay.
Check the setup/h old with single clock edges, multip le clocks 1 Select the lo gic anal yzer setup /h old time. a In the l ogic a naly zer F orm at me nu, sel ect M aster Clock. b Select and ac tivate any two clock edges. c Select the Se tup/Hold field and sele ct the s etup/hold to be te sted for all pods.
c Adjust the puls e generator channel 1 Delay, then s elect P recision Edge Find in th e oscil loscope Delta T menu. Repeat thi s s tep until the pul ses are al igned according to the s etup time of t he setup/hol d combi nation selec ted, +0. 0 ps or − 10 0 ps.
5 5 If yo u have not already created a Compar e file for the prev ious test (sing le-c lock, sing le-e dge state acq uisitio n, pa ge 3-3 1), use the fol lowing steps to create one. For subseque nt passes t hrough this t est, s kip this step and go to st ep 6.
9 Using th e Delay m ode of th e pu lse gen erator cha n nel 1, position the pu lses acc ording t o th e setup time of th e setup/ h old co mbinatio n sele cted, +0 .0 ps o r − 100 ps. a In the osci l losc ope Delt a V m enu, set the Marker 1 Pos i t ion to Chan 1, then set Marker 1 at − 1 .
11 Press the b lue shift k ey, then p ress the Ru n key. If 2 - 4 acqu isitions a re ob tain ed without th e "Stop Condition S atisfied" message appeari ng, then the test pass es. Press Stop to halt the a cqu isition . R ecord the Pass or Fa i l resu lts in t he performa nce test record.
To tes t the si ngle -cloc k, m ulti ple -edg e, sta te a cquisi tion Tes ting the sing le-clock, multipl e-edge, state acqui sition verifies the perfor m ance of the following specificati o ns: • Minimum master to master clock t ime. • Maximum state acqu isition spee d .
3 Se t u p the osc illoscop e. Osc i llosco pe Setup Time Base Display Delta V Delta T Time/Div: 1.00 ns/div avg V marker s on T marker s on # of avg : 16 mark er 1 pos i tion: Chan 1 start on : Neg Edge 1 screen: dua l marker 2 position: Cha n 1 s top on: Neg E dge 2 Channel C hannel 1 Channe l 2 Di spl ay on o n Probe At ten 20.
2 Set u p the Format menu. a Pres s the For mat key. Sele ct Stat e Acqui sition Mode, then sel ect Full Channel/4 K Memory/ 50MHz . b Select the f i eld to the right of each pod fi eld, then sel ect ECL. 3 Set u p the Trigger menu. a Pres s t he Tri gger key .
Connect the logic analyzer 1 1 Using the 6 -by-2 test con nec tors, con nec t the logi c ana lyzer cl oc k an d data ch annel s listed in the follow i ng t a ble to th e pu lse gen erato r. Install a BNC cable betwee n the pulse genera t or c h annel 2 o utput a n d th e 6x2 test con n e ctor with the lo gic a nalyzer clo ck l ead s .
c Pres s the Tri gger key . Ma ke sure pattern term a is "A". If not, se lect the field next to "a" unde r the label Lab1. Type "A" the n press the Sel ect ke y . Ve r ify the test signal 1 Check the clo ck p eri o d. Using th e oscil losco pe, verify that the clock period is 20 ns, +0 ps o r − 2 50 ps .
2 Check the da t a pul s e w i dth. Usin g the osci lloscope, verify tha t the data p ulse width is 4.000 ns, +0 ps or − 100 ps. a In the osci l losc ope Time base menu, select Sweep Speed 1. 00 ns/ div. b Select Delay. Usi ng the oscill oscope knob, pos ition the data waveform (Channel 1) so that t he waveform i s centered on t he sc reen.
Check the setup/h old comb ination 1 Select the lo gic anal yzer setup /h old time. a In the l ogic a naly zer F orm at me nu, sel ect M aster Clock. NOTE The first ti me through this tes t , a ss ign the clocks according to the firs t tes ting combinat ion in step 3 of these proce dures.
c Adjust the puls e generator channel 2 Delay, then s elect P recision Edge Find in th e oscil loscope Delta T menu. Repeat this s tep unti l the pul ses a re ali gned ac cording to the s etup time of t he setup/hol d combi nation selec ted, +0. 0 ps or − 10 0 ps.
6 Test the n ext c l ock. a Pres s t he For m at key, then select Mas ter Clock. b Turn of f and d isconnec t the clock jus t teste d. c Repeat steps 3 and 5 for the next clock listed in the table in step 3, unt il all lis ted clock edges hav e been tested.
To test the tim e inte rva l a ccura cy Testin g the time interval accuracy doe s not check a s p ecification, but does check the following : • 125 MHz osci llator This test verifie s that the 125 MH z timing acquisition synch ro n izing oscill ator is operatin g within limi ts.
3 Set up the functio n gen erator accord ing t o t he follow ing tab le. Funct ion G ener ator Set up Freq: 20 0 000 . 0 Hz Main Fu n ction: Squa re wave Amptd: 3.00 0 V High V oltage: Disab l ed (L ED Off) Phase: 0.0 de g DC Off set: 0.0 V Set up the logic analyzer 1 Set up the C onfi gur ation menu .
2 Set u p the Format menu. a Pres s t he For mat key. Select T iming Acquis ition Mode, then selec t Tra nsiti onal Full Channel 125 MHz . b Sel ect t he fiel d to the right of the Pod 1 fiel d, then selec t ECL. c Select the f ield showing the channe l ass ignments for P od 1.
4 Set u p the Wavefo rm menu . a Pres s the Waveform key. b Move the curs or to the s ec/Div fi e l d, the n use the RPG knob to dial in 2.00 µ s. c Select the Markers Off fiel d, the n sel ect P attern. d Select the Spe cify Pa tterns fi eld. Sele ct X ente ring 1 and O entering 1 .
Acquire the da t a 1 Enab le the pulse gener ator ch annel 1 outp ut (wi th th e LE D off). 2 Press the bl ue key, then p ress the Run key to selec t Run-Re petitive. Allo w the l ogic analyzer to a cquire data for at least 100 va l id r u ns as indic ated in the pa t ter n statistic s field.
Perform ance Te st Rec ord Performa nce Tes t Record 1664A Lo gic Analyzer _______ Serial No.______________________ Work Order No .___________________ Recommended T est Interval - 2 Year/ 4000 hours D.
Performa nce Tes t Record ( continued ) Tes t Sett ings Res ults Single-Cl ock, Singl e -Edge Acquis ition Pas s/Fa i l Pass/ Fail Set up/ Ho l d T ime 3.5/ 0.0 ns J ↑ K ↑ ________ ________ J ↓ K ↓ ________ ________ Set up/ Ho l d T ime 0.0/ 3.
4 Logic anal yzer cali brat ion 4 -2 To adjust the C RT moni tor alig nment 4-3 To adjust the C RT inte nsity 4 -5 Calibrating and Adjusting.
Cal ibrating and Adj usting This chap ter gives you instr uctions for calibr ating and adjus tin g th e lo gic an alyzer . Adju stmen ts to the logic analyzer incl ude adjustin g the CRT mo nito r as semb ly. To period ically veri fy the performance of the analyzer, refer to "Te sting Performance " in chap ter 3.
To adj ust the CR T monitor a l ignme nt WA RNING Do not touch the CRT m onitor s weep board. Hi gh vol tages exi st on t he sw eep boa rd that can cause personal injury.
4 Enter the S ys PV tests , then enter th e Displa y Te st . A grid pat tern shoul d appear. 5 If the d ispl ay is tilted (rotated ) , adju st the C RT yo k e by rota t ing it to straigh ten the display . 6 If the grid pattern is n ot cen t ered h orizon tally, adjust the H-Ho ld .
To adjust the C RT inte nsity WA RNING Do not touch the CRT m onitor s weep board. Hi gh vol tages exi st on t he sw eep boa rd that can cause personal injury.
WA RNING Do not touch the CRT m onitor s weep board. Hi gh vol tages exi st on t he sw eep boa rd that can cause personal injury. 7 The light p o wer meter sho u ld rea d 137 -154 c d/m 2 . If the measure ment is out o f this ran ge, use the a d jus t me nt tool to adjus t the Con trast poten tiometer o n th e mon itor driver boa rd .
5 To use the flowcharts 5-2 To check the power-up tests 5 -15 To run the self- tests 5-16 To t est t he power suppl y voltag es 5 -21 To test the CRT monit or signals 5-23 To t est t he keyboard signa.
Trou bleshootin g This chapter h elps you trou bleshoot the logic analyzer to find d efective assembli es. The troub les hooting consists of flowcharts, self - test ins tructi ons, and tests. This info rmation is not intend ed for component-le vel repai r.
Troubl eshoo t ing Fl owcha r t 1 Troubles hooting To use t he flo wchart s 5–3.
Troubl eshoo t ing Fl owcha r t 2 Troubles hootin g To use the fl owchar t s 5– 4.
Troubl eshoo t ing Fl owcha r t 3 Troubles hooting To use t he flo wchart s 5–5.
Troubl eshoo t ing Fl owcha r t 4 Troubles hootin g To use the fl owchar t s 5– 6.
Troubl eshoo t ing Fl owcha r t 5 Troubles hooting To use t he flo wchart s 5–7.
Troubl eshoo t ing Fl owcha r t 6 Troubles hootin g To use the fl owchar t s 5– 8.
Troubl eshoo t ing Fl owcha r t 7 Troubles hooting To use t he flo wchart s 5–9.
Troubl eshoo t ing Fl owcha r t 8 Troubles hootin g To use the fl owchar t s 5– 10.
Troubl eshoo t ing Fl owcha r t 9 Troubles hooting To use t he flo wchart s 5– 11.
Troubl eshoo t ing Fl owcha r t 10 Troubles hootin g To use the fl owchar t s 5– 12.
Troubl eshoo t ing Fl owcha r t 11 Troubles hooting To use t he flo wchart s 5– 13.
Troubl eshoo t ing Fl owcha r t 12 Troubles hootin g To use the fl owchar t s 5– 14.
To check the power-up tests The logic analyzer autom atically performs power-up tests when you apply power to the instrument (during the boot-up seq uence). T he revision number of the operating system shows in the upper-right corner of the screen during these power-up tes ts .
To run the self-tests Self-tes t s identify the correct operatio n of major functional areas of the instrum ent. You can run all s elf-te sts without accessing the interior of the instrume nt. If a self-test fails, th e troub leshooting flowcharts i nstruct yo u to chang e a part of the instrument .
6 Select Run, then se lect Si ngle. The te s t runs one ti me, th e n the screen show s the resul ts . W hen th e test is finishe d , se lect Done. To run a test cont inuously, select Re petitive . Se lect Sto p t o hal t a Run Repetitive. 7 Select B oard Tests, then sel ect Run.
10 Select the Pri nter/Co ntroller field next to Sys PV. Sele ct System Test an d press th e Select k ey t o acce s s the system tests. You can run all t ests at one time by running All System Tests. To see more details about each test, you can run e ach test individually.
For a Single run, the test runs one tim e, and the screen shows the results. 13 To exit t he ROM Test, sel ect Don e . No t e that th e status chan ges to Passed or Fa iled. 14 Install a f ormatted disk t hat is n ot wr ite pro tected into the disk drive .
17 17 To exit the te s ts, press the System key, t hen sel ect Ex it Test i n th e pop-u p men u and pre ss the select key. Re install th e disk con t aini n g the ope rating system, then selec t Exit Test System an d press the select k ey. If you are performing the self-test s as part of the troub leshooti ng flowchart, return to th e flowchart.
To test t he p o wer supply voltages To check t he volt ages, the power supply must be l oaded by eit her the acq uisiti on board or with an added resis t or. Refer to chapter 6, "Replacing Assem b lies, " for inst ructions to remove o r replace co vers and asse mblies .
6 Check for the vo ltage s o n the power sup ply cabl e usin g the values in th e f ollo wing tabl e. Sig nals o n the Pow er Suppl y Ca ble Pi n S ignal Pi n Si gnal 1 +5.
To test t he CRT monitor signals Refer to chapter 6, "Replacing Assem b lies, " for inst ructions to remove o r replace co vers and asse mblies . WA RNING Haz ard vol tages exis t on t he powe r suppl y , t he CRT, a nd the CRT driver boa rd.
To test the keyboard signals Refer to chapter 6, "Replacing A ssemblies, " for inst ructions to remo ve covers and assemb lies. WA RNING Haz ard vol tages exis t on t he powe r suppl y , t he CRT, a nd the CRT driver boa rd.
To test the disk drive volt ages Refer to chapter 6, "Replacing Assem b lies, " for inst ructions to remove o r replace co vers and asse mblies . WA RNING T h is procedure i s to be performed by s ervice- trained personnel aware of the haz ards involve d, s uch as fire and e l ectric a l s hock.
6 Check for the fol lowin g vol tages an d si gna ls u sing an oscillosc o pe. Disk D rive Volt ages P in Si gn a l D e sc r ip ti o n P in S ig n al D es c rip ti on 1 NC 2 Disk Chan ge 3 NC 4 High D.
To perf o rm t he BNC test Equipme nt Requi red Equip me nt Criti cal Spec i ficat ion Recommen ded Mode l /Pa r t Digitizin g Oscilloscope 100 MHz Ba ndwidth Ag i lent 5 4 600 A BNC Shorting Cap 1250- 0074 BNC Cable Agilent 105 0 3A BNC-Bana na Adapter 125 1 -2277 1 Press the Config k ey.
To test t h e logic analyzer probe cables This test allows you to functi onally veri fy the pro b e cab le and prob e tip as sembly of any of the logic anal yzer po ds. Only o ne probe cab le can be t este d at a ti me. Repeat this test for each prob e cable to be tes ted.
4 Set u p the Format menu. a Pres s the Fo rm at key. b Move the cursor to the f ield show ing the channel a s si gnments for the pod under t e st. Pres s the Clea r Entry key unti l the pod channels are all as signed (all as terisks (*)). Pres s the Done key.
e Select the f i eld to the right of the pod being t ested, then s elect T TL . 5 Set u p the Trigger menu. a Pres s the Tri gger key . b Sel ect Cl ear T rigger, then sele ct All. 6 Se t u p the Lis ting men u. a Pres s t he Li st key. b Sel ect t he fiel d to the rig ht of Base, then s elect Binary.
7 Using four 6- by-2 te s t co n nector s, fou r BNC Cou plers, and fo ur SMA (m) - BNC (f) Adap t e rs, conn ect the l o gic anal yzer to the pulse gener ator ch annel outp uts. To make the test connecto rs, see c h apte r 3, "Testin g Perfor mance.
To test the auxiliary power The +5 V aux iliary powe r is prot ected b y a curre nt o verload protect ion device . If the current on pins 1 and 39 e xceed 0.3 3 amps, t he ci rcuit will open. When t he s hort is removed, t he circuit will reset in approxi mately 1 minute.
6 To remove and replace t he Handle 6 -5 Feet and tilt stand 6-5 Cover 6 -5 Disk drive 6-6 Power supply 6-7 Main circuit b oard 6 -7 Switch actuat or assem b ly 6 -8 Rear pane l assemb ly 6- 9 Front p.
Rep lacing Assemblie s This chap ter contain s the i nstru ctions for removing and replacin g the assemb lies o f the log ic an alyzer. Al so in this chapter are instru ctions for returning assembl ies. WA RNING Haz ardous volt ages exi st on the power supply, the CRT , and the CRT dri ver board.
Exp l o de d Vi ew Li st in g A1 Main c ircuit bo ard MP3 Fa n guard MP 32 Spacer A2 Ke ybo ard MP4 Rea r pa ne l MP3 3 Labe l A3 Switch a ctuator MP 5 Line filt er A 4 P r ob e c a bl e M P 6 Ha n dl.
Explo ded View of the 16 6 4A Replacing A ssemblies 6– 4.
To remove and replace the handle • Remove the tw o scre ws in the end caps, then lift o ff the han dl e. To remove and replace the feet and tilt stand 1 Re move th e sc rews co n nectin g the four rea r fe et to th e instru ment. 2 Separ ate the rear fe et from t he in s trumen t to re move them.
To remove and replace the d isk drive 1 Using p rev io u s pro cedure s , remo ve the followin g assembl ies: • Handle • Rear Fee t • Cover 2 Disco nnect t he disk d rive cable from th e rear o f the disk d riv e. 3 Remove the two scre ws that attach the disk drive b racket to the power supply.
To remove and replace the power supply 1 Using p rev io u s pro cedure s , remo ve the followin g assembl ies: • Handle • Rear Fee t • Cover • Disk D rive WA RNING Haz ardous volt ages exi st on the power supply. To a void elect rical s hock, disconnect the power from the ins trument before perf orming the following procedures .
To remove and replace the swit ch act uator assembly 1 Using p rev io u s pro cedure s , remo ve the followin g assembl ies: • Handle • Rear Fee t • Cover • Disk D rive • Power Supply • Main Circuit b oa rd 2 Make s ure the pow er swi t ch is in the of f positio n .
To remove a nd replace the rear panel assembly 1 Using p rev io u s pro cedure s , remo ve the followin g assembl ies: • Handle • Rear Fee t • Cover 2 Re move th e sw itch a ctuato r cab le from the line filte r acco rding to "To remov e and replac e the switch actua t or assembl y .
To remove and replace the f ront panel and keyboard 1 Using p rev io u s pro cedure s , remo ve the followin g assembl ies: • Handle • Rear Fee t • Cover • Disk D rive • Power Supply • Main Circuit b oa rd 2 Re move th e fo ur scr ews co n n ecting th e fron t pan el.
To remov e and replace the monitor 1 Using p rev io u s pro cedure s , remo ve the followin g assembl ies: • Handle • Rear Fee t • Cover • Disk D rive • Power Supply • Main Circuit b oa rd • Rear Panel WA RNING Haz ardous volt ages exi st on the CRT and t he CRT drive r board.
To remove and replace the f an 1 Using p rev io u s pro cedure s , remo ve the followin g assembl ies: • Handle • Rear Fee t • Cover • Disk D rive • Power Supply • Rear Panel 2 Disco nnect t he fan ca ble fro m the main circ uit bo ard. 3 Re move th e fo u r fan sc rews.
To remov e and replace the option al GPIB and RS-232C cab les 1 Using p rev io u s pro cedure s , remo ve the followin g assembl ies: • Handle • Rear Fee t • Cover • Disk D rive • Power Supply • Rear Panel 2 Disco nnect interface cables from the main ci rcu it b oard.
To return as sem blies Before shi pping the l ogic analyzer or assemb lies to Agilent T echnolo gies, co ntact your neare s t Agilent Technologi es sales office for additional details. 1 Wr ite the foll owing i nfor mation on a tag and a ttach it to th e pa rt to be returne d .
7 Replaceabl e Parts Ordering 7–2 Explo ded View 7–3 Replaceabl e Parts List 7– 4 Power Cables and Plug Co nfigurations 7–8 Replac eable Parts.
Rep lacea ble Pa rt s This chapter co ntains informati on fo r iden tifying an d orde ring re placeable parts for you r l ogic analy zer. Replaceable Parts Ordering Parts listed To o rder a part on t .
Explo ded View Explo ded view o f the 1 6 64A l og ic an alyzer. Replaceab le Parts Explod ed View 7–3.
Replaceable Parts Lis t The repl aceable parts l i st is organized b y reference de s ignatio n and shows e xchange asse mblies , electri cal assemb lies, then othe r parts. The exploded view does not show all of the parts in the replaceable parts list.
1664 A Replacea ble Part s Ref . Des. Ag il en t P art Nu mber Qty Des c ript ion Exchang e Board 016 6 4-695 0 1 Exchang e main circuit as sembly Replacement Parts A1 016 6 4-6 6501 1 Main c i rcuit .
1664 A Replacea ble Part s Ref . Des. Ag il en t P art Nu mber Qty Des c ript ion H25 125 2 -2220 1 Cable Retaining Clip-34-pin conn ector (Disk drive cable) MP1 0 1 660 - 616 0 6 1 Intensit y adju s .
1664 A Replacea ble Part s Ref . Des. Ag il en t P art Nu mber Qty Des c ript ion W7 0 1650 - 616 01 1 Monito r sweep cable O p tio n #0 20 E5 016 5 0-6 3 202 1 RS- 232 loopback conne ctor H26 0 380- 1 482 2 Hex stando f f (GPI B Cab le) H27 2 1 90- 0 0 09 2 WIL .
Power Cables an d Plug Configurations This instrum ent is e quipped wit h a three- wire power cab le. The type of power cabl e plug shipped wit h the inst rument depe nds on the country of des tination. The W 10 reference designato rs (t a ble, previous page) show opti on numbers of available power cables and plug configurati ons.
8 Block-L evel The ory 8- 3 The 166 0 Series Log ic Analyz er 8-3 The Lo gic Acq uisitio n Circuit ry 8-6 Self-Te s ts D escriptio n 8-9 Power- up Self-Tests 8 - 9 Syst em Te sts (Syst em PV) 8-10 Ana.
The ory of Op eration This chap ter tells the theory of operatio n for the logic analyzer and descri bes the sel f- te sts. The infor m ati on in this chapter is to help you und erstand h ow th e lo gic anal yzer o perates and what the sel f -tests are testin g.
Bloc k-Lev el The ory The block-le vel theor y is divid ed into two parts : theory for the logic analy zer and the ory for the main circuit board . A block diagram is shown with each theory .
1664A T heory CPU Located on the m ain circuit bo ard, the mi croprocessor is a Motorola 68EC02 0 running at 25 MHz . The micropro cessor contro ls all of the functions of the logic analyzer including processing and stori ng data, dis playing data, and configuring the acq uis itio n ICs to obtai n and store data.
External Keyboard Interface Agilent proprietary ICs make up the external keyb oard interface. The ICs e st abli s h a l ink with the control ler IC on the ext ernal keybo ard. T he keyb oard signals are route d through the acquisit ion circuit board to the CPU board.
The Logic Acquisition Circuitry The Mai n Cir cuit B oard L og ic A cquis i t ion Ci rcui try The ory of Operat ion The Lo gic Ac quisi t ion Ci rcuitry 8– 6.
Main C ircuit Bo ard Logic Acqu isition Theo ry Probin g The probi ng circuit includes the prob e cable and terminat ions. T he prob e cabl e consist s of two 1 7-channel pods which are connecte d to t he circuit bo ard using a high-densi ty connector.
Clock opti mizati on involve s using programmab le delay s on b oard the IC t o pos it i on the maste r clock transit ion where valid data is captured. This procedure greatly reduces the effects of channel-to -channel skew and o ther propagat i on delays.
Self-Te sts De s cription The self-tests iden tify the correct oper ation of major function al areas i n th e l ogic anal yzer. Th e s elf-tests are not intend ed for component-le vel diagn ostics.
RAM T est The RAM t est checks the video RAM (VRAM) , syst em dynamic RAM (DRA M), and static RAM memory withi n the real time clock IC. The microproces sor first performs a write/read in each memory locatio n of the VRAM. A t each VRAM me mory lo cation a t e st pat tern is wri t ten, re ad, and compared.
GPIB Test The GPIB test performs a write/ read operati on to each of the registe rs of the G PIB IC. A test pattern is writte n to each register in the GPIB IC. The pattern is then read and compared with a k nown value. The GPIB test will ret urn a valid "P ass" or "F ail" st atus even i f opt ion 02 0 is not inst alled .
Perform Test All Selecting Perform Test All will initiat e all of the previo us functional verificatio n test s in the order they are listed. The failure o f any or all of the tests will be repo rted in the test menu field of each of the tests. The P erform All Test will not init iate t he F ront Panel Test or th e Display Test.
Analyzer Tests (Analy PV) The analy zer te st s are funct ional perfo rmance verificat i on tests . There are three types o f analyzer tests: the Board Test, the Chip Test, and the Data Input Inspectio n.
Resou rce Test The pattern, range, edge , and g litch reco gnizers are test ed and verified. First , the t est regi ster is verified for correct operati on. N ext, the pattern co mparators are teste d to ens ure that e ach bit in t he recogniz er memo ry locat ion as wel l as the logic driver/recei ver are operat ing.
GPIB ( Optional) The Gen eral Purpose Interface bus (GPIB ) is Agilen t Technologi es’ implemen tation of IEEE Standard 488-1978 , "Standar d Digital Interface fo r Programming Instrumen tation." GPIB is a carefully defin e d interface that simpli f ies the inte gration of vari ous instr uments and compu ters into syste ms.
RS-23 2C(Optiona l) The logic analyzer interfaces with RS-232C communicatio n l ines throu g h a stand ard 25 pin D connector. The logic analy zer is compatibl e with RS-232 C proto col.
Centr onix The logic analyzer i n terfaces with Centro nix (parallel printe r) communication lines thr oug h a stan dard 25 pi n D connector . The logic anal yzer is co m patib le with Ce ntronix protoco l. BUSY is used to i ndicate when data can be transfered from the log ic an alyzer to th e p rin ter.
8– 18.
DECLARA TION OF CO NFO RMITY according to IS O/IEC Gu ide 22 and EN 45014 Manuf ac turer’ s Name: A gilent Technol ogies Manuf a cturer’ s Address: 1 900 Garde n of t he Gods Roa d Colorado Springs , CO 809 01 U.
.
Copyr ight Ag i lent Techn ologie s 1987–2000 All Rig hts Rese rved. Reprod uc t ion, ad aptati on, or tra n slati o n wi thou t prior wri t ten permi ssio n is pr ohibit ed, exce pt as allowed under the copyrig ht l aws. Docume nt Wa rra nty The informati on contained in t his document is su bject to chan ge without noti ce.
Produc t War ranty This Ag i lent Technologies prod uct has a war ranty against defects i n mate r i al a n d workman ship for a period of on e year from date of shipment . During the warranty period, Ag i lent Te ch nologi es wil l , at it s opti on, either repair o r re place p rodu c ts that prove to be defe cti ve.
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