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USBS6 V 0.3 June 29, 2010 User Manual C1030-5510 SP A RT AN-6 TM FPGA board with U SB2.0, SPI-Flash and JT A G interface. Order number: C1030-5510 USBS6 / C1030-5510 http://www .
C o p y r i g h t i n f o r m a t i o n Copyright © 2010 CESYS GmbH. Al l Rights Reserved. The information in this document is proprietary to CESYS GmbH.
O v e r v i e w S u m m a r y o f U S B S 6 USBS6 is a low-cost multilayer PCB with SP AR T AN-6 TM FPGA and USB 2.0 Interface. 34 I/O balls of the FPGA a re available on standard 2.54mm h eaders, 81 I/O balls can be reached through a industry standard VG 96-pin connector .
H a r d w a r e B l o c k D i a g r a m S p a r t a n - 6 T M F P G A XC6SLX16-2CSG324C FPGA features: Logic cells 14,579 Configurable logic blocks (Slices / Flip-Flops) 2,278 / 18,224 Max distributed.
USBS6 / C1030-5510 http://www . cesys.com/ User Doc V0.3 -5- preliminary Figur e 2: USBS6 T op V iew.
P o w e r i n g U S B S 6 USBS6 ma y be use d bus-powered (see SW2 below) without the need of any external power supply other than USB. In this mode VCCO_IO on J3,PIN A3, B3, C3 sourcing capability is limited due to the fact, that USB power supply current is limited dependi ng on which system is used as host.
! It is strongly recommended to check XILINX TM UG381 about Spartan-6 FPGA SelectIO Signal Standards on XILINX TM website. C o n f i g u r a t i o n Configuration of USBS6 can be accomplished in several ways: JT AG, SPI-Flash or USB. The default configuration mode is booting from SPI-Flash.
FPGA the reader is encouraged to take a lo ok at the user guide UG380 on XILINX TM web page. U S B 2 . 0 c o n t r o l l e r CYPRESS TM FX2LP TM is a highly integrated, low power USB2.0 microcontroller , that integrates USB2.0 transceiver , serial interface engine (SIE), enhanced 8051 micro- controller and a programmable peripheral interface.
USB2.0 FX2LP TM Microcontroller CYPRESS TM CY7C68013A Signal Name FPGA IO Comment FX2_FD1 1 U13 FX2_FD12 V13 FX2_FD13 U10 FX2_FD14 R8 FX2_FD15 T8 E x t e r n a l m e m o r y USBS6 offers the opportu nit y to use v arious external memory architectures in one´s FPGA design.
LPDDR SDR A M MT46H64M16LFCK-5 Signal Name FPGA IO Comment MCB1_RAS_n K15 Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. * MCB1_CAS_n K16 MCB1_WE_n K12 MCB1_CS_n -- MCB1_CKE_n D17 Clock enable: CKE HIGH activates, and CKE LO W d eactivates, the internal clock signals, input buf fers, and output drivers.
LPDDR SDR A M MT46H64M16LFCK-5 Signal Name FPGA IO Comment MCB1_DQ12 T17 MCB1_DQ13 T18 MCB1_DQ14 U17 MCB1_DQ15 U18 MCB1_UDQS N15 Data strobe for Upper Byte Data bus: Output with read data, input with write data. DQS is edge-aligned with read data, center-align ed in write data.
configurable LEDs allow to make internal monitoring status signa ls visible by driving the appropriate FPGA IO to a H IGH level. LEDs Signal Name FPGA IO Comment SYS_LED0 -- Internal 5V power supply . SYS_LED1 -- Power OK- signal from onboard voltage regulator .
HEX rotary DIP s w itch DIAL FPGA Pin N8 FPGA Pin M1 1 FPGA Pin M10 FPGA P in N9 5 0 1 0 1 6 1 0 0 1 7 0 0 0 1 8 1 1 1 0 9 0 1 1 0 A 1 0 1 0 B 0 0 1 0 C 1 1 0 0 D 0 1 0 0 E 1 0 0 0 F 0 0 0 0 FT232R from FTDI is a USB to serial UART interface.
J3 VG 96-pin external expansion connector PIN FPGA IO Comment PIN FPGA IO Comment PIN FPGA IO Comment A32 -- GND B32 -- GND C32 -- GND A31 F13 VG96_IO78 B31 E13 VG96_IO79 C31 C4 VG96_IO80 A30 F12 VG96.
J3 VG 96-pin external expansion connector PIN FPGA IO Comment PIN FPGA IO Comment PIN FPGA IO Comment A7 N2 VG96_IO9 B7 N1 V G96_IO10 C7 N4 VG9 6_IO1 1 A6 P2 VG96_IO6 B6 P1 VG96_IO7 C6 N 3 VG96_IO8 A5.
J4 IDC 2x25-Pin external expansion connector PIN FPGA IO Comment PIN FPG A IO Comment 25 B1 1 ADD_IO16 26 A1 1 ADD_IO17 27 B12 ADD_IO18 28 A12 ADD_IO19 29 B14 ADD_IO20 30 A14 ADD_IO21 31 B16 ADD_IO22 .
F P G A d e s i g n C y p r e s s F X - 2 L P a n d U S B b a s i c s Several data transfer types are defined in USB 2.0 specificati on. High-speed bulk transfer is the one and only mode of interest to end users. USB transfers are packet ori ented and have a time framing scheme.
In FPGA designs with multiple clock domains asy nchronous FIFOs have to be used for transferring data from one clock domain to the other and compre hensive control signals have to be resynchronized.
VHDL. V erilog and schematic entr y desig n flows are not supported. • The design “usbs6_soc” demonstrates the implem entation of a system-on-chip (SoC) with host software access to the peripherals like GPIOs, externa l Flash Memory , LPDDR Memory and internal BlockRAM over USB.
After ProgramFPGA() is called and the FPGA design is completel y download ed, the pin #RESET (note: t he prefix # means, that the signal is active low) is automatically pulsed (HIGH/LOW/HIGH). This signa l can be used for resetting the FPGA design. The API- function ResetFPGA() can be called to initiate a pulse on #RESET at a user given time.
HARDW ARE-CIRCUITS OR AN Y OTHER KIND OF ASIC OR PROGRAMMABLE LOGIC DESIGN), EVEN IF THE COPY RIGHT HOLDER HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. D e s i g n “ u s b s 6 _ s o c ” An on-chip-bus system is implemented in this design. The VHDL so urce code shows you, how to build a 32 Bit WISHBONE based shared bus architecture.
(BFM), too. These can be use d for behavioral simulation purposes. src/usbs6_soc_top.vhd: This is the top level entity of the design. The WISHBONE components are instantiated here. src/wb_intercon.vhd: All WISHBONE devices are connected to this shared bus interconnectio n logic.
programming FPGA configuration bitstream to SPI-FLASH and the other accesses QUAD- SPI-FLASH for storing nonvolatile application data. src/wb_sl_mcb.vhd: WISHBONE adapter for one port of Spartan-6 TM build in multiport memory c ontroller block (MCB). src/wb_sl_uart.
The upper waveform demonstrates the behavior of app_fifo_wr_full_o and app_fifo_wr_count_o when there is no transaction on the slave FIFO controller side of the FIFO. During simultaneous FIFO-read- and FIFO-write-transactions, the signals do not change.
src/sync_fifo.vhd: This entity is a general purpose sy nchronous FIFO buffer . It is build of FPGA distributed RAM. src/sfifo_hd_a1Kx18b0K5x36.vhd: This entity is a general purpose sy nchronous FIFO buffer with mismatched port widths. It is build of a FPGA BlockRAM.
incremented automatically in block transfers. Y ou can find details on enabling/disabling the burst mode and address auto-increment mode in the CESY S application note “ T ransfer Protocol for CESYS USB products” and soft ware API documentation. CESYS USB transfer protocol is converted into one or more WISHBONE data transaction cycles.
The WISHBONE signals in these illustrations and explanations are sh own as simple bit types or bit vector types, but in the VHDL code these signals could be encapsulated in extended data types like arrays or records. Example: ... port map ( ... ACK_I => intercon.
WISHBONE cycles. It is a reduced version of “usbs6_soc” example implem enting a single BlockRAM slave. Files and modules src/wishbone_pkg.vhd: See chapter “Design usbs6_soc ” src/usbs6_bram_top.vhd: This is the top level module. It instantiates FX-2 module as a WISHBONE master device (wb_ma_fx2.
wb_sl_bram_tb.cmd: Win32 batch file automatically starting ModelSim with example testbench and ap propriate simulation script (wb_sl_bram_tb.do). Just doubleclick for running the demo! USBS6 / C1030-5510 http://www .
S o f t w a r e I n t r o d u c t i o n The UDK (Unified Development Kit) is used to allow developers to communic ate with Cesys's USB and PCI(e) devices. Older releases were just a releas e of USB and PCI drivers plus API combined with some shared code components.
W i n d o w s Requirements T o use the UDK in own projects, the following is required: • Installed drivers • Microsoft V isual Studio 2005 or 2008; 2010 is experimental • CMake 2.6 or higher ⇒ http://www .cmake.org • wx W idgets 2.8.10 or higher (must be build separately ) ⇒ http://www .
lets assume to use c:udkapi . c: cd udkapi CMake allows the build directory separated to the source directory , so it's a good idea to do it inside an empty sub-directory: mkdir build cd build The following code requires an installation of CM ake and at least one supported Vis ual Studio version.
Linux There are too many distributions and releases to of fer a unique w a y to the UDK installation. We've chos en to work with the most recent Ubuntu release, 9.10 at the moment. All commands are tested on an up to date installation and may need som e tweaking on other systems / versions.
following command has to be done: sudo make install This will do the following things: • Install the kernel module inside the module library path, update module dependencies • Install a new udev rule to give device nodes the correct access ri ghts (0666) (/etc/udev/rules.
Build drivers: cd PlxSdk/Linux/Driver PLX_SDK_DIR=`pwd`/../../ ./buildalldrivers Loading the driver manually requires a successful buil d, it is done using the following commands: cd ~/udkapi2.
the application that uses it. Otherwise unwanted side ef fects in exception handling w ill occur ! (See example in Add project to UDK build ). USBS6 / C1030-5510 http://www .
U s e A P I s i n o w n p r o j e c t s C++ API • Include file: udkapi.h • Library file: • Windows: udkapi_vc[ver]_[arch].lib, [ver] is 8, 9 , 10 , [arch] is x86 or amd64 , resides in lib/[build] / • Linux: libusbapi.
.NET API • Include file: - • Library file: udkapinet.dll, resided in bin/[build] • Namespace: cesys.ceUDK The .NET API, as well as it example application is separated from the normal UDK buil d. First of all, CMake doesn't have native support .
Methods/Functions GetLastErrorCode A P I Code C++ unsign ed int ceException::GetErrorCode() C unsigned int GetLastErrorCode() .NET uint ceException.GetLastErr orCode() Returns an error code which is intended to group the error int o different kinds.
Device enumeration The complete device handling is done by the API internally . It manages the resources of all enumerated devices and of fers either a device pointer or handle to API users. Calling Init() prepares the API itself, while DeInit() does a complete cleanup and invalidates all device pointers and handles.
Enumerate A PI Code C++ static void ceDevice::Enumerate(ceDevice::ceDevice T ype DeviceT ype) C CE_RESUL T Enumerate(unsigned int DeviceT ype) .NET static void ceDevice.Enumerate(ceDevice.ceDeviceT ype DeviceT ype) Search for (newly plugged) devices of the given ty pe and add them to the internal list.
GetDevice A P I Code C++ static ceDevice *ceDevice::GetD evice(unsigned int uiIdx) C CE_RESUL T GetDevice(unsigned int uiIdx, CE _DEVICE_HANDLE *pHandle) .NET static ceDevice ceDevice.GetDevice(uint uiIdx) Get device pointer or handle to the device with the given index, which must be small er than the device count returned by GetDeviceCount().
Information gathering The functions in this chapter return valuable information. All except GetUDKV ersionString() are bound to devices and can be used after getting a device po inter or handle from GetDevice() only .
Return device type name of given device pointer or handle. Notice C API: pszDest is the buffer w ere the value is stored to, it must be at least of size uiDestSize. GetBusT ype A P I Code C++ ceDevice::ceBusT ype ceDevice::GetBusT ype() C CE_RESUL T GetBusT ype(CE_DEVICE_HANDLE Handle, unsigned int *puiB usT ype) .
Using devices After getting a device pointer or handle, devices can be used. Before transferrin g data to or from devices, or catching interrupts (PCI), devices must be accessed, which is done by calling Open(). All calls in this section require an open device, which must be freed by calling Close() after usage.
Finish working with the given device. ReadRegister A P I Code C++ unsigned int ceDevice::R eadRegister(unsiged int uiRegister) C CE_RESUL T ReadRegister(CE_DEVICE_HANDLE Handle, unsign ed int uiRegister , unsigned int *puiV alue) .
unsigned char *pucData, unsigned int uiSiz e, unsigned int uiIncAddress) .NET void ceDevice. WriteBlock(uint uiAddess, byte[] Data, uint uiLen, bool bIncAd dress) T ransfer a given block of data to the 32 bit bus system address uiAddress. Th e size should never exceed the value retrieved by GetMaxT ransferSize() for the specific device.
Pulses the FPGA reset line for a short time. This should be used to sync th e FPGA design with the host side peripherals. ProgramFPGAFromBIN A P I Code C++ void ceDevice::Progra mFPGAFromBIN(const char *pszFileName) C CE_RESUL T ProgramFPGAFromBIN(CE_DEVICE_HANDLE Handle, co nst char *pszFileName) .
Set the timeout in milliseconds for data transfers. If a transfer is not completed inside this timeframe, the API generates a timeout error . EnableBurst A P I Code C++ void ceDevice::EnableBurst( bool bEnable) C CE_RESUL T EnableBurst(CE_DEVICE_HANDLE Handle, unsign ed int uiEnable) .
U D K L a b Introduction UDKLab is a replacement of the former cesys-Monitor , as well as cesys-Lab and fpgaconv . It is primary targeted to support FPGA designers by offering the possibil it y to read an d write values from and to an active design.
The main screen The following screen shows an active session w ith an EFM01 device. The base v iew is intended to work with a device, while additiona l functionality can be found in the tools menu.
Using UDKLab After starting UDKLab, most of the UI components are disabled. The y will be enabled at the point they make sense. As no device is selected, only device independent functions are availabl.
After a device has been selected, most UI components are availa ble: • FPGA configuration • FPGA design flashing [if device has support] • Project controls • Initializer controls (Related to projects) The last disabled component at this point is the content panel.
FPGA design flashing This option stores a design into the flash component on devices that have sup port for it. The design is loaded to the FPGA after device power on without host intervention. How and under which circumstances this is done can be found in the hardw are description of the corresponding device.
projects can be created. Only one project can be active in one s ession. Initializing sequence The initializing sequence is a list of actions that must be executed in or der to work with the FPGA on the device.
• Download design from host • Load design from flash (supported on EFM01, USBV4F a nd USBS6) So the first entry in the initialize list must be a program entry or , if loaded from flash, a reset entry (T o s ync communicat ion to the host side).
Sequence start The button sitting below the list runs all actions from top to bottom. In addition to this, the remaining UI components, the content panel, will be enabl ed, as UDKLab expects a working communication at this point. The sequence can be modified an started as often as wished.
Register entry A register entry can be used to communicate w ith a 32 bit register inside the FPGA. In UDKLab, a register consists of the following values: • Address • Name • Info text The visua.
Data area entry A data area entry can be used to communicate w ith a data block inside the FPGA, examples are RAM or flash areas. Data can be transfered from and to files, as w ell as displayed in a live view .
A d d i t i o n a l i n f o r m a t i o n U s i n g S P I - F l a s h f o r c o n f i g u r a t i o n How to store configuration data in SPI-Flash T o allo w configuration of the FPGA via onboard SPI-Flash on power-up first an appropriate configuration file has to be stored in the SPI-Flash.
programming software is not supported. But w ith the help of some tiny FPGA design which only has to bypass SPI signals to external IO pins on connectors J3 or J4 it is poss ible to access all needed SPI-Flash pins. Connect JT AG adapter to external IO pins as described in the following chart.
I O p a i r i n g a n d e t c h l e n g t h r e p o r t J3 VG-96 pin connector - Differential pairs (28 IN, 12 IN/OUT ) PIN Net na me FPGA IO P / N Direction FPGA BANK Etch Length (mm) A4 VG 96_IO0 U2 P IN BANK 3 62.370 B4 VG96_IO1 U1 N IN BANK 3 62.368 A5 VG 96_IO3 T2 P IN BANK 3 60.
PIN Net na me FPGA IO P / N Direction FPGA BANK Etch Length (mm) A1 1 VG96_IO21 F2 P IN BANK 3 52.506 B1 1 VG96_IO22 F1 N IN BANK 3 52.504 C1 1 VG96_IO23 J3 P IN BANK 3 60.987 C10 VG96_IO20 J1 N IN BANK 3 60.972 A12 VG96_IO24 D2 P IN BANK 3 50.233 B12 VG96_IO25 D1 N IN BANK 3 50.
PIN Net na me FPGA IO P / N Direction FPGA BANK Etch Length (mm) B18 VG96_IO43 H5 N IN BANK 3 63.426 C19 VG96_IO45 J7 P IN BANK 3 64.103 C18 VG96_IO46 J6 N IN BANK 3 64.144 A20 VG96_IO47 H7 P IN BANK 3 63.630 B20 VG96_IO44 G6 N IN BANK 3 63.609 A21 VG96_IO48 E4 P IN BANK 3 60.
PIN Net na me FPGA IO P / N Direction FPGA BANK Etch Length (mm) A28 VG96_IO69 G1 1 P IN / OUT BANK 0 73.791 B28 VG96_IO70 F10 N IN / OUT BANK 0 73.594 C28 VG96_IO71 G8 P IN / OUT BANK 0 69.296 C27 VG96_IO68 F8 N IN / OUT BANK 0 69.246 A29 VG96_IO72 D1 1 P IN / OUT BANK 0 72.
PIN Net na me FPGA IO P / N Direction FPGA BANK Etch Length (mm) 13 ADD_IO B4 P IN / OUT BANK 0 19.754 14 ADD_IO A4 N IN / OUT BANK 0 19.743 15 ADD_IO B6 P IN / OUT BANK 0 20.143 16 ADD_IO A6 N IN / OUT BANK 0 20.131 19 ADD_IO B8 P IN / OUT BANK 0 20.
PIN Net na me FPGA IO P / N Direction FPGA BANK Etch Length (mm) 44 ADD_IO C14 N IN / OUT BANK 0 42.9 90 45 ADD_IO C15 P IN / OUT BANK 0 43.603 46 ADD_IO A15 N IN / OUT BANK 0 43.
M e c h a n i c a l d i m e n s i o n s USBS6 / C1030-5510 http://www . cesys.com/ User Doc V0.3 -68- preliminary Figur e 20: USBS6 mechanical dimensions in mm.
T able of conten ts T able of Contents Copyright information .................................................................................................................. .... ... . 2 Overview .....................................................
src/wb_sl_uart.vhd: ............................................................................................................. ... .... 23 src/xil_uart_macro/: ........................................................................................
Prerequisites ........................................................................................................................ .... ... 35 Makefile creation and build ............................................................................
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