Benutzeranleitung / Produktwartung PCI-1710 des Produzenten Advantech
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PCI-1710/1710HG Multifunction DAS Card for PCI Bus User's manual.
Copyright This documentation and the software included with this product are copyrighted 1998 by Advantech Co., Ltd. All rights are reserved. Advantech Co., Ltd. reserves the right to make improvements in the products described in this manual at any time without notice.
Contents Chapter 1: General Information ............................. 1 1 . 1 Introduction ............................................................... 2 1. 2 Features .................................................................... 3 1 . 3 Specifications .
4 .7 Control Register ....................................................... 39 4 .8 Status Register ......................................................... 40 4.9 Clear Interrupt and FIFO ......................................... 41 4.10 D/A Channel 0 Output .
Chapter 1 General Information 1 1 General Information CHAPTER.
2 PCI-1710 /1710HG User's Manual 1.1 Introduction The PCI-1710/1710HG is a multifunction D AS card for the PCI bus. Advanced circuit design brings you higher quality and more func- tions, includi.
Chapter 1 General Information 3 On-board Programmable Counter The PCI-1710/1710HG pro vides a pro g rammab le counter for generat- ing a pacer trigger for the A/D conv ersion. The counter chip is an 82C54 or equivalent, which includes three 16-bit counters on a 10 MHz clock.
4 PCI-1710 /1710HG User's Manual 1.3 Specifications Analog Input: • Channels: 16 single-ended or 8 differential (software programma- ble) • Resolution: 12-bit • On-board FIFO: 4K samples .
Chapter 1 General Information 5 • Maximum data throughput: PCI-1710: 100 kHz PCI-1710HG: (variable, depending on PGIA settling time) PC I -1710HG G ain Speed 0. 5 , 1 100 kH z 5, 10 35 kH z 50, 100 7 kH z 500, 1000 770 Hz PC I -1710 PC I -1710HG G ai n A ccur acy G ai n A ccur acy Rem ark 0.
6 PCI-1710 /1710HG User's Manual Analog Output: • Channels: 2 • Resolution: 12-bit • Relative accuracy: ±1/2 LSB • Gain error: ±1 LSB • Maximum update rate: 100 K samples/s • Sle w .
Chapter 1 General Information 7 Programmable Timer/Counter • Counter chip: 82C54 or equivalent • Counters: 3 channels, 16 bits, 2 channels are permanently configured as programmable pacers; 1 chan.
8 PCI-1710 /1710HG User's Manual 1.4 Block Diagram Figure 1-1: PCI-1710/PCI-1710HG block diagram PCI Controller Address Decoder 16-bit Digital Output 16-bit Digital Input 12-bit D/A Output 0 12-b.
Chapter 2 Installation 9 2 Installation CHAPTER.
10 PCI-1751/1710HG User's Manual 2.1 Initial Inspection Before installing the PCI-1710/1710HG, check the card for visible damage. W e ha ve carefull y inspected the card both mechanically and electrically before shipment. It should be free of marks and in perfect order upon receipt.
Chapter 2 Installation 11 2.3 Installation Instructions The PCI-1710/1710HG can be installed in any PCI slot in the computer . Ho w ev er, refer to the computer user's manual to a void an y mistakes and danger before you follow the installation procedure below: 1.
12 PCI-1751/1710HG User's Manual.
Chapter 3 Signal Connections 1 3 3 Signal Connections CHAPTER.
14 PCI-1710/1710HG User's Manual 3.1 Overview Correct signal connections are one of the most important factors in ensuring that your application system is sending and receiving data correctly . A good signal connection can a void much unnecessary and costly damage to your valuable PC and other hardware devices.
Chapter 3 Signal Connections 1 5 Figure 3-1: I/O connector pin assignments for the PCI-1710/1710 HG card AI0 AI2 AI4 AI6 AI8 AI10 AI12 AI14 AIGND DA0_REF DA0_OUT AOGND DI0 DI2 DI4 DI6 DI8 DI10 DI12 DI.
16 PCI-1710/1710HG User's Manual I/O Connector Signal Descriptions Si gnal N ame Ref ere nce Di rec ti on Desc ri pt i on AI <0…1 5> AI GN D I n put A nalog I nput C hannels 0 t hrough 15. Each ch an n el pair , AI <i, i +1> (i = 0, 2 , 4.
Chapter 3 Signal Connections 1 7 I/O Connector Signal Descriptions (part II) Si gnal Name Ref er ence Di rec ti on Desc ri pt i on DI <0 .. 15> DG N D I n pu t Di git al I nput si gnal s D O<0 ..15 > D GND Ou tput Di git al Out put si gnal s DG N D - - Di gi ta l G round .
18 PCI-1710/1710HG User's Manual I/O Connector Signal Descriptions (part III) Si gnal N ame Ref ere nce Di rec ti on Desc ri pt i on PA C E R _O UT D GND Ou tp u t Pacer Clock Out put - T h i s pi n pu lses on ce for each pacer cl ock wh en tu rn ed on .
Chapter 3 Signal Connections 1 9 3.3 Analog Input Connections The PCI-1710/1710HG card supports either 16 single-ended or 8 differential analog inputs. Input channel configuration is selected by software. Selection by software is more convenient than selection by a slide switch on the card.
20 PCI-1710/1710HG User's Manual Figure 3-2: Single-ended input channel connection Differential Channel Connections The differential input configuration has two signal wires for each channel, and the differential input responds only to voltage differenc- es between High and Low inputs.
Chapter 3 Signal Connections 2 1 card. W ith this connection, the PGIA rejects a common-mode voltage V cm between the signal source and the PCI-1710/1710HG ground, shown as V cm in Figure 3-3.
22 PCI-1710/1710HG User's Manual Figure 3-4: Differential input channel connection - floating signal source Ho w ev er, this connection has the disadv antage of loading the source down with the series combination (sum) of the two resistors.
Chapter 3 Signal Connections 2 3 Figure 3-5: Analog output connections 3.4 Analog Output Connections The PCI-1710/1710HG card provides two D/A output channels, D A0_OUT and D A1_OUT . Users ma y use the PCI-1710/1710HG internally provided precision –5V (-10V) reference to generate 0 to +5 V (+10 V) D/A output range.
24 PCI-1710/1710HG User's Manual 3.5 Trigger Source Connections Internal Pacer Trigger Connection The PCI-1710/1710HG card includes one 82C54 compatible programma- ble timer/counter chip which provides three 16-bit counters connected to a 1 MHz clock, designated as Counter 0, Counter 1 and Counter 2.
Chapter 3 Signal Connections 2 5 3.6 Field Wiring Considerations When you use the PCI-1710/1710HG card to acquire outside data, environmental noise can seriously affect the accuracy of your mea- surements if you don’t provide any protection.
26 PCI-1710/1710HG User's Manual.
Chapter 4 Register Structure and Format 2 7 4 Register Structure and Format CHAPTER.
28 PCI-1710/1710HG User's Manual 4.1 Overview The PCI-1710/1710HG is delivered with an easy-to-use 32-bit DLL driv er for user programming under the W indows 95/NT operating system.
Chapter 4 Register Structure and Format 2 9 Table 4-1: PCI-1710/1710HG register format (Part 1) Bas e Ad dr e ss + d e c im a l Rea d 7 6 5 432 1 0 Cha nnel Num ber and A /D Da t a 1 CH 3 CH 2 CH 1 C .
30 PCI-1710/1710HG User's Manual Bas e Ad dr e ss + d e c im a l Rea d 76543 2 1 0 N/ A 15 14 D ig ita l In p u t 17 DI 15 DI 14 DI 13 DI 12 DI 1 1 DI 10 DI 9 DI 8 16 DI 7 DI 6 DI 5 DI 4 DI 3 DI .
Chapter 4 Register Structure and Format 3 1 Bas e Ad dr e ss + d e c im a l Write 765 4 3 2 1 0 S o ftw a r e A/D Trig g e r 1 0 A / D Channel Range Se tt i ng 3 2S / D B / U G 2 G 1 G 0 MU X C o n tr.
32 PCI-1710/1710HG User's Manual Bas e Ad dr es s + d e c im a l Write 7 654 32 1 0 D/ A Refe r ence Cont rol 15 14 DA 1_I /E DA 1_5/10 DA 0_I /E D A0_5 /10 D ig ita l Outp ut 17 DO 15 DO 14 DO 1.
Chapter 4 Register Structure and Format 3 3 4.3 Channel Number and A/D Data BASE+0 and BASE+1 These two bytes, BASE+0 and BASE+1, hold the result of A/D conversion data. The 12 bits of data from the A/D conversion are stored in BASE+1 bit 3 to bit 0 and BASE+0 bit 7 to bit 0.
34 PCI-1710/1710HG User's Manual 4.5 A/D Channel Range Setting BASE+2 Each A/D channel has its own input range, controlled by a range code stored in the on-board RAM.
Chapter 4 Register Structure and Format 3 5 PC I -1710 G ai n I nput Range( V) B/U Ga in Code G2 G1 G0 1 - 5 t o + 5 0 000 2 - 2.5 t o + 2.5 0 0 0 1 4 - 1.25 t o +1. 25 0 0 1 0 8 - 0.625 t o + 0.625 0 0 1 1 0. 5 - 10 to 10 0 1 0 0 N/A 0 1 0 1 N/A 0 1 1 0 N / A 0 111 1 0 t o 1 0 1 000 20 t o 51 0 0 1 40 t o 2 .
36 PCI-1710/1710HG User's Manual PC I - 1710HG G ain Input R ange(V) B/U Gain C o d e G2 G1 G0 1 - 5 t o + 5 000 0 10 -0.5 to +0 .5 0 0 0 1 100 -0. 05 to +0. 05 0 0 1 0 1000 -0. 00 5 t o +0. 005 0 0 1 1 0.5 -10 t o +10 0 1 0 0 5- 1 t o + 1 0 1 0 1 50 -0.
Chapter 4 Register Structure and Format 3 7 4.6 MUX ControlBASE+4 and BASE+5 Table 4.6: The register for multiplexer control CL3 ~ CL0 Start Scan Channel Number CH3 ~ CH0 Stop Scan Channel Number BASE+4 bit 3 to bit 0, CL3 ~ CL0, act as a pointer when you program the A/D channel setting (see previous section).
38 PCI-1710/1710HG User's Manual the stop channel and then repeat. The following examples show the scan sequences of the MUXs (all channels are set as single-ended).
Chapter 4 Register Structure and Format 3 9 differential, and AI14 is differential, then the scan sequence is AI11, AI12, AI14, AI11, AI12, AI14, AI11… W arning! Only ev en channels can be set as differential. An odd channel will become unav ailab le if its preceding channel is set as diff erential.
40 PCI-1710/1710HG User's Manual GA TE External trigger gate function enable bit Set 1 to enable external trigger gate function, and set 0 to disable.
Chapter 4 Register Structure and Format 4 1 F/H FIFO Half-full flag This bit indicates whether the FIFO is half-full. 1 means that the FIFO is half-full. F/F FIFO Full flag This bit indicates whether the FIFO is full. 1 means that the FIFO is full. IRQ Interrupt flag This bit indicates the interrupt status.
42 PCI-1710/1710HG User's Manual 4. 10 D/A Output Channel 0 BASE+10 and BASE+11 The write-only re gisters of B ASE+10 and B ASE+11 accept data for D/A Channel 0 output. Table 4-10: Registers for D/A channel 0 data D A11 ~ D A0 Digital to Analog data D A0 is the LSB and D A11 is the MSB of the D/A data.
Chapter 4 Register Structure and Format 4 3 4.12 D/A Reference Control BASE+14 The write-only register of BASE+14 allows users to set the D/A reference source.
44 PCI-1710/1710HG User's Manual 4.13 Digital I/O Registers BASE+16 and BASE+17 The PCI-1710/1710HG card offers 16 digital input channels and 16 digital output channels. These I/O channels use the input and output ports at addresses BASE+16 and BASE+17.
Chapter 5 Calibration 45 5 Ca libr atio n CHAPTER.
46 PCI-1710/1710HG User's Manual 5.1 Introduction Regular calibration checks are important to maintain accuracy in data acquisition and control applications. W e pro vide tw o calibration programs, ADCAL.EXE and DACAL.EXE, on the PCI-1710/1710HG software CD-ROM.
Chapter 5 Calibration 47 The following list shows the function of each VR: VR Function VR1 A/D unipolar offset VR2 A/D bipolar offset VR3 A/D full scale (gain) VR4 D/A channel 0 full scale VR5 D/A channel 1 full scale 5.3 A/D Calibration Regular and accurate calibration procedures ensure the maximum possible accurac y .
48 PCI-1710/1710HG User's Manual 5.4 D/A Calibration In a way similar to the ADCAL.EXE program, the DACAL.EXE program leads you through the whole D/A calibration procedure. Y ou can either use the on-board -5 V (-10 V) inter nal reference voltage or use an external reference.
Chapter 5 Calibration 49 5.5 Self A/D Calibration Under man y conditions, it is diff icult to f ind a good enough DC voltage source for A/D calibration. There is a simple method to solve this problem. F irst, you should calibrate D/A channel 0, D A0_OUT , with internal reference -5 V , and D/A channel 1, D A1_OUT , with reference -10 V .
50 PCI-1710/1710HG User's Manual.
Appendix A 8524 Counter Chip Functions 51 A 82C54 Counter Chip Functions APPENDIX.
52 PCI-1750 User's Manual A.1 The Intel 82C54 The PCI-1710/1710HG uses one Intel 82C54 compatible programma- ble interval timer/counter chip. The popular 82C54 offers three independent 16-bit counters, counter 0, counter 1 and counter 2. Each counter has a clock input, control gate and an output.
Appendix A 8524 Counter Chip Functions 53 A.2 Counter Read/Write and Control Registers The 82C54 programmable interval timer uses four registers at addresses BASE + 24(Dec), BASE + 26(Dec), BASE + 28(Dec) and BASE + 30(Dec) for read, write and control of counter functions.
54 PCI-1750 User's Manual RW1 & RW0 Select read/write operation Operation RW1 RW0 Counter latch 0 0 Read/write LSB 0 1 Read/write MSB 1 0 Read/write LSB first, 1 1 then MSB M2, M1 & M0 Se.
Appendix A 8524 Counter Chip Functions 55 becomes: BASE + 30(Dec) 82C54 control, read-back mode Bit D7 D6 D5 D4 D3 D2 D1 D0 Value 1 1 C N T S T A C 2C 1C 0X CNT = 0 Latch count of selected counter(s). STA = 0 Latch status of selected counter(s). C2, C1 & C0 Select counter for a read-back operation.
56 PCI-1750 User's Manual A.3 Counter Operating Modes MODE 0 Stop on Terminal Count The output will initially be low after you set this mode of operation. After you load the count into the selected count register, the output will remain low and the counter will count.
Appendix A 8524 Counter Chip Functions 57 The gate input, when low, will force the output high. When the gate input goes high, the counter will start from the initial count. You can thus use the gate input to synchronize the counter. With this mode the output will remain high until you load the count register.
58 PCI-1750 User's Manual A.4 Counter Operations Read/Write Operation Before you write the initial count to each counter, you must first specify the read/write operation type, operating mode and counter type in the control byte and write the control byte to the control register [BASE + 30(Dec)].
Appendix A 8524 Counter Chip Functions 59 Counter Latch Operation Users often want to read the value of a counter without disturbing the count in progress. You do this by latching the count value for the specific counter then reading the value. The 82C54 supports the counter latch operation in two ways.
60 PCI-1750 User's Manual.
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