Benutzeranleitung / Produktwartung YMF724F des Produzenten Yamaha
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YMF724F DS-1 YAMAHA CORPORAT ION September 21, 1998 Preliminary OVERVIEW YMF724F (DS -1) is a hi gh perf ormance au dio controller f or the PCI Bu s. DS-1 consists of tw o separated fun ctional blocks. One i s the PCI Au dio block and th e other is th e Legacy Audi o block.
YMF724F September 21, 1998 -2- LOGOS 1. GM system level 1 GM sy stem level 1 is a w orld standard f ormat about MIDI sy nthesizer w hich provides voice arrang ements and MI D I functions. 2. XG XG is a format abou t MIDI synthes izer that is proposed by YAMA HA, and keeps the upper com patibility of GM sy stem lev el 1.
YMF724F September 21, 1998 -3- PIN CONFIGURATI ON YMF724F- V GP4 GP5 GP6 GP7 RXD TXD ROMDO/VOLDW# ROMSK/VOLUP# VDD5 VDD3 VSS VSS IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 INTA# VSS RST# VDD5 PVSS PCICLK GNT# REQ# AD.
YMF724F September 21, 1998 -4- PIN DESCRIPTION 1. PCI Bus Interface (53-pin) name I/O T ype Size function PCIC LK I P PCI C lock RST# I P Reset AD[31: 0] IO Ptr Address / Data C/BE[3:0]# IO Ptr Co mma.
YMF724F September 21, 1998 -5- 3. YMF727( AC3F2) Interface (9-pin) name I/O type size function XRST# O C 2mA Reset for local device ACS # O T 3m A Chip se lect for AC 3F2 ASCL K O T 6m A Clock for Ser.
YMF724F September 21, 1998 -6- 6. Miscell aneous (15-pin) name I/O type Size function ROMCS O T 3mA Chip select for external EEPROM ROMSK / VOLUP# IO Tup 3mA Serial clock for external EEPROM or Hardw .
YMF724F September 21, 1998 -7- BLOCK DIAGRAM PCI Bus Interf ace BUS Master DMA Controller Memor y XG Synthesizer Direct Sound Acc. W av e In/Out PC-PCI / D-DMA / S-IRQ SB Pro OPL3 MPU401 Jo ystick Rat.
YMF724F September 21, 1998 -8- SYSTEM DIAGRAM WaveIn Device WaveOut Device MidiOut Device XG/DLS Engine DS-1 Slot Manager (Up to 64-sound) Soft Effect DirectSound HAL DLS Appllication AC-3 Application.
YMF724F September 21, 1998 -9- FUNCTION OVERVIEW 1. PCI INTERFACE DS-1 su pports the PCI bus interf ace and complies to PCI revision 2.1. 1-1. PCI Bus Com mand DS-1 s upports th e follow ing PC I Bus com man ds.
YMF724F September 21, 1998 -10- 1-2. PCI Config uration Reg ister In addition to the Configuration Register defined b y PCI Revision 2.1, DS-1 provides p roprietary PCI Configuratio n Registers in o rde r to contro l legacy audi o functio n, such as O P L3, Sound B laster Pro , M PU4 01 and Joystick.
YMF724F September 21, 1998 -11- 00 - 01h: Vendor ID Read Only Default: 1073h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Vendor ID b[15:0] ........Vendor ID This register contains the YAMAHA Vendor ID registered in Revision 2.
YMF724F September 21, 1998 -12- b8 ................ SER: SERR# Enable This bit enables DS-1 to drive SERR#. “0”: Do not dr ive SERR#. (default) “1”: Drives SERR# w hen DS-1 detects an A ddress Parity Error on norm al target cycle or a Data Parity Error on special cy cle.
YMF724F September 21, 1998 -13- 08h: Revision ID Read Only Default: 03h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Revision I D b[7:0] ..........Revision ID This re gister co ntains the r e vision number o f DS -1 . T his registe r is hard wired to 03h .
YMF724F September 21, 1998 -14- 0Dh: Latency Timer Read / W rite Default: 00h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Latency Tim er b[7:0] ..........Latency Timer When DS-1 becomes a Bus Master device, this register indicates the initial value of the Master Latency Tim er .
YMF724F September 21, 1998 -15- 2C-2Dh: Subsystem Vendor ID Read Only Default: 1073h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsys t em V endor I D b[15:0] ........Subsystem Vendor ID This register contains the Subsystem Vendor ID.
YMF724F September 21, 1998 -16- 3Ch: Interrupt Li ne Read / W rite Default: 00h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Li ne b[7:0] ..........Interrupt Line This register indicates the interrupt channel that INT A# is assigned to.
YMF724F September 21, 1998 -17- 40 - 41h: Legacy A udio Control Read / W rite Default: 907Fh Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 LAD SIEN MPUIR Q SBIRQ SDMA I/O MIEN MEN GPEN FMEN SBEN b0 ............
YMF724F September 21, 1998 -18- b[7:6] ..........SDM A : Sound Blaster DM A -8 Channel Select These bits select the DMA chan nel for the Sound Blaster Pro block. “0”: DMA ch0 “1”: DMA ch1 (default) “2”: reserved “3”: DMA ch3 b[10:8] ..
YMF724F September 21, 1998 -19- 42 - 43h: Extended Legacy A udio Control Read / W rite Default: 0000h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IMOD SBVER SMOD - - MA IM J SI O MPUI O SB IO FMIO b[1:0] ....
YMF724F September 21, 1998 -20- b[12:11] ......SM OD: SB DM A mode These bits det ermin e the protocol to achi eve the DMA C(8237) fun ction on th e PCI bus. “0”: PC/PCI (default) “1”: reserved “2”: Distribu ted DMA “3” reserved b[14:13] .
YMF724F September 21, 1998 -21- 46-47h: Subsystem ID Write Regist er Read / W rite Default: 000Dh Access Bus W idth: 16-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsyste m ID W rite b[15:0] ........Subsystem ID Write Register This register sets the Subsy stem ID that is read from 2E-2Fh (Subsys tem ID regis ter).
YMF724F September 21, 1998 -22- b2 ................ DPLL1: Disable PLL1 Clock Oscillation Setting this bit to “1” disab les the o scillation of PLL for the PCI Audio function.
YMF724F September 21, 1998 -23- b12 .............. PR4: A C-2 Power dow n Control 4 This bit contro ls the p ower state of the AC-link in AC -2. “0”: Normal (default) “1”: Pow er dow n b13 .............. PR5: A C-2 Power dow n Control 5 Setting this bit to “1” disables the internal clock of AC- 2.
YMF724F September 21, 1998 -24- 4C-4Dh: D-DM A Slave Configurat i on Read / W rite Default: 0000h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Base Addres s EA TS CE b0 ................ CE: Channel Enable This bit enables the Distrib uted DMA function.
YMF724F September 21, 1998 -25- 51h: Next It em Poi nt er Read Only Default: 00h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Nex t Item Pointer b[7:0] ..........Next Item Pointer DS-1 does not provide other new capability besid es Power Management.
YMF724F September 21, 1998 -26- 54-55h: Pow er Management Cont rol / Status Read / W rite Default: 0000h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ---------- ---- PS b[1:0] ..........PS: Pow er State These bits determ ine th e power stat e of DS-1.
YMF724F September 21, 1998 -27- 2. ISA Comp atible Device DS-1 contains the following functions to maintain the compatibility w ith the past ISA Sound Devices. These devices are considered L egacy devices and the f unctions are ref erred to as Legacy Audio.
YMF724F September 21, 1998 -28- DS-1 su pports PC/PCI and D-DMA protocols to em ulate the DMA of SB Pro on the PCI. In addition, DS-1 supports the old ty pe of inte rrupts used by ISA an d the Seriali zed IRQ protocol. Yamah a recomm ends the combination of PC/PCI and Serialized IRQ.
YMF724F September 21, 1998 -29- 2-1. OPL3 Block OPL3 Block is register com patible w ith YMF289B. However, Pow er Managem ent reg ister has been deleted because it is now controlled by the PCI Configu ration Register. The follo wing show s the FMBase I /O map of OPL3.
YMF724F September 21, 1998 -30- 2-1-2. OPL3 Data Regist er OPL3 Data Register Array 0 (R/W) : A d d r e s s D 7D 6D 5D 4D 3D 2D 1D 0 00 - 01h LSI TES T 02h TIMER 1 03h TIMER 2 04h RST MT1 MT2 - - - ST.
YMF724F September 21, 1998 -31- 2-2. Sound Blast er Pro Block This block emu lates the DSP comm ands of Sound Blaster and Soun d B laster Pro. Only playback fun ctions are supported (record function s are not supported). However, to m aintain com patibility for gam es, it is designed so that every DSP comm and receives a correct response.
YMF724F September 21, 1998 -32- 2-2-1. DSP Com m and The follow ing show s the list of DSP Com man ds that are su pported by th e SB Pro engine. Both SB and SB Pro com mands are supported.
YMF724F September 21, 1998 -33- 2-2-2. Sound Blaster Pro Mixer The follow ing show s the register m ap of the Mixer section of Sound Blaster Pro. A d d r e s s b 7b 6b 5b 4b 3b 2b 1b 0 R e m a r k 00h.
YMF724F September 21, 1998 -34- (1) Volum e for MIDI MID I Vol. (26h) 01234567 mut e mute mu te mute mu te mu te mut e mute 0 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h mut e -52dB -42dB -36dB -3.
YMF724F September 21, 1998 -35- 2-2-3. SB Suspend / Res ume The SB block can read the in ternal stat e as to support S uspend and Resum e functi ons. The intern al state is m ade up of 218 fl ip flops. To read the state, these st ates are shi fted in order and read 8 bits at a tim e from the SCAN DA T A register.
YMF724F September 21, 1998 -36- F1h: Scan In/ O ut Data Read / W rite Default: 00h b7 b6 b5 b4 b3 b2 b1 b0 SCAN DATA b[7:0] ..........SCA N DATA This is the data p o rt for reading and writing the internal state. F8h: Interrupt Fl ag Regi ster Read Only Default: 00h b7 b6 b5 b4 b3 b2 b1 b0 ------- S B I b0 .
YMF724F September 21, 1998 -37- 2-3. MPU401 This block is for tran smitting and receiving MIDI data. It is compatible with UART mode of “MPU401”. Full duplex operation is possible using the 16-by te FIFO for each direction, transm itting and receiving .
YMF724F September 21, 1998 -38- 3. DMA Emulati on Protocol The form er syn thesizer LSI f or the ISA bus such as th e Sound Bl aster used the DMA controller (8237: ISA DMAC) on the sy stem to transfer the sound data fro m/to the host.
YMF724F September 21, 1998 -39- 3-2. D- DMA DS-1 prov ides the f ollowin g registers to support D- DMA. D-DMA Slave C onfigurat ion Register (4C -4Dh) of the PCI Conf iguration register is used to set th e Base address of the Slave Address.
YMF724F September 21, 1998 -40- 4. Interrupt Routi ng DS-1 su pports three ty pes of i nterrupts, i nterrupt s ignal on th e PCI bus (INTA#), in terrupt sig nal on th e ISA bus (IRQ[5,7,9,10,11]), an d Serialized IRQ. The IRQs on DS-1 are rout ed as shown below .
YMF724F September 21, 1998 -41- 6. Hard ware Volu me Co ntro l The hardware volume control de termines the A C-2 master volume without using any software control using the external circuit listed below. Two pins, VOL UP# for increasing the v olume and VOL DW# for decreasing the volu me, are used.
YMF724F September 21, 1998 -42- ELECTRICAL CHARACTERISTI CS 1. Absolute Maximum Ratings Item Sym bol Min. Max. Un it Power Su pply Voltage 1 (PVDD, VDD5) V DD5 -0. 5 7.0 V Power Su pply Voltage 2 (VDD3, LVDD) V DD3 -0.3 4. 6 V Inpu t Voltage 1 (PVDD, VDD5) V IN5 -0.
YMF724F September 21, 1998 -43- 3. DC Charact eristics Item Symbol Condition Min. T yp. Max. Unit High Level Input Voltage 1 V IH1 *1 2. 2 V DD5 +0.5 V Low Level Input Voltage 1 V IL1 *1 -0 .5 0. 8 V High Level Input Voltage 2 V IH2 *2 2. 2 V DD5 +0.5 V Low Level Input Voltage 2 V IL2 *2 -0 .
YMF724F September 21, 1998 -44- 4. AC Charact eristics 4-1. Master Clock (Fig.1) Item Sym bol Min. Typ. Max. Unit XI24 Cy cle T ime t XICYC - 40.69 - ns XI24 High Tim e t XIHIGH 16 - 24 n s XI24 Low Time t XILOW 16 - 24 ns Note : T op = 0-70°C, PVDD=5.
YMF724F September 21, 1998 -45- 4-3. PCI Interface (Fig.3, 4) Item Sym bo l Condition Min. Typ. Max. Unit PCICLK Cy cle Time t PCYC 30 - - ns PCI CLK Hi gh T ime t PHIGH 11 - - ns PCI CLK Lo w Ti me t.
YMF724F September 21, 1998 -46- 4-4. AC-2 / AC3F2 Master Clock (Fig.5) Item Sym bol Min. Typ. Max. Unit CMCLK Cycle Time t CMCYC - 40.69 - ns CMCLK High Time t CMHIGH 8- - n s CMCLK Low Time t CMLOW 8- n s CMCLK Rising Ti me t CMR -4 . 6- n s CMCLK Falling T i me t CMF -2 .
YMF724F September 21, 1998 -47- CBCLK CSYNC CSDI CSDO 0.8 V 1.5 V 2.0 V 0.8 V 2.0 V 0.8 V 2.0 V 0.8 V 1.5 V 2.0 V t CBIHIGH t CV AL t CBILOW t CBICYC t CV AL t COH t CSYCYC t CSYHIGH t COH t CSYLOW t CISU t CIH Fig.6: AC-link timing 4-6 AC3F2 Interface (Fig.
YMF724F September 21, 1998 -48- ASCLK A CDI A CS, ACDO 2.0 V 0.8 V 2.0 V 0.8 V 0.8 V 1.5 V 2.0 V t ASCHIGH t ASCLOW t ASCCYC t AC V A L t A COH t A CISU t A CIH Fig.7: AC 3F2 Control Interface tim ing ABCLK ASDI ASDO, ALRCK 2.0 V 0.8 V 2.0 V 0.8 V 0.8 V 1.
YMF724F September 21, 1998 -49- EXTERNAL DIMENSIONS YMF724F- V (1.00) 0-10˚ 0.50±0.20 LEAD THICKNESS : 0.15+0.10 -0.06 20.00±0.30 22.00±0.40 0.20±0.10 P-0.50TYP 36 1 37 72 73 108 109 144 1.40±0.20 1.70MAX. 0 MIN. (STAND OFF) 22.00±0.40 20.00±0.
YMF724F September 21, 1998 -50- IMPORTANT NOTICE 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The informati on contained in this docum ent has been carefully checked and is believed to be reliable.
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