Benutzeranleitung / Produktwartung TLCS-900 des Produzenten Toshiba
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TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CM22FG Semiconductor Company.
Preface Thank you very much for making us e of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”.
TMP92CM22 2007-02-16 92CM22-1 CMOS 32-Bit Microcontrollers TMP92CM22FG 1. Outline and Device Characteristics TMP92CM22 is high -speed advanced 32-bit microc ontroller dev eloped for controlling equipment, which processes mass data. TMP92CM22FG is a microcontroller , which has a high-per formance CPU (900/H1 CP U) and various built-in I/Os.
TMP92CM22 2007-02-16 92CM22-2 (4) External memory expansion • Expandable up to 16 Mb ytes (Shared program/data area) • Can simultaneously support 8-/1 6- bit width external data bus ･･･ Dyna.
TMP92CM22 2007-02-16 92CM22-3 Figure 1.1 TMP92CM22 Block Dia g ram XSP XIZ XI Y XIX XHL XDE XBC XWA 900/H1 CPU F SR 32 bits IX IY IZ SP L H E D C B A W P C 32-Kbyte RAM Serial I/O SIO0 PF1 (RXD0) PF0 .
TMP92CM22 2007-02-16 92CM22-4 2. Pin Assignment and Functions The assignment of input/outp ut pins for the TMP92CM22F G, their names and functions are as follows. 2.1 Pin Assignment Figure 2.1.1 shows the pin assignment of th e TMP92CM22FG. Figure 2.1.
TMP92CM22 2007-02-16 92CM22-5 2.2 Pin Names and Functions The following tab les show the names and function s of the input/output pins. T able 2.2.1 Pin Names an d Functions (1/2) Pin Names Number of Pins I/O Functions D0 to D7 8 I/O Data (Lower): Data bus D0 to D7.
TMP92CM22 2007-02-16 92CM22-6 T able 2.2.2 Pin Names an d Functions (2/2) Pin Names Number of Pins I/O Functions PC0 TA0IN 1 I/O Input Port C0: I/O port. Timer input: 8-bit timer A0 input. PC1 INT1 TA1OUT 1 I/O Input Output Port C1: I/O port. Interrupt request pin 1: Interrupt request pin with programmable level/rising edge/falling edge.
TMP92CM22 2007-02-16 92CM22-7 3. Operation This section describes the bas ic components, functions and oper ation of the TMP92CM22. 3.1 CPU The TMP92CM22 incorporates a high -performan ce 32-bit CPU (The TLCS-9 00/H1 CPU).
TMP92CM22 2007-02-16 92CM22-8 3.1.2 Reset Operation When resetting the TMP 92CM22 microcontrolle r , ensure that the powe r supply volta ge is within the operatin g voltage range, and that th e internal high-frequency osci llator has stabilized. Then hold the RESET input to low for at least 20 system cloc ks (16 μ s at fc = 40 MHz).
TMP92CM22 2007-02-16 92CM22-9 Figure 3.1.1 Reset T iming Example 3.1.3 Outline of Operation Mode Set AM1 and AM0 pins to “10” to use 8-b it exte rnal bus, or set it to “01” to use 16-bit external bus.
TMP92CM22 2007-02-16 92CM22-10 3.2 Memory Map Figure 3.2.1 shows memory map of TMP92CM22. Figure 3.2.1 Memory Map Note 1: When use emulator , optional 64 Kbytes of 16-Mbyte area are u sed to control emu lator . Therefore, don’t use this area. Note 2: Don’t use the last 16-byte area (FFFFF0H to FFFFF FH).
TMP92CM22 2007-02-16 92CM22-1 1 3.3 Clock Function and S tandby Function TMP92CM22 contains (1) Cl ock gear , (2) Standby controller and (3) Noise-reducin g circuit. It is used fo r low-power , low-noi se systems. This chapter is organized as follows: 3.
TMP92CM22 2007-02-16 92CM22-12 The clock operating m odes are as follows: (a) Single clock mode (X1 and X2 pins only), (b) Dual clock mode (X1, X2 pins and PLL).
TMP92CM22 2007-02-16 92CM22-13 3.3.1 Block Diagram of System Clock Figure 3.3.2 Block Diagram of Dual Clo ck a nd System Clock ÷ 4 ÷ 16 ÷ 8 ÷ 4 ÷ 2 X2 fc/16 fc/8 fc/4 fc/2 ÷ 8 φ T φ T0 f FPH .
TMP92CM22 2007-02-16 92CM22-14 3.3.2 SFRs 7 6 5 4 3 2 1 0 Bit symbol − − Read/Write R/W R/W After reset 1 0 Function Always write “1”. A l w a y s write “0”. Bit symbol − GEAR2 GEAR1 GEAR0 Read/Write R/W After reset 0 1 0 0 Function Always write “0”.
TMP92CM22 2007-02-16 92CM22-15 7 6 5 4 3 2 1 0 Bit symbol PLLON FCSEL LWUPFG Read/Write R/W R After reset 0 0 0 Function 0: PLL stop 1: PLL run 0: fc = OSCH 1: fc = PLL ( × 4) PLL warm-up flag 0: Don’t end up or stop 1: End up Note: Logic of PLLCR< LWUPFG> is different DFM of 900/L1.
TMP92CM22 2007-02-16 92CM22-16 3.3.3 System Clock Controller The system clock contr o ller gene rates the system clock signal (f SYS ) for the CPU core and i n te r n a l I / O .
TMP92CM22 2007-02-16 92CM22-17 3.3.4 Clock Doubler (PLL) PLL outputs the f PL L clock signal, which is four times as fast as f OSCH . A reset initializes PLL to stop status, setting to PLLCR register is needed befo re use. Like an oscillator , this circuit requires time to stabilize.
TMP92CM22 2007-02-16 92CM22-18 Example 2: PLL stopping PLLCR EQU 10E8H LD (PLLCR), 10XXXXXXB ; Changes fc from 40 MHz to10 MH z. LD (PLLCR), 00XXXXXXB ; Stop PLL. X: Don’t care Limitation p oint on the us e of PLL 1. When PLL is started, don’t set fc from f OSCH to f PLL at same time.
TMP92CM22 2007-02-16 92CM22-19 3.3.5 Noise Reduction Circuits Noise reduction circuits are bu ilt in for redu ction EMI (Unnec essary radius noise) and reinforcemen t EMS (Measure of endure noise), allow ing implementation of the followin g features.
TMP92CM22 2007-02-16 92CM22-20 (2) Single dr ive for high-fr equency oscillator (Purpose) Not need twin-driv e and protect mistake operation by inpu tted noise to X2 pin when the external oscill ator is used.
TMP92CM22 2007-02-16 92CM22-21 (3) Runaway pr ovision with SFR protection register (Purpose) Provision in runaway of program by noise mixin g . W rite operat ion to specified SFR is proh ibited so tha.
TMP92CM22 2007-02-16 92CM22-22 3.3.6 S tandby Controller (1) HAL T modes When the HAL T instruction is executed, the operating mode switches t o IDLE2, IDLE1, or STOP mode, depending on the contents o f the SYSCR2<HAL TM1:0> register . The subsequent actions perf ormed in each mode ar e as follows: a.
TMP92CM22 2007-02-16 92CM22-23 (2) How to release the HAL T mode These halt states ca n be released by r e setting or r equesting an interrupt. The halt release sources are d etermined by the com bination betw een the states of interrupt mask register <IFF2:0> and the HAL T modes.
TMP92CM22 2007-02-16 92CM22-24 T able 3.3.3 Source of Halt Stat e Release and Halt Release Operation Status of Received Interrupt Interrupt Enable (Interrupt level) ≥ (Interrupt mask) Interrupt Disa.
TMP92CM22 2007-02-16 92CM22-25 (3) Operation a. IDLE2 mode In IDLE2 mode only sp ecific internal I/ O operations, as designated b y the IDLE2 setting regist er , can take place. Instruction execut ion by the CPU stops. Figure 3.3.6 illustrates an examp le of the timing for clearanc e of the IDLE2 mode halt state by an interrupt.
TMP92CM22 2007-02-16 92CM22-26 c. ST OP mode When STOP mode is selected, all inte rnal circuits stop, including the inter nal oscillator pin status in STOP mode depends on the settings in the SYSCR2<SELDR V , DRVE> register . T able 3.3.5, T able 3.
TMP92CM22 2007-02-16 92CM22-27 T able 3.3.5 Input Buffer S tate T able Input Buffer State In HALT mod e (IDLE1/STOP) Input Buffer State Input Buffer State Condition A (Note) Condition B (Note) Port Na.
TMP92CM22 2007-02-16 92CM22-28 T able 3.3.6 Output Buffer S tate T able Note: Condition A/B are as follows. SYSCR2 register setting HALT mode <DRVE> <SELDRV> IDLE1 STOP 0 0 Condition B 0 1.
TMP92CM22 2007-02-16 92CM22-29 3.4 Interrupt Interrupts of TLCS-900/H1 are controlled by the CPU interru pt mask flip-fl op (IFF2:0) and by the built-in interrupt controller .
TMP92CM22 2007-02-16 92CM22-30 Figure 3.4.1 Interrupt and Micro DMA Processing Sequence Interrupt processing Interrupt vector “V” read Interrupt request F/F clear Interrupt specified by micro DMA .
TMP92CM22 2007-02-16 92CM22-31 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt , it usually performs the fo llowing sequenc e of operations. That is also the same as TLCS-900/L, TLCS-900/H, and TLCS-9 00/L1. (1) The CPU rea ds the interrupt vector fr om the interrupt controller .
TMP92CM22 2007-02-16 92CM22-32 T able 3.4.1 TMP92CM22 Interrupt V ectors and Micro DMA S tart V ectors Default Priority T ype Interrupt Source Ve c t o r V alue Address Refer to Ve c t o r Micro DMA S.
TMP92CM22 2007-02-16 92CM22-33 Default Priority T ype Interrupt Source Ve c t o r V alue Address Refer to Ve c t o r Micro DMA St a r t Ve c t or 52 INTAD: AD conversion end 00CCH FFFFCCH 33H 53 INTTC.
TMP92CM22 2007-02-16 92CM22-34 3.4.2 Micro DMA In addition to gener al-purpose int errupt processing, the TMP 92CM22 also includes a micro DMA function.
TMP92CM22 2007-02-16 92CM22-35 Although the contr ol registers used for setting the transfer source and transfer destination addresses ar e 32 bits wide, this type of regist er can only output 24-bit addresses. Accordingly , micro DMA can only access 16 Mbytes (the upper eight bits of a 32-bit address are not valid).
TMP92CM22 2007-02-16 92CM22-36 (2) Soft start functi on In addition to starting th e micro DMA function by interrupts, TMP92C M22 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DM AR register .
TMP92CM22 2007-02-16 92CM22-37 (4) Detaile d description of th e transfer mode regist er 0 0 0 Mode DMAM0 to DMAM7 DMAM [4:0] Operation Execution T ime 000 zz Destination address INC mode (DMADn + ) .
TMP92CM22 2007-02-16 92CM22-38 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the int e rrupt circuits. The left-h and side of the diagram shows the interrupt controller ci rcuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit.
TMP92CM22 2007-02-16 92CM22-39 Figure 3.4.3 Block Diagram of Interrupt Controller Interrupt request signal to CPU Micro DMA start ve ctor setting register During STOP 36 3 3 3 1 6 2 2 4 6 34 4-input O.
TMP92CM22 2007-02-16 92CM22-40 (1) Interrupt priority settin g registers Symbol Name Address 7 6 5 4 3 2 1 0 INT2 INT1 I2C I2M2 I2M1 I2M0 I1C I1M2 I1M1 I1M0 R R/W R R/W INTE12 INT1&INT2 enable D0H 0 0 0 0 0 0 0 0 − INT3 − − − − I3C I3M2 I3M1 I3M0 − − R R/W INTE3 INT3 enable D1H Note: Always write “0”.
TMP92CM22 2007-02-16 92CM22-41 Symbol Name Address 7 6 5 4 3 2 1 0 INTAD INT0 IADC IADM2 IADM1 IADM0 I0C I0M2 I0M1 I0M0 R R/W R R/W INTE0AD INT0&INTAD enable F0H 0 0 0 0 0 0 0 0 INTTC1 (DMA1) INTT.
TMP92CM22 2007-02-16 92CM22-42 (2) External in terrupt control Symbol Name Address 7 6 5 4 3 2 1 0 I3EDGE I2EDGE I1EDGE I0EDGE I0LE NMIREE W R/W 0 0 0 0 0 0 IIMC Interrupt input mode control 00F6H (Pr.
TMP92CM22 2007-02-16 92CM22-43 T able 3.4.2 Function Setting of External Interrupt Pin Interrupt Pin Shared Pin Mode Setting Method Rising edge IIMC<I0LE> = 0, INT0EDGE = 0 Falling edge IIMC<.
TMP92CM22 2007-02-16 92CM22-44 (3) SIO receive interrupt control Symbol Name Address 7 6 5 4 3 2 1 0 IR1LE IR0LE W 1 1 SIMC SIO Interrupt mode control F5H (Prohibit RMW) 0: INTRX1 edge mode 1: INTRX1 .
TMP92CM22 2007-02-16 92CM22-45 (4) Interrupt request flag clear register The interrupt requ est flag is cleared by writing the ap propriate micro DMA start vector , as gi ven in T able 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT 0, perform the foll owing register operation after e xecution of the DI inst ruction.
TMP92CM22 2007-02-16 92CM22-46 Symbol Name Address 7 6 5 4 3 2 1 0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 R/W 0 0 0 0 0 0 DMA0V DMA0 start vector 100H DMA0 start vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 .
TMP92CM22 2007-02-16 92CM22-47 (6) Specificat ion of a micro DMA burst Specifying the micro DMA burst function ca uses micro DMA transfer , once started, to continue until the va lue in the transfer co unt er register reaches 0.
TMP92CM22 2007-02-16 92CM22-48 (7) Notes The instruction execut ion unit and the bus interface unit in this CPU oper ate independentl y . Therefore if, imm ediately befor e an interrupt is generated, .
TMP92CM22 2007-02-16 92CM22-49 3.5 Port Function The TMP92CM22 features 50-bit sett ings wh ich relate to the various I/O ports. As well as general- purpose I/O port fu nctionalit y , the port pins also have I/O funct i ons which relate to the built-in CPU and internal I/Os.
TMP92CM22 2007-02-16 92CM22-50 T able 3.5.2 I/O Port Setting List (1/2) I/O Register Setting V alue Ports Input Pins S pecification Pn PnCR PnFC PnODE Input port × 0 Output port × 1 0 Port 1 P10 to .
TMP92CM22 2007-02-16 92CM22-51 T able 3.5.3 I/O Port Setting List (2/2) I/O Register Setting V alue Ports Input Pins S pecification Pn PnCR PnFC PnODE Port A PA0, PA1, PA2, PA7 Input port × None None.
TMP92CM22 2007-02-16 92CM22-52 3.5.1 Port 1 (P10 to P17) Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control regist er P1CR and function regi ster P1FC. In addition to functioning as a general-purp ose I/O port, port1 can also function as a data bus (D8 to D15).
TMP92CM22 2007-02-16 92CM22-53 Port 1 Register 7 6 5 4 3 2 1 0 Bit symbol P17 P16 P15 P14 P13 P12 P11 P10 Read/Write R/W After reset Data from external port (Output latch register is clear to “0”.
TMP92CM22 2007-02-16 92CM22-54 3.5.2 Port 4 (P40 to P47) Port 4 is an 8-bit general-purpose I/O port*. Bi ts can be individually set as eith er inputs or outputs by control regis ter P4CR and function r egister P4FC*. In addition to functionin g as a general-purp ose I/O port, p o rt 4 can also function as a address bus (A0 to A7).
TMP92CM22 2007-02-16 92CM22-55 Port 4 Register 7 6 5 4 3 2 1 0 Bit symbol P47 P46 P45 P44 P43 P42 P41 P40 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”.
TMP92CM22 2007-02-16 92CM22-56 3.5.3 Port 5 (P50 to P57) Port 5 is an 8-bit general-purpose I/O port*. Bi ts can be individually set as eith er inputs or outputs by control regis ter P5CR and function r egister P5FC*. In addition to function ing as a general-purp os e I/O port, port 5 can also function as an address bus (A8 to A15).
TMP92CM22 2007-02-16 92CM22-57 Port 5 Register 7 6 5 4 3 2 1 0 Bit symbol P57 P56 P55 P54 P53 P52 P51 P50 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”.
TMP92CM22 2007-02-16 92CM22-58 3.5.4 Port 6 (P60 to P67) Port 6 is an 8-bit general-purpose I/O port*. Bi ts can be individually set as eith er inputs or outputs by control regis ter P6CR and function r egister P6FC*. In addition to function ing as a general-purp os e I/O port, port 6 can also function as an address bus (A16 to A23).
TMP92CM22 2007-02-16 92CM22-59 Port 6 Register 7 6 5 4 3 2 1 0 Bit symbol P67 P66 P65 P64 P63 P62 P61 P60 Read/Write R/W After reset Data from external port (Output latch register is cleared to “0”.
TMP92CM22 2007-02-16 92CM22-60 3.5.5 Port 7 (P70 to P76) Port 7 is a 7-bit general-purpose I/O p ort (P70 to P75 are used for output only). Bits can be individ ually set as either inputs or outputs by co ntrol register P7CR and function register P7FC.
TMP92CM22 2007-02-16 92CM22-61 Figure 3.5.10 Port 7 (P76) Port 7 Register 7 6 5 4 3 2 1 0 Bit symbol P76 P75 P74 P73 P72 P71 P70 Read/Write R/W After reset Data from external port (Note) 1 1 1 1 1 1 Note: Output latch register is cleared to 0.
TMP92CM22 2007-02-16 92CM22-62 3.5.6 Port 8 (P80 to P83) Port 8 is 4-bit output port. Resetting sets outpu t latch of P82 to “0” and set output latches of P80, P81, and P83 to “1”. In addition to functioning as a output port, port 8 can also function as a output chip select signal ( CS0 to CS3 ).
TMP92CM22 2007-02-16 92CM22-63 3.5.7 Port 9 (P90 to P92) Port 9 is 3-bit general-purpose I/O port. Each bit can be set individually for input or output.
TMP92CM22 2007-02-16 92CM22-64 Port 9 Register 7 6 5 4 3 2 1 0 Bit symbol P92 P91 P90 Read/Write R/W After reset Data from exte rnal port (Output latch register is set to 1) Port 9 Control Register 7 .
TMP92CM22 2007-02-16 92CM22-65 3.5.8 Port A (P A0 to P A2, P A7) Port A is 4-bit general-pur pose input port with pull-up resistor . Figure 3.5.16 Port A Port A Register 7 6 5 4 3 2 1 0 Bit symbol PA7 PA2 PA1 PA0 Read/Write R R After reset D a ta fro m external port Data from external port Figure 3.
TMP92CM22 2007-02-16 92CM22-66 3.5.9 Port C (PC0, PC1, PC3, PC5, and PC6) Port C is 5-bit general-purpose I/O port. Each bit can be set individually for input or output.
TMP92CM22 2007-02-16 92CM22-67 (2) PC1 (INT1, T A1OUT), PC5 (INT2, T A3OUT), PC6 (INT3, TB0OUT0) In addi tion to f unction as I/O port , port PC1, PC5, and PC6 can also function as external interrupt inpu t pin INT1 to INT3 and output pin of timer channel T A 1OUT , T A 3OUT , and TB0OUT0.
TMP92CM22 2007-02-16 92CM22-68 (3) PC3 (INT0) In addition to function as I/O port, port PC3 can also function as external interrupt pin INT0. Figure 3.
TMP92CM22 2007-02-16 92CM22-69 Port C Register 7 6 5 4 3 2 1 0 Bit symbol PC6 PC5 PC3 PC1 PC0 Read/Write R/W R/W R/W After reset Data from external port (Note) Data fro m external port (Note) Data from external port (Note) Note: Output latch register is set to 1.
TMP92CM22 2007-02-16 92CM22-70 3.5.10 Port D (PD0 to PD3) Port D is 4-bit general-purpose I/O port. Each bit can be set individually for input or output.
TMP92CM22 2007-02-16 92CM22-71 (2) PD2 (TB1OUT0) and PD 3 (TB1OUT1) In addition to function as I/O port, port PD0 an d PD1 can also function as timer channel output pins TB1OUT0 and TB1OUT1.
TMP92CM22 2007-02-16 92CM22-72 Port D Register 7 6 5 4 3 2 1 0 Bit symbol PD3 PD2 PD1 PD0 Read/Write R/W After reset Data from external port (Output latch register is set to 1) Port D Control Register.
TMP92CM22 2007-02-16 92CM22-73 3.5.11 Port F (PF0 to PF7) Port F is 8-bit general-purpose I/O port. Each bit can be set individ ually for input or output. Resetting resets the PFCR and PFFC to “0 ”, and sets all bits to input po rt. And all bits of output latch register to “1”.
TMP92CM22 2007-02-16 92CM22-74 (2) Ports PF1 and PF4 (RXD0 and XD1) In addition to function as I/O port, port PF1 and PF4 can also function as RXD input pin of serial channel.
TMP92CM22 2007-02-16 92CM22-75 (3) Port PF2 ( CTS0 , SCLK0) and port PF5 ( CTS1 , SCLK1) In addition to function as I/O port, port PF2 and PF5 can also function as CTS input pin of serial channel or SCLK I/O pin. Figure 3.5.27 Port F (PF2 and PF5) (4) Port PF6 and port PF7 These ports are genera l-purpose I/O port.
TMP92CM22 2007-02-16 92CM22-76 Port F Register 7 6 5 4 3 2 1 0 Bit symbol PF7 PF6 PF5 PF4 PF PF2 PF1 PF0 Read/Write R/W After reset Data from external port (Output latch register is set to 1) Port F C.
TMP92CM22 2007-02-16 92CM22-77 3.5.12 Port G (PG0 to PG7) Port G is 8-bit input port and can als o be used as the an alog input pins for the internal AD converter .
TMP92CM22 2007-02-16 92CM22-78 3.6 Memory Controller 3.6.1 Function TMP92CM22 has a memory contro ller with a variable 4-block address area that contr ols as follows. (1) 4-block address area support Specifies a start address a nd a bloc k size for 4-bloc k address area.
TMP92CM22 2007-02-16 92CM22-79 3.6.2 Control Register and Operation after Reset Release This section describes the regi sters to control the memory co ntro ller , the state after reset release and necessary settings. (1) Control register The control registers of the memory controll er are as follows.
TMP92CM22 2007-02-16 92CM22-80 3.6.3 Basic Functions and Register Setting In this section, setting of the block address area, the connecting memory and the number of waits out of th e memory controller ’s func tions are described. (1) Block addres s area specification The block address area is specified b y two registers.
TMP92CM22 2007-02-16 92CM22-81 (iii) Example of register setting T o set the block address area 1 to 512 bytes from address 1 10000H, set the register as follows.
TMP92CM22 2007-02-16 92CM22-82 (2) Connection memory specification Setting the BnOM1 to BnOM0 bit of the control register (BnCSH) specifies the memory type to be connect ed with the block address areas. The int erface signal is output according to the s e t memory as foll ows.
TMP92CM22 2007-02-16 92CM22-83 CPU Data Data Size (Bit) St a r t Address Data Width in Memory Side (Bit) CPU Address D15 to D8 D7 to D0 4n + 0 8/16 4n + 0 xxxxx b7 to b0 8 4n + 1 xxxxx b7 to b0 4n + 1.
TMP92CM22 2007-02-16 92CM22-84 (4) Wa it contro l The external bus cycle completes a wait of two states at least (100 ns at f SYS = 20 MHz). Setting the <BnWW2: 0> and <BnWR2: 0> of BnCSL specifies the number of w aits in the read cycle and the wri te cycle.
TMP92CM22 2007-02-16 92CM22-85 • When not inserting a dummy (0 waits) • When inserting a dummy cycle (0 waits) CLKOUT Address CSm CSn RD CLKOUT Address CSm CSn RD Dummy.
TMP92CM22 2007-02-16 92CM22-86 (5) Bus access timing • External read/write bus cycle (0 waits) • External read/write bus cycle (1 wait) CS WR RD Address in p ut output Read Write CLKOUT (20 MHz) D.
TMP92CM22 2007-02-16 92CM22-87 • External read/write bus cycle (0 waits at WAIT pin input mode) • External read/write bus cycle (n waits at WAIT pin input mode) CS WR RD Address In p ut Out p ut R.
TMP92CM22 2007-02-16 92CM22-88 Example of WAIT input cycle (5 waits) D Q CK RES D Q CK RES D Q CK RES D Q CK RES D Q CK RES FF0 FF1 FF2 FF3 FF4 CLKOUT (20 MHz) 1 2 345 6 7 CSn RD WAIT FF _ RES FF0 _ D.
TMP92CM22 2007-02-16 92CM22-89 (6) Co nnecting exter nal memory Figure 3.6.1 shows an example of how to connect ext e rnal memory to the TMP92CM22. This example connects ROM and SRAM in 16-bit width. Figure 3.6.1 Example of External Memory By resetting, TMP92CM2 2 function as output port.
TMP92CM22 2007-02-16 92CM22-90 3.6.4 ROM Control (Page mode) This section describes ROM pa ge mode accessing and how to set registers. ROM page mode is set by the page ROM control register . (1) Operation and how t o set the registers The TMP92CM22 supports ROM acc ess of th e page mode .
TMP92CM22 2007-02-16 92CM22-91 3.6.5 List of Registers The memory control registers and the sett ings are described as follows. For the addresses of the registers, see list of special function registers in section 5. (1) Control registers The control register is a pair of BnCSL and Bn CSH.
TMP92CM22 2007-02-16 92CM22-92 B2REC Sets the dummy cycle for data output recovery time. 0 = Not insert a dummy cycle (Default) 1 = Insert a dummy cycle B2OM[1:0] 00 = SRAM or ROM (Default) Others = (Reserved) B2BUS[1:0] Sets the data bus width.
TMP92CM22 2007-02-16 92CM22-93 BEXCSL 7 6 5 4 3 2 1 0 Bit symbol BEXWW2 BEXWW1 BEXWW0 BEXWR2 BEXWR1 BEXWR0 Read/Write W W After reset 0 1 0 0 1 0 BEXWW[2:0] S pecifies the number of write waits.
TMP92CM22 2007-02-16 92CM22-94 (1) Block addres s area specification register A start address and range in t he block address are specified b y the memory start address register (MSARn) an d the memory address mask register (MAMRn). The memory start address register sets all start address similarly regardless of the block address areas.
TMP92CM22 2007-02-16 92CM22-95 (2) Page ROM contr ol register (PMEMCR) The page ROM cont rol regi ster set s page ROM accessing. ROM page accessing is executed only in bl ock address area 2. PMEMCR 7 6 5 4 3 2 1 0 Bit symbol OPGE OPWR1 OPWR0 PR1 PR0 Read/Write R/W After reset 0 0 0 1 0 OPGE Enable bit.
TMP92CM22 2007-02-16 92CM22-96 T able 3.6.1 Control Register 7 6 5 4 3 2 1 0 B0CSL Bit symbol B0WW2 B0WW1 B0WW0 B0WR2 B0WR1 B0WR0 (0140H) Read/Write W W After reset 0 1 0 0 1 0 B0CSH Bit symbol B0E .
TMP92CM22 2007-02-16 92CM22-97 3.6.6 Caution If the parasitic capacitance of th e read signal (Output enable signal) is greater than that of the chip select signal, it is possible that an unintended read cycle occurs due to a delay in the read sign al.
TMP92CM22 2007-02-16 92CM22-98 (2) The cautions at th e time of the fun ctional change of a CSn . A chip select signal output has the ca se of a combinatio n terminal with a general-purpose port function.
TMP92CM22 2007-02-16 92CM22-99 3.7 8-Bit T imers (TMRA) The TMP92CM22 features 4 built-in 8-b it timers. These timers are pa ired into four m odules: TMRA01 and T MRA23. Each m odule consists of t wo channels and can operat e in any of the foll owing four oper ating modes.
TMP92CM22 2007-02-16 92CM22-100 3.7.1 Block Diagrams Figure 3.7.1 TMRA01 Block Diagram φ T1 φ T16 φ T256 8-bit comparator (CP1) 8-bit comparator (CP0) 8-bit up counter (UC0) 2 n overflow 8-bit up c.
TMP92CM22 2007-02-16 92CM22-101 Figure 3.7.2 TMRA23 Block Diagram φ T1 φ T16 φ T256 8-bit comparator register (CP3) 8-bit comparator (CP2) 8-bit up counter (UC2) 2 n over- flow 8-bit up counter (UC.
TMP92CM22 2007-02-16 92CM22-102 3.7.2 Operation of Each Circuit (1) Prescaler A 9-bit prescaler generates the input clock to T MRA01. The prescaler ’ s operation can be controlled using T A 01RUN<T A0PRUN> in the timer control register .
TMP92CM22 2007-02-16 92CM22-103 (3) Timer registers (T A0REG and T A1REG) These are 8-bit regist ers, which can be used to set a time interval. When th e value set in the timer register T A0REG or T A1REG matches the value in the corresp onding up counter , the comparator match detect signal goes Active.
TMP92CM22 2007-02-16 92CM22-104 (4) Comparator (CP0) The comparator compar es the value in an up counter with the value set in a timer register . If they match, the up counter is cleared to 0 and an interrupt signal (INTT A0 or INTT A1) is generate d.
TMP92CM22 2007-02-16 92CM22-105 3.7.3 SFRs 7 6 5 4 3 2 1 0 Bit symbol TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN Read/Write R/W R/W After reset 0 0 0 0 0 TMRA01 prescaler UP counter (UC1) UP counter (UC0) F.
TMP92CM22 2007-02-16 92CM22-106 7 6 5 4 3 2 1 0 Bit symbol TA01M1 TA01M0 PWM01 PWM 00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Operation mode 00: 8-bit timer.
TMP92CM22 2007-02-16 92CM22-107 7 6 5 4 3 2 1 0 Bit symbol TA23M1 TA23M0 PWM21 PWM 20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Operation mode 00: 8-bit timer.
TMP92CM22 2007-02-16 92CM22-108 7 6 5 4 3 2 1 0 Bit symbol TA1FFC1 TA1FFC0 TA1FFCIE TA1FF CIS Read/Write R/W After reset 1 1 0 0 Function 00: Invert TA1FF 01: Set TA1FF to “1” 10: Clear TA1FF to .
TMP92CM22 2007-02-16 92CM22-109 TMRA3 Flip-Flop Control Regi ster 7 6 5 4 3 2 1 0 Bit symbol TA3FFC1 TA3FFC0 TA3FFCIE TA3FF CIS Read/Write R/W After reset 1 1 0 0 Function 00: Invert TA3FF 01: Set TA3.
TMP92CM22 2007-02-16 92CM22-1 1 0 Symbol Address 7 6 5 4 3 2 1 0 − W TA0REG 1102H Undefined − W TA1REG 1103H Undefined − W TA2REG 110AH Undefined − W TA3REG 110BH Undefined Note: Read-modify-write instruction is prohibited for above re gisters.
TMP92CM22 2007-02-16 92CM22-1 1 1 3.7.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be use d independently as 8-bit int erval timers.
TMP92CM22 2007-02-16 92CM22-1 1 2 2. Generating a 50% duty ratio square wave pulse The state of the timer f lip-flop (T A1FF1) is inverted at co nstant intervals and its status output via the tim er output pin (T A1OUT).
TMP92CM22 2007-02-16 92CM22-1 1 3 3. Making TMRA1 count up on the match signal fr om the TMRA0 comparator Select 8-bit timer mode and set the comparat or output from TMRA0 to be the input clock to TMRA1.
TMP92CM22 2007-02-16 92CM22-1 1 4 The comparator m atch signal is output from T MRA0 each tim e the up count er UC0 matches T A0REG, though the up-coun ter UC0 is not cleared. In the case of the T MRA1 comparator , the match detect signal is output o n each comparator puls e on which the values in the up count er UC1 and T A1REG match.
TMP92CM22 2007-02-16 92CM22-1 1 5 In this mode, a programmable square wave is generated by inver ting the timer output each time the 8-bit up count er (UC0) matches t he value in one of th e timer registers TA0REG or TA1REG. The value set in TA0RE G must be smaller than th e value set in TA1REG.
TMP92CM22 2007-02-16 92CM22-1 1 6 Example: To generate 1/4 duty 62.5 kHz pulses (at f C = 40 MHz): Calculate the value that should be set in the timer regi ster .
TMP92CM22 2007-02-16 92CM22-1 1 7 (4) 8-bit PWM (P ulse width modulation ) output mode This mode is only val id for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can b e output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which i s also used as PC1).
TMP92CM22 2007-02-16 92CM22-1 1 8 In this mode, the value of the register buffer will be shifted into TA0REG if 2 n overflow is detected when the T A0REG doubl e buffer is enabled. Use of the double buffer facilitates th e handling of low dut y ratio waves.
TMP92CM22 2007-02-16 92CM22-1 1 9 T able 3.7.4 Relationship of PWM Cycle and 2 n Counte r PWM cycle TAxxMOD<PWMx1:0> 2 6 (x64) 2 7 (x128) 2 8 (x256) TAxxMOD<TAxCLK1:0> TAxxMOD<TA xCLK1:.
TMP92CM22 2007-02-16 92CM22-120 3.8 16-Bit Timer/Event Counters (TMRB) The TMP92CM22 contains 2 chann els 16-bit ti mer/event counter (TMRB) which have the following op eration modes: • 16-bit inter.
TMP92CM22 2007-02-16 92CM22-121 3.8.1 Block Diagram Figure 3.8.1 Block Diagram of TMRB0 Capture, external interrupt control Timer flip-flop control Match detection Match detection 32 16 8 4 2 φ T1 φ.
TMP92CM22 2007-02-16 92CM22-122 Figure 3.8.2 Block Diagram of TMRB1 Timer flip-flop control Match detection Match detection 32 16 8 4 2 φ T1 φ T4 φ T16 Run/ clear φ T1 φ T4 φ T16 TB1MOD<TB1CL.
TMP92CM22 2007-02-16 92CM22-123 3.8.2 Operation (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock ( φ T0 ) is a divided clock (D ivided by 8) from selected cloc k by the register SYSCR1<GEA R1:0> of clock gear .
TMP92CM22 2007-02-16 92CM22-124 (3) T imer registers (TB0 RG0H/L and TB0RG1H/L) These two 16-bit registers are used to set the interval tim e. When the value i n the up counter UC10 matches the value set in th is timer register , the comparator match detect signal will go active.
TMP92CM22 2007-02-16 92CM22-125 (4) Capture reg isters (TB0CP0H/L, TB 0CP1H/L, TB1CP0H/ L and TB1CP1H/ L) These 16-bit reg isters are used to latch the va lues in the up counters UC10. Data in the capture registers should be read both upper and lower all 16 bits.
TMP92CM22 2007-02-16 92CM22-126 (6) Comparators (CP10 and CP1 1) CP10 and CP1 1 are 16-bit comparators which compare the value in th e up counter UC10 with the value set i n TB0RG0H/L or TB0RG1H/L respect ively , in order to detect a match. If a match is detected, the comparator generates an interrupt (INTTB00 or INTTB01 respectively).
TMP92CM22 2007-02-16 92CM22-127 3.8.3 SFRs TMRB0 Run Register 7 6 5 4 3 2 1 0 Bit symbol TB0RDE − I2TB0 TB0PRUN TB0RUN TB0RUN (1180H) Read/Write R/W R/W R/W After reset 0 0 0 0 0 TMRB0 Prescaler Up counter UC10 Function Double buffer 0: Disable 1: Enable Always write “0”.
TMP92CM22 2007-02-16 92CM22-128 TMRB0 Mode Register 7 6 5 4 3 2 1 0 Bit symbol − − TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0 TB0MOD (1182H) Read/Write R/W W R/W After reset 0 0 1 0 0 0 0 0 Function Always write “0”.
TMP92CM22 2007-02-16 92CM22-129 TMRB1 Mode Register 7 6 5 4 3 2 1 0 Bit symbol TB1CT1 TB1ET1 TB1CP0I T B1CPM1 TB1CPM0 TB1CLE TB1CLK1 TB1CLK0 TB1MOD (1192H) Read/Write R/W W R/W After reset 0 0 1 0 0 0.
TMP92CM22 2007-02-16 92CM22-130 TMRB0 Flip-flop Control Registe r 7 6 5 4 3 2 1 0 Bit symbol − − TB0C1T1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FFC1 TB0FFC0 TB0FFCR (1183H) Read/Write W R/W W * After reset 1 1 0 0 0 0 1 1 TB0FF0 inversion trigger 0: Trigger disable 1: Trigger enable Function Always write “11” .
TMP92CM22 2007-02-16 92CM22-131 TMRB1 Flip-flop Control Registe r 7 6 5 4 3 2 1 0 Bit symbol TB1FF1C1 TB1FF1C0 TB1C1T1 TB1C0T1 TB1E1T1 TB1E0T1 TB1FFC1 TB1FFC0 TB1FFCR (1193H) Read/Write W * R/W W * Af.
TMP92CM22 2007-02-16 92CM22-132 TMRB0 register 7 6 5 4 3 2 1 0 bit Symbol − Read/Write W TB0RG0L (1188H) After reset Undefined bit Symbol − Read/Write W TB0RG0H (1189H) After reset Undefined bit S.
TMP92CM22 2007-02-16 92CM22-133 3.8.4 Operation in Each Mode (1) 16-bit interval tim er mode Generating interrupts at fixed intervals in th is example, th e interval time is set the timer register TB0RG1H/L to ge nerate the interrupt INTTB01. 7 6 5 4 3 2 1 0 TB0RUN ← 0 0 X X − 0 X 0 Stop TMRB0.
TMP92CM22 2007-02-16 92CM22-134 (3) 16-bit progra mmable pulse generation (PPG) output mode Square wave pulses can be generated at any frequency and duty rati o.
TMP92CM22 2007-02-16 92CM22-135 The following block diagr am illustrates this mode. Figure 3.8.1 1 Block Diagram of 16-Bit PPG Mode The following ex ample shows how to s e t 16-bit PPG outp ut mode: 7 6 5 4 3210 TB0RUN ← 0 0 X X − 0 X 0 Disable the TB0RG0H/L double buffer and stop T MRB0.
TMP92CM22 2007-02-16 92CM22-136 (4) Capture function examples Used capture functi on, they can be applicabl e in many ways, for examp l e: 1. One-shot pulse output from ext ernal trigger pulse 2. Frequency measurement 3. Pulse width measurement 4. Measurement of differenc e time 1.
TMP92CM22 2007-02-16 92CM22-137 Example: To output a 2 [ms] one-shot pul se with a 3 [ms] delay to the external trigger pulse via the TB1IN0 pin. * Clock state : Clock gear 1/1 (f c) Setting in Main Set free running. Count using φ T1. TB1MOD ← X X 1 0 1 001 Load into TB1CP 0H/L by rising edge of TB1IN0 pin input.
TMP92CM22 2007-02-16 92CM22-138 Figure 3.8.13 One-shot Pu lse Output (without delay) 2. Frequency measurement The frequenc y of the exter nal clock can be measured in this mode. Frequenc y is measured by the 8-bit timers TMRA23 and the 16-bit timer/event count er .
TMP92CM22 2007-02-16 92CM22-139 3. Pulse width measurement This mode allows m easuring the high level wi dth of an exter nal pulse. While keeping the 16-bit tim er/event counter counting (Free running) with the pres caler output clock input, external pu lse is input through the TB1 IN0 pin.
TMP92CM22 2007-02-16 92CM22-140 4. Measurement of differenc e time This mode is used to measure the d ifference in time between the rising ed ges of external pulses inpu t through TB1IN0 and TB1IN1.
TMP92CM22 2007-02-16 92CM22-141 3.9 Serial Channels (SIO) The TMP92CM22 includes 2 serial I/O channels. Each chann el is called SIO0 and SIO1. For both channels ei ther UART M ode (Asynchronous transm ission) or I/O interface mod e (Synchronous transmissi on) can be selected.
TMP92CM22 2007-02-16 92CM22-142 Figure 3.9.1 Data Form at Bit0 1 234567 Bit0 12345 6S t o p Start Bit0 12345 Parity Stop Start 6 Bit0 12345 7 Stop Start Bit0 12345 Parity Stop Start 7 6 6 Bit0 12345 8.
TMP92CM22 2007-02-16 92CM22-143 3.9.1 Block Diagram Figure 3.9.2 Block Diagram of SIO0 Selector φ T0 φ T2 φ T8 φ T32 SC0MOD0 <SC1:0> Receive buffer 1 (Shift register) RXDCLK SC0MOD0 <CTSE.
TMP92CM22 2007-02-16 92CM22-144 Figure 3.9.3 Block Diagram of SIO1 Selector φ T0 φ T2 φ T8 φ T32 SC1MOD0 <SC1:0> Receive buffer 1 (Shift register) RXDCLK SC1MOD0 <CTSE> Prescaler Selec.
TMP92CM22 2007-02-16 92CM22-145 3.9.2 Operation of Each Circuit (1) Prescaler There is a 6-bit prescaler for generating a clock to SIO0. The clock selected using SYSCR1<GEAR2:0> is divided by 8 and input to the prescaler as φ T0. The prescaler can be run only case of selecting the baud ra te generat or as the serial transfer clock.
TMP92CM22 2007-02-16 92CM22-146 (2) Baud rate generator The baud rate generator is a circuit that ge nerates transmission and receivin g clocks that determine the transfer rate of th e serial channels. The input clock to the baud rate generator , φ T0, φ T2, φ T8, or φ T32, is generated by the 6-bit prescaler which is shared by the timers.
TMP92CM22 2007-02-16 92CM22-147 • Intege r divider (N divider) For example, when the f C = 39.3216 MHz, the input clock freq uency = φ T2, the frequency divider N (BR0CR<BR0S3:0>) = 8, and BR0CR<BR0ADDE> = 0, the baud rate in UART mode is as follows: ∗ Clock st at e Cloc k gear: 1/1 (f C ) f C /32 8 = 39.
TMP92CM22 2007-02-16 92CM22-148 T able 3.9.3 UART Baud Rate Sele ction (when using baud rate generater an d BR0 CR<BR0ADDE> = 0) Unit (k bps) f SYS [MHz] Input Clock Frequency Divider φ T0 (f SYS /4) φ T2 (f SYS /16) φ T8 (f SYS /64) φ T32 (f SYS /256) 9.
TMP92CM22 2007-02-16 92CM22-149 (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and rec eiving data. • In I/O interface mode In SCLK output mode with th e setting SC0CR<IOC> = 0, th e basic clock is generated by div iding the ou tput of the baud rate gen erator by 2, as described previously .
TMP92CM22 2007-02-16 92CM22-150 (6) The receivi ng buffers To prevent ov errun errors, the rec eiving buff ers are arranged in a double-buffer structure.
TMP92CM22 2007-02-16 92CM22-151 Handshake function Use of CTS0 pin allows data to be sent in units of one d ata format; thus, overrun errors can be avoided.
TMP92CM22 2007-02-16 92CM22-152 (9) T ransmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CP U form the least significant bit in or der . When all the bits are shifted out, the transmission buffer becomes e mpty an d generat es an I NTTX0 interrupt.
TMP92CM22 2007-02-16 92CM22-153 2. Parity error <PERR> The parity generat ed for the data sh ifted into re ceiving buffe r 2 (SC0BUF) is compared with the parity bit rec e ived via the RXD pin. If they are n ot equal, a parity error is generated.
TMP92CM22 2007-02-16 92CM22-154 3.9.3 SFRs 7 6 5 4 3 2 1 0 Bit symbol TB8 CTSE RXE WU SM1 SM0 SC1 SC0 SC0MOD0 (1202H) Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function T ra ns f e r data bit8 Handsh.
TMP92CM22 2007-02-16 92CM22-155 7 6 5 4 3 2 1 0 Bit symbol TB8 CTSE RXE WU SM1 SM0 SC1 SC0 SC1MOD0 (120AH) Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Transfer data bit8 Handshake function con.
TMP92CM22 2007-02-16 92CM22-156 7 6 5 4 3 2 1 0 Bit symbol RB8 EVEN PE OERR PERR FERR SCLKS IOC SC0CR (1201H) Read/Write R R/W R (Cleared to 0 when read) R/W After reset Undefined 0 0 0 0 0 0 0 Functi.
TMP92CM22 2007-02-16 92CM22-157 7 6 5 4 3 2 1 0 Bit symbol RB8 EVEN PE OERR PERR FERR SCLKS IOC SC1CR (1209H) Read/Write R R/W R (Cleared to 0 when read) R/W After reset Undefined 0 0 0 0 0 0 0 Functi.
TMP92CM22 2007-02-16 92CM22-158 7 6 5 4 3 2 1 0 Bit symbol − BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 BR0CR (1203H) Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Always write “0”.
TMP92CM22 2007-02-16 92CM22-159 7 6 5 4 3 2 1 0 Bit symbol − BR1ADDE BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 BR1CR (120BH) Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Always write “0”.
TMP92CM22 2007-02-16 92CM22-160 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 (for transmission) SC0BUF (1200H) 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (for receiving) Note: Prohibit read-mo dify-write for SC0BUF Figure 3.
TMP92CM22 2007-02-16 92CM22-161 3.9.4 Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increas e in the number o f I/O pins available for transm itting data to or receiving data from an external shift register .
TMP92CM22 2007-02-16 92CM22-162 Bit0 Bit1 Bit6 Bit5 SCLK0 input (<SCLKS> = 0 rising mode) SCLK0 input (<SCLKS> = 1 falling mode) TXD0 ITX0C (INTTX0 interrupt request) 1.
TMP92CM22 2007-02-16 92CM22-163 2. Receiving In SCLK output mod e, the synchronou s clock is outputted from SCLK0 pin a nd the data is shifted to receiv ing buffer 1. This starts when the receive interrupt flag INTES0<IRX0C> is cleared by reading th e received data.
TMP92CM22 2007-02-16 92CM22-164 3. T ransmission and receiving (Full duplex mode) When the full duplex m ode is used, set the leve l of receive inter rupt to “0” and set enable the in terrupt level (1 to 6) to the transfer interru pts.
TMP92CM22 2007-02-16 92CM22-165 (2) Mode 1 (7-bit UART mode) 7-bit UART mode is selected by se tting serial channel mode register SC0MOD0<SM1:0> to 01.
TMP92CM22 2007-02-16 92CM22-166 (4) Mode 3 (9-bit UART mode) 9-bit UART mode is selected by set ting SC0MOD0<SM1:0> to 1 1. In this mode parity bit cannot be added. In the case of transmission the MSB (9th bit) is programmed to SC0MOD0<TB8>.
TMP92CM22 2007-02-16 92CM22-167 Protocol 1. Select 9-bit UART mode on the master and slave controllers. 2. Set the SC0MOD0<WU> bit on each slave co ntroll er to 1 to enable data receiving. 3. The master control ler transmits one- frame data including the 8- bit select code for the slave controll ers.
TMP92CM22 2007-02-16 92CM22-168 Example: To link two slave controllers serially with the master controller using the system clock f IO as the transfer cl ock. • Master controller setting Main routine PFCR ← − − − − − − 01 PFFC ← − − − − − − X1 Set PF0 to TXD0, and set PF1 to RXD0 pin.
TMP92CM22 2007-02-16 92CM22-169 3.9.5 Support for IrDA Mode SIO0 includes support for the IrDA 1.0 in frared data communication specificat ion. Figure 3.
TMP92CM22 2007-02-16 92CM22-170 (3) Data format Format of transmission/receiving must set to data length 8-bit, without parity bit, 1 bit of stop bit. Any other settings don’ t guarantee the normal op eration. (4) SFR Figure 3.9.27 shows the control regist er SIRCR.
TMP92CM22 2007-02-16 92CM22-171 As the same reason, + (16 − K)/16 d ivision function in the baud rate gene rator of SIO0 cannot be used to generate 1 15.2 kbps baud rate. Also when the 38.4 kbps and 1/16 pulse width, + (16 − K)/16 division function cannot be used.
TMP92CM22 2007-02-16 92CM22-172 3.10 Serial Bus Interface (SBI) The TMP92CM22 has a 1-channel serial bus int erface. Serial bus int erface (SBI0) include following 2 o peration modes.
TMP92CM22 2007-02-16 92CM22-173 3.10.2 Control The following re gisters are used to c ontrol the serial b us interface and m onitor the operation status.
TMP92CM22 2007-02-16 92CM22-174 3.10.4 I 2 C Bus Mode Control Register The following regist ers are used to control and monitor the operation status when us ing the serial bus inter face (SBI) in the I 2 C bus m ode.
TMP92CM22 2007-02-16 92CM22-175 Serial Bus Interface Control Register 2 7 6 5 4 3 2 1 0 Bit symbol MST TRX BB PIN SBIM1 SBIM0 SWRST1 SWRST0 SBI0CR2 (1243H) Read/Write W W (Note 1) W (Note 1) After reset 0 0 0 1 0 0 0 0 Read- modify-write instruction is prohibited.
TMP92CM22 2007-02-16 92CM22-176 Serial Bus Interface S tatus Register 7 6 5 4 3 2 1 0 Bit symbol MST TRX BB PIN AL AAS AD0 LRB SBI0SR (1243H) Read/Write R After reset 0 0 0 1 0 0 0 0 Read- modify-write instruction is prohibited.
TMP92CM22 2007-02-16 92CM22-177 Serial Bus Interface Baud Rate Register 0 7 6 5 4 3 2 1 0 Bit symbol − I2SBI0 SBI0BR0 (1244H) Read/Write W R/W After reset 0 0 Function Always write “0”.
TMP92CM22 2007-02-16 92CM22-178 3.10.5 Control in I 2 C Bus Mode (1) Acknowledge mode spe cification Set the SBI0CR1<A C K> to 1 for oper ation in the acknowledge mode. The TMP92CM22 generates an addit ional clock pulse for an acknowledge signal wh en operating in master mode .
TMP92CM22 2007-02-16 92CM22-179 2. Clock synchronization In the I 2 C bus mode, in order to wir ed-AND a bus, a master device which pulls down a clock line to l ow level, in the fir st place, invalidate a clock pulse of an other master device which g enerates a high- level clock pulse.
TMP92CM22 2007-02-16 92CM22-180 (6) Transmitter/receiver selection Set the SBI0CR2<TRX> to “1” for oper atin g the TMP92CM22 as a transmitter.
TMP92CM22 2007-02-16 92CM22-181 (8) Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request 0 (INTSBE0) occurs, the SBI0S R2 <PIN> is cleared to “0”. During the time that the SBI0SR2<PIN> is “0”, the SCL line is pulled down to the low level.
TMP92CM22 2007-02-16 92CM22-182 The TMP92CM 22 compares the l evels on the bus’s SDA li ne with those of the internal SDA output on the rising ed ge of the SCL line. If the levels do not match, arbitration is lost and SBI 0SR<AL> is set to “1”.
TMP92CM22 2007-02-16 92CM22-183 (14) Software reset function The software reset function is used t o init ialize the SBI circuit, when S BI is rocked by external noises, etc. When write first “10” next “01” to SBI0CR 2<SWRST1:0>, reset signal is inputted to serial bus interface c ircuit, and circuit is ini tialized.
TMP92CM22 2007-02-16 92CM22-184 3.10.6 Data Tr ansfer in I 2 C Bus Mode (1) Device initializati on In first, set the SBI0BR1 <P4EN>, SBI0 CR1<ACK, SCK2:0>. Set SBI0B R1<P4EN> to “1” and clear bits 7 to 5 and 3 in the SBI0 CR1 to “0”.
TMP92CM22 2007-02-16 92CM22-185 Figure 3.10.13 S tart Conditi on and Slave Address Generation (3) 1-wo rd da ta t ransfer Check the <MST> by the INTSBE0 interrupt process after the 1-w ord data transfer is completed, and det ermine whether t he mode is a master or slave.
TMP92CM22 2007-02-16 92CM22-186 When the <TRX> is “0” (Receiver mode) When the next transmitted data is other than 8 bits, set <BC2:0> <ACK> and read the rece ived data from SBI0DBR to rel ease the SCL lin e (Data which is read immediately after a slave address is sent is und efined).
TMP92CM22 2007-02-16 92CM22-187 2. If <MST> = 0 (Slave mode) In the slave mod e the TMP92C M22 operates eith er in normal slav e mode or in slave mode after losing ar bitration.
TMP92CM22 2007-02-16 92CM22-188 (4) Stop condition generation When SBI0SR<BB> = 1, the sequence for gen erating a stop conditio n is started by writing “111” to SBI0CR2<MST, TRX, PIN> and “0” to SBI0CR2<BB>.
TMP92CM22 2007-02-16 92CM22-189 (5) Restart Restart is used during data transfer between a master d e vice and a slave d e vice to change the data transfer direction. The following descrip tion explains how to restart when this device is in the master mo de.
TMP92CM22 2007-02-16 92CM22-190 3.10.7 Clocked-synchronous 8-bit SIO Mode Control The following reg isters are used to control and monit or the operation status when the serial bus interface (SBI ) is being operated in clocked synchro nous 8-bit SIO mode.
TMP92CM22 2007-02-16 92CM22-191 Serial Bus Interface 0 Control Register 2 7 6 5 4 3 2 1 0 Bit symbol SBIM1 SBIM0 − − SBI0CR2 (1243H) Read/Write W After reset 0 0 0 0 Read- modify-write instruction is prohibited.
TMP92CM22 2007-02-16 92CM22-192 (1) Serial Clock 1. Clock source SBI0CR1<SCK2:0> is used to se lect the following function s: Internal clock In internal clock mode on e of seven frequencies can be selected. The serial clock signal is output to th e outside on the SCK p in.
TMP92CM22 2007-02-16 92CM22-193 2. Shift edge Data is transmitted on the leading ed ge of the clock and received on the trailing edge. Leading edge shift Data is shifted on the lea ding edge of the serial clock (on the fal ling edge of t he SCK pin i nput/out put).
TMP92CM22 2007-02-16 92CM22-194 (2) Transfer modes The SBI0CR1<SIOM1: 0> is used to select a transmit, receiv e or transmit/receive mode. 1. 8-bit transmit mode Set a control register to a transmit mode and write transmission data to the SBI0DBR.
TMP92CM22 2007-02-16 92CM22-195 Figure 3.10.25 T ransmission Mode Example: Program to stop data transmissi on (when an external clock is used) STEST1 : BIT 2, (SBI0SR) ; If <SEF> = 1 th en loop. JR NZ, STEST1 STEST2 : BIT 0, (P9) ; If SCK = 0 then loop.
TMP92CM22 2007-02-16 92CM22-196 Figure 3.10.26 T ransmission Data Hold Time at End Tra nsmit 2. 8-bit receive mode Set the control register to receive mode and s et the SBI0CR1<SIOS> to “1” for switching to receiv e mode.
TMP92CM22 2007-02-16 92CM22-197 Figure 3.10.27 Receiver Mode (Example: Internal clock) 3. 8-bit transmit/receive mode Set a control register to a transmit/recei ve mod e and write data to the SBI0D BR. After the data is w ritten, set the SBI0CR<SIOS> to “1” t o start transmitting/receiving.
TMP92CM22 2007-02-16 92CM22-198 Figure 3.10.28 T ransmission/Receiving Mode (when an extern al cl ock is used) Figure 3.10.29 T ransmission Data Hol d T ime at End of Transmi ssion/Receiving (T ransmi.
TMP92CM22 2007-02-16 92CM22-199 3.11 Analog/Digital Converter The TMP92CM22 incorpora tes a 10-bit succe ssive appr oximation-type analog/digital converter (AD converter) with 8-channel an alog input. Figure 3.1 1.1 is a block diagram of the AD c onverter .
TMP92CM22 2007-02-16 92CM22-200 3.11.1 Analog/Digital Converter Registers The AD convert er is controlled by the three AD m ode control re gisters: ADMOD0, ADMOD1, and ADMOD2. The eigh t AD conversion data result registers (ADREG0H/L to ADREG7H/L) stor e the results of AD conversion.
TMP92CM22 2007-02-16 92CM22-201 AD Mode Control Register 1 7 6 5 4 3 2 1 0 Bit symbol VREFON I2AD − − − ADCH2 ADCH1 ADCH0 ADMOD1 (12B9H) Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function VREF application control 0: OFF 1: ON IDLE2 0: Stop 1: Operate Always write “0”.
TMP92CM22 2007-02-16 92CM22-202 AD Conversion Result Registe r 0 Lo w 7 6 5 4 3 2 1 0 Bit symbol ADR01 ADR00 ADR0RF ADREG0L (12A0H) Read/Write R R After reset Undefined 0 Function Stores lower 2 bits .
TMP92CM22 2007-02-16 92CM22-203 AD Conversion Result Registe r 2 Lo w 7 6 5 4 3 2 1 0 Bit symbol ADR21 ADR20 ADR2RF ADREG2L (12A4H) Read/Write R R After reset Undefined 0 Function Stores lower 2 bits of AD conversion result.
TMP92CM22 2007-02-16 92CM22-204 AD Conversion Result Registe r 4 Lo w 7 6 5 4 3 2 1 0 Bit symbol ADR41 ADR40 ADR4RF ADREG4L (12A8H) Read/Write R R After reset Undefined 0 Function Stores lower 2 bits of AD conversion result.
TMP92CM22 2007-02-16 92CM22-205 AD Conversion Result Registe r 6 Lo w 7 6 5 4 3 2 1 0 Bit symbol ADR61 ADR60 ADR6RF ADREG6L (12ACH) Read/Write R R After reset Undefined 0 Function Stores lower 2 bits of AD conversion result.
TMP92CM22 2007-02-16 92CM22-206 3.11.2 Description of Operation (1) Analog reference voltage A high-level anal og reference voltage i s applied to the VREFH pin; a low-leve l analog reference voltag e is applied to the VREFL pin.
TMP92CM22 2007-02-16 92CM22-207 (3) Starting AD conversion To start AD conversion, program “1” to AD MOD0<ADS> in AD mode contro l register 0, or ADMOD1<ADTRGE> in AD m ode control register 1 and input fall ing edge on ADTRG pin.
TMP92CM22 2007-02-16 92CM22-208 3. Channel fixed repeat conversion mode Setting ADMOD0<REP EAT> and ADMOD0<SCAN> to “10” selects conversion channel fixed repeat conversion mode. In this mode data on one specified channe l is converted re peatedly.
TMP92CM22 2007-02-16 92CM22-209 (5) AD conversion time 84 states (8.4 μ s at f SYS = 20 MHz) are require d for the AD conver sion of one channe l. (6) Storing and reading the results of AD conv ersion The AD conversion da ta upper and lower registers (ADREG0 H/L to ADREG7H/L) store the results of AD convers ion.
TMP92CM22 2007-02-16 92CM22-210 Example: 1. Convert the analog input volt age on the AN3 pin a nd write the result, to m emory address 0800H using the AD in terrupt (INTAD) processin g routine. Setting of main routine 7 6 543210 INTE0AD ← X 1 0 0 − − − − Enable INTAD and set it to interrupt level 4.
TMP92CM22 2007-02-16 92CM22-21 1 3.12 W atchdog T imer (Runaway detection timer) The TMP92CM22 contains a watchdog timer of ru naway detecting. The watchdog timer (WDT ) is used to return the CPU to th e normal state when it detects that the CPU has started to malfunc tion (Runaway) due to causes such as nois e.
TMP92CM22 2007-02-16 92CM22-212 3.12.2 Operation The watchdog timer generates an INT WD interrupt when the detection tim e set in the WDMOD<WDTP1:0> has elaps e d. The watchdog timer must be clear e d “0” in software before an INTWD interrupt will b e generated.
TMP92CM22 2007-02-16 92CM22-213 3.12.3 Control Registers The watchdog timer (WDT) is contr olled by two control register s WDMOD and WDCR. (1) W atchdog timer mode register (WDMOD) 1.
TMP92CM22 2007-02-16 92CM22-214 7 6 5 4 3 2 1 0 Bit symbol WDTE WDTP1 WDTP0 − I2WDT RESCR − WDMOD (1300H) Read/Write R/W R/W After reset 1 0 0 0 0 0 0 Function WDT control 1: Enable Select detecti.
TMP92CM22 2007-02-16 92CM22-215 4. Electrical Characteristics 4.1 Absolute Maximum Ratings Parameter Symbol Rating Unit Power supply voltage Vcc − 0.
TMP92CM22 2007-02-16 92CM22-216 DC Characteristic s (1/2 ) Vcc = 3.3 ± 0.3 V /fc = 4 to 40 MHz/Ta = − 40 to 85°C Parameter Sym bol Condition Min Typ. Max Unit Power supply voltage (DVCC = AVCC) (DVSS = AVSS = 0 V) V CC fc = 4 to 40 MHz (f SYS = 125 kHz to 20 MHz) 3.
TMP92CM22 2007-02-16 92CM22-217 DC Characteristic s (2/2 ) Vcc = 3.3 ± 0. 3 V/fc = 4 to 40 MHz/Ta = − 40 to 85°C Parameter Symbol Con dition Min Typ. Max Unit Output low voltage V OL IOL = 1.6 mA 0.45 Output high voltage V OH IOH = − 400 μ A 2.
TMP92CM22 2007-02-16 92CM22-218 4.2 AC Characteristics 4.2.1 Basis Bus Cycle Read cycle Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = − 40 to 85°C No. Parameter Symbol Min Max f SYS = 20 MHz (fc = 40 MH.
TMP92CM22 2007-02-16 92CM22-219 (1) Read cycle (0 waits, fc = f OSCH , f FPH = fc/1) Note: The phase relation between X1 input signal and the ot her signals is unsettled.
TMP92CM22 2007-02-16 92CM22-220 (2) Write cycle (0 waits, fc = f OSCH , f FPH = fc/1) Note: The phase relation between X1 input signal and the ot her signals is unsettled.
TMP92CM22 2007-02-16 92CM22-221 (3) Read cycle (1 wait) (4) W rite cycle (1 wait ) A 0 to A23 WAIT Data input t RD3 t RR3 t AD3 CLKOUT D0 to D31 RD CSx R/ W A 0 to A23 WAIT Data out p ut CLKOUT D0 to .
TMP92CM22 2007-02-16 92CM22-222 4.2.2 Page ROM Read Cycle (1) 3-2- 2-2 mode Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = − 40 to 85° C No. Parameter Symbol Min Max f SYS = 20 MHz (fc = 40 MHz ) f SYS = 125 kHz (fc = 4 MHz) Unit 1 S ystem clock period ( = T) t CYC 50 8000 50 8000 ns 2 A0, A1 → D0 to D31 input t AD2 2.
TMP92CM22 2007-02-16 92CM22-223 4.3 AD Conversion Characteristics Parameter Symbol Min Typ. Max Unit Analog reference voltage ( + ) V REFH VCC − 0.2 VCC VCC Analog reference voltage ( − ) V REFL VSS VSS VSS + 0.
TMP92CM22 2007-02-16 92CM22-224 4.5 Serial Channel T iming (I/O interface mode) Note: S ymbol “X” in the following table means the period of clock “f SYS ”, it’s same period of the system clock “f SYS ” for CPU core. The period of f SYS depends on the clock gear setting or changing high-speed oscillator/low-speed oscillator and so on.
TMP92CM22 2007-02-16 92CM22-225 4.6 Interrupt, Capture Note: S ymbol “X” in the following table means the period of clock “f SYS ”, it’s same period of the system clock “f SYS ” for CPU core. The period of f SYS depends on the clock gear setting or changing high-speed oscillator/low-s peed oscillator and so on.
TMP92CM22 2007-02-16 92CM22-226 4.7 Recommended Oscillation Circuit TMP92CM22 is evaluat ed by below os cillator vender . When selecting ext ernal parts, make use of this information. Note 1: T otal loads value of oscill ation is sum of external (or internal) loads (C1 and C2) and floating loads of actual assemble board.
TMP92CM22 2007-02-16 92CM22-227 (2) TMP92CM22 recommended ceramic oscillator: Murata Manufacturing Co., Ltd. Following tabl e shows circ uit parameter recommende d.
TMP92CM22 2007-02-16 92CM22-228 5. T able of S pecial Function Registers (SFRs) The SFRs includ e the I/O ports and p eripheral contr o l registers all ocated to the 8 K bytes address space from 000000H to 001FFFH.
TMP92CM22 2007-02-16 92CM22-229 T able 5.1 I/O Register Address Map [1] I/O port Address Name Address Name Address Name Address Name 0000H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH P1 P1CR P1FC 001.
TMP92CM22 2007-02-16 92CM22-230 [2] Interrupt controller [3] DMA controller Address Name Address Name Address Name Address Name 00D0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH INTE12 INTE3 INTETA01.
TMP92CM22 2007-02-16 92CM22-231 [6] 8-bit timer [7] 16-bit timer [8] UART/SIO Address Name Address Name Addre ss Name Address Name 1100H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH TA01RUN TA0REG TA1.
TMP92CM22 2007-02-16 92CM22-232 (1) I/O port (1/3) Symbol Name Address 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 R/W P1 Port 1 0004H Data from external port (Output latch register is cleared to .
TMP92CM22 2007-02-16 92CM22-233 I/O port (2/3) Symbol Name Address 7 6 5 4 3 2 1 0 P17C P16C P15C P14C P13C P12C P11C P10C W 0 0 0 0 0 0 0 0 P1CR Port 1 control register 0006H (Prohibit RMW) 0: Input .
TMP92CM22 2007-02-16 92CM22-234 I/O port (3/3) Symbol Name Address 7 6 5 4 3 2 1 0 P92C P91C P90C W 0 0 0 P9CR Port 9 control register 0026H (Prohibit RMW) 0: Input 1: Output P92F P91F P90F W 0 0 0 P9.
TMP92CM22 2007-02-16 92CM22-235 (2) Interrupt control (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 INT2 INT1 I2C I2M2 I2M1 I2M0 I1C I1M2 I1M1 I1M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTE12 INT1 & INT2 enable 00D0H 1: INT2 Interrupt r equest level.
TMP92CM22 2007-02-16 92CM22-236 Interrupt control (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 − INTP0 − − − − IP0C IP0M2 IP0M1 IP0M0 − − − − R R/W 0 0 0 0 0 0 0 0 INTEP0 INTP0 enable 00EEH Alwa ys wr i t e “0” .
TMP92CM22 2007-02-16 92CM22-237 (3) DMA controller Symbol Name Address 7 6 5 4 3 2 1 0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 R/W 0 0 0 0 0 0 DMA0V DMA0 start vector 0100H DMA0 start vector DMA1V5 .
TMP92CM22 2007-02-16 92CM22-238 (4) Memory contr oller (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 B0WW2 B0WW1 B0WW0 B0WR2 B0WR1 B0WR0 W W 0 1 0 0 1 0 B0CSL Block 0 MEMC control register low 0140H (Proh.
TMP92CM22 2007-02-16 92CM22-239 Memory control ler (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 BEXWW2 BEXWW1 BEXWW0 BEXWR2 BEXWR1 BEXWR0 W W 0 1 0 0 1 0 BEXCSL Block EX MEMC control register low 0158H (.
TMP92CM22 2007-02-16 92CM22-240 (5) Clock gear Symbol Name Address 7 6 5 4 3 2 1 0 − − R/W R/W 1 0 SYSCR0 System clock control 0 10E0H Always write “1”. A l w a y s write “0”. − GEAR2 GEAR1 GEAR0 R / W 0 1 0 0 SYSCR1 System clock control 1 10E1H A l w a y s write “0”.
TMP92CM22 2007-02-16 92CM22-241 (6) 8-bit timer Symbol Name Address 7 6 5 4 3 2 1 0 TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN R/W R/W 0 0 0 0 0 TMRA01 prescaler UP counter (UC1) UP counter (UC0) TA01RUN TM.
TMP92CM22 2007-02-16 92CM22-242 (7) 16-bit timer (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 TB0RDE − I2TB0 TB0PRUN TB0RUN R/W R/W R/W 0 0 0 0 0 TMRB0 prescaler UP counter (UC10) TB0RUN Timer B0 RUN register 1180H Double buffer 0: Disable 1: Enable Always write “0”.
TMP92CM22 2007-02-16 92CM22-243 16-bit timer (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 TB1RDE − I 2 TB 0 TB1PRUN TB1 R UN R/W R/W R/W 0 0 0 0 0 TMRB1 prescaler UP counter (UC12) TB1RUN Timer B1 RUN register 1190H Double buffer 0: Disable 1: Enable Always write “0”.
TMP92CM22 2007-02-16 92CM22-244 (8) UART/Serial channel (1/2 ) Symbol Name Address 7 6 5 4 3 2 1 0 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 TB1 RB0 TB0 R(Receiving) / W(Transmission) SC0BUF.
TMP92CM22 2007-02-16 92CM22-245 UART/Serial channel (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 TB1 RB0 TB0 R (Receiving)/W (Transmission) SC1BUF Seri.
TMP92CM22 2007-02-16 92CM22-246 (9) I 2 C bus/Serial channel (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 BC2 BC1 BC0 ACK SCK2 SCK1 SCK0/ SWRMON W R/W W R/W 0 0 0 0 0 0 0/1 1240H (Prohibit RMW) I 2 C mod.
TMP92CM22 2007-02-16 92CM22-247 I 2 C bus/Serial channel (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 − I2SBI0 W R/W 0 0 1244H (I 2 C mode) (Prohibit RMW) Always write “0”. IDLE2 0: Abort 1: Operate − − W R/W 0 0 SBI0BR0 SBI0 baud rate register 0 1244H (SIO mode) (Prohibit RMW) Always write “0”.
TMP92CM22 2007-02-16 92CM22-248 (10) AD converter (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 EOCF ADBF − − ITM0 REPEAT SCAN ADS R R/W 0 0 0 0 0 0 0 0 ADMOD0 AD mode control register 0 12B8H AD conversion end flag 0: Busy 1: End AD conversion busy flag 0: End 1: Busy Always write “0”.
TMP92CM22 2007-02-16 92CM22-249 AD converter (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 ADR41 ADR40 ADR4RF R R ADREG4L AD result register 4 low 12A8H Undefined 0 ADR49 ADR48 ADR47 A DR46 ADR45 ADR44 AD.
TMP92CM22 2007-02-16 92CM22-250 (1 1) W atchdog timer Symbol Name Address 7 6 5 4 3 2 1 0 WDTE WDTP1 WDTP0 − I2WDT RESCR − R/W R/W 1 0 0 0 0 0 0 WDMOD WDT mode register 1300H WDT control 1: Enable Select detecting time 00: 2 15 /f IO 01: 2 17 /f IO 10: 2 19 /f IO 11: 2 21 /f IO Always write “0”.
TMP92CM22 2007-02-16 92CM22-251 6. Port Section Equivalent Circuit Diagram ■ Reading the circuit diagram Basically , the gate symbo ls written are the sam e as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below .
TMP92CM22 2007-02-16 92CM22-252 ■ P70 ( RD ), P71 ( WRLL ), P72 ( WRLU ), P73, P74 (CLKOUT), P75 ( W R/ ), P80 ( CS0 ), P81 ( CS1 ), P82 ( CS2 ), and P83 ( CS3 ) ■ P A0, P A1, P A2, and P A7 ■ P.
TMP92CM22 2007-02-16 92CM22-253 ■ PF0 (TXD0) and PF3 (TXD1) ■ PG0 (AN0), PG1 (AN1), PG2 (AN2), PG3 (AN3/ ADTRG ), PG4 (AN4), PG5 (AN5), PG6 (AN6), and PG7 (AN7) ■ RESET VCC Output data Open-drai.
TMP92CM22 2007-02-16 92CM22-254 ■ X1 and X2 ■ VREFH and VREFL ■ AM0 and AM1 ■ NMI String resistance VREFON VREFH P-ch VREFL Input data Input NMI Input Schmitt Clock High-frequency oscillation .
TMP92CM22 2007-02-16 92CM22-255 7. Points to Note and Restrictio ns (1) Notation 1. The notation for built-in I/ O registers is as follows register sy mbol < Bit symbol>. Example: T A01RUN<T A0RUN> denotes bit T A0RUN of register T A01RUN.
TMP92CM22 2007-02-16 92CM22-256 (2) Poin ts to note a) AM0 and AM1 pins This pin is connected t o the VCC (Pow er supply level) or VSS (Ground le vel) pins. Do not alter the level when the p in is active. b) Reservation area of address area TMP92CM22 don’t inclu de reservation area.
TMP92CM22 2007-02-16 92CM22-257 8. Package Dimensions P-LQFP100-144-0.50F Unit: mm.
TMP92CM22 2007-02-16 92CM22-258.
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