Benutzeranleitung / Produktwartung SLAU081 des Produzenten Texas Instruments
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January 2002 AAP Data Acquisition (Dallas) User ’ s Guide SLAU081.
IMPORT ANT NOTICE T exas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
EVM IMPORT ANT NOTICE T exas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EV ALUA TION PURPOSES ONL Y and is not considered by TI to be fit for commercial use.
EVM W ARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of ± 12 V and the output voltage range of ± 12 V . Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM.
Running Title — Attribute Reference v Chapter Title — Attribute Reference Contents 1 Introduction 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 EVM Modes 1-2 .
Running Title — Attribute Reference vi Figures 2 – 1 SAM Configuration 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T ables 2 – 1 Default Switch Settings 2-3 . . . . .
1-1 Introduction This chapter contains an overview of the features and functions of the EVM. T opic Page 1.1 EVM Modes 1–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Analog Input Conditioning 1–3 .
EVM Modes 1-2 This user ’ s guide has been written to help you get the most from your evaluation module (EVM). The TLC4541 EVM is a member of the multipurpose (MP) family of serial EVMs. It provides a platform to demonstrate the performance and functionality of the TLC4541 ADC and the TL V5636 DAC.
Analog Input Conditioning 1-3 Introduction 1.1.1 Stand-Alone Mode A unique feature of this EVM is the facility it offers the user to closely couple the ADC and DAC with a minimum of user intervention. This feature allows the serial bit stream from the digitized analog output to be fed directly to the DAC.
2-1 Getting Started Getting Started This chapter describes how the user can modify the various options of this EVM. T opic Page 2.1 Shipping (Default Configuration) 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Jumpers 2-4 . . .
Shipping (Default Configuration) 2-2 It is very important that users feel comfortable with the EVM from the beginning. T o achieve this, each unit is manufactured and shipped in a predetermined condition. This allows the user to begin evaluation of the system immediately and to have confidence that the EVM is working.
Shipping (Default Configuration) 2-3 Getting Started T able 2 – 1. Default Switch Settings Switch Settings Default Configuration Description SW1-1 On Stand-alone mode is selected, LED is on SW1-2 Off Reserved SW1-3 Off Reserved SW1-4 Off Reserved T able 2 – 2.
Jumpers 2-4 2.2 Jumpers The table below lists the functions that users can reconfigure along with the shipping condition. T able 2 – 3. Jumper/Function Reference Function Reference Designator Subsection Channel 0 Analog input W1, W1 1, W4, W2, W3 3.
Jumpers 2-5 Getting Started 2.2.3 Channel 0 Analog Output With a one-channel DAC installed, this signal is the primary analog output (output A). With a two-channel DAC installed, the pinout of these devices effectively resolves this channel to be the secondary analog output (output B).
Switches 2-6 2.2.7 Clock/Timer Routing A variety of options are available to the user . Be careful about altering these. Clock/Timer Routing Reference Designator Functional Description W21 This jumper defines the clock that the ADC and DAC use for all their timing.
Connectors 2-7 Getting Started If SW1-1 is set to the on position, user mode is selected. In this case the user has absolute control of the data and control signals for the ADC and DAC. With SW1-1 in the on position, the logic that generates the control for SAM is disabled and plays no active part in the process.
Connectors 2-8 Reference Designator Description Pin Number Function J4 Analog input option, 26-pin 1 Channel 0 input g, DIL header 2 AGND 3 Channel 1 input 4 AGND 5 Not connected 6 AGND 7 Not connecte.
Connectors 2-9 Getting Started Reference Designator Description Pin Number Function J7 EVM power 1 5 V 2 – 12 V 3 0 V 4 12 V J8 Analog output option, 1 No output g, 26-pin DIL header 2 AGND 3 Analog.
Connectors 2-10 Reference Designator Description Pin Number Function J9 Analog input option 1 Noninverting input signal to dual operational amplifier , (2) g for universal o p erational-am p lifier 2 .
ADC and DAC Direct Access 2-1 1 Getting Started 2.5 ADC and DAC Direct Access J10 and J1 1 offer users the facility to directly inspect the digital signals coming from and going to the ADC and DAC.
Host Communication 2-12 2.6.1 Common Connector Reference Designator Description Pin Number Function J16 80-pin memory interface connector for ’ C5000 and ’ C6000 DSK 1 5 V y EVMs. Pins unused by this EVM are omitted for clarity . 2 5 V 11 PCI ground 12 PCI ground 21 5 V 22 5 V 29 PCI ground 30 PCI ground 31 PCI ground 32 PCI ground 41 3.
Host Communication 2-13 Getting Started Reference Designator Description Pin Number Function J17 80-pin peripheral and control connector for ’ C5000 and ’ C6000 1 12 V DSK EVMs.
Host Communication 2-14 2.6.2 Legacy Connector J12, J13, and J15 are three 2x20 headers daisy-chained together and are collectively referred to as the legacy connector . The principle behind this arrangement is to eliminate the confused and untidy custom cabling that is typically present when connecting a legacy DSP to an EVM.
Host Communication 2-15 Getting Started Consider a host cable signal assignment as shown below: Host Connector Pin No. Signal Pin No. Signal 1 NA 2 DGND 3 NA 4 DGND 5 CLKX 6 CLKR 7 TOUT 8 DGND 9 DX 10 DR 11 FSX 12 FSR 13 NA 14 DGND 15 XF 16 DGND 17 NA 18 NA 19 NA 20 CLKS The host connector mates with J12.
Host Communication 2-16 For clarity , the above table can be redrawn with J12 removed. J13 J15 Pin No. Signal Pin No. Signal 2 NA 1 DGND 4 NA 3 DGND 6 CLKX 5 CLKR 8 TOUT 7 DGND 10 DX 9 DR 12 FSX 11 FS.
Host Communication 2-17 Getting Started All of the signals required to interface the EVM to the host are now available on either J13 or J15. This is simply a matter of wire-wrapping in the following way: J13 Wire Wrap J13 Pin No.
Host Communication 2-18 All of these connectors are shown below: Reference Designator Description Pin Number Signal Name/Function J12 20-pin connector 1 J13 pin 2 2 J15 pin 1 3 J13 pin 4 4 J15 pin 3 5.
Host Communication 2-19 Getting Started Reference Designator Description Pin Number Signal Name/Function J13 20-pin signal connector 1 ADC select signal 2 J12 pin 1 3 CLKX/transmit clock 4 J12 pin 3 5.
Host Communication 2-20 Reference Designator Description Pin Number Signal Name/Function J15 20-Pin connector 1 J12 pin 2 2 DGND 3 J12 pin 4 4 DGND 5 J12 pin 6 6 DGND 7 J12 pin 8 8 DGND 9 J12 pin 10 1.
A-1 Bill of Materials, Board Layout, and Schematics Bill of Materials, Board Layout, and Schematics This appendix contains the bill of materials, board layouts, and the EVM schematics.
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 11 4 Block Di agram DATE: 28-Nov.
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 21 4 Power & Re ference DAT .
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 31 4 Power DAT E: 28-Nov-2001 Pow er 6430333 A4 +VI N REF_IN -VI N IN 3 IN 4 PG 8 SENSE / FB 7 OUT 6 OUT 5 /ENA 2 GND 1 U6 TPS77801D D2 + C26 4.
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 41 4 Referenc e DAT E: 28-Nov-20.
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 51 4 ADC DAT E: 28-Nov-2001 ADC 6430333 A4 In _0 ADC_Data_out C19 10uF C22 0.
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 61 4 DAC DAT E: 28-Nov-2001 DAC .
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 71 4 Output conditioning DAT E: 28-Nov-2001 DAC Out put 6430333 A4 +Vs -Vs RV11 100K R35 4.
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 81 4 U ser connec tors D ATE: 28.
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 91 4 Dig ital Inte rface DATE: 28-N ov-2001 Di g i tal In terface 6430333 A4 DSP_DX DSP_X F ADC_D ata _out DSP_TOUT R40 33 DSP_F SX DSP_F SR DSP_CLKR J14 DSP_CLKS R46 49.
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 10 14 S tand Alone Mode DATE: 28.
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 11 14 Input configuration DA TE:.
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 12 14 S ig nal Generator D ATE: 28-N ov-2001 Sig n a l Ge n e r a t o r 6430333 A4 -V s +V s R60 49.
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 13 14 Prot otype Area DA TE: 28-.
12 34 A B C D 4 3 2 1 D C B A 12500 TI Boul evard . Dal l as, Texas 75243 TI TL E: SHEET : OF: FILE: SI ZE: REV: Drawn By: Engineer: DO C UMENT C O NT R O L # : 14 14 S ig nal Conditi oning DAT E: 28-Nov-2001 S ig nal Conditi oning 6430333 A4 OUT _1 IN_1 R3 NI R4 0 -V s +V s RV2 100K OUT _0 IN_0 R1 NI R2 0 -V s +V s RV1 100K C37 0.
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