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MSP-FET430 FLASH Emulation Tool (FET) ( For use with IAR Wo rkb ench Version 3.x) 2004 SLAU138A Mixed Signal Products Us e r ' s G u i d e User's Guide.
ii IMPORTANT NOTICE Texas Instrum ents and its subsidiaries (TI) reserve the right to make c hanges to their products or to disc ontinue any product or servic e without notice, and advise customers to obt ai n the latest vers ion of relevant information t o verify, before placing orders , that inform ation being relied on is c urrent and complete.
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July 2004 Us e r ' s G u i d e.
iii Preface Read This First About This Manual This ma nual doc uments th e Texas Instrum ents MS P-FET430 Flash Emulatio n Tool ( FET). Th e F ET is the pr ogram develo pment to ol for th e MSP430 u ltra low power microc ontroller. B oth avai labl e interfac es, the Paralle l-Por t-Interf ace and t he USB- Interfac e, are descr ibed here.
iv Information About Cautions and Warnings This bo ok may con tain caut ions a nd warni ngs. C AU T I O N W A RNI NG The inform ation in a caut ion or a w arning is prov ided f or your protect ion.
v If You Need Assistance Support f or the MS P430 device and the F ET is pr ovide d by the T exas Instrume nts Produc t Inform ation Ce nter (PIC) . Contact informat ion for th e PIC can be found on t he TI web sit e at www.t i.com . Ad dition al devic e- specific infor mation ca n be found on the MSP 430 web s ite at www.
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vii Contents Read This F irst ................................................................................................................ iii About This Manual ......................................................................................
viii Frequently A sked Ques tions ....................................................................................... A-1 A.1 Hardwa re ........................................................................................................ A-2 A.
ix Figures Figure 3-1. S ignal conn ections for MSP-FET43 0X110. ............................................... 3-5 Figure 3-2. JTAG Signa l Connections ......................................................................... 3-7 Figure A-1. Mod ificat ion to FET Inter face module .
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1-1 Chapter 1 Get Started Now! This chapt er will enab le you to inventor y your F ET, an d then it wi ll instr uct yo u to install the sof twar e and hardwar e, and the n run the de monstr at ion progra ms . Topic Page 1.1 Kit Contents, MSP-FET 430X110 1-2 1.
Get Started Now! 1-2 1.1 Kit Content s, MSP-FET430X110 One READ ME FIRST documen t. One MSP430 CD-ROM. One MSP- FET430 X110 F las h Emula tion To ol. T his is t he PCB on whic h is mounted a 2 0-pin Z IF sock et for the MSP430F 11xIDW , MSP430F 11x1AID W, or M SP430F1 1x2IDW d evice.
Get Started Now! 1-3 MSP-FET 430P430: Eight PCB 1x 20 pin headers (Four male a nd four fe male). MSP-FET 430P440: Eight PCB 1x 25 pin headers (Four male a nd four fe male).
Get Started Now! 1-4 1.6 Hardware Install ation, M SP-FET430Pxx0 ( ‘P120, ‘P14 0, ‘P410, ‘ P430, ‘P4 40) 1) Use the 25-c onductor cable to connect th e FET Interfa ce modul e to the paralle l port of y our PC. 2) Use the 14-c onductor cable to connect th e FET Interfa ce modul e to the supplied Target S ocket mo dule.
Get Started Now! 1-5 3) Click on the tab at t he bott om of t he work space windo w that cor responds t o your tool (FETxxx) and desired languag e (assembler or C).
Get Started Now! 1-6 1.9 Important MSP430 Documents on the CD-ROM and WEB The primar y sourc es of MS P430 infor mation are the d evice s pecific data she et and User ’s Guide. T he mos t up to d ate versio ns of t hese docum ents ava ilab le at the time of product ion have been prov ided on the CD- ROM inc luded w ith this tool.
2-1 Chapter 2 Development Flow This chapter discusses how to use K ickstart to develop your application software, and how to use C-SP Y to debug it. Topic Page 2.1 Overview 2-2 2.2 Using Kickstart 2-2 2.2.1 Project Settings 2-3 2.2.2 Creating a Project from Scra tch 2-5 2.
Developm ent Flow 2-2 2.1 Overview Applicat ions are dev eloped in as sembler and/or C usin g the Wor kbench, and they are debugged using C-SP Y. C-SP Y is seaml essly int egrate d into the Workbenc h. However , it is more conv enient t o make t he distinc tion between th e code dev elopment enviro nment ( Workbe nch) an d the debu gger (C- SPY).
Developm ent Flow 2-3 The simul ator wil l input a maximum of 4K by tes of cod e. A “Full” (i.e., unr estricted) ver sion of th e softw are tools can be purchase d from IAR. A mid- feature d tool s et – cal led “Base line”, with a 12K byte C co de size limita tion and basic f loatin g-point oper ations – is als o availa ble from IAR.
Developm ent Flow 2-4 Enable th e Device Descript ion file. Th is file makes C- SPY “a ware” of the specifics of the device it is debugg ing. This file w ill cor res pond to the specifi ed target .
Developm ent Flow 2-5 Note: Avoid the use of absolute pathnames when referenc ing files. Instead, us e the re lative p athna me keywords $TOO LKIT_DIR$ and $PROJ_DIR $.
Developm ent Flow 2-6 Note: How to add ass embler sou rce files t o you r project The defau lt file type presen ted in t he Add F iles windo w is “C/C++ F iles”. In ord er to view a ssembler fi les (.s43 ), select “A ssembler File s” in the “Files of type” dro p-dow n menu.
Developm ent Flow 2-7 system st ack wit h in C program s. CSTACK ca n also be use d in assemb ler programs [ MOV #SF E(CST ACK), SP]. CSTA CK is def ined t o extend fr om t he last locati on of R AM for 50 bytes (i.e., the stack ex tends downw ards throu gh RAM for 50 bytes).
Developm ent Flow 2-8 Note: Some exa mple pr ograms require a 32KHz crys tal on LF XT1, and not all FET s are su pplie d with a 32KHz c rystal..
Developm ent Flow 2-9 2.3 Using C-SPY Refer to A ppendix C for a desc ription of F ET-spec ific menus w ithin C-SPY. 2.3.1 Breakpoint Types The C-SPY breakp oint mec hanism m akes use of a li mited numb er of on- chip debugging r esour ces ( specifica lly, N breakp oint reg ister s, refer to T able 2- 1 below).
Developm ent Flow 2-10 The RUN TO CURSO R operation temp orarily requires a breakpoint. Consequent ly, only N-1 break points can b e activ e when RUN TO CURSOR is used if v irtual br eakpoints a re disable d.
Developm ent Flow 2-11 2.3.4 Using Watch Windows The C-SPY Watch Window mechanism perm its C variabl es to be m onitored during th e debu gging ses sion. Althou gh not or iginally desig ned to d o so, t he Watch W indow mec hanism can be ex tended to monito r ass embler var iables.
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3-1 Chapter 3 Design Considerations for In-Circuit Programming This chapt er pres ents s ignal req uireme nts for in -circ uit progra mming of the MSP430. Topic Page 3.1 Bootstrap Loader 3-2 3.2 External Power 3-2 3.3 Device Signals 3-3 3.4 Signal Connections for I n-System Progr amming and Debugging, MSP-FET430X110 3-4 3.
Design Cons idera tions for In-C ircuit Pr ogramm ing 3-2 3.1 Bootstrap Loader The JTAG pins prov ide ac cess to the Flash memory of the MSP430F d evice. On some devices, t hese pins must b e “shar ed” with the devic e port pins, an d this shari ng of p ins can c omplic ate a d esign (or it may simply not be possible t o do so).
Design Cons idera tions for In-C ircuit Pr ogramm ing 3-3 levels accor dingly) . Again, r efer to the Target Socke t modu le sche matic in Append ix B.
Design Cons idera tions for In-C ircuit Pr ogramm ing 3-4 3.3 Device Signals The foll owing dev ice signa ls s hould be brought out (i.e ., made acc essible) so that the F ET, GANG 430, and P RGS430 t.
Design Cons idera tions for In-C ircuit Pr ogramm ing 3-5 3.4 Signal Connections for In-System Programming and Debuggin g, MSP- FET430X110 With th e proper c onnecti ons, y ou can use the C-S PY debu gger and the MSP- FET430X1 10 to pro gram a nd debu g code on y our ow n targe t board.
Design Cons idera tions for In-C ircuit Pr ogramm ing 3-6 Note: Connection to XOUT is not required No JTAG c onnecti on is r equired to the XOUT pin of the M SP430 as shown on s ome sc hematic s.
Design Cons idera tions for In-C ircuit Pr ogramm ing 3-7 3.5 Signal Connections for In-System Programming and Debuggin g, MSP- FETP430IF, MSP-FET 430UIF With the pr oper c onnecti ons, y ou can use t.
Design Cons idera tions for In-C ircuit Pr ogramm ing 3-8 TDO /TD I 1 13 11 9 7 5 3 2 14 12 10 8 6 4 V C C(Fr omTo ol) GND TCK TM S TDI Te st V C C(Local Sense) RST/NMI 10uF 100nF 100K TDO/TDI RST /NM.
A-1 Appendix A Frequently Asked Questions This ap pendix pres ents s olutio ns to fre quently asked q uestions regard ing hardware, pr ogram develop ment, an d debuggi ng too ls. Topic Page A.1 Hardware A-2 A.2 Program Deve lopment (Assembler, C -Compiler, Linker) A-3 A.
Frequently Aske d Quest ions A-2 A.1 Hardware 1) The state o f the de vice (CPU registers, RAM memory, etc.) is undefined following a reset. Exceptions t o the a bove s tatement are that the PC is lo aded w ith the word at 0xfffe ( i.
Frequently Aske d Quest ions A-3 low power mode is restored (usin g GO) . This behavi or appears to happen on a ll dev ices ex cept the M SP430F 12x. 12) The foll owing ZIF socket s are us ed in the F.
Frequently Aske d Quest ions A-4 9) It is possibl e to mix as sembler an d C prog rams wi thin the Workbench. Refer to the A ssembler Langua ge Interfa ce chapter of the C/C++ Comp iler Ref erence Guid e from IAR . 10) The Workbenc h can pr odu ce an obj ect file in Texas Inst ruments .
Frequently Aske d Quest ions A-5 Optimizati on: NO NE is sup por ted wit hi n PROJ ECT- > OPT IONS- >C/C++ COM PILER-> CODE->OPTI MIZATIONS. Alter natively, variables can be d eclare d vol at il e . 16) The IAR Tutorial assumes a Full or Baseline versio n of the Workbench.
Frequently Aske d Quest ions A-6 software can preven t the C -SPY/FET driver from ac ces sing the paralle l port, an d, hence, comm unicatin g with t he devi ce. It may be n ecess ary to reb oot the com puter to c omp lete the i nstallat ion of the requ ired par allel port dr ivers.
Frequently Aske d Quest ions A-7 For revis ions 1.0, 1.1, and 1.2 of th e FET I nterface mo dule, ins tall a 0.1 uF cap acitor between the indicate d points ( pins 4 and 5 of U1).
Frequently Aske d Quest ions A-8 2) C-SPY can download data into RAM, INFORMATION, and Fla sh MAIN memori es. A war ning mes sage is output if an at tempt is made to download data o utside of the dev ice mem ory spac es. 3) C-SPY can debug applications that utilize interrupt s and low power modes .
Frequently Aske d Quest ions A-9 the JTAG pins and the me asur ements wil l be erro neou s. Refer to F AQ, Debugging #12) and Hardw ar e #11). 11) Most C-SPY setting s (break points, etc .) are now preserved between sessions. 12) When C-SP Y has co ntrol of the d evice, the C PU is ON (i.
Frequently Aske d Quest ions A-10 (RESYNCHRON IZE JTAG) ) and before C-SPY has regained c ontrol of the device that the device will execut e normally . T his behavi or may have sid e effects . Once C- SPY h as rega ined contr ol of the dev ice, it will perfor m a res et of the d evice an d retain contro l.
Frequently Aske d Quest ions A-11 26) On devices e quipp ed with a Data T ransfer C ontroll er (DT C), the completion of a data t ransfer cycl e will p reempt a single st ep of a low power mode instruction . The devic e will a dvanc e beyond t he low power mod e instr uction on ly after an in terrupt is proce ssed.
Frequently Aske d Quest ions A-12 35) Special Function Re gisters (SF Rs) – or t he peri pheral reg isters – are now di splayed in VIEW- >REGIST ER ; ther e is no lon ger an SFR Window. 36) The putch ar()/getch ar() b reakpoint s are set only if these fu nctions are pres ent (and the mec h anism is enab led) .
B-1 Appendix B Hardware This ap pendix c ontains info rmation re lating to the F ET hardwar e, inc luding schematic s and PCB p ictori als. Topic Page Figure B-1. MSP-FET 430X110, Schematic B-2 Figure B-2. MSP-FET 430X110, PCB Pictorial s B-3 Figure B-3.
Hardware B-2 Figure B-1. MSP-FET430X110, Schematic.
Hardware B-3 J2 J3 P2.1 RST XOUT P2.5 TST P2.4 P1 .1 P1.3 P1.5 P1.7 P2.2 P2.0 XIN Vss Vcc P2.3 P1.0 P1.2 P1.4 P1.6 Figure B-2. MSP-FET430X110, PCB Pictorials LED connected to P1.
Hardware B-4 Figure B- 3. MSP-FET430IF FET Interface m odule, Schematic.
Hardware B-5 Figure B-4. MSP-FET430IF FET Interface module, PCB Pictorial R6 Ensure value is 82 ohms.
Hardware B-6 Note : Connections betwe en the J TAG header and pins XOUT and XI N are no longer required , and should no t be made. Figure B-5. MSP-TS430DW28 Target Socket module, Schematic.
Hardware B-7 Figure B-6. MSP-TS430DW28 Target Socket module, PCB Pictorials Jum per J4 Open to disconn ect LED Orien t Pin 1 of MSP430 device Jum per J5 Open to measure cu rrent Connect or J3 External power con nector Remo ve R8 and ju mpe r R9 LED connected to P1.
Hardware B-8 Note : Connections betwe en the J TAG header and pins XOUT and XI N are no longer required , and should no t be made. Figure B-7. MSP-TS430PM64 Target Socket module, Schematic, Rev.
Hardware B-9 Figure B-8. MSP-TS430PM64 Target Socket module, PCB Pictorials, Rev. 1.0 LED conn ected to pin 12 Jumper J7 Open to measure cu rren t Jum per J6 Open to disconn ect LED Orien t Pin 1 of M.
Hardware B-10 Note : Connections betwe en the J TAG header and pins XOUT and XI N are no longer required , and should no t be made. Figure B-9. MSP-TS430PM64 Target Socket module, Schematic, Rev.
Hardware B-11 Figure B-10. MSP-TS430PM64 Target Socket module, PCB Pictorials, Rev. 1.1 Connect or J5 External power con nection Re mo ve R8 a nd j u mp e r R 9 LED conn ected to pin 12 Jumper J7 Open.
Hardware B-12 B.1 History of changes to MSP-TS430PM64 Target Socket module Changes from Rev. 0 .1 to 1.0: Connector J 5 for ex ternal power was add ed Connectors FETJ2 a nd FE TJ3 were rem oved C8 was cha nged fro m 100nF to 10nF R5 was cha nged fro m 100k to 47k R13 and R 14 were a dded t o support B SL usage on F4 13.
Hardware B-13 Figure B-11. MSP-TSPN80 Target Socket module, Schematic.
Hardware B-14 Figure B-12. MSP-TSPN80 Target Socket module, PCB Pictorials Connect or J5 External power con nection Re mo ve R8 a nd j u mp e r R 9 Orient P in 1 of M SP 430 devi ce LED conn ected to .
Hardware B-15 Note : Connections betwe en the J TAG header and pins XOUT and XI N are no longer required , and should no t be made. Figure B-13. MSP-TSPZ100 Target Socket module, Schematic.
Hardware B-16 Figure B-14. MSP-TSPZ100 Target Socket module, PCB Pictorials Connect or J5 External power con nection Remo ve R8 and ju mpe r R9 Orient P in 1 of M SP 430 devi ce LED conn ected to pin .
Hardware B-17 Figure B-15. MSP-FET430UIF USB Interf ace schematics.
Hardware B-18.
Hardware B-19.
Hardware B-20.
Hardware B-21.
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C-1 Appendix C FET Specific Menus This ap pendix d escr ibes the C-S PY men us that ar e spec ific to th e FET. Topic Page C.1 EMULATOR C-2 C.1.1 EMULATOR->RELEASE JT A G ON GO C-2 C.1.2 EMULATOR->RESYNCHRONIZE JTAG C-2 C.1.3 EMULATOR->INIT NEW DEVICE C-2 C.
FET Spec ific Menus C-2 C.1 EMULATOR The current devic e ty pe is display ed. C.1.1 EMULATOR->RELEASE JTAG O N GO C-SPY uses the d evice JT AG sign als t o debug th e dev ice. On som e MSP430 devices, th ese JT AG signa ls ar e shared with th e devic e port pins.
FET Spec ific Menus C-3 Refer to A ppendix D . C.1.7 EMULATO R->ADVANCED- >MEMO RY DUMP Write the specif ied dev ice memory contents t o a s pecified file. A c onvent ional dialog is displ ayed that permits the user to spec ify a f ile name, a memory starting address , and a l ength.
FET Spec ific Menus C-4 C.1.14 EMULATO R ->GI E on/off Enables or disa bles al l inter rupts. Nee ds to be re stored manual ly befor e GO. C.1.15 EMULATOR->LEAVE TARG ET RUNNING If C-SPY is close d, the targ et keeps ru nning the user program. C.
D-1 Appendix D 80-pin MSP430F44x and MSP430F43x Device Emulation 80-pin M SP430F44x and MSP430F4 3x dev ices c an be emulated by the 100-pin MSP43 0F44 9 devi c e. Table D-1. F 4xx/8 0-pin S ignal Map ping lis ts wher e the pin sign als of an 80- pin devic e appear on th e pins of an MSP- TS43 0PZ100 Target Socket module.
80-pin M SP430F44x and M SP430F4 3x Device Emulati on D-2 Table D-1. F4xx/80-pin Signal Mapping F4xx/80-pin Signal F4xx/80-pin Pin Number MSP430- TS430PZ100 Pin Number Connection required between indicated pin s of MSP430- TS430PZ100 socket DVcc1 1 1 P6.
80-pin M SP430F44x and M SP430F4 3x Device Emulati on D-3 P5.5/R13 49 57 P5.6/R23 50 58 P5.7/R33 51 59 DVcc2 52 60 DVss2 53 61 P2.5/URXD0 54 74† P2.4/UTXD0 55 75 P2.3.TB2 56 76 P2.2/TB1 57 77 P2.1/TB0 58 78 P2.0/TA2 59 79 P1.7/CA1 60 80 P1.6/CA0 61 81 P1.
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E-1 Appendix E TI to IAR 2.x/3.x Assembler Migration Texas Ins truments made a suite of develo pment t ools f or the MS P430, includi ng a compr ehens ive as sembler and dev ice sim ulator.
TI to IAR 2.x/ 3.x Ass embler Migration E-2 E.1 Segment Control RSEG def ines a Re locat able S EGment. A reloc atable segment m eans t hat the code th at fol lows the R SEG stat ement w ill be plac e *som ewhere* in the region d efined for that seg ment (in t he .
TI to IAR 2.x/ 3.x Ass embler Migration E-3 consecutive backslashes (). In Asm 430 syntax, a quot e is represented by two consecut ive q uotes ( “”). See ex amples below: Character String Asm430 Syntax (TI) A430 Syntax (IAR) PLAN “C” “PLAN “”C””” “PLAN ”C”” doscomm and.
TI to IAR 2.x/ 3.x Ass embler Migration E-4 E.2.4 Constant Initi alization Directives Description Asm430 Dir ective (TI) A430 Directive (IAR) Initialize o ne or more s uccessive b ytes or text strings .byte or .strin g DB Initialize a 48-bit MSP430 floating-po int constant .
TI to IAR 2.x/ 3.x Ass embler Migration E-5 E. 2 . 6 F i l e Ref e r en ce D i r e cti ves Description Asm430 Dir ective (TI) A430 Directive (IAR) Include sour ce stat em ents from another file .copy or .in clude #include or $ Identify one or more symbo ls that are defined in th e current mo dule and used in other module s .
TI to IAR 2.x/ 3.x Ass embler Migration E-6 X SET X+1 ; Increment count er ENDR ENDM Additional A430 D irectives (I AR) A430 Directi ve (IAR) Repeatable block assem bly: Formal argum ent is subs tituted by e ach character of a string. REPTC Repeatable block assem bly: fo rmal argument is substitut ed by each string of a list of a ctual argum ents.
TI to IAR 2.x/ 3.x Ass embler Migration E-7 E.2.9 Macro Directives Description Asm430 Dir ective (TI) A430 Directive (IAR) Define a macro .macro MACRO Exit premature ly from a m acro .
TI to IAR 2.x/ 3.x Ass embler Migration E-8 Additional A430 D irectives (I AR) A430 Directi ve (IAR) Assign a va lue to a prepr ocessor s ymbol #defi ne Undefine a preprocessor s ymbol #undef Conditio.
TI to IAR 2.x/ 3.x Ass embler Migration E-9 LSTPAG (+/-) #if, #else, # elif COM MON LSTXREF (+/-) #ifde f, #ifndef STAC K #endif ALIG N #include ORG #error.
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F-1 Appendix F MSP-FET430UIF Installation Guide This sec tion d escribes the hardware instal lation pr oces s of the MS P- FET430UIF USB deb ug int er face on a PC runni ng Windows XP. The installation procedure for a Windows 2000 system is v ery similar and therefore no t show n here.
MSP-FET430UIF Installa tion Gu ide F-2 F.1 Hardware Installation 1) Connect the MSP-F ET430UIF USB Debug Interf ace with a USB ca ble to a US B port of y our PC 2) Windows now shou ld recog nize the n ew hardwar e as a n “MSP4 30 USB FET x. xx.xx” (Figure F-1).
MSP-FET430UIF Installa tion Gu ide F-3 Figure F-3. WinXP Driver Location Selection Folder 6) The Wizar d shoul d genera te a m essage t hat an appr opriate driver has been found. 7) Note that WinXP sh ows a warning t hat the dr iver is n ot certif ied by Microsoft.
MSP-FET430UIF Installa tion Gu ide F-4 Figure F-4. WinXP Driver Installation 8) In the next s tep t he Wizar d insta lls the dr iver files. 9) The Wizar d now sh ows a mes sage that it has fi nishe d the ins tallat ion of the softw are for “M SP430 US B FET A dapter” .
MSP-FET430UIF Installa tion Gu ide F-5 Figure F-5. Device Manager.
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