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CC2420 SWRS041B Page 1 of 89 2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver Applications 2.4 GHz IEEE 802.15.4 systems ZigBee systems Home/building automation Industrial Control Wireless sensor networks PC peripherals Consumer Electronics Product Description The CC2420 is a true single-chip 2.
CC2420 SWRS041B Page 2 of 89 Table of contents 1 Abbreviations _________________________________________________________________ 5 2 Referen ces _______________________________________________________.
CC2420 SWRS041B Page 3 of 89 17 RF Data Buffering __________________________________________________________ 39 17.1 Buffered transmi t mode _____________________________________________________ 39 17.2 Buffered recei ve mode _____________________________________________________ 39 17.
CC2420 SWRS041B Page 4 of 89 40.1 Package thermal properties __________________________________________________ 84 40.2 Soldering inform ation ______________________________________________________ 84 40.3 Plastic tube sp ecificat ion ____________________________________________________ 85 40.
CC2420 SWRS041B Page 5 of 89 1 Abbreviations ADC - Analog to Digital Converter AES - Advanced Encryption Standard AGC - Automatic Gain Control ARIB - Association of Radio Industries and Businesses BER.
CC2420 SWRS041B Page 6 of 89 SHR - Synchronisation Header SPI - Serial Peripheral Interface TBD - To Be Decided / To Be Defined T/R - Transmit / Receive TX - Transmit VCO - Voltage Controlled Oscillator VGA - Variable Gain Amplifier 2 References [1] IEEE std.
CC2420 SWRS041B Page 7 of 89 3 Features 2400 – 2483.5 MHz RF Transceiver Direct Sequence Spread Spectrum (DSSS) transceiver 250 kbps data rate, 2 MChip/s chip rate O-QPSK with half sine pulse shaping modulation Very low current consumption (RX: 18.
CC2420 SWRS041B Page 8 of 89 4 Absolute Maximum Ratings Parameter Min. Max. Units Condition Supply voltage for on-chip voltage regulator, VREG_IN pin 43. -0.3 3.6 V Supply voltage (VDDIO) for digital I/Os, DVDD3.3 , pin 25. -0.3 3.6 V Supply voltage (VDD) on AVDD_VCO , DVDD1.
CC2420 SWRS041B Page 9 of 89 6 Electrical Specifications Measured on CC2420 EM with transmission line balun, T A = 25 C, DVDD3.3 and VREG_IN = 3.3 V, internal voltage regulator used if nothing else stated. 6.1 Overall Parameter Min. Ty p. Max. Unit Condition / Note RF Frequency Range 2400 2483.
CC2420 SWRS041B Page 10 of 89 6.3 Receive Section Parameter Min. Ty p. Max. Unit Condition / Note Receiver Sensitivity -90 -95 dBm PER = 1%, as specified by [1] Measured in a 50 single-ended load through a balun.
CC2420 SWRS041B Page 11 of 89 Parameter Min. Ty p. Max. Unit Condition / Note Frequency error tolerance -300 300 kHz Difference between centre frequency of the received RF signal and local oscillator .
CC2420 SWRS041B Page 12 of 89 Parameter Min. Ty p. Max. Unit Condition / Note Crystal load capacitance 12 16 20 pF 16 pF recommended Crystal ESR 60 Crystal oscillator start-up time 1.
CC2420 SWRS041B Page 13 of 89 6.8 Voltage Regulator Parameter Min. Ty p. Max. Unit Condition / Note General Note that the internal voltage regulator can only supply CC2420 and no external circuitry. Input Voltage 2.1 3.0 3.6 V On the VREG_IN pin Output Voltage 1.
CC2420 SWRS041B Page 14 of 89 Parameter Min. Ty p. Max. Unit Condition / Note Current Consumption, transmit mode: P = -25 dBm P = -15 dBm P = -10 dBm P = − 5 dBm P = 0 dBm 8.5 9.9 11 14 17.4 mA mA mA mA mA The output power is delivered differentially to a 50 singled ended load through a balun, see also page 54.
CC2420 SWRS041B Page 15 of 89 7 Pin Assignment VREG_ OUT AVDD_CHP QLP48 7x7 1 2 3 4 5 6 7 8 9 10 11 12 35 34 33 32 31 30 29 28 27 26 25 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 4.
CC2420 SWRS041B Page 16 of 89 Pin Pin Name Pin type Pin Description 16 NC - Not Connected 17 AVDD_ADC Power (analog) 1.8 V Power supply for analog parts of ADCs and DACs 18 DVDD_ADC Power (digital) 1.
CC2420 SWRS041B Page 17 of 89 8 Circuit Description Serial microcontrol ler interface LNA DIGITAL DEMODULATOR - Digital RSSI - Gain Control - Image Suppression - Channel Filtering - Demodulation - Fra.
CC2420 SWRS041B Page 18 of 89 and Q LO signals to the down-conversion mixers in receive mode and up-conversion mixers in transmit mode. The VCO operates in the frequency range 4800 – 4966 MHz, and the frequency is divided by two when split in I and Q.
CC2420 SWRS041B Page 19 of 89 9 Application Circuit Few external components are required for the operation of CC2420 . A typical application circuit is shown in Figure 4. The external components shown are described in Table 1 and typical values are given in Table 2.
CC2420 SWRS041B Page 20 of 89 Ref Description C42 Voltage regulator load capacitance C61 Balun and match C62 DC block to antenna and match C71 Front-end bias decoupling and match C81 Balun and match C.
CC2420 SWRS041B Page 21 of 89 35 34 33 32 31 30 29 28 27 26 25 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 QLP4 8 7x7 CC2420 RF Transceiv er D.
CC2420 SWRS041B Page 22 of 89 35 34 33 32 31 30 29 28 27 26 25 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 QLP48 7x7 CC2420 RF Transceiver DSU.
CC2420 SWRS041B Page 23 of 89 Item Single ended output, transmission line balun Single ended output, discrete balun Differential antenna C42 10 µF, 0.5 < ESR < 5 10 µF, 0.5 < ESR < 5 10 µF, 0.5 < ESR < 5 C61 Not used 0.
CC2420 SWRS041B Page 24 of 89 10 IEEE 802.15.4 Modulation Format This section is meant as an introduction to the 2.4 GHz direct sequence spread spectrum (DSSS) RF modulation format defined in IEEE 802.15.4. For a complete description, please refer to [1].
CC2420 SWRS041B Page 25 of 89 1 01 0 11 0 1 I-phase Q-phase 1 00 1 10 0 1 0 00 11 0 0 1 0 11 00 1 0 1 T C 2T C Figure 7. I / Q Phases w hen transmitting a zero-sy mbol chip sequence, T C = 0.5 µs 11 Configuration Overview CC2420 can be configured to achieve the best performance for different applications.
CC2420 SWRS041B Page 26 of 89 12 Evaluation Software Texas Instruments (TI) provides users of CC2420 with a software program, SmartRF ® Studio (Windows interface) which may be used for radio performance and functionality evaluation. SmartRF® Studio can be downloaded from TI’s web page: http://www.
CC2420 SWRS041B Page 27 of 89 13 4-w ire Serial Configuration and Data Interface CC2420 is configured via a simple 4-wire SPI-compatible interface (pins SI , SO , SCLK and CSn ) where CC2420 is the slave. This interface is also used to read and write buffered data (see page 39).
CC2420 SWRS041B Page 28 of 89 0 0 A5 A4 A3 A2 A0 A1 D W 15 D W 14 D W 13 D W 12 D W 11 D W 10 D W 9 D W 8 D W 7 D W 6 D W 5 D W 4 D W 3 D W 2 D W 1 D W 0 S7 S6 S5 S4 S3 S2 S0 S1 0 1 A5 A4 A3 A2 A0 A1 .
CC2420 SWRS041B Page 29 of 89 Bit # Name Description 7 - Reserved, ignore value 6 XOSC16M_STABLE Indicates whether the 16 MHz oscillator is running or not 0 : The 16 MHz crystal oscillator is not running 1 : The 16 MHz crystal oscillator is running 5 TX_UNDERFLOW Indicates whether an FIFO underflow has occurred during transmission.
CC2420 SWRS041B Page 30 of 89 divided into three memory banks: TXFIFO (bank 0), RXFIFO (bank 1) and security (bank 2). The FIFO banks are 128 bytes each, while the security bank is 112 bytes. A6:0 is transmitted directly after the RAM/Register bit as shown in Figure 9.
CC2420 SWRS041B Page 31 of 89 Address Byte Ordering Name Description 0x16F – 0x16C - - Not used 0x16B – 0x16A MSB LSB SHORTADR 16-bit Short address, used for address recognition. 0x169 – 0x168 MSB LSB PANID 16-bit PAN identifier, used for address recognition.
CC2420 SWRS041B Page 32 of 89 CSn SI ADDR ADDR DATA 8MSB DATA 8LSB DATA ADDR+1 SO ADDR TXFI FO DATA ADDR DATA ADDR+2 Status Status - - Status Status Status Status Command Strobe Register Read TXFIFO Write Figure 11.
CC2420 SWRS041B Page 33 of 89 14.2 Receive mode In receive mode, the SFD pin goes active after the start of frame delimiter (SFD) field has been completely received. If address recognition is disabled or is successful, the SFD pin goes inactive again only after the last byte of the MPDU has been received.
CC2420 SWRS041B Page 34 of 89 Preamb le SFD Length Data received o ver RF SFD Pin FIFO Pin FIFOP Pin, if threshold higher th an frame leng th FIFOP Pin, if threshold lower than fra me length S F D d e.
CC2420 SWRS041B Page 35 of 89 Preamble SFD Length Data transmitted over RF SFD Pin S F D t r a n s m i t t e d L a s t M P D U b y t e t r a n s m i t t e d o r T X u n d e r f l o w MAC Protocol Data.
CC2420 SWRS041B Page 36 of 89 Digita l IF Channel Filtering ADC Digital Data Filtering Frequency Offset Compensatio n Symbol Correlators and Synchronisat ion RSSI Generator I / Q Analog IF sign al Data Symbol Output RSSI Average Correlation Value (may be used for LQI) Figure 16.
CC2420 SWRS041B Page 37 of 89 additional zero symbols in SYNCWORD make CC2420 compliant with [1]. In reception, CC2420 synchronises to received zero-symbols and searches for the SFD sequence defined by the SYNCWORD register.
CC2420 SWRS041B Page 38 of 89 There is no hardware support for the data sequence number, this field must be inserted and verified by software. CC2420 includes hardware address recognition, as described in the Address Recognition section on page 41.
CC2420 SWRS041B Page 39 of 89 MPDU Length byte n MPDU 1 MP DU 2 MPDU n-2 RSSI (signed) CRC / Corr 7 6 5 4 3 2 1 0 Bit number CRC OK Correlation value (unsigne d) Data in RXFIFO Figure 21. Data in RXFIFO w hen MDMCTRL0.AUTOCRC is set 17 RF Data Buffering CC2420 can be configured for different transmit and receive modes, as set in the MDMCTRL1.
CC2420 SWRS041B Page 40 of 89 Multiple data frames may be in the RXFIFO simultaneously, as long as the total number of bytes does not exceed 128. See the RXFIFO overflow section on page 33 for details on how a RXFIFO overflow is detected and signalled.
CC2420 SWRS041B Page 41 of 89 18 Address Recognition CC2420 includes hardware support for address recognition, as specified in [1]. Hardware address recognition may be enabled / disabled using the MDMCTRL0.ADR_DECODE control bit. Address recognition is based on the following requirements, listed from section 7.
CC2420 SWRS041B Page 42 of 89 AUTOACK may be used for non-beacon systems as long as the frame pending field (see Figure 19) is cleared. The acknowledge frame is then transmitted 12 symbol periods after t he last symbol of the incoming frame. This is as specified by [1] for non-beacon networks.
CC2420 SWRS041B Page 43 of 89 20 Radio control state machine CC2420 has a built-in state machine that is used to switch between different operational states (modes). The change of state is done either by using command strobes or by internal events such as SFD detected in receive mode.
CC2420 SWRS041B Page 44 of 89 W ait for the specified crystal oscillator start-up tim e, or poll the XOSC16M_STABLE s tatus bit Power Do wn (PD) [0] SXOSCON S T X O N IDLE [1] W ait until voltage regu.
CC2420 SWRS041B Page 45 of 89 21 MAC Security Operations (E ncryption and Authentication) CC2420 features hardware IEEE 802.15.4 MAC security operations. This includes counter mode (CTR) encryption / decryption, CBC-MA C authentication and CCM encryption + aut hentication.
CC2420 SWRS041B Page 46 of 89 flag setting is stored in the most significant byte of the nonce. The flag byte used for encryption and authentication is then generated as shown in Figure 26. The frame counter part of the nonce must be incremented for each new packet by software.
CC2420 SWRS041B Page 47 of 89 RX in-line security operations are always performed on the first frame currently inside the RXFIFO, even if parts of this have already been read out over the SPI interface. This allows the receiver to first read the source address out to decide which key to use before doing authentication of the complete frame.
CC2420 SWRS041B Page 48 of 89 21.8 Timing Table 8 shows some examples of the time used by the security module for different operations. Mode l(a) l(m) l(MIC) Time [us] CCM 50 69 8 222 CTR - 15 - 99 CBC 17 98 12 99 Stand- alone - 16 - 14 Table 8.
CC2420 SWRS041B Page 49 of 89 -60 -40 -20 0 20 40 60 -100 -80 -60 -40 -20 0 RF Level [dBm] RSSI Register Value Figure 27. Typical RSSI v alue vs. input power 24 Link Quality Indication The link quality indication (LQI) measurement is a characterisation of the strength and/or quality of a received packet, as defined by [1].
CC2420 SWRS041B Page 50 of 89 25 Clear Channel Assessment The clear channel assessment signal is based on the measured RSSI value and a programmable threshold. The clear channel assessment function is used to implement the CSMA-CA functionality specified in [1].
CC2420 SWRS041B Page 51 of 89 27 VCO and PLL Self-Calibration 27.1 VCO The VCO is completely integrated and operates at 4800 – 4966 MHz. The VCO frequency is divided by 2 to generate frequencies in the desired band (2400- 2483.
CC2420 SWRS041B Page 52 of 89 In applications where the internal voltage regulator is not used, connect VREG_EN and VREG_IN to ground. VREG_OUT shall be left open. Note that the battery monitor will not work when the voltage regulator is not used. VREG_IN Internal bandgap voltage reference 1.
CC2420 SWRS041B Page 53 of 89 The battery monitor is controlled through the BATTMON control register. The battery monitor is enabled and disabled using the BATTMON.BATTMON_EN control bit. The voltage regulator must also be enabled when using the battery monitor.
CC2420 SWRS041B Page 54 of 89 C381 C391 XTAL XOSC16_Q1 XOS C16_Q2 C381 C391 XTAL XTAL XOSC16_Q1 XOS C16_Q2 Figure 30. Crystal oscillator circuit Item C L = 16 pF C381 27 pF C391 27 pF Table 10. Crystal oscillator component v alues 32 Input / Output Matching The RF input / output is differential ( RF_N and RF_P ).
CC2420 SWRS041B Page 55 of 89 A Unit dBm RF Att 30 dB 1AVG 1S A Ref Lvl 3 dBm Ref Lvl 3 dBm Center 2 .45 GHz Span 2 M Hz 200 kHz/ RBW 10 kHz VBW 10 kHz SWT 50 ms -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -97 3 Date: 23.OCT.2003 21:38:33 Figure 31. Single carrier output 33.
CC2420 SWRS041B Page 56 of 89 A Unit dBm RF Att 30 dB Ref Lvl 0 dBm Ref Lvl 0 dBm SWT 5 ms Center 2 .45 GHz Span 10 MHz 1 MHz/ 1AVG 1S A RBW 100 kHz VBW 100 kHz -90 -80 -70 -60 -50 -40 -30 -20 -10 -100 0 Date: 23.
CC2420 SWRS041B Page 57 of 89 34 System Considerations and Guidelines SRD regulations International regulations and national laws regulate the use of radio receivers and transmitters. SRDs (Short Range Devices) for license free operation are allowed to operate in the 2.
CC2420 SWRS041B Page 58 of 89 34.6 Low -cost systems As the CC2420 provides 250 kbps multi- channel performance without any external filters, a very low- cost system can be made. A differential antenna will eliminate the need for a balun, and the DC biasing can be achieved in the antenna topology.
CC2420 SWRS041B Page 59 of 89 The RXCTRL1.RXBPF_LOCUR control bit should be set to 1. The simplest way of making a PER measurement will be to use another CC2420 as the reference transmitter. However, this makes it difficult to measure the exact receiver performance.
CC2420 SWRS041B Page 60 of 89 ( /4). They are very easy to design and can be implemented simply as a “piece of wire” or even integrated into the PCB. The length of the /4-monopole antenna is given by: L = 7125 / f where f is in MHz, giving the length in cm.
CC2420 SWRS041B Page 61 of 89 37 Configuration Registers The configuration of CC2420 is done by programming the 16-bit configuration registers. Complete descriptions of the registers are given in the following tables. After chip reset (from the RESETn pin or programmable through the MAIN.
CC2420 SWRS041B Page 62 of 89 Address Register Register ty pe Description 0x0E SAES S AES Stand alone encryption strobe. SPI_SEC_MODE is not required to be 0, but the encryption module must be idle.
CC2420 SWRS041B Page 63 of 89 MAIN (0x10) - Main Control Register Bit Field Name Reset R/W Description 15 RESETn 1 R/W Active low reset of the entir e circuit should be applied before doing anything else. Equi valent to using the RESETn reset pin. 14 ENC_RESETn 1 R/W Active low reset of the encrypt ion module.
CC2420 SWRS041B Page 64 of 89 MDMCTRL0 (0x11) - Modem Control Register 0 Bit Field Name Reset R/W Description 15:14 - 0 W0 Reserved, write as 0 1 3 RESERVED_FRAME_MODE 0 R/W Mode for accepting reserved IEE 802.15.4 frame types when address recognition is enabled ( MDMCTRL0.
CC2420 SWRS041B Page 65 of 89 MDMCTRL1 (0x12)– Modem Control Register 1 Bit Field Name Reset R/W Description 15:11 - 0 W0 Reserved, write as 0. 10:6 CORR_THR[4:0] 2 0 R/W Demodulator correlator threshold value, required before SFD search. Note that on early CC2420 versions the reset value was 0.
CC2420 SWRS041B Page 66 of 89 SYNCWORD (0x14) - Sync Word Bit Field Name Reset R/W Description 15:0 SYNCWORD[15:0] 0xA70F R/W Synchronisation word. The SYNCWORD is processed from the least significant nibble (F at reset) to the most significant nibble (A at reset).
CC2420 SWRS041B Page 67 of 89 RXCTRL0 (0x16) – Receive control register 0 Bit Field Name Reset R/W Description 15:14 - 0 W0 Reserved, write as 0. 13:12 RXMIXBUF_CUR[1:0] 1 R/W RX mixer buffer bias current. 0: 690uA 1: 980uA (nominal) 2: 1.16mA 3: 1.
CC2420 SWRS041B Page 68 of 89 RXCTRL1 (0x17) - Receive control register 1 Bit Field Name Reset R/W Description 15:14 - 0 W0 Reserved, write as 0. 13 RXBPF_LOCUR 0 R/W Controls reference bias current t.
CC2420 SWRS041B Page 69 of 89 FSCTRL (0x18) - Frequency Sy nthesizer Control and Status Bit Field Name Reset R/W Description 15:14 LOCK_THR[1:0] 1 R/W Number of consecutive reference clock periods wit.
CC2420 SWRS041B Page 70 of 89 SECCTRL0 (0x19) - Security Control Register Bit Field Name Reset R/W Description 15:10 - 0 W0 Reserved, write as 0 9 RXFIFO_PROTECTION 1 R/W Protection enable of the RXFIFO, see description in the RXFIFO overflow section on page 33.
CC2420 SWRS041B Page 71 of 89 SECCTRL1 (0x1A) - Security Control Register Bit Field Name Reset R/W Description 15 - 0 W0 Reserved, write as 0 14:8 SEC_TXL 0 R/W Multi-purpose length byte for TX in-lin.
CC2420 SWRS041B Page 72 of 89 IOCFG0 (0x1C) – I/O Configuration Register 0 Bit Field Name Reset R/W Description 15:12 - 0 W0 Reserved, write as 0 11 BCN_ACCEPT 0 R/W Accept all beacon frames when address recognition is enabled. This bit should be set when the PAN identifier programmed into CC2420 RAM is equal to 0xFFFF and cleared otherwise.
CC2420 SWRS041B Page 73 of 89 MANFIDH (0x1F) - Manufacturer ID, Upper 16 Bit Bit Field Name Reset R/W Description 15:12 VERSION[3:0] 3 R Version number. Current version is 3. Note that previous CC2420 versi ons will have lower reset values. 11:0 PARTNUM[15:4] 0 R The device part number.
CC2420 SWRS041B Page 74 of 89 MANAND (0x21) - Manual signal AND override register 1 Bit Field Name Reset R/W Description 15 VGA_RESET_N 1 R/W The VGA_RESET_N signal is used to reset the peak detectors in the VGA in the RX chain.
CC2420 SWRS041B Page 75 of 89 MANOR (0x22) - Manual signal OR override register Bit Field Name Reset R/W Description 15 VGA_RESET_N 0 R/W The VGA_RESET_N signal is used to reset the peak detectors in the VGA in the RX chain.
CC2420 SWRS041B Page 76 of 89 AGCTST0 (0x24) - AGC Test Register 0 Bit Field Name Reset R/W Description 15:12 LNAMIX_HYST[3:0] 3 R/W Hysteresis on the switching betw een different RF front-end gain mo.
CC2420 SWRS041B Page 77 of 89 FSTST0 (0x27) - Frequency Sy nthesizer Test Register 0 Bit Field Name Reset R/W Description 15:12 - 0 W0 Reserved, write as 0 1 1 VCO_ARRAY_SETTLE_LONG 0 R/W When '1' this control bit doubles the time allowed for VCO settling during VCO calibration.
CC2420 SWRS041B Page 78 of 89 FSTST3 (0x2A) - Frequency Sy nthesizer Test Register 3 Bit Field Name Reset R/W Description 15 CHP_CAL_DISABLE 1 R/W Disable charge pump during VCO calibration when set.
CC2420 SWRS041B Page 79 of 89 ADCTST (0x2D) - ADC Test Register Bit Field Name Reset R/W Description 15 ADC_CLOCK_DISABLE 0 R/W ADC Clock Disable 0 : Clock enabled when ADC enabled 1 : Clock disabled, even if ADC is enabled 14:8 ADC_I[6:0] 0 R Read the current ADC I-branch value.
CC2420 SWRS041B Page 80 of 89 TOPTST (0x2F) - Top Level Test Register Bit Field Name Reset R/W Description 15:8 - 0 W0 Reserved, write as 0. 7 RAM_BIST_RUN 0 R/W Enable BIST of the RAM 0 : RAM BIST disabled, normal operation 1 : RAM BIST Enabled. Result output to pin, as set in IOCFG1.
CC2420 SWRS041B Page 81 of 89 38 Test Output Signals The two digital output pins CCA and SFD , can be set up to output test signals defined by IOCFG1.CCAMUX and IOCFG1.
CC2420 SWRS041B Page 82 of 89 SFDMUX Signal output on SFD pin Description 0 SFD Normal operation 1 ADC_I[0] ADC, I-branch, LSB used for random number generation 2 DEMOD_RESYNCH_EARLY High one 16 MHz clock cycle each time the demodulator resynchronises early 3 LOCK_STATUS Lock status, same as FSCTRL.
CC2420 SWRS041B Page 83 of 89 39 Package Description (QLP 48) Note: The figure is an illustration only and not to scale. Quad Leadless Package (QLP) D D1 E E1 e b L D2 E2 QLP 48 Min Max 6.9 7.0 7.1 6.65 6.75 6.85 6.9 7.0 7.1 6.65 6.75 6.85 0.5 0.18 0.
CC2420 SWRS041B Page 84 of 89 40 Recommended layout for package (QLP 48) Note: The figure is an illustration only and not to scale. There are nine 14 mil diameter via holes distributed symmetrically in the gr ound pad under the package. See also the CC2420 EM reference design.
CC2420 SWRS041B Page 85 of 89 40.3 Plastic tube specification QLP 7x7mm antistatic tube. Tube Specification Package Tube Width Tube Height Tube Length Units per Tube QLP 48 8.5 0.2 mm 2.2 +0.2/-0.1 mm 315 1.25 mm 43 40.4 Carrier tape and reel specification Carrier tape and reel is in accordance with EIA Specification 481.
CC2420 SWRS041B Page 86 of 89 42 General Information 42.1 Document History Revision Date Description/Changes SWRS041b 2007-03-19 Slightly changed optimum load impedanc e on Page 9 and 19 to better describe the Application circuit. SWRS041a 2006-12-18 Updated ordering information.
CC2420 SWRS041B Page 87 of 89 Revision Date Description/Changes 1.2 2004-06-09 Output power range: 24 dB (was 40 dB). Deleted option for single ended external PA. Adjacent channel rejection corrected to 46 dB for + 5MHz (was 39 dB), 39 dB for –5 MHz (was 46 dB) 58 dB for +10 MHz (was 53 dB) and 55 dB for-10 MHz (was 57 dB).
CC2420 SWRS041B Page 88 of 89 43 Address Information Texas Instruments Norway AS Gaustadalléen 21 N-0349 Oslo NORWAY Tel: +47 22 95 85 44 Fax: +47 22 95 85 46 Web site: http://ww w.ti.com/lpwrf 44 TI Worldw ide Technical Support Internet TI Semiconductor Product Information Center Home Page: support.
CC2420 SWRS041B Page 89 of 89 Asi a Phone International +886-2-23786800 Domestic T oll-Free Number Australia 1-800-999-084 China 800-820-8682 Hong Kong 800-96-5941 India +91-80-51381665 (Toll) Indones.
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