Benutzeranleitung / Produktwartung STP2002QFP des Produzenten Sun Microsystems
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Revision 1.0–April 1996 STP2002QFP STP2002QFP F ast Ether net, Parallel P ort, SCSI (FEPS) USER’S GUIDE O VERVIEW 1 1.1 Introduction The STP2002QFP FEPS (Fast Ethernet ® , Parallel, SCSI) is an ASIC that pro- vides integrated high-performance SCSI, 10/100 Base-T Ethernet, and a Cen- tronics compatible parallel port.
2 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP terface (CEI) for slave and DMA transfers with the SBus (via SBA). The SBA provides buffering and bus conversion between the SBus and the channel en- gine interface.
3 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 109 rev10h, ISO/IEC 8802-3, IEEE 802.3u 100 Base-T, IEEE 1149.1 ( JTAG), Centronics-protocol-compatible parallel port, and the Sun4u system architecture.
4 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Figure 1. STP2002QFP Block Diagram SBus SBA Channel Engine Interface SCSI_IRQ ENET_IRQ PP_IRQ SCSI DVMA ENET DM.
5 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 1.6 Pin Descriptions The signal pins are grouped by function in the following tables.
6 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP SCSI_XT AL2 O 1 SCSI crystal output SCSI_XT AL1 I 1 SCSI crystal input POD I 1 SCSI power detect T otal SCSI 30.
7 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, T able 4: Parallel P ort Signals Signal Name Type Pin Count Description PP_D A T A[7:0] I/O 8 Parallel port data b.
8 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP T able 6: P ower/Ground/Other Signals Signal Name Type Pin Count Description VDD_CORE 4 VSS_CORE 4 V DD 21 V SS.
9 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, SB US A D APTER 2 2.1 Introduction The SBus Adapter (SBA) is the layer between the Channel Engine Interface (CEI) and the SBus.
10 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP slave accesses from SBus. The physical address is decoded to select a target CE to respond to the access. A physical address that cannot be resolved to the selection of any channel engine will cause SBus Adapter to return Error Ack.
11 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, machine. After this the arbiter is available to arbitrate and grant the next re- quest on the CEI provided that there is a DMA write or read buffer still avail- able.
12 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP SCSI C HANNEL 3 3.1 Introduction The SCSI channel consists of SCSI DVMA (also referred to as SCSI channel engine) and FAS366, a “Fast and Wide” SCSI controller core.
13 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, - 5-MHz synchronous (normal SCSI) - 6-MHz asynchronous • REQ/A CK programmable assertion/deassertion control .
14 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP P ARALLEL P OR T C HANNEL 4 4.1 Introduction The parallel port interface implementation of FEPS is almost identical to the one on the STP2000 Master I/O controller chip to leverage the existing device driver.
15 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, None of these conditions will cause draining if P_ERR_PEND = 1, indi- cating that a memory error has occurred. If condition 4 or 5 occurs when the P_ERR_PEND bit is 1, the P_FIFO will be invalidated and all dirty data will be discarded.
16 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP fined as three SBus clocks. That is, the minimum data strobe width is three SBus clocks. The following table shows the nominal range of programmabil- ity for different SBus clock speeds.
17 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, The desired handshake protocol can be selected using the ACK_OP (acknowledge operation) and BUSY_OP (busy operation) bits of the opera- tions configuration register ( OCR ).
18 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP when the peripheral device cannot receive another byte of data. P_BSY (PP_BSY) is sampled before data strobe becomes active and after data strobe becomes inactive, to ensure that a data transfer is not attempted while the de- vice is busy.
19 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Figure 3. 4.3.1.1.3 Handshake with Busy (ACK_OP=0, BUSY_OP=1) Data transfers are controlled by the use of P_D_STRB (PP_STB) and P_BSY (PP_BSY). P_ACK (PP_ACK) is a don’t care in this mode.
20 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 4.3.1.2 Bidirectional Operation Bidirectional data transfer over the parallel port can be accomplished by the use of either of two master/slave protocols. The “master write” protocol or the “master read/write” protocol.
21 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, When DIR is set to 1, the pins configured as bidirectional change direction and their corresponding direction control pins are set accordingly. Note that the input status pins (ERR, SLCT, PE), which are readable in the input regis- ter, are not configurable.
22 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP These two bits allow selection of one of four possible handshake protocols. The following table summarizes the protocol definitions for transfers to the parallel port from the peripheral device.
23 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, as required to gate further transfers but not as a handshake signal. The oper- ation of the interface as defined assumes the bidirectional sense of each signal has been configured as follows: DIR =1, DS_DSEL =1, ACK_DSEL =1, BUSY_DSEL =1.
24 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Figure 7. 4.3.1.3.4 Handshake with ACK and BUSY: (BUSY_OP=1, ACK_OP=1) Both P_ACK (PP_ACK) and P_BSY (PP_BSY) are generated in response to a data strobe.
25 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 4.3.1.4 Master Read/Write Protocol (Xerox Mode) This section describes the parallel port operation while master read cycles are performed.
26 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP eration for transfers to and from the peripheral device. 4.3.2.1 PIO on Transfers to the Peripheral Device For transfers to the peripheral device, all signals are under the control of soft- ware.
27 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 4.4 Differences fr om STP2000 (MA CIO) Parallel Port • PP_INIT and PP_AFXN hav e extra functions: high and low .
28 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP E THERNET C HANNEL 5 5.1 Introduction The Ethernet channel is a dual-channel intelligent DMA controller on the sys- tem side, and an IEEE 802.3 Media Access Control (MAC) on the network side.
29 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, For TCP packets, hardware support is provided for TCP checksum compu- tation. On transmit, it is assumed that the entire packet is loaded into the local FIFO before its transmission begins.
30 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP • T ransceiver interface (XIF) - Implements the MII interface protocol (excluding the management interface) .
31 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 5.2.2.2 Management Interface Function (MIF) The management interface block implements the management portion of the MII interface to an external transceiver, as defined in the IEEE 802.
32 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP ation can only be used when the MIF is in the frame mode. 5.2.2.3 Ethernet Transmit Block (ETX) The Ethernet transmit block provides the DMA engine for transferring frames from the host memory to the BigMAC.
33 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Receive Clock Domain This clock is used to drive the receive protocol engine in the BigMAC core. It is sourced by the MII and has the operating frequency of 2.5/25 MHz 100 ppm.
34 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP The size of the descriptor ring is programmable, and it can be varied in the range of 16–256 in increments of 16 descriptors: 16, 32, 48, .
35 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 5.2.8 T ransmit FIFO Data Structures When a transmit packet is transferred from the host into the local memory, the first byte of the packet in the FIFO is always loaded to be word (or double- word) aligned.
36 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 5.3 Error Conditions and Reco very There are two types of error conditions that can be encountered during the normal operation of the Ethernet channel: fatal errors and non-fatal errors.
37 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, programmed I/O write cycle. FIFO_Tag_Error The data structures in the local FIFOs make use of tag bits for delimiting packet boundaries. The last data word and the control/status word of a frame are expected to have their tag bits set to 1.
38 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP and gets ready to receive the next frame. This way the FIFO locations that were occupied by the long fragment are reused by the next frame.
39 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 5.4 Programmer’ s Reference 5.4.1 Overview During normal operation, the software-to-hardware interaction is primarily performed via the host memory data structures, with a minimal command/sta- tus handshake (less than one interrupt per packet).
40 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 5.4.3 T ransmit Data Structures Programming Restrictions: • If a packet occupies more than one descriptor , the software must turn ov er the ownership of the descriptors to the hardware last-to-first, in order to av oid race conditions.
41 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, nearest burst boundary and e xecute a full D VMA burst read. Figure 10.
42 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 5.4.4 Receive Data Structures Programming Restrictions: • Free receiv e data buf fers must be 64-byte aligned.
43 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 5.4.5 Local Memory Data Structures The local memory data structures are organized as wrap-around FIFOs that can store an unlimited number of packets.
44 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Figure 11. Recei ve Host Data Structure The software has the capability to read and write the FIFOs (including tags) at any time, using programmed I/O instructions.
45 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Figure 12 below shows the organization of the TxFIFO. The first byte of the frame is always loaded to be word or double-word aligned. 5.4.7 RxFIFO Data Structures Figure 13 below shows the organization of the RxFIFO.
46 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Figure 12. TxFIFO Or ganization 5.4.8 Other User Accessible Resources Besides the host and local memory data s.
47 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, less specified otherwise. Figure 13. RxFIFO Or ganization junk junk junk junk Frame #1 Data Frame #1 Data Frame #1 Control 32-Bit Mode Wrap- Around FIFO 64-Bit Mode 0 31 32 Tag_1 63 Tag_0 Addr_0 junk 0 .
48 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP T EST ABILITY 6 6.1 Introduction This section describes the features of the JTAG Test Access Port (TAP) and other testability structures for the FEPS. The JTAG macro which implements the IEEE Standard 1149.
49 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, The above signals describe the I/O signals of the JTAG macro. The JTAG macro is composed of the following blocks:.
50 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Figure 15. 6.2.2 Instruction Register The instruction register is used to select the test to be performed and/or the test data register to be accessed.
51 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Figure 16. The following instructions are supported in the FEPS.
52 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 6.2.3 Instruction Decode Logic Figure 17. The instruction decode logic decodes the value at the parallel outputs of the instruction register and selects the appropriate scan data register and control signals.
53 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Figure 18. 6.2.4 Bypass Register The bypass register provides a minimum length path between the test data in- put and the test data output.
54 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 6.2.5 Internal Register Clocking Logic This module generates the scan clock for the internal scan flops and the scan enable to for the scan flops. Figure 20. 6.2.
55 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Figure 22. 6.2.8 TDO MUX logic This block implements the muxing of the signal which is to appear at the TDO output pin.
56 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Figure 23. 6.3 Special JT A G Instructions In addition to the mandatory instructions, the FEPS JTAG implements some special instructions. 6.3.1 Deb ug Modes 6.3.
57 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 6.4 Clock Stop Pin This pin can deterministically stop the clocks in FEPS. After the instruction register is updated with the SEL_CCR instruction, an initializing pattern is loaded into the CCR scan data register.
58 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP P R OGRAMMING M ODEL 7 7.1 Introduction Refer to the FEPS application note (STB0106) for programming notes and a complete address map for the registers for all interfaces.
59 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, The RESET state of this register is as follows: P_ERR_PEND = 0 P_INT_EN = 0 P_INVALIDATE = 0 P_SLAVE_ERR = 0 P_RE.
60 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP P_DRAINING bits are not valid while P_ERR_PEND is set and should be ig- nored. P_INVALIDATE: Setting this bit invalidates the P_FIFO. If P_ERR_PEND = 0 when P_INVALIDATE is set, all dirty data in the P_FIFO will first be drained to memory.
61 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, P_BURST_SIZE: This field defines the sizes of SBus read and write bursts used by the FEPS for parallel port transfers. All reads from memory will be one size, either 4, 8, or 1 word (in “no burst mode).
62 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.2.2 DMA Address and Next Address Register This 32-bit read/write register contains the virtual address for parallel port DMA transfers. It is implemented as a 32-bit loadable counter which points to the next byte that will be accessed via the parallel port.
63 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.2.3 Byte Count Register This register is implemented as a 24-bit down counter.
64 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.2.4 T est Control/Status Register T able 25: T est Control/Status Register Address Register Physical Address.
65 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Note: The P_TST_CSR is intended for diagnostic and test use only and should never be written while a DMA transfer is active 7.
66 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP DSS : Data setup to data strobe. This 7-bit quantity is used to define several differ- ent timing specifications for the interface. The contents of this field of the reg- ister are used to load a hardware timer whose timebase is the SBus clock.
67 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, IDLE : When this bit is set, it indicates that the parallel port data transfer state ma- chines are in their idle states. The state machines should be idle when chang- ing direction and/or configuring operational modes and when enabling a memory clear operation.
68 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP isters. This bit must be reset by software. ACK_OP : Used to specify the handshake protocol to be used on the interface. The mean- ing of this bit differs depending on the direction of transfer.
69 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, PP_ACKDIR0 1 BUSY_DSEL : This bit is a bidirectional select for the PP_BSY signal. When reset, PP_BSY is fixed as an input. When set, PP_BSY is a bidirectional signal.
70 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.2.7 P arallel Data Register The data register is an 8-bit read/write port used to transfer data to and from the external device.
71 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, T able 33: Transf er Control Register Address Register Physical Address Access Size T ransfer Control register (P.
72 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP DS : Reading this bit reflects the state of the bidirectional PP_STB pin. Writing this bit with DS_DSEL=0 or with DS_SEL=1 and DIR=0 will cause the value written to be driven onto PP_STB.
73 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, DMA direction. The state of the DIR bit is reflected in the P_WRITE bit of the P_CSR. Reset state of this bit is 1. 7.2.9 Output Register The output register is an 8-bit read/write register whose contents are driven on to the corresponding external pins.
74 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.2.11 Interrupt Control Register This 16-bit read/write register is used to specify operation of the parallel port interrupts. Interrupt enables, polarity, and IRQ pending bits are contained in this register.
75 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, *_IRQ_EN: When set, enables interrupts on the corresponding bits of the input and transfer control registers. Note that the interrupt enable bit of the PD_SCR must also be enabled to allow a hardware interrupt to be generated.
76 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP ing a 0 to these locations leaves the bit(s) unchanged. ACK_IRQ : When set, an interrupt is pending due to the receipt of PP_ACK. The interrupt is set on the 0 to 1 transition of PP_ACK.
77 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, D_INT_PEND: D_WRITE 8 DMA direction for SCSI transfers; 1 = to mem- ory , 0 = from memory R/W D_EN_DMA 9 When set.
78 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP This bit is set to indicate that FAS366 has asserted its interrupt signal. Once FAS366 asserts its interrupt signal, all the bytes in prefetch buffers are drained to the host memory, before setting this bit or generating an interrupt on SBus.
79 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, place. Note: To determine the exact address at which an error occurred, two cases have to be dealt with.
80 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP • Byte counter is decremented, every time a byte is transferred between SCSI and F AS366. • No interrupt is generated when the D_BCNT reaches 0 (expires). • D_BCNT will clear to 0, if D_RESET is asserted.
81 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, buffers, it will be looped back to host memory. FAS366 is completely by- passed during this operation. As the prefetch buffers can store 128 bytes, 128 bytes will be moved from the host memory to SCSI CE.
82 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP This completes the loop-back of 128 bytes. This sequence can be repeated any number of times.
83 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.4 F AS366 (SCSI Controller Cor e) Registers The FAS366 registers are used by the CPU to control the operation of the SCSI bus.
84 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.4.2 F AS366 T ransfer Count Lo w Register (Write Only) This 16-bit transfer count register is comprised of two eight-bit, write-only registers. The transfer count register is normally loaded prior to writing a DMA command to the command register.
85 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.4.4 F AS366 T ransfer Count High (Write Only) Register 7.4.5 F AS366 FIFO Register The SCSI data FIFO consists of 16 registers, each two bytes wide. Data can be read/written from/to FIFO, with a slave or DMA access.
86 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.4.7 F AS366 Status #1 Register This eight-bit, read-only register indicates the status of the FAS366 core and the SCSI bus phase, and qualifies the reason for an interrupt.
87 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, s 7.4.8 F AS366 Select/Reselect Bus ID Register The select/reselect bus ID register is an eight-bit, write-only register that stores encoded values for the SCSI bus ID and the selection/reselection ID.
88 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.4.10 F AS366 Select/Reselect T ime-Out Register The select/reselect time-out register is an eight-bit, write-only register that specifies the amount of time to wait for a response during selection or rese- lection.
89 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.4.12 F AS366 Synchronous T ransfer P eriod Register The synchronous transfer period register is an eight-bit, write-only register.
90 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.4.15 F AS366 Configuration #1 Register The configuration #1 register is an eight-bit, read/write register that specifies different operating options for the FAS366.
91 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.4.17 F AS366 Status #2 Register The status #2 register is a read-only register that indicates detailed status in- formation about the FIFO, the DMA interface, the sequence counter, the transfer counter, the recommand counter, and the command register.
92 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.4.19 F AS366 Configuration #2 Register Configuration #2 is an eight-bit read/write register that specifies different op- erating options for the FAS366.
93 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, After power-up or a chip reset, and until the recommand counter register is loaded, the FAS366 part-unique ID code is readable from the recommand counter low register.
94 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP When both bits read back as 0s, the software is allowed to continue to program the hardware. 7.5.2 Global Configuration Register This five-bit register is used to determine the system-related parameters that control the operation of the DMA channels.
95 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.4 Global Status Register This 32-bit register is used to communicate the software events that were de- tected by the hardware. If a status bit is set to 1, it indicates that the corre- sponding event has occurred.
96 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Excessiv e_Collision_Counter_Expired 12 The Excessi ve_Collision_Counter rolled over from FF to 00 R Late_Coll.
97 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.5 ETX T ransmit P ending Command This one-bit command must be issued by the software for every packet that the driver posts to the hardware. The bit is set to 1 using a programmed I/O write to the defined address.
98 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP The default value of this register is set to 0x3FE 7.5.7 ETX T ransmit Descriptor P ointer (RW) This 29-bit register points to the next descriptor in the ring.
99 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Default: 0xF; 256 descriptor entries. 7.5.9 ETX T ransmit Data Buffer Base Address 7.5.10 ETX T ransmit Data Buffer Displacement (R O) This 10-bit counter keeps track of the next DVMA read burst address.
100 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.11 ETX T ransmit Data P ointer This 32-bit register points to the next DVMA read burst address. Its contents is the sum of the transmit data buffer base address and the transmit data buffer displacement.
101 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.13 ETX TxFIFO Write P ointer This nine-bit loadable counter points to the next location in the FIFO that will be loaded with SBus data, the checksum, or the frame control word.
102 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.15 ETX TxFIFO Read P ointer This nine-bit loadable counter points to the next location in the FIFO that will be read from to retrieve packet data that is transferred to the TX_MAC.
103 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, rewind the read pointer for frame retransmission due to a collision on the net- work. 7.5.17 ETX State Machine Register This 23-bit register provides the current state for all the state machines in ETX.
104 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP • Writing to the lower aperture will load 32 bits of data and clear the tag bit to 0 at the addressed locat.
105 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.20 ERX Receive Descriptor P ointer T able 124: ERX Configuration Register Definition Field Bits Description Type Rx_DMA_Enable 0 When set to 1’, the DMA operation of the channel is enabled.
106 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Note: The receive descriptor pointer must be initialized to a 2K byte- aligned value after power-on or software reset. 7.5.21 ERX Receive Data Buf fer P ointer This 28-bit loadable counter keeps track of the next DVMA write burst ad- dress.
107 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, T able 129: ERX RxFIFO Write P ointer Register Address Register Physical Address Access Size ERX RxFIFO Write Po.
108 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.23 ERX RxFIFO Shado w Write P ointer This nine-bit register points to the first word of the packet that is either cur- rently being loaded or is about to be loaded into the FIFO.
109 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.25 ERX RxFIFO P ack et Counter This eight-bit up/down counter keeps track of the number of frames that cur- rently reside in the RxFIFO.
110 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.27 ERX RxFIFO For diagnostic purposes, a PIO path has been provided into the RxFIFO. When using PIOs, the configuration of the RxFIFO will be 512 × 33bits.
111 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.28 XIF Configuration Register This 10-bit register determines the parameters that control the operation of the transceiver interface.
112 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Default: 0x140. Note: To ensure proper operation of the hardware, when a loop-back configuration is entered or exited, a global initialization sequence should be performed.
113 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, T able 144: TX_MA C Configuration Register Definition Field Bits Description Type TX_MA C_Enabl e 0 When set to 1, the TX_MAC will start requesting packet data from the ETX, and the transmit Ethernet protocol execution will be gin.
114 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Note: To ensure proper operation of the TX_MAC, the TX_MAC_En bit must always be cleared to 0 and a delay imposed before a PIO write to any of the other bits in the TX_MAC Configuration register or any of the MAC parameters registers is performed.
115 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.32 TX_MA C InterP ack etGap2 Register This eight-bit register defines the second 1/3 portion of the InterPacketGap parameter. Default value: 0x04. 7.5.33 TX_MA C AttemptLimit Register Default value: 0x10.
116 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Default value: 0x40. 7.5.35 TX_MA C P A Size Register Default value: 0x07.
117 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.37 TX_MA C SFD P attern Register Default value: 0xAB 7.5.38 TX_MA C J amSize Register Default value: 0x04.
118 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Default value: 0x05EE. 7.5.40 TX_MA C TxMinF rameSize Register Default value: 0x40 7.
119 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.42 TX_MA C Defer T imer 7.5.43 TX_MA C Normal Collision Counter 7.
120 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.45 TX_MA C Excessive Collision Counter 7.5.46 TX_MA C Late Collision Counter This eight-bit loadable counter increments for every transmit frame that has experienced a late collision.
121 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.47 TX_MA C Random Number Seed Register This 10-bit register is used as a seed for the random number generator in the backoff algorithm.
122 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.49 RX_MA C Software Reset Command This 16-bit command performs a software reset to the logic in the RX_MAC. The defined address must be written with the value of 0x0000.
123 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, Note: To ensure proper operation of the RX_MAC, the RX_MAC_En bit must always be cleared to 0 and a delay of 3.
124 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP may be polled, and when this bit reads back as a 0, all the registers mentioned above may be written. 7.5.51 RX_MA C RxMaxF rameSize Register Default value: 0x05EE.
125 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.53 RX_MA C MA C Address 2 Register T able 188: RX_MA C MA C Address 2 Register Address Register Physical Add.
126 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.54 RX_MA C MA C Address 1 Register 7.5.55 RX_MA C MA C Address 0 Register T able 189: RX_MA C MA C Address 2 Register Definition Field Bits Description Type 15:0 16 most significant bits of the MAC address.
127 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.56 RX_MA C Receive F rame Counter 7.5.57 RX_MA C Length Error Counter 7.5.58 RX_MA C Alignment Error Counter This eight-bit loadable counter increments when an alignment error was de- tected in a receive frame.
128 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.59 RX_MA C FCS Error Counter 7.5.60 RX_MA C State Machine Register This seven-bit register provides the current state for all the state machines in the RX_MAC.
129 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.61 RX_MA C Rx Code V iolation Counter 7.5.62 RX_MA C Hash T able 3 Register 7.
130 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.64 RX_MA C Hash T able 1 Register 7.5.65 RX_MA C Hash T able 0 Register 7.5.66 RX_MA C Address F ilter 2 Register T able 209: RX_MA C Hash T able 2 Register Definition Field Bits Description Type 15:0 Contains bits [47:32] of the hash table.
131 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.67 RX_MA C Address F ilter 1 Register 7.5.68 RX_MA C Address F ilter 0 Register 7.
132 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.70 MIF Bit-Bang Clock This one-bit register is used to generate the MDC clock waveform on the MII management interface when the MIF is programmed in the Bit-Bang Mode.
133 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.73 MIF F rame/Output Register This 32-bit register serves as an “instruction register” when the MIF is pro- grammed in the frame mode.
134 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 7.5.74 MIF Configuration Register This 15-bit register controls the operation of the MIF. REGAD 22:18 REGister ADdress. When issuing an instruction, this field should be loaded with the address of the register that is to be read/ written.
135 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.75 MIF Mask Register This 16-bit register is used to determine which bits in the poll status portion of the MIF status register will cause an interrupt.
136 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Default value: 0xFFFF. 7.5.76 MIF Status Register This 32-bit register is used in conjunction with the poll mode in the MIF. It contains two portions: poll data and poll status.
137 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 7.5.77 MIF State Machine Register This nine-bit register provides the current state for all the state machines in the MIF.
138 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP P IN A SSIGNMENTS 8 8.1 Pin Assignments The Table 235 describes the pin assignments for the 240-pin PQFP FEPS package. T able 235: STP2002QFP Pin Assignments Pin No.
139 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 28 ENET_RX_D V I_SCSI_A0 29 ENET_RXD[0] I_SCSI_A2 30 VSS_CORE 31 ENET_RXD[1] I_SCSI_A3 32 VDD_CORE 33 ENET_RXD[2.
140 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 62 SCSI_D[6] 63 SCSI_D[5] 64 SCSI_D[4] 65 VSS_IO 66 SCSI_D[3] 67 SCSI_D[2] 68 SCSI_D[1] 69 VSS_IO 70 SCSI_D[0.
141 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 96 SB_SEL 97 SB_AS 98 SB_D[0] 99 VDD_IO 100 SB_D[1] 101 VSS_IO 102 SB_D[2] 103 SB_D[3] 104 VSS_IO 105 SB_D[4] 10.
142 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 130 SB_D[19] 131 SB_D[20] 132 VSS_IO 133 SB_D[21] 134 VDD_IO 135 SB_D[22] 136 VSS_IO 137 SB_D[23] 138 SB_D[24.
143 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 164 VSS_IO 165 SB_P A[0] IO_SCSI_DB[04] 166 SB_P A[1] IO_SCSI_DB[03] 167 SB_P A[2] IO_SCSI_DB[02] 168 VSS_IO 169.
144 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP 198 V SS 199 SB_P A[20] 200 SB_P A[21] 201 SB_P A[22] 202 VSS_IO 203 SB_P A[23] 204 VDD_IO 205 SB_P A[24] 206.
145 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, 232 PP_D[2] 233 VSS_IO 234 PP_D[1] 235 PP_D[0] 236 PP_SLCT_IN 237 PP_INIT 238 VDD_IO 239 PP_DS_DIR 240 VSS_IO T able 235: STP2002QFP Pin Assignments Pin No.
146 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP E RRA T A 9 9.1 Description of Errata in FEPS Rev 2.2 The following are some known problems and workarounds for Rev 2.2. of the FEPS. The device driver for the SCSI channel has software workarounds for all of these problems.
147 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, byte count must become 1 before it can initiate the padding. So byte count not decrementing all the way to 1 makes the SCSI CE not write the last one byte to the FAS366 (when all of the conditions described above are met).
148 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Work Around : Device driver normally does not access the FAS366 after enabling DMA, so it is not a problem. Device driver may access the FAS366 after enabling the DMA, in the case of error recovery.
149 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems, operation. After power-on, the D_ADDR register does not get self initialized.
150 STP2002QFP Sun Microelectronics Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Work Around : After every external reset (coming from the SCSI bus to the FAS366), the de- vice driver should issue a chip reset to the FAS366. This prevents a mismatch between REQs and ACKs.
151 STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP Sun Microsystems,.
A Sun Microsystems Inc. Business 2550 Garcia A venue, Mountain V iew , CA, U.S.A. 94043 (408) 774-8545 Fax (408) 774-8537 © 1996 Sun Microsystems Incorporated All rights reserved. This publication contains information considered proprietary by Sun Microsystems Incorporated.
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Wenn Sie Sun Microsystems STP2002QFP noch nicht gekauft haben, ist jetzt ein guter Moment, um sich mit den grundliegenden Daten des Produkts bekannt zu machen. Schauen Sie zuerst die ersten Seiten der Anleitung durch, die Sie oben finden. Dort finden Sie die wichtigsten technischen Daten für Sun Microsystems STP2002QFP - auf diese Weise prüfen Sie, ob das Gerät Ihren Wünschen entspricht. Wenn Sie tiefer in die Benutzeranleitung von Sun Microsystems STP2002QFP reinschauen, lernen Sie alle zugänglichen Produktfunktionen kennen, sowie erhalten Informationen über die Nutzung. Die Informationen, die Sie über Sun Microsystems STP2002QFP erhalten, werden Ihnen bestimmt bei der Kaufentscheidung helfen.
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