Benutzeranleitung / Produktwartung SME5224AUPA-400 des Produzenten Sun Microsystems
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DA T ASHEET 1 SME5224A UP A-400 UltraSP ARC ™ -II CPU Module 400 MHz CPU, 4.0 MB E-Cache M ODULE D ESCRIPTION The UltraSP ARC™–II, 400 MHz CPU, 4.
2 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc CPU D ESCRIPTION UltraSP ARC-II CPU The UltraSP ARC™-II CPU is the second generation in the UltraSPARC™ s-series microprocessor family.
3 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc D ATA B UFFER D ESCRIPTION UltraSP ARC-II Data Buf fer (UDB-II) The UltraSP.
4 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc M ODULE C OMPONENT O VER VIEW The UltraSP ARC™–II, 400 MHz CPU, 4.
5 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc S YSTEM I NTERF A CE Figure 2 shows the major components of a UP A based uniprocessor system. The system controller [1] for the UP A bus arbitrates between the UltraSP ARC™–II, 400 MHz CPU, 4.
6 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc Module ID Module IDs are used to configur e the UP A address of a module. The UP A_PORT_ID[4:3] ar e hardwir ed on the module to “0”. UP A_POR T_ID[1:0] are br ought out to the connector pins.
7 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc S IGNAL D ESCRIPTION [1] System Interface Signal T ype Name and Function UP A_ADDR[35:0] I/O P ack et s witched transaction request b us.
8 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc JT A G/Debug Interface Signal T ype Name and Function TDO O IEEE 1149 test data output. A three-state signal driven only when the T AP controller is in the shift-DR state.
9 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc UP A AND CPU C LOCKS Module Clocks The module receives three differ ential pair low voltage PECL (L VPECL) clock signals (CPU_CLK, UP A_CLK0 and UP A_CLK1) from the systemboar d and terminates them.
10 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc . LOW VOL T AGE PECL T wo trace signals compose each clock: one positive signal and one negative signal. Each signal is 180-degrees out of phase with the other .
11 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc E LECTRICAL C HARA CTERISTICS Absolute Maximum Ratings [1] 1. Operation of the device at v alues in excess of those listed above will result in deg radation or destruction of the device .
12 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc Module P ower Consumption This UltraSP ARC-II module requires two supply voltages. The requir ed voltages (provided to the module) for the V DD and V DD_CORE , are r espectively 3.
13 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc UP A Data Bus SPICE Model A typical circuit for the UP A data bus and ECC signals is illustrated in Figure 4 :. Figure 4. Module System Loading: Example for UP A_DA T A, UP A_ECC 3.
14 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc U P AA CT IMING S PECIFICA TIONS The UP A AC T iming Specifications are refer enced to the UP A connector . The timing assumes that the clocks are corr ectly distributed, (see the section "System Clock Distribution," on page 9).
15 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc The following table, "Propagation Delay , Output Hold T ime Specifications," specifies the propagation delay and output hold times for the UltraSP ARC™–II, 400 MHz CPU, 4.
16 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc M ECHANICAL S PECIFICA TIONS The module components and dimensions are specified in Figure 6 , Figur e 7 , Figure 8 and Figure 9 . Figure 6. CPU Module Components Figure 7.
17 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc Figure 8. CPU Module Side View Figure 9. CPU Module Side View Dimensions NOTE: A minimum backside clearance is requir ed for airflow cooling of the backside heatsink.
18 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc T HERMAL S PECIFICA TIONS The maximum CPU operating frequency and I/O timing is r educed when the junction temperature (Tj) of the CPU device is raised.
19 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc Thermal Definitions and Specifications T erm Definition Specification Comments Tj Maximum device junction temperature 85 ° C, The Tj can't be measured directly by a thermo-couple probe.
20 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc T emperature Estimating and Measuring Methods The following methods can be used to estimate air cooling requir ements and calculate junction temperature based on thermo-couple temperature measur ements.
21 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc Case T emperature Measuring Method The relationship between case temperatur e and junction temperature is described in the following thermal equation.
22 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc JT A G T EST ABILITY The UltraSP ARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUP A-400), implements the IEEE 1 149.1 standard to aid in boar d level testing.
23 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc JT A G (IEEE 1149.1) T IMING Figure 10. V oltage W avef orms - Setup and Hold Times Data Input t H 1.5V V IH V IL Clock t SU 2.
24 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc UP A C ONNECT OR P IN A SSIGNMENTS (T OP V IEW ) Pin 1 (Pin 4) UP A_ADDR[1] (Pin 1) UP A_AD.
25 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc UP A C ONNECT OR P IN A SSIGNMENTS (B OT TO M V IEW ) UP A_ADDR[9] (Pin 6).
26 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc H ANDLING CPU M ODULES CAUTION : Handle a module by carefully holding it by its edges and by the lar ge CPU heatsink. Do not bump or handle the SRAM heatsinks because this action can cause unseen damage to the solder connections.
27 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc O RDERING I NFORMA TION [1] 1. T o order the data sheet for this device use the document part number: 805-6390-05 Part Number CPU Speeds Description SME5224A UP A-400 400 MHz CPU The UltraSP ARC™–II, 400 MHz CPU, 4.
©1999 Sun Microsystems, Inc. All Rights reserved. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED “AS IS” WITHOUT ANY EXPRESS REPRESENTATIONS OF WARRANTIES.
DA T ASHEET 1 SME5224A UP A-400 UltraSP ARC ™ -II CPU Module 400 MHz CPU, 4.0 MB E-Cache M ODULE D ESCRIPTION The UltraSP ARC™–II, 400 MHz CPU, 4.
2 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc CPU D ESCRIPTION UltraSP ARC-II CPU The UltraSP ARC™-II CPU is the second generation in the UltraSPARC™ s-series microprocessor family.
3 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc D ATA B UFFER D ESCRIPTION UltraSP ARC-II Data Buf fer (UDB-II) The UltraSP.
4 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc M ODULE C OMPONENT O VER VIEW The UltraSP ARC™–II, 400 MHz CPU, 4.
5 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc S YSTEM I NTERF A CE Figure 2 shows the major components of a UP A based uniprocessor system. The system controller [1] for the UP A bus arbitrates between the UltraSP ARC™–II, 400 MHz CPU, 4.
6 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc Module ID Module IDs are used to configur e the UP A address of a module. The UP A_PORT_ID[4:3] ar e hardwir ed on the module to “0”. UP A_POR T_ID[1:0] are br ought out to the connector pins.
7 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc S IGNAL D ESCRIPTION [1] System Interface Signal T ype Name and Function UP A_ADDR[35:0] I/O P ack et s witched transaction request b us.
8 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc JT A G/Debug Interface Signal T ype Name and Function TDO O IEEE 1149 test data output. A three-state signal driven only when the T AP controller is in the shift-DR state.
9 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc UP A AND CPU C LOCKS Module Clocks The module receives three differ ential pair low voltage PECL (L VPECL) clock signals (CPU_CLK, UP A_CLK0 and UP A_CLK1) from the systemboar d and terminates them.
10 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc . LOW VOL T AGE PECL T wo trace signals compose each clock: one positive signal and one negative signal. Each signal is 180-degrees out of phase with the other .
11 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc E LECTRICAL C HARA CTERISTICS Absolute Maximum Ratings [1] 1. Operation of the device at v alues in excess of those listed above will result in deg radation or destruction of the device .
12 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc Module P ower Consumption This UltraSP ARC-II module requires two supply voltages. The requir ed voltages (provided to the module) for the V DD and V DD_CORE , are r espectively 3.
13 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc UP A Data Bus SPICE Model A typical circuit for the UP A data bus and ECC signals is illustrated in Figure 4 :. Figure 4. Module System Loading: Example for UP A_DA T A, UP A_ECC 3.
14 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc U P AA CT IMING S PECIFICA TIONS The UP A AC T iming Specifications are refer enced to the UP A connector . The timing assumes that the clocks are corr ectly distributed, (see the section "System Clock Distribution," on page 9).
15 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc The following table, "Propagation Delay , Output Hold T ime Specifications," specifies the propagation delay and output hold times for the UltraSP ARC™–II, 400 MHz CPU, 4.
16 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc M ECHANICAL S PECIFICA TIONS The module components and dimensions are specified in Figure 6 , Figur e 7 , Figure 8 and Figure 9 . Figure 6. CPU Module Components Figure 7.
17 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc Figure 8. CPU Module Side View Figure 9. CPU Module Side View Dimensions NOTE: A minimum backside clearance is requir ed for airflow cooling of the backside heatsink.
18 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc T HERMAL S PECIFICA TIONS The maximum CPU operating frequency and I/O timing is r educed when the junction temperature (Tj) of the CPU device is raised.
19 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc Thermal Definitions and Specifications T erm Definition Specification Comments Tj Maximum device junction temperature 85 ° C, The Tj can't be measured directly by a thermo-couple probe.
20 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc T emperature Estimating and Measuring Methods The following methods can be used to estimate air cooling requir ements and calculate junction temperature based on thermo-couple temperature measur ements.
21 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc Case T emperature Measuring Method The relationship between case temperatur e and junction temperature is described in the following thermal equation.
22 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc JT A G T EST ABILITY The UltraSP ARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUP A-400), implements the IEEE 1 149.1 standard to aid in boar d level testing.
23 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc JT A G (IEEE 1149.1) T IMING Figure 10. V oltage W avef orms - Setup and Hold Times Data Input t H 1.5V V IH V IL Clock t SU 2.
24 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc UP A C ONNECT OR P IN A SSIGNMENTS (T OP V IEW ) Pin 1 (Pin 4) UP A_ADDR[1] (Pin 1) UP A_AD.
25 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc UP A C ONNECT OR P IN A SSIGNMENTS (B OT TO M V IEW ) UP A_ADDR[9] (Pin 6).
26 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc H ANDLING CPU M ODULES CAUTION : Handle a module by carefully holding it by its edges and by the lar ge CPU heatsink. Do not bump or handle the SRAM heatsinks because this action can cause unseen damage to the solder connections.
27 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc O RDERING I NFORMA TION [1] 1. T o order the data sheet for this device use the document part number: 805-6390-05 Part Number CPU Speeds Description SME5224A UP A-400 400 MHz CPU The UltraSP ARC™–II, 400 MHz CPU, 4.
©1999 Sun Microsystems, Inc. All Rights reserved. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED “AS IS” WITHOUT ANY EXPRESS REPRESENTATIONS OF WARRANTIES.
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