Benutzeranleitung / Produktwartung F77G des Produzenten Panasonic
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MICROCOMPUTER MN101C MN101C77C/F77G LSI User ’ s Manual Pub.No.21477-01 1E.
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PanaXSeries is a trademark of Matsus hita Electr ic Industrial Co., Ltd. The other corporation names, logotype and product names written in this bo ok are tradem arks or registered trademarks of their corresponding corporations.
About This Manual 1 Organization In this LSI manual, this LSI functions are presented in the following order : overview , basic CPU functions, interrupt functions, port functions, timer functions, serial functions, and other peripheral hardware functions.
About This Manual 2 Finding Desired Information This manual provides three methods for finding desired information quickly and easily. (1) Consult the index at the front of the manual to locate the beginning of each section. (2) Consult the table of contents at the front of the manual to locate desired titles.
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Chapter 1 Overview 1 Chapter 2 CPU Basics 2 Chapter 3 Interrupts 3 3 Chapter 4 I/O Ports 4 1 1 2 Chapter 5 Prescaler 5 Chapter 6 8-bit Timers 6 Chapter 7 16-bit Timer 7 Chapter 8 Time Base Timer / 8-b.
contents ii Chapter 1 Overview 1 - 1 Overview ..................................................................................................................... I - 2 1-1-1 Overview ..................................................................
contents iii 2-3-1 Bus Controller ......................................................................................... II - 15 2-3-2 Control Registers ..................................................................................... II - 16 2 - 4 Standby Function .
contents iv 3-3-8 A C Zero-Cross Detector ........................................................................ III - 54 Chapter 4 I/O Ports 4 - 1 Overview ............................................................................................
contents v 4-10-1 Registers ................................................................................................ IV - 4 5 4-10-2 Operation ................................................................................................ IV - 4 6 4-11 Synchronous Output (Port 7) .
contents vi 6-7-1 Operation ................................................................................................ VI - 3 0 6-7-2 Setup Example ........................................................................................ V I - 31 6 - 8 Serial Interface Transfer Clock Output .
contents vii 7-8-1 Operation ............................................................................................ VII - 31 7-8-2 Setup Example .................................................................................... VII - 32 7-9 16-bit T imer Capture .
contents viii 11-1 Overview .................................................................................................................. XI - 2 11-1-1 Functions ....................................................................................
contents ix 13-1-2 Block Diagram ....................................................................................... XIII - 3 13-2 Control Registers ..................................................................................................
contents x 15-1-2 Block Diagram ........................................................................................ XV - 3 15-2 Control Registers ....................................................................................................
contents xi 18-4 Reprogramming Flow ........................................................................................... XVIII - 9 18-5 PROM writer mode ...........................................................................................
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Chapter 1 Overview 1.
Chapter 1 Overview I - 2 Overview 1-1 Overview 1-1-1 Overview The MN101C series of 8-bit single-chip microcontroller incorporates multiple types of peripheral functions.
I - 3 Chapter 1 Overview Hardware Functions 1-2 Hardware Functions CPU Core MN101C Core - LOAD-STORE architecture (3-stage pipeline) - Half-byte instruction set / Handy addressing - Memory addressing space is 256 KB - Minimum instructions execution time (3.
Chapter 1 Overview I - 4 Hardware Functions < Serial interface interrupts > - Serial interface 0 reception interrupt (Full-Duplex UART) - Serial interface 0 transmission interrupt (synchronous +.
I - 5 Chapter 1 Overview Hardware Functions Timer 4 ( 8-Bit timer for general use or UART baud rate timer ) - Square wave output ( Timer pulse output ), PWM output, Event count Simple pulse width meas.
Chapter 1 Overview I - 6 Hardware Functions Watchdog timer - Watchdog timer frequency can be selected from fs/2 16 , fs/2 18 or fs/2 20 . Remote control output Based on the timer 0, and timer 3 output, a remote control carrier with duty cycle of 1/2 or 1/3 can be output.
I - 7 Chapter 1 Overview Hardware Functions Serial interface 1 ( Full-Duplex UART / Synchronous serial interface ) ❑ Synchronous serial interface - Transfer clock source fosc/2, fosc/4, fosx/16, fosc/64, fs/2, fs/4 1/2 of UART baud rate timer ( timer 4 ) output - MSB/LSB can be selected as the first bit to be transferred.
Chapter 1 Overview I - 8 Hardware Functions On Flash version MN101CF77G, NC pin cannot be used as user pin as it is used as V PP pin. Refer to chapter 18 Flash EEPROM when designing your board for compatibility with Flash version. Set V REF + to V DD , V REF - to V SS even when A/D converter is not used.
I - 9 Chapter 1 Overview Pin Description 1-3 Pin Description 1-3-1 Pin Configuration Figure 1-3-1 Pin Configuration ( 64 LQFP/64TQFP : Top view ) MN101C77C - 64 pin for general use - 5 6 7 8 9 10 11 1.
Chapter 1 Overview I - 10 Pin Description 1-3-2 Pin Specification Table 1-3-2 Pin Specification P00 SBO1A TXD1A in/out P0DIR0 P0PLU0 SBO1A : Serial Interface 1 transmission data output TXD1A : UART 1 .
I - 11 Chapter 1 Overview Pin Description 1-3-3 Pin Functions Table 1-3-3 Pin Function Summary (1/6) Nam e N o. I / O F unc t ion O t her F unct io n Des cr ipt ion V DD 7 Power s upply p in VS S 1 0 .
Chapter 1 Overview I - 12 Pin Description Table 1-3-4 Pin Function Summary (2/6) Nam e No. I / O F unct ion O t her F unc t i on Descr i pt ion P2 0 2 7 I/O I/O p o rt 2 IR Q0 P21 28 IRQ1, A C Z P22 2 9 IRQ2 P23 3 0 IRQ3 P24 3 1 IRQ4 P27 14 I np ut I/ O por t 2 NRST P27 has an n-c hannel ope n-dr ain conf igu rat ion.
I - 13 Chapter 1 Overview Pin Description Table 1-3-5 Pin Function Summary (3/6) Nam e N o. I / O F unc t ion Ot her F unct ion D es cript ion SB O 0A 18 O ut put P03, T X D 0A SBO0B 48 P7 0 , T X D 0.
Chapter 1 Overview I - 14 Pin Description Table 1-3-6 Pin Function Summary (4/6) N a m e N o . I/O Fu n c ti o n Oth e r Fu n c ti o n D e s c r i p ti o n RX D0A 19 I nput SBI 0A , P 04 R X D 0 B 4 9.
I - 15 Chapter 1 Overview Pin Description Table 1-3-7 Pin Function Summary (5/6) N a m e N o . I/O Fu n c ti o n Oth e r Fu n c ti o n D e s c r i p ti o n BUZ Z E R 21 O ut put Buz z er out put P06 Piez o elect r ic buz z er driv e r pin. T he driv in g f r equency can be s e lect ed by t he DLY C T R re g i s te r .
Chapter 1 Overview I - 16 Pin Description Table 1-3-8 Pin Function Summary (6/6) Nam e N o. I / O F unct ion Ot her F un ct ion Des cr i pt ion KEY 0 3 7 I /O P60 , SD O0 KEY 1 3 8 P61 , SDO1 KEY 2 3 .
I - 17 Chapter 1 Overview Block Diagram 1-4 Block Diagram 1-4-1 Block Diagram Figure 1-4-1 Block Diagram CPU MN101C Low Speed oscillator ROM 48KB RAM 3KB 8-Bit Timer 0 8-Bit Timer 1 8-Bit Timer 4 16-B.
Chapter 1 Overview I - 18 Electrical Characteristics 1-5 Electrical Characteristics *1 Applied to any 100 ms period. *2 Connect at least one bypass capacitor of 0.
I - 19 Chapter 1 Overview Electrical Characteristics 1-5-2 Operating Conditions *1 tc1, tc2, tc3 : 1/2 of high speed oscillation tc4 : 1/2 of high speed oscillation [ NORMAL mode : fs=fosc/2, SLOW mod.
Chapter 1 Overview I - 20 Electrical Characteristics *1 The clock duty rate should be 45% to 55%. Certain operating conditions differ between the mask ROM version and the Flash version. Refer to chapter 18 Flash EEPROM for electrical characteristics of the Flash version.
I - 21 Chapter 1 Overview Electrical Characteristics t wh2 t wl2 t wf2 t wc2 t wr2 0.9V DD 0.1V DD Figure 1-5-3 OSC1 Timing Chart Figure 1-5-4 XI Timing Chart t wh1 t wl1 0.
Chapter 1 Overview I - 22 Electrical Characteristics 1-5-3 DC Characteristics *1 Measured under conditions of Ta=25 °C, without load. - The supply current during operation, I DD1 (I DD2 ), is measure.
I - 23 Chapter 1 Overview Electrical Characteristics Figure 1-5-5 AC Zero-Cross Detector t rs ( Input ) ( Output ) V DD V DHL V DHH V DLL V DLH V SS t fs Input voltage level 1 Input voltage level 2 T a = - 40 o C to +8 5 o C V DD =1 .
Chapter 1 Overview I - 24 Electrical Characteristics T a =- 40 o C t o +85 o C V DD = 1 .8 V t o 3 .6 V V SS =0 V MIN T YP MAX I nput pin 3 P 27 ( NRST ) 19 20 21 I/O p i n 4 P A0 to P A6 22 23 24 25 .
I - 25 Chapter 1 Overview Electrical Characteristics MI N T YP MA X I/O p i n 7 P8 0 to P8 7 42 43 44 45 46 47 48 Unit P ar am et er Sy m bol Cond it ions V DD=1 . 8 V t o 3. 6 V V SS = 0 V Rat ing Ta = -4 0 o C t o +85 o C ± 10 V DD V I nput high c ur rent I IH7 V DD = 3 .
Chapter 1 Overview I - 26 Electrical Characteristics 1-5-4 A/D Converter Characteristics *2 *1 Set the potential difference between V REF+ and V REF- over 2 V. *2 The value is measured with A/D Converter, not with D/A Converter. T a =- 4 0 o C t o +85 o C V DD = 3.
I - 27 Chapter 1 Overview Precautions 1-5-5 D/A Converter Characteristics *2 *1 The standard value is guaranteed under condition of V DD =V REF+ =3.3 V, V REF -=0.0 V . *2 The value is measured with D/A Converter, not with A/D Converter. T a = -40 o C t o +85 o C V DD = 3.
Chapter 1 Overview I - 28 Electrical Characteristics 1-6 Precautions 1-6-1 General Usage Connection of V DD pin, and V SS pin All V DD pins should be connected directly to the power supply and all Vss pins should be connected to ground in the external.
I - 29 Chapter 1 Overview Precautions 1-6-2 Unused Pins Unused Pins (only for input) Insert 10 k Ω to 100 k Ω resistor to unused pins (only for input) for pull-up or pull-down. If the input is unstable, Pch transistor and Nch transistor of input inverter are on, and through current goes to the input circuit.
Chapter 1 Overview I - 30 Precautions Unused pins (for I/O) Unused I/O pins should be set according to pins' condition at reset. If the output is high impedance (Pch / Nch transistor : output off) at reset, to stabilize input, set 10 k Ω to 100 k Ω resistor to be pull-up or pull- down.
I - 31 Chapter 1 Overview Precautions 1-6-3 Power Supply The Relation between Power Supply and Input Pin Voltage Input pin voltage should be supplied only after power supply is on. If the input pin voltage is applied supplies before power supply is on, a latch up occurs and causes the destruction of micro controller by a large current flow.
Chapter 1 Overview I - 32 Precautions 1-6-4 Power Supply Circuit Cautions for Setting Power Supply Circuit The CMOS logic microcontroller is high speed and high density. So, the power circuit should be de- signed, taking into consideration of AC line noise, ripple caused by LED driver.
I - 33 Chapter 1 Overview Package Dimension 1-7 Package Dimension Package Code : LQFP064-P-1414 Units : mm.
Chapter 1 Overview I - 34 Precautions Package Code : TQFP064-P-1010C Units : mm.
Chapter 2 CPU Basics 2 1 1 2.
Chapter 2 CPU Basics II - 2 Overview 2-1 Overview The MN101C CPU has a flexible optimized hardware configuration. It is a high speed CPU with a simple and efficient instruction set. Specific features are as follows: Table 2-1-1 Basic Specifications 1.
II - 3 Chapter 2 CPU Basics Overview Figure 2-1-1 Block Diagram and Function 2-1-1 Block Diagram A1 A0 D1 D0 D3 D2 T1 T2 Clock generator Source oscillation Instruction execution controller Instruction.
Chapter 2 CPU Basics II - 4 Overview 2-1-2 CPU Control Registers This LSI locates the peripheral circuit registers in memory space (x'03F00' to x'03FFF') with memory- mapped I/O. CPU control registers are also located in this memory space.
II - 5 Chapter 2 CPU Basics Overview 2-1-3 Instruction Execution Controller The instruction execution controller consists of four blocks: memory, instruction queue, instruction regis- ters, and instruction decoder. Instructions are fetched in 1-byte units, and temporarily stored in the 2-byte instruction queue.
Chapter 2 CPU Basics II - 6 Overview 2-1-4 Pipeline Process Pipeline process means that reading and decoding are executed at the same time on different instruc- tions, then instructions are executed without stopping. Pipeline process makes instruction execution continual and speedy.
II - 7 Chapter 2 CPU Basics Overview Address Registers (A0, A1) These registers are used as address pointers specifying data locations in memory. They support the operations involved in address calculations (i.e. addition, subtraction and comparison).
Chapter 2 CPU Basics II - 8 Overview 2-1-7 Processor Status Word Processor status word (PSW) is an 8-bit register that stores flags for operation results, interrupt mask level, and maskable interrupt enable.
II - 9 Chapter 2 CPU Basics Overview Zero Flag (ZF) Zero flag (ZF) is set to "1", when all bits are '0' in the operation result. Otherwise, zero flag is cleared to "0". Carry Flag (CF) Carry flag (CF) is set to "1", when a carry from or a borrow to the MSB occurs.
Chapter 2 CPU Basics II - 10 Overview 2-1-8 Addressing Modes The MN101C77G series supports the nine addressing modes. Each instruction uses a combination of the following addressing modes.
II - 11 Chapter 2 CPU Basics Overview Table 2-1-4 Addressing Modes Addressing mode Effective address Explanation Register direct Immediate Register indirect Register relative indirect (d7, PC) (d8, An) (An) imm4/imm8 imm16 Dn/DWn An/SP PSW 0 0 0 0 H (d16, An) (branch instructions only) An An+d8 An+d16 PC+d7 Directly specifies the register.
Chapter 2 CPU Basics II - 12 Memory Space 2-2 Memory Space 2-2-1 Memory Mode ROM is the read only area and RAM is the memory area which contains readable/writable data. In addition to these, peripheral resources such as memory-mapped special registers are allocated.
II - 13 Chapter 2 CPU Basics Memory Space Figure 2-2-1 Single-chip Mode 2-2-2 Single-chip Mode In single-chip mode, the system consists of only internal memory. This is the optimized memory mode and allows construction of systems with the highest performance.
Chapter 2 CPU Basics II - 14 Memory Space 2-2-3 Special Function Registers The MN101C series locates the special function registers (I/O spaces) at the addresses x'03F00' to x'03FFF' in memory space. The special function registers of this LSI are located as shown below.
II - 15 Chapter 2 CPU Basics Bus Interface 2-3 Bus Interface 2-3-1 Bus Controller The MN101C series provides separate buses to the internal memory and internal peripheral circuits to reduce bus line loads and thus realize faster operation. There are three such buses: ROM bus, RAM bus, and peripheral expansion bus (I/O bus).
Chapter 2 CPU Basics II - 16 Bus Interface 2-3-2 Control Registers Bus interface is controlled by these 8 bytes of registers : the memory control register (MEMCTR), memory area control register (AREACTR) and bus mode control register (CSMDn).
II - 17 Chapter 2 CPU Basics Bus Interface Memory Area Control Register (AREACTR) Figure 2-3-3 Memory Area Control Register (AREACTR : x'03F03', R/W) The MN101CF77 contains internal memory in CSI area. Therefore, set the CS1EXT flag of the memory area control register (AREACTR) to "0" .
Chapter 2 CPU Basics II - 18 Bus Interface Bus Mode Control Register (CSMDn) Figure 2-3-4 Bus Mode Control Register (CSMDn : x'03F05' to x'03F09', R/W) Select 101C bus mode for the area (CS1 to CS8) where internal memory is set with the memory area control register.
II - 19 Chapter 2 CPU Basics Standby Functions 2-4 Standby Function 2-4-1 Overview This LSI has two sets of system clock oscillator (high speed oscillation, low speed oscillation) for two CPU operating modes (NORMAL and SLOW), each with two standby modes (HALT and STOP).
Chapter 2 CPU Basics II - 20 Standby Functions HALT Modes (HALT0, HALT1) − The CPU stops operating. But both of the oscillators remain operational in HALT0 and only the high- frequency oscillator stops operating in HALT1. − An interrupt returns the CPU to the previous CPU operating mode that is, to NORMAL from HALT0 or to SLOW from HALT1.
II - 21 Chapter 2 CPU Basics Standby Functions Figure 2-4-2 Operating Mode and Clock Oscillation (CPUM : x'3F00', R/W) 2-4-2 CPU Mode Control Register Transition from one mode to another mode is controlled by the CPU mode control register (CPUM).
Chapter 2 CPU Basics II - 22 Standby Functions 2-4-3 Transition between SLOW and NORMAL This LSI has two CPU operating modes, NORMAL and SLOW. Transition from SLOW to NORMAL requires passing through IDLE mode. A sample program for transition from NORMAL to SLOW mode is given below.
II - 23 Chapter 2 CPU Basics Standby Functions 2-4-4 Transition to STANDBY Modes The program initiates transitions from a CPU operating mode to the corresponding STANDBY (HALT/ STOP) modes by specifying the new mode in the CPU mode control register (CPUM).
Chapter 2 CPU Basics II - 24 Standby Functions Transition to HALT modes The system transfers from NORMAL mode to HALT0 mode, and from SLOW mode to HALT1 mode. The CPU stops operating, but the oscillators remain operational. There are two ways to leave a HALT mode: a reset or an interrupt.
II - 25 Chapter 2 CPU Basics Clock Switching Figure 2-5-2 CPU Mode Control Register (CPUM : x'03F00', R/W) 2-5 Clock Switching This LSI can select the best operation clock for system by switching clock cycle division factor by program.
Chapter 2 CPU Basics II - 26 Clock Switching Figure 2-5-3 Clock Switching Circuit Figure 2-5-4 Setting Division Factor at NORMAL mode by combination of OSCSEL and OSCDBL Figure 2-5-5 Setting Division Factor at SLOW mode by combination of OSCSEL and SOSC2DS On clock switching, set each flag of OSCDBL, OSCSEL, SOSCSEL and OSC0, individually.
II - 27 Chapter 2 CPU Basics Bank Function Table 2-6-1 Address Range 2-6 Bank Function 2-6-1 Overview CPU of MN101C00 series has basically 64 KB memory address space. On this LSI, address space can be expanded up to 4 banks (256 KB) based on units of 64 KB, by bank function.
Chapter 2 CPU Basics II - 28 Bank Function Bank Register for Source Address The SBNKR register is used to specify bank area for loading instruction from memory to register. Once this register is specified, bank control is valid for all addressing modes except I/O short instruction and stack relative indirect instruction.
II - 29 Chapter 2 CPU Basics Bank Function 2-6-3 Bank Memory Space When bank function is used, the memory space, where CPU can access as data, shows as the following hatched part.
Chapter 2 CPU Basics II - 30 ROM Correction 2-7 ROM Correction 2-7-1 Overview This LSI can correct and change max. 3 parts in a program on mask ROM with ROM correction function. The correct program is read from the external to the RAM space by using the external EEPROM or by using the serial transmission.
II - 31 Chapter 2 CPU Basics ROM Correction The ROM correction setup procedure is as follows. (1) Set the head address of the program to be corrected to the ROM correction address setting register (RCnAPH/M/L). (2) Set the correct program at RAM area.
Chapter 2 CPU Basics II - 32 ROM Correction 2-7-3 ROM Correction Control Register ROM correction control register (RCCTR) and ROM correction address setting register (RCnAPL, RCnAPM, RCnAPH) control the ROM correction.
II - 33 Chapter 2 CPU Basics ROM Correction This register set the head address, which instructions to be corrected are stored to. Once the instruction execution address reaches to the set value to this register, program counter branches indirectly to the set address to the RC vector table (RCnV(L), RCnV(H)).
Chapter 2 CPU Basics II - 34 ROM Correction Here is the correspondence of the ROM correction address setting register, a ROM correction control flag of ROM correction control register and the RC rector table.
II - 35 Chapter 2 CPU Basics ROM Correction 2-7-4 ROM Correction Setup Example Initial Routine with ROM Correction The following routine should be set to correct the program. Also store the ROM correction setup and the correct program to the external EEPROM, in advance.
Chapter 2 CPU Basics II - 36 ROM Correction The first correct program instruction code 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 03 19 09 01 B4 06 FD 08 01 BC 06 0A 00 85 93 C2 91 F0 FF 0A 14 85 93 02 90 00 Program management version.
II - 37 Chapter 2 CPU Basics ROM Correction 108FC 108FD 108FF 10900 10901_ 85 A011 58 EC1 A081 Address Data The second program to be corrected (internal ROM) sub d1, d1 mov 11, d0 mov d0, (a0) addw 1,.
Chapter 2 CPU Basics II - 38 Reset 2-8 Reset 2-8-1 Reset operation The CPU contents are reset and registers are initialized when the NRST pin is pulled to low. Initiating a Reset There are two methods to initiate a reset. (1) Drive the NRST pin low.
II - 39 Chapter 2 CPU Basics Reset Sequence at Reset (1) When reset pin comes to high level from low level, the innternal 14-bit counter (It can be used as watchdog timer, too.) starts its operation by system clock. The period from starting its count from its overflow is called oscillation stabilization wait time.
Chapter 2 CPU Basics II - 40 Reset 7 0 1/2 15 to 1/2 20 R R internal reset release WDIRQ S 1/2 to 1/2 14 R MUX fs/2 14 fs/2 6 fs/2 12 fs/2 4 fs/2 10 fs/2 8 fs/2 2 HALT fs (sysclk) MUX fs/2 20 fs/2 22 .
II - 41 Chapter 2 CPU Basics Reset Control the Oscillation Stabilization Wait Time At recovering from STOP mode, the bit 3-2 (DLYS1, DLYS0) of the oscillation stabilization wait time control register can be set to select the oscillation stabilization wait time from 2 14 , 2 10 , 2 6 , 2 2 x system clock.
Chapter 2 CPU Basics II - 42 Register Protection 2-9 Register Protection 2-9-1 Overview This LSI features a function to protect important register data. When this function is enabled, data is rewritten only when write is done for several times to a register and other write is disabled.
Chapter 3 Interrupts 3.
Chapter 3 Interrupts III - 2 Overview 3-1 Overview This LSI speeds up interrupt response with circuitry that automatically loads the branch address to the corresponding interrupt service routine from an interrupt vector table : reset, non-maskable interrupts (NMI), 16 maskable peripheral interrupts, and 5 external interrupts.
III - 3 Chapter 3 Interrupts Overview Table 3-1-1 Interrupt Functions 3-1-1 Functions 3 I nt errupt t y pe Res et (int err upt ) Non-m as kable inter r upt M as kable in t er r upt V ect or num ber 0 .
Chapter 3 Interrupts III - 4 Overview 3-1-2 Block Diagram Figure 3-1-1 Interrupt Block Diagram 7 6 5 4 3 2 1 0 Interrupt IRQNM1 Level deter- mined IM1 IRQLVL 2-0 IM0 NMICR Vector 1 Vector 2 Vector N V.
III - 5 Chapter 3 Interrupts Overview 3-1-3 Operation ■ Interrupt Processing Sequence For interrupts other than reset, the interrupt processing sequence consists of interrupt request, interrupt acceptance, and hardware processing.
Chapter 3 Interrupts III - 6 Overview ■ Interrupt Sources and Vector Addresses Here is the list of interrupt vector address and interrupt group. Table 3-1-2 Interrupt Vector Address and Interrupt Group For unused interrupts and reserved interrupts, set the address on which the RTI instruction is described to the corresponded address.
III - 7 Chapter 3 Interrupts Overview ■ Interrupt Level and Priority This LSI allocated vector numbers and interrupt control registers (except reset interrupt) to each inter- rupt. The interrupt level (except reset interrupt, non-maskable interrupt) can be set by software, per each interrupt group.
Chapter 3 Interrupts III - 8 Overview ■ Determination of Interrupt Acceptance The following is the procedure from interrupt request input to acceptance. (1) The interrupt request flag (xxxIR) in the corresponding external interrupt control register(IRQnICR) or internal interrupt control register (xxxICR) is set to '1'.
III - 9 Chapter 3 Interrupts Overview MIE='0' and interrupts are disabled when: - MIE in the PSW is reset to '0' by a program - Reset is detected MIE='1' and interrupts a.
Chapter 3 Interrupts III - 10 Overview ■ Interrupt Acceptance Operation When accepting an interrupt, this LSI hardware saves the handy address register, the return address from the program counter, and the processor status word (PSW) to the stack and branches to the interrupt handler using the starting address in the vector table.
III - 11 Chapter 3 Interrupts Overview Figure 3-1-6 Processing Sequence for Maskable Interrupts ■ Maskable Interrupt Figure 3-1-6 shows the processing flow when a second interrupt with a lower priority level (xxxLV1- xxxLV0='10') arrives during the processing of one with a higher priority level (xxxLV1-xxxLV0='00').
Chapter 3 Interrupts III - 12 Overview ■ Multiplex Interrupt When an MN101C77 series device accepts an interrupt, it automatically disables acceptance of subse- quent interrupts with the same or lower priority level.
III - 13 Chapter 3 Interrupts Overview Figure 3-1-7 Processing Sequence with Multiple Interrupts Enabled Interrupt 1 generated (xxxLV1,0='10') Main program IM1,0='11' Interrupt ser.
Chapter 3 Interrupts III - 14 Overview 3-1-4 Interrupt Flag Setup (1) Disable all maskable interrupts. PSW bp6 : MIE = 0 (2) Select the interrupt factor. (3) Enable the interrupt request flag to be rewritten. MEMCTR (x'3F01') bp2 : IRWE = 1 (4) Rewrite the interrupt request flag.
III - 15 Chapter 3 Interrupts Control Registers 3-2 Control Registers 3-2-1 Registers List Table 3-2-1 Interrupt Control Registers If the interrupt level flag (xxxLVn) is set to "level 3", its vector is disabled, regardless of interrupt enable flag and interrupt request flag.
Chapter 3 Interrupts III - 16 Control Registers 3-2-2 Interrupt Control Registers The interrupt control registers include the maskable interrupt control registers (xxxICR) and the non- maskable interrupt control register (NMICR).
III - 17 Chapter 3 Interrupts Control Registers Figure 3-2-2 External Interrupt 0 Control Register (IRQ0ICR : x'03FE2', R/W) IRQ0 LV1 Interrupt level flag for external interrupt IRQ0 LV0 0 1.
Chapter 3 Interrupts III - 18 Control Registers ■ External Interrupt 1 Control Register (IRQ1ICR) The external interrupt 1 control register (IRQ1ICR) controls interrupt level of external interrupt 1, active edge, interrupt enable and interrupt request.
III - 19 Chapter 3 Interrupts Control Registers ■ External Interrupt 2 Control Register (IRQ2ICR) The external interrupt 2 control register (IRQ2ICR) controls interrupt level of external interrupt 2, active edge, interrupt enable and interrupt request.
Chapter 3 Interrupts III - 20 Control Registers ■ External Interrupt 3 Control Register (IRQ3ICR) The external interrupt 3 control register (IRQ3ICR) controls interrupt level of external interrupt 3, active edge, interrupt enable flag and interrupt request.
III - 21 Chapter 3 Interrupts Control Registers ■ External Interrupt 4 Control Register (IRQ4ICR) The external interrupt 4 control register (IRQ4ICR) controls interrupt level of external interrupt 4, active edge, interrupt enable flag and interrupt request.
Chapter 3 Interrupts III - 22 Control Registers ■ Timer 0 Interrupt Control Register (TM0ICR) The timer 0 interrupt control register (TM0ICR) controls interrupt level of timer 0 interrupt, interrupt enable flag and interrupt request.
III - 23 Chapter 3 Interrupts Control Registers ■ Timer 1 Interrupt Control Register (TM1ICR) The timer 1 interrupt control register (TM1ICR) controls interrupt level of timer 1 interrupt, interrupt enable flag and interrupt request.
Chapter 3 Interrupts III - 24 Control Registers ■ Timer 4 Interrupt Control Register (TM4ICR) The timer 4 interrupt control register (TM4ICR) controls interrupt level of timer 4 interrupt, interrupt enable flag and interrupt request.
III - 25 Chapter 3 Interrupts Control Registers ■ Timer 5 Interrupt Control Register (TM5ICR) The timer 5 interrupt control register (TM5ICR) controls interrupt level of timer 5 interrupt, interrupt enable flag and interrupt request.
Chapter 3 Interrupts III - 26 Control Registers ■ Timer 6 Interrupt Control Register (TM6ICR) The timer 6 interrupt control register (TM6ICR) controls interrupt level of timer 6 interrupt, interrupt enable flag and interrupt request.
III - 27 Chapter 3 Interrupts Control Registers ■ Time Base Interrupt Control Register (TBICR) The time base interrupt control register (TBICR) controls interrupt level of time base interrupt, interrupt enable flag and interrupt request.
Chapter 3 Interrupts III - 28 Control Registers Timer 7 Interrupt Control Register (TM7ICR) The timer 7 interrupt control register (TM7ICR) controls interrupt level of timer 7 interrupt, interrupt enable flag and interrupt request.
III - 29 Chapter 3 Interrupts Control Registers ■ Timer 7 Compare Register 2-match Interrupt Control Register (TOC2ICR) The timer 7 compare register 2-match interrupt control register (TOC2ICR) controls interrupt level of timer 7 compare register 2-match interrupt , interrupt enable flag and interrupt request.
Chapter 3 Interrupts III - 30 Control Registers ■ Serial Interface 0 Reception Interrupt Control Register (SC0RICR) The serial Interface 0 reception interrupt control register (SC0RICR) controls interrupt level of serial Interface 0 reception interrupt, interrupt enable flag and interrupt request.
III - 31 Chapter 3 Interrupts Control Registers ■ Serial Interface 0 Transmission Interrupt Control Register (SC0TICR) The serial Interface 0 transmission interrupt control register (SC0TICR) controls interrupt level of serial Iinterface 0 transmission interrupt, interrupt enable flag and interrupt request.
Chapter 3 Interrupts III - 32 Control Registers ■ Serial Interface 1 Reception Interrupt Control Register (SC1ICR) The serial Interface 1 reception interrupt control register (SC1ICR) controls interrupt level of serial Interface 1 reception interrupt, interrupt enable flag and interrupt request.
III - 33 Chapter 3 Interrupts Control Registers ■ Serial Interface 1 Transmission Interrupt Control Register (SC1TICR) The serial Interface 1 transmission interrupt control register (SC1TICR) controls interrupt level of serial Iinterface 1 transmission interrupt, interrupt enable flag and interrupt request.
Chapter 3 Interrupts III - 34 Control Registers ■ Serial Interface 3 Interrupt Control Register (SC3ICR) The serial interface 3 interrupt control register (SC3ICR) controls interrupt level of serial interface 3 interrupt, interrupt enable flag and interrupt request.
III - 35 Chapter 3 Interrupts Control Registers ■ Serial Interface 4 Interrupt Control Register (SC4ICR) The serial interface 4 interrupt control register (SC4ICR) controls interrupt level of serial interface 4 interrupt, interrupt enable flag and interrupt request.
Chapter 3 Interrupts III - 36 Control Registers ■ A/D Converter Interrupt Control Register (ADICR) The A/D converter interrupt control register (ADICR) controls interrupt level of A/D converter interrupt, interrupt enable flag and interrupt request.
III - 37 Chapter 3 Interrupts Control Registers ■ ATC 1 Interrupt Control Register (ATC1ICR) The ATC 1 interrupt control register (ATC1ICR) controls interrupt level of ATC 1 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable inter- rupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts III - 38 External Interrupts 3-3 External Interrupts There are 5 external interrupts in this LSI. The circuit (external interrupt interface) for the external interrupt input signal, is built-in between the external interrupt input pin and the interrupt controller block.
III - 39 Chapter 3 Interrupts External Interrupts 3-3-2 Block Diagram Figure 3-3-1 External Interrupt 0 Interface and External Interrupt 1 Interface Block Diagram ■ External Interrupt 0 Interface, E.
Chapter 3 Interrupts III - 40 External Interrupts Figure 3-3-2 External Interrupt 2 Interface and External Interrupt 3 Interface, Block Diagram ■ External Interrupt 2 Interface, External Interrupt 3.
III - 41 Chapter 3 Interrupts External Interrupts Figure 3-3-3 External Interrupt 4 Interface Block Diagram ■ External Interrupt 4 Interface Block Diagram IRQ4 Interrupt request 0 7 IRQ4IR IRQ4IE - .
Chapter 3 Interrupts III - 42 External Interrupts 3-3-3 Control Registers The external interrupt input signal, which operated in each external interrupt 0 to 4 interface generate interrupt requests.
III - 43 Chapter 3 Interrupts External Interrupts ■ Noise Filter Control Register 0 (NFCTR0) The noise filter control register (NFCTR0) sets the noise remove function for IRQ0 and IRQ1 and also selects the sampling cycle of noise remove function. And this register also set the AC zero cross detec- tion function for IRQ1.
Chapter 3 Interrupts III - 44 External Interrupts ■ Noise Filter Control Register 1 (NFCTR1) The noise filter control register (NFCTR1) sets the noise remove function for IRQ2 to IRQ4.
III - 45 Chapter 3 Interrupts External Interrupts Figure 3-3-6 Both Edges Interrupt Control Register (EDGDT : x'03F8F', R/W) ■ Both Edges Interrupt Control Register (EDGDT) The both edges interrupt control register (EDGDT) selects interrupt edges of IRQ0 to IRQ4.
Chapter 3 Interrupts III - 46 External Interrupts Figure 3-3-7 Port 6 Key Interrupt Control Register (P6IMD : x'03F3E', R/W) ■ Port 6 Key Interrupt Control Register (P6IMD) The port 6 key interrupt control register (P6IMD) selects if key interrupt is approved, and if external interrupt IRQ4 is approved.
III - 47 Chapter 3 Interrupts External Interrupts 3-3-4 Programmable Active Edge Interrupt ■ Programmable Active Edge Interrupts (External interrupts 0 to 4) Through register settings, external interrupts 0 to 5 can generate interrupt at the selected edge either rising or falling edge.
Chapter 3 Interrupts III - 48 External Interrupts 3-3-5 Both Edges Interrupt ■ Both Edges Interrupt (External interrupts 0 to 4) Both edges interrupt can generate interrupt at both the falling edge and the rising edge by the input signal from external input pins.
III - 49 Chapter 3 Interrupts External Interrupts 3-3-6 Key Input Interrupt ■ Key Input Interrupt (External interrupt 4) This LSI can set port 6 pin (P60 to P67) by 2 bits to key input pin. Key input interrupt can generate an interrupt at the falling edge, if at least 1 key input pin outputs low level.
Chapter 3 Interrupts III - 50 External Interrupts If there is at least one input signal, from the P60 to P63 pins, shows low level, the external interrupt 4 is generated at the falling edge.
III - 51 Chapter 3 Interrupts External Interrupts 3-3-7 Noise Filter ■ Noise Filter (External interrupts 0 to1) Noise filter reduce noise by sampling the input waveform from the external interrupt pins (IRQ0, IRQ1). Its sampling cycle can be selected from 4 types (fosc, fosc/2 8 , fosc/2 9 , fosc/2 10 ).
Chapter 3 Interrupts III - 52 External Interrupts Figure 3-3-8 Noise Remove Function Operation ■ Noise Remove Function Operation (External interrupts 0 to 4) After sampling the input signal to the e.
III - 53 Chapter 3 Interrupts External Interrupts ■ Noise Filter Setup Example (External interrupt 0 and 1) Noise remove function is added to the input signal from P20 pin to generate the external interrupt 0 (IRQ0) at the rising edge. The sampling clock is set to fosc, and the operation state is fosc = 20 MHz.
Chapter 3 Interrupts III - 54 External Interrupts 3-3-8 AC Zero-Cross Detector This LSI has AC zero-cross detector circuit. The P21 / ACZ pin is the input pin of AC zero-cross detector circuit. AC zero-cross detector circuit output the high level when the input level is at the middle, and outputs the low level at other level.
III - 55 Chapter 3 Interrupts External Interrupts ■ AC Zero-Cross Detector Setup Example (External interrupt 1) AC zero-cross detector generates the external interrupt 1 (IRQ1) by using P21/ACZ pin. An example setup procedure, with a description of each step is shown below.
.
Chapter 4 I/O Ports 4.
Chapter 4 I/O Ports IV - 2 Overview 4-1 Overview 4-1-1 I/O Port Diagram A total of 54 pins on this LSI, including those shared with special function pins, are allocated for the 8 I/O ports of ports 0 to 2, ports 5 to 8 and port A. Each I/O port is assigned to its corresponding special function register area in memory.
IV - 3 Chapter 4 I/O Ports Overview 4-1-2 I/O Port Status at Reset Table 4-1-1 I/O Port Status at Reset (Single chip mode) 4 P or t Nam e I / O m ode P ull- up / P ull- dow n r es is t or I / O port ,.
Chapter 4 I/O Ports IV - 4 Overview 4-1-3 Control Registers Ports 0 to 2, ports 5 to 8 and port A are controlled by the data output register (PnOUT), the data input register (PnIN), the I/O direction .
IV - 5 Chapter 4 I/O Ports Overview Table 4-1-3 I/O Port Control Registers List (2/2) Regis t er A d dres s R/ W F u nct ion Page P 7 O U T x'0 3 F1 7 ' R /W P o r t 7 o u tp u t r e g i s t.
Chapter 4 I/O Ports IV - 6 Port 0 4-2 Port 0 General Port Setup Each bit of the port 0 control I/O direction register (P0DIR) can be set individually to set each pin as input or output. The control flag of the port 0 direction control register (P0DIR) should be set to "1" for output mode, and "0" for input mode.
IV - 7 Chapter 4 I/O Ports Port 0 4-2-2 Registers Figure 4-2-1 Port 0 Registers 0 1 2 4 5 6 73 P0OUT P0OUT6 - P0OUT5 P0OUT4 P0OUT3 P0OUT2 P0OUT1 P0OUT0 0 1 L(V SS level) Output data H(V DD level) P0OU.
Chapter 4 I/O Ports IV - 8 Port 0 R D L Q Reset Write Read Read R D L Q Reset Write Read D L Q Write Read R Reset Pull-up resistor control I/O direction control Port output data Serial interface 1 rec.
IV - 9 Chapter 4 I/O Ports Port 0 R D L Q Reset Write Read R D L Q Reset Write Read D L Q Write Read Read R Reset Pull-up resistor control I/O direction control Port output data SC0MD1 register SC0SBO.
Chapter 4 I/O Ports IV - 10 Port 0 Figure 4-2-6 Block Diagram (P04) Figure 4-2-7 Block Diagram (P05) R D L Q Reset Write Read R D L Q Reset Write Read D L Q Write Read Read R Reset Pull-up resistor co.
IV - 11 Chapter 4 I/O Ports Port 0 Figure 4-2-8 Block Diagram (P06) R D L Q Reset Write Read R D L Q Reset Write Read D L Q Write Read Read R Reset Pull-up resistor control I/O direction control Port .
Chapter 4 I/O Ports IV - 12 Port 1 4-3 Port 1 4-3-1 Description General Port Setup Each bit of the port 1 control I/O direction register (P1DIR) can be set individually to set pins as input or output.
IV - 13 Chapter 4 I/O Ports Port 1 4-3-2 Registers Figure 4-3-1 Port 1 Registers (1/3) 0 1 2 4 5 6 73 P1OUT P1OUT3 P1OUT2 P1OUT1 P1OUT0 - - - P1OUT4 0 1 Low (V SS level) Output data High (V DD level) P1OUT 0 1 2 4 5 6 73 P1IN P1IN3 P1IN2 P1IN1 P1IN0 - - - P1IN4 0 1 Pin is low(V SS level).
Chapter 4 I/O Ports IV - 14 Port 1 Figure 4-3-2 Port 1 Registers (2/3) 0 1 2 4 5 6 73 P1OMD ( At reset : - 0 0 0 0 0 0 0 ) P1OMD3 P1OMD4 P1OMD2 P1OMD1 P1OMD0 0 1 I/O port P10 output mode selection Tim.
IV - 15 Chapter 4 I/O Ports Port 1 0 1 2 4 5 6 73 P1TCNT P1CNT3 P1CNT2 P1CNT5 P1CNT4 P1CNT1 P1CNT0 P10 Output Control register ( P1TCNT : X'03F7E', R/W) P1CNT1 0 0 1 I/O port High output Low.
Chapter 4 I/O Ports IV - 16 Port 1 4-3-3 Block Diagram Figure 4-3-4 Block Diagram (P10, P12, P14) Figure 4-3-5 Block Diagram (P11, P13) R D CK Q Reset Write Read R D CK Q Reset Write Read D CK Q Write.
IV - 17 Chapter 4 I/O Ports Port 2 4-4 Port 2 4-4-1 Description General Port Setup Each bit of the port 2 control I/O direction register (P2DIR) can be set individually to set pins as input or output.
Chapter 4 I/O Ports IV - 18 Port 2 4-4-2 Registers Figure 4-4-1 Port 2 Registers 0 1 2 4 5 6 72 P2OUT P2OUT7 0 1 Low (V SS level) Output data High (V DD level) P2OUT 0 1 2 4 5 6 72 P2IN P2IN7 P2IN4 P2IN2 P2IN2 P2IN1 P2IN0 0 1 Pin is Low (V SS level). Input data Pin is High (V DD level).
IV - 19 Chapter 4 I/O Ports Port 2 Figure 4-4-2 Block Diagram (P20, P22 to P24) 4-4-3 Block Diagram Figure 4-4-3 Block Diagram (P21) R D L Q Reset Write Read Read Pull-up resistor control Port input d.
Chapter 4 I/O Ports IV - 20 Port 2 Figure 4-4-4 Block Diagram (P27) R S D L Q Reset Reset Write Port output data Port input data Data bus Read Read Reset P27 P2OUT7 P2IN7 Schmitt trigger input Noise f.
IV - 21 Chapter 4 I/O Ports Port 5 4-5 Port 5 4-5-1 Description General Port Setup Each bit of the port 5 control I/O direction register (P5DIR) can be set individually to set pins as input or output. The control flag of the port 5 direction control register (P5DIR) is set to "1" for output mode, and "0" for input mode.
Chapter 4 I/O Ports IV - 22 Port 5 4-5-2 Registers Figure 4-5-1 Port 5 Registers 0 1 2 4 5 6 73 P5OUT P5OUT4 P5OUT3 P5OUT2 P5OUT1 P5OUT0 0 1 Low (V SS level) Output data High (V DD level) P5OUT 0 1 2 4 5 6 73 P5IN P5IN4 P5IN3 P5IN2 P5IN1 P5IN0 0 1 Pin is Low (V SS level).
IV - 23 Chapter 4 I/O Ports Port 5 Figure 4-5-2 Block Diagram (P50) Figure 4-5-3 Block Diagram (P51) R D L Q Reset Write Read R D L Q Reset Write Read D L Q Write Read Read R Reset Pull-up resistor co.
Chapter 4 I/O Ports IV - 24 Port 5 Figure 4-5-4 Block Diagram (P52) Figure 4-5-5 Block Diagram (P53) R D L Q Reset Write Read R D L Q Reset Write Read D L Q Write Read Read R Reset Pull-up resistor co.
IV - 25 Chapter 4 I/O Ports Port 5 R D L Q Reset Write Read R D L Q Reset Write Read D L Q Write Read Read R Reset Pull-up resistor control I/O direction control Port output data SC4AD1 register SELI2.
Chapter 4 I/O Ports IV - 26 Port 6 4-6 Port 6 4-6-1 Description General port Setup Each bit of the port 6 control I/O direction register (P6DIR) can be set individually to set pins as input or output. The control flag of the port 6 direction control register (P6DIR) is set to "1" for output mode, and "0" for input mode.
IV - 27 Chapter 4 I/O Ports Port 6 4-6-2 Registers Figure 4-6-1 Port 6 Registers (1/2) 0 1 2 4 5 6 73 P6OUT P6OUT6 P6OUT7 P6OUT5 P6OUT4 P6OUT3 P6OUT2 P6OUT1 P6OUT0 0 1 Low (V SS level) Output data High (V DD level) P6OUT 0 1 2 4 5 6 73 P6IN P6IN6 P6IN7 P6IN5 P6IN4 P6IN3 P6IN2 P6IN1 P6IN0 0 1 Pin is Low (V SS level).
Chapter 4 I/O Ports IV - 28 Port 6 Figure 4-6-2 Port 6 Registers (2/2) 0 1 2 4 5 6 73 FLOAT PARDWN P7RDWN SYOEVS1SYOEVS0 Pull-up/pull-down resistor selection, pin control register (FLOAT: X'03F2E.
IV - 29 Chapter 4 I/O Ports Port 6 4-6-3 Block Diagram Figure 4-6-3 Block Diagram (P60 to P67) R D L Q Reset Write Read R D L Q Reset Write Read Pull-up resistor control I/O direction control Port out.
Chapter 4 I/O Ports IV - 30 Port 7 4-7 Port 7 4-7-1 Description General Port Setup Each bit of the port 7 control I/O direction register (P7DIR) can be set individually to set pins as input or output. The control flag of the port 5 direction control register (P7DIR) is set to "1" for output mode, and "0" for input mode.
IV - 31 Chapter 4 I/O Ports Port 7 0 1 2 4 5 6 73 P7OUT P7OUT6 P7OUT7 P7OUT5 P7OUT4 P7OUT3 P7OUT2 P7OUT1 P7OUT0 0 1 Low (V SS level) Output data High (V DD level) P7OUT 0 1 2 4 5 6 73 P7IN P7IN6 P7IN7 P7IN5 P7IN4 P7IN3 P7IN2 P7IN1 P7IN0 0 1 Pin is Low (V SS level).
Chapter 4 I/O Ports IV - 32 Port 7 Figure 4-7-2 Port 7 Registers (2/2) 0 1 2 4 5 6 73 FLOAT PARDWN P7RDWN SYOEVS1 SYOEVS0 Pull-up / Pull-down resistor selection, Pin control register (FLOAT : x'0.
IV - 33 Chapter 4 I/O Ports Port 7 Figure 4-7-3 Block Diagram (P70) 4-7-3 Block Diagram Figure 4-7-4 Block Diagram (P71) Read R D L Q Reset Write Read R D L Q Reset Write Read R D L Q Reset Write Read.
Chapter 4 I/O Ports IV - 34 Port 7 Figure 4-7-5 Block Diagram (P72 ) Read R D L Q Reset Write Read R D L Q Reset Write Read R D L Q Reset Write Read Read R Reset D L Q Write Pull-up/down resistor cont.
IV - 35 Chapter 4 I/O Ports Port 7 Figure 4-7-7 Block Diagram (P74 ) Read R D L Q Reset Write Read R D L Q Reset Write Read R D L Q Reset Write Read Read R Reset D L Q Write Pull-up/down resistor cont.
Chapter 4 I/O Ports IV - 36 Port 7 Figure 4-7-9 Block Diagram (P76, P77 ) Read R D L Q Reset Write Read R D L Q Reset Write Read R D L Q Reset Write Read Read R Reset D L Q Write Pull-up/down resistor.
IV - 37 Chapter 4 I/O Ports Port 8 4-8 Port 8 4-8-1 Description General Port Setup Each bit of the port 8 control I/O direction register (P8DIR) can be set individually to set each pin as input or output. The control flag of the port 8 direction control register (P8DIR) is set to "1" for output mode, and "0" for input mode.
Chapter 4 I/O Ports IV - 38 Port 8 4-8-2 Registers Figure 4-8-1 Port 8 Registers (1/2) 0 1 2 4 5 6 73 P8OUT P8OUT6 P8OUT7 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUT0 0 1 Low (V SS level) Output data High (V DD level) P8OUT 0 1 2 4 5 6 73 P8IN P8IN6 P8IN7 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P8IN0 0 1 Pin is Low (V SS level).
IV - 39 Chapter 4 I/O Ports Port 8 0 1 2 4 5 6 73 P8LED P8LED6 P8LED7 P8LED5 P8LED4 P8LED3 P8LED2 P8LED1 P8LED0 0 1 Normal output Transistor selection LED output P8LED Port 8 LED Control register (P8L.
Chapter 4 I/O Ports IV - 40 Port 8 4- 8 -3 Block Diagram Figure 4-8-3 Block Diagram (P80 to P87) R D L Q Reset Write Read R D L Q Reset Write Read D L Q Write R Reset R Reset Pull-up resistor control .
IV - 41 Chapter 4 I/O Ports Port A 4- 9 Port A 4- 9 -1 Description General Port Setup Each bit of the port A control I/O direction register (PADIR) can be set individually to set each pin as input or output.
Chapter 4 I/O Ports IV - 42 Port A 4-9-2 Registers Figure 4-9-1 Port A Registers (1/2) 0 1 2 4 5 6 73 PAIN PAIN5 PAIN4 PAIN3 PAIN2 PAIN1 PAIN0 0 1 Pin is low (Vss level) Input data Pin is high (Vdd le.
IV - 43 Chapter 4 I/O Ports Port A Figure 4-9-2 Port A Registers (2/2) 0 1 2 4 5 6 73 FLOAT PARDWN P7RDWN SYOEVS1 SYOEVS0 Pull-up/pull-down resistor selection, Pin control register (FLOAT: X'03F2.
Chapter 4 I/O Ports IV - 44 Port A 4-9-3 Block Diagram Figure 4-9-3 Block Diagram (PA0 to PA1) Figure 4-9-4 Block Diagram (PA2 to PA6) Read R D L Q Reset Write Read R D L Q Reset Write Read R D L Q Re.
IV - 45 Chapter 4 I/O Ports Real Time Output Control (Port 1) 4-10 Real Time Output Control (Port 1) P10 , P12 and P14 has a real time output function that can switch pin's output at the falling edge of the external interrupt 0 pin (P20/IRQ0).
Chapter 4 I/O Ports IV - 46 Real Time Output Control (Port 1) 4-10-2 Operation Real Time Output Pin Setup The real time output pin is set by the port 1 output control register(P1TCNT). The selectable pins are P10, P12 and P14. Those can be specified by each pin.
IV - 47 Chapter 4 I/O Ports Real Time Output Control (Port 1) External interrupt 0 (IRQ0) P1n output (n=0,2,4) PITCNT set value="0" Timer output Writing to P1OUT register Figure 4-10-1 Real .
Chapter 4 I/O Ports IV - 48 Synchronous Output (Port 7) 4-11 Synchronous output (Port 6) Port 6 has the synchronous output function that outputs the any set data to pins, in synchronization with the generation of the specified event.
IV - 49 Chapter 4 I/O Ports Synchronous Output (Port 7) Table 4-11-1 Synchronous Output Control Registers 4-11-2 Registers Table 4-11-1 shows the synchronous output control registers of port 6.
Chapter 4 I/O Ports IV - 50 Synchronous Output (Port 7) 4-11-3 Operation Synchronous Output Setup The synchronous output control register (P6SYO) selects the synchronous output pin of the port 6, in each bit. The synchronous output event is selected by the pin control register (FLOAT).
IV - 51 Chapter 4 I/O Ports Synchronous Output (Port 7) Figure 4-11-2 Synchronous Output Timing by Event Generation (IRQ2) Port 6 Synchronous Output (External interrupt 2 IRQ2)) The synchronous output timing when the synchronous output event is set at the falling edge of the external interrupt 2, is shown below.
Chapter 4 I/O Ports IV - 52 Synchronous Output (Port 7) A setup example of the port 6 synchronous output by the external interrupt 2 (IRQ2) is shown as follows. As it is operated, the initial output data of port 6 is "55", the synchronous output data is "AA", and the rising edge of the IRQ2 is selected at the synchronous event.
Chapter 5 Prescaler 5.
Chapter 5 Prescaler V - 2 Overview 5-1 Overview This LSI has 2 prescalers that can be used by its peripheral functions at the same time. Each of them count with fosc or fs as a base clock.
V - 3 Chapter 5 Prescaler Overview Table 5-1-1 Peripheral Functions Used with Prescaler Output 5-1-1 Peripheral Functions Table 5-1-1 shows several kinds of clock source that can be selected by each peripheral functions from prescaler output.
Chapter 5 Prescaler V - 4 Overview 5-1-2 Block Diagram Figure 5-1-1 Prescaler Block Diagram fs/2 bp0 bp7 CK4MD TM4BAS TM4PSC0 TM4PSC1 4 2 4 2 PSC1 PSC0 bp0 bp7 PSCMD PSCEN 7bit Prescaler ck S fosc fs .
V - 5 Chapter 5 Prescaler Control Registers 5-2 Control Register 5-2-1 Registers List Table 5-2-1 shows registers to control prescaler. Table 5-2-1 Prescaler Control Registers R/W : Readable/Writable .
Chapter 5 Prescaler V - 6 Control Registers 5-2-2 Control Registers Registers that select prescaler outputs cycle clock and prescaler operation control, consists of the prescaler control register (PSCMD), the timer prescaler selection register (CKnMD) and the serial trans- fer clock selection register (SCnCKS).
V - 7 Chapter 5 Prescaler Control Registers The timer prescaler selection register selects the count clock that used in 8-bit timer. Timer 0 Prescaler Selection Register (CK0MD) Figure 5-2-2 Timer.
Chapter 5 Prescaler V - 8 Control Registers Figure 5-2-4 Timer 4 Prescaler Selection Register (CK4MD : x'03F66', R/W) Timer 4 Prescaler Selection Register (CK4MD) 0 1 2 4 5 6 73 CK4MD 0 .
V - 9 Chapter 5 Prescaler Control Registers 0 1 2 4 5 6 73 SC1CKS 0 0 0 0 0 1 1 1 1 0 X 1 1 fosc/2 fosc/4 fosc/16 fs/2 fosc/64 fs/4 Timer 4 output Clock source selection SC1PSC1 SC1PSC2 SC1PSC0 SC1PSC.
Chapter 5 Prescaler V - 10 Control Registers Figure 5-2-8 Serial Interface 3 Transfer Clock Selection Register (SC3CKS : x'03FAF', R/W) 0 1 2 4 5 6 73 SC3CKS 0 0 0 0 0 1 1 1 1 0 1 1 fosc/2 f.
V - 11 Chapter 5 Prescaler Operation 5-3 Operation 5-3-1 Operation Prescaler Operation (Prescaler 0 to 1) Prescaler 0 is a 7-bit and prescaler 1 is a 3-bit free-running counter that divides the base clock. This prescaler can be started or stopped by the PSCEN flag of the prescaler control register (PSCMD).
Chapter 5 Prescaler V - 12 Operation Enable the prescaler counting by the PSCEN flag of the prescaler control register (PSCMD). The prescaler counting is started after it is enabled. Start the timer operation after the prescaler is set. Also, the selection of the prescaler output should be set by the timer mode register.
Chapter 6 8-bit Timers 6.
Chapter 6 8-bit Timers VI - 2 Overview 6-1 Overview This LSI contains two general purpose 8-bit timers (Timers 0 and 1) and two 8-bit timers (Timers 4 and 5) that can be also used as baud rate timer. The general purpose 8-bit timers can be used as 16-bit timers with cascade connection.
VI - 3 Chapter 6 8-bit Timers Overview 6-1-2 Block Diagram Timers 0 and 1 Block Diagram Figure 6-1-1 Timers 0 and 1 Block Diagram IRQ2=H : Count Stop 0 7 TM0CK0 TM0CK1 TM0CK2 TM0PWM TM0EN TM0MOD T.
Chapter 6 8-bit Timers VI - 4 Overview Timer 4 and 5 Block Diagram Figure 6-1-2 Timer 4 and 5 Block Diagram IRQ4=H: Count Stop 0 7 TM4CK0 TM4CK1 TM4CK2 TM4PWM TM4EN TM4MOD TM4MD P24/IRQ4 8-bit cou.
VI - 5 Chapter 6 8-bit Timers Overview Remote Control Carrier Output Block Diagram Figure 6-1-3 Remote Control Carrier Output Block Diagram Synchronizing circuit MUX RMCTR P10/ TM0IO output / Remo.
Chapter 6 8-bit Timers VI - 6 Control Registers 6-2 Control Registers Table 6-2-1 8-bit Timer Control Registers 6-2-1 Registers Table 6-2-1 shows registers that control timers 0, 1, 4, 5 and remote co.
VI - 7 Chapter 6 8-bit Timers Control Registers R/W : Readable / Writable R : Readable only R egi ster A ddress R / W Fu n ct ion Page Ti m e r 4 T M4BC x '03F60' R T i mer 4 bi n ary c ou n.
Chapter 6 8-bit Timers VI - 8 Control Registers 6-2-2 Programmable Timer Registers Each of timers 0, 1, 4 and 5 has 8-bit programmable timer registers. Programmable timer register consists of compare register and binary counter. Compare register is 8-bit register which stores the value to be compared to binary counter.
VI - 9 Chapter 6 8-bit Timers Control Registers Binary counter is 8-bit up counter. If any data is written to compare register during counting is stopped, binary counter is cleared to x'00'.
Chapter 6 8-bit Timers VI - 10 Control Registers 6-2-3 Timer Mode Registers Timer mode register is readable/writable register that controls timers 0, 1, 4 and 5.
VI - 11 Chapter 6 8-bit Timers Control Registers Timer 1 Mode Register (TM1MD) Figure 6-2-10 Timer 1 Mode Register (TM1MD : x'03F55', R/W) TM1CK2 - 0 TM1CK1 0 1 1 tm1psc ( Prescaler outp.
Chapter 6 8-bit Timers VI - 12 Control Registers Timer 4 Mode Register (TM4MD) Figure 6-2-11 Timer 4 Mode Register (TM4MD : x'03F64', R/W) TM4CK2 - 0 TM4CK1 0 1 1 tm4psc (Prescaler outpu.
VI - 13 Chapter 6 8-bit Timers Control Registers Timer 5 Mode Register (TM5MD) Figure 6-2-12 Timer 5 Mode Register (TM5MD : x'03F65', R/W) TM5CK2 - 0 TM5CK1 0 1 1 tm5psc (Prescaler outpu.
Chapter 6 8-bit Timers VI - 14 Control Registers Figure 6-2-13 Remote Control Carrier Output Control Register (RMCTR : x'03F6E', R/W) Remote Control Carrier Output Control Register (RMCT.
VI - 15 Chapter 6 8-bit Timers 8-bit Timer Count 6-3 8-bit Timer Count 6-3-1 Operation The timer operation can constantly generate interrupts. 8-bit Timer Operation (Timers 0, 1, 4 and 5) The generation cycle of timer interrupts is set by the clock source selection and the setting value of the compare register (TMnOC), in advance.
Chapter 6 8-bit Timers VI - 16 8-bit Timer Count 02 03 M NM 00 01 02 N-1 N 00 01 Count clock TMnEN flag Compare register Binary counter Interrupt request flag (A) (B) (C) (D) (E) Count Timing of Timer Operation (Timers 0, 1, 4 and 5) Binary counter counts up with selected clock source as a count clock.
VI - 17 Chapter 6 8-bit Timers 8-bit Timer Count 6-3-2 Setup Example Timer Operation Setup Example (Timers 0, 1, 4 and 5) Timer function can be set by using timer 0 that generates the constant interrupt. By selecting fs/4 (at fosc = 20 MHz) as a clock source, interrupt is generated every 250 clock cycles (100 µs).
Chapter 6 8-bit Timers VI - 18 8-bit Timer Count (7) Set the TM0IE flag of the TM0ICR register to "1" to enable the interrupt. (8) Set the TM0EN flag of the TM0MD register to "1" to start the timer 0. Setup Procedure (7) Enable the interrupt.
VI - 19 Chapter 6 8-bit Timers 8-bit Event Count M N 00 01 02 N-1 N 00 01 TMnIO input TMnEN flag Compare register Binary counter Interrupt request flag 6-4 8-bit Event Count 6-4-1 Operation Event count operation has 2 types ; TMnIO input and synchronous TMnIO input can be selected as the count clock.
Chapter 6 8-bit Timers VI - 20 8-bit Event Count Count Timing of Synchronous TMnIO Input (Timers 0, 1, 4 and 5) If the synchronous TMnIO input is selected, the synchronizing circuit output signal is input to the timer n count clock.
VI - 21 Chapter 6 8-bit Timers 8-bit Event Count 6-4-2 Setup Example Event Count Setup Example (Timers 0, 1, 4 and 5) If the falling edge of the TM0IO input pin signal is detected 5 times with using timer 0, an interrupt is generated. An example setup procedure, with a description of each step is shown below.
Chapter 6 8-bit Timers VI - 22 8-bit Event Count Every time TM0BC detects the falling edge of TM0IO input , TM0BC counts up from 'x00'. When TM0BC reaches the setting value of theTM0OC register, the timer 0 interrupt request flag is set at the next count clock, then the value of TM0BC becomes x'00' and counting up is restarted.
VI - 23 Chapter 6 8-bit Timers 8-bit Timer Pulse Output 6-5 8-bit Timer Pulse Output 6-5-1 Operation The TMnIO pin can output a pulse signal with any cycle. Operation of Timer Pulse Output (Timers 0, 1, 4 and 5) The timers can output 2 x cycle signal, compared to the setting value in compare register (TMnOC).
Chapter 6 8-bit Timers VI - 24 8-bit Timer Pulse Output 6-5-2 Setup Example Timer Pulse Output Setup Example (Timers 0, 1, 4 and 5) TM0IO (P10) pin outputs 50 kHz pulse by using timer 0. For this, select fosc as clock source, and set a 1/ 2 cycle (100 kHz) for the timer 0 compare register (at fosc=20 MHz).
VI - 25 Chapter 6 8-bit Timers 8-bit Timer Pulse Output TM0BC counts up from x'00'. If TM0BC reaches the setting value of the TM0OC register, then TM0BC is cleared to x'00', TM0IO output signal is inverted and TM0BC restarts to count up from x'00'.
Chapter 6 8-bit Timers VI - 26 8-bit PWM Output 6-6 8-bit PWM Output The TMnIO pin outputs the PWM waveform, which is determined by the match timing for the compare register and the overflow timing of the binary counter.
VI - 27 Chapter 6 8-bit Timers 8-bit PWM Output Count Timing of PWM Output (when the compare register is x'00') (Timers 0, 4 and 5) Here is the count timing when the compare register is .
Chapter 6 8-bit Timers VI - 28 8-bit PWM Output 6-6-2 Setup Example PWM Output Setup Example (Timers 0, 4 and 5) The 1/4 duty cycle PWM output waveform is output from the TM0IO output pin at 128 Hz by using timer 0 (at fx=32.768 kH z ). Cycle period of PWM output waveform is decided by the overflow of the binary counter.
VI - 29 Chapter 6 8-bit Timers 8-bit PWM Output (5) Set the "H" period of PWM output to the timer 0 compare register (TM0OC). The setting value is set to 256 / 4 = 64 (x'40'), because it should be the 1/4 duty of the full count (256).
Chapter 6 8-bit Timers VI - 30 Synchronous Output 6-7 8-bit Timer Synchronous Output 6-7-1 Operation When the binary counter of the timer reaches the set value of the compare register, the latched data is output from port 6 at the next count clock.
VI - 31 Chapter 6 8-bit Timers Synchronous Output 6-7-2 Setup Example Synchronous Output Setup Example (Timer 1, Timer 5) Setup example that latch data of port 6 is output constantly (100 µs) by using timer 1 from the synchronous output pin is shown below.
Chapter 6 8-bit Timers VI - 32 Synchronous Output TM1BC counts up from x'00'. If any data is written to the port 6 output register (P6OUT), the data of port 6 is output from the synchronous output pin in every time an interrupt request is generated by the match of TM1BC and the set value of the TM1OC register.
VI - 33 Chapter 6 8-bit Timers Serial Transfer Clock Output 6-8 Serial Interface Transfer Clock Output 6-8-1 Operation Serial interface transfer clock can be created by using the timer output signal.
Chapter 6 8-bit Timers VI - 34 Serial Transfer Clock Output 6-8-2 Setup Example Serial Interface Transfer Clock Setup Example (Timer 4) How to create a transfer clock for half duplex UART (Serial interface 1) using with timer 4 is shown below.
VI - 35 Chapter 6 8-bit Timers Serial Transfer Clock Output TM4BC counts up from x'00'. Timer 4 output is the clock of the serial interface 1 at transmission and reception. For the compare register setup value and the serial operation setup, refer to chapter 11.
Chapter 6 8-bit Timers VI - 36 Simple Pulse Width Measurement 6-9 Simple Pulse Width Measurement 6-9-1 Operation Timer measures the "L" duration of the pulse signal input from the external interrupt pin.
VI - 37 Chapter 6 8-bit Timers Simple Pulse Width Measurement 6-9-2 Setup Example Set up Example of Simple Pulse Width Measurement by 8-bit Timer (Timers 0, 4 and 5) The pulse width of 'L" period of the external interrupt 2 (IRQ2) input signal is measured by timer 0.
Chapter 6 8-bit Timers VI - 38 Simple Pulse Width Measurement TM0BC starts to count up with negative edge of the external interrupt 2 (IRQ2) input as a trigger. Timer 0 continues to count up during "L" period of IRQ2 input, then stop the counting with positive edge of IRQ2 input as a trigger.
VI - 39 Chapter 6 8-bit Timers Cascade Connection 6-10 Cascade Connection 6-10-1 Operation Cascading timers 0 and 1 form a 16-bit timer. 8-bit Timer Cascade Connection Operation (Timer 0 + Timer 1) Timer 0 and timer 1 are combined to be a 16-bit timer.
Chapter 6 8-bit Timers VI - 40 Cascade Connection At cascade connection, the binary counter and the compare register are operated as a 16 bit regis- ter. At operation, set the TMnEN flag of the upper and lower 8-bit timers to "1" to be operated.
VI - 41 Chapter 6 8-bit Timers Cascade Connection 6-10-2 Setup Example Cascade Connection Timer Setup Example (Timer 0 + Timer 1) Setting example of timer function that an interrupt is constantly generated by cascade connection of timer 0 and timer 1, as a 16-bit timer is shown.
Chapter 6 8-bit Timers VI - 42 Cascade Connection TM1BC + TM0BC counts up from x'0000' as a 16-bit timer. When TM1BC + TM0BC reaches the set value of TM1OC + TM0OC register, the timer 1 inte.
VI - 43 Chapter 6 8-bit Timers Remote Control Carrier Output 6-11 Remote Control Carrier Output 6-11-1 Operation Carrier pulse for remote control can be generated. Operation of Remote Control Carrier Output (Timer 0, Timer 5) Remote control carrier pulse is based on output signal of timer 0 or timer 5.
Chapter 6 8-bit Timers VI - 44 Remote Control Carrier Output 6-11-2 Setup Example Remote Control Carrier Output Setup Example (Timer 0, Timer 5) Here is the setting example that the RMOUT pin outputs the 1/3 duty carrier pulse signal with "H" period of 36.
VI - 45 Chapter 6 8-bit Timers Remote Control Carrier Output Setup Procedure Description (6) Select the normal timer operation. TM0MD (x'3F54') bp 4 : TM0PWM = 0 bp 5 : TM0MOD = 0 (7) Select the count clock source. TM0MD (x'3F54') bp2-0 : TM0CK2-0 = 000 (8) Set the base cycle of remote control carrier.
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Chapter 7 16-bit Timer 7.
Chapter 7 16-bit Timer VII - 2 Overview 7-1 Overview This LSI contains a general-purpose 16-bit timer (Timer 7). Its compare register is double buffer type.
VII - 3 Chapter 7 16-bit Timer Overview 7-1-2 Block Diagram Timer 7 Block Diagram Figure 7-1-1 Timer 7 Block Diagram T7OC2IRQ OVF M U X M U X 1/2 R TM7CL TM7MD1(bp5) M U X TM7IO output / PWM7 rese.
Chapter 7 16-bit Timer VII - 4 Control Registers 7-2 Control Registers Timer 7 contains the binary counter (TM7BC), the compare register 1 (TM7OC1), and its double buffer preset register (TM7PR1), the compare register 2 (TM7OC2) and its double buffer preset register 2 (TM7PR2), the capture register (TM7IC).
VII - 5 Chapter 7 16-bit Timer Control Registers 7-2-2 Programmable Timer Registers Timer 7 has a 16-bit programmable timer register. It contains a compare register, a preset register, a binary counter and a capture register. Each register has 2 sets of 8-bit register.
Chapter 7 16-bit Timer VII - 6 Control Registers Figure 7-2-5 Timer 7 Preset Register 1 Lower 8 bits (TM7PR1L : x'03F74', R/W) Timer 7 Preset Register 1 (TM7PR1) Figure 7-2-6 Timer 7 Pre.
VII - 7 Chapter 7 16-bit Timer Control Registers Binary counter is a 16-bit up counter. If any data is written to a preset register when the counting is stopped, the binary counter is cleared to x'0000'.
Chapter 7 16-bit Timer VII - 8 Control Registers 7-2-3 Timer Mode Registers This is a readable / writable register that controls timer 7. Timer 7 Mode Register 1 (TM7MD1) Figure 7-2-13 Timer 7 Mod.
VII - 9 Chapter 7 16-bit Timer Control Registers Timer 7 Mode Register 2 (TM7MD2) Figure 7-2-14 Timer 7 Mode Register 2 (TM7MD2 : x'03F79', R/W) T7ICT1 0 T7ICT0 0 1 0 1 1 IRQ1 (External .
Chapter 7 16-bit Timer VII - 10 16-bit Timer Count 7-3 16-bit Timer Count 7-3-1 Operation The timer operation can constantly generate interrupts. 16-bit Timer Operation (Timer 7) The generation cycle of an timer interrupt is set by the clock source selection and the set value of the compare register 1 (TM7OC1), in advance.
VII - 11 Chapter 7 16-bit Timer 16-bit Timer Count Count Timing of Timer Operation (Timer 7) The binary counter counts up with the selected clock source as the count clock.
Chapter 7 16-bit Timer VII - 12 16-bit Timer Count (C) Even if the preset register is rewritten as the TM7EN flag is "1", the binary counter is not changed. (D) If the binary counter reaches the value of the compare register 1, the set value of the preset register is loaded to the compare register at the next count clock.
VII - 13 Chapter 7 16-bit Timer 16-bit Timer Count 7-3-2 Setup Example Timer Operation Setup Example (Timer 7) Timer 7 generates an interrupt constantly for timer function. Fosc/2 (fosc=20 MHz) is selected as a clock source to generate an interrupt every 1000 cycles (100 µs).
Chapter 7 16-bit Timer VII - 14 16-bit Timer Count (7) Set the TM7EN flag of the TM7MD1 register to "1" to start timer 7. Setup Procedure (7) Start the timer operation. TM7MD1 (x'3F78') bp4 : TM7EN = 1 Description TM7BC counts up from x'0000'.
VII - 15 Chapter 7 16-bit Timer 16-bit Event Count N 0000 0001 0002 N-1 N 0000 0001 TM7IO input TM7EN flag Compare register 1 Binary counter Interrupt request flag 7-4 16-bit Event Count 7-4-1 Operation Event count operation has 2 types ; TM7IO input and synchronous TM7IO input can be selected as the count clock.
Chapter 7 16-bit Timer VII - 16 16-bit Event Count Count Timing of Synchronous TM7IO Input (Timer 7) If the synchronous TM7IO input is selected, the synchronizing circuit output signal is input to the count clock. The synchronizing circuit output signal is changed at the falling edge of the system clock after the TM7IO input signal is changed.
VII - 17 Chapter 7 16-bit Timer 16-bit Event Count 7-4-2 Setup Example Event Count Setup Example (Timer 7) If the falling edge of the TM7IO input pin signal is detected 5 times with using timer 7, an interrupt is generated. An example setup procedure, with a description of each step is shown below.
Chapter 7 16-bit Timer VII - 18 16-bit Event Count Every time TM7BC detects the falling edge of the TM7IO input, TM7BC counts up from x'0000'.
VII - 19 Chapter 7 16-bit Timer 16-bit Timer Pulse Output 7-5 16-bit Timer Pulse Output 7-5-1 Operation TM7IO pin can output a pulse signal with an arbitrary frequency.
Chapter 7 16-bit Timer VII - 20 16-bit Timer Pulse Output Count Timing of Timer Pulse Output (Timer 7) N 0000 0001 N-1 N Count clock TM7EN flag Compare register 1 Binary counter Interrupt request flag 0000 0001 0000 N-1 N 0000 0001 N-1 N TM7IO output The TM7IO pin outputs 2 x cycle, compared to the value in the compare register 1.
VII - 21 Chapter 7 16-bit Timer 16-bit Timer Pulse Output 7-5-2 Setup Example Timer Pulse Output Setup Example (Timer 7) TM7IO pin outputs 50 kHz pulse by using timer 7. For this, select fosc as clock source, and set a 1/2 cycle (100 kHz) for the timer 7 compare register (at fosc=20 MHz).
Chapter 7 16-bit Timer VII - 22 16-bit Timer Pulse Output At TM7OC1 = x'0000' and x'0001', the timer pulse output has the same waveform. Either binary counter stops or operates, the timer output is "L", when the TM7CL flag of the TM7MD2 register is set to "1".
VII - 23 Chapter 7 16-bit Timer 16-bit Standard PWM Output 7-6 16-bit Standard PWM Output (Only duty can be changed consecutively) The TM7IO pin outputs the standard PWM output, which is determined by the over flow timing of the binary counter, and the match timing of the timer binary counter and the compare register.
Chapter 7 16-bit Timer VII - 24 16-bit Standard PWM Output Count Timing of Standard PWM Output (when Compare Register 1 is x'0000')(Timer 7) Here is the count timing at setting x'0000' to the compare register 1.
VII - 25 Chapter 7 16-bit Timer 16-bit Standard PWM Output 7-6-2 Setup Example Standard PWM Output Setup Example (Timer 7) The TM7IO output pin outputs the 1/4 duty PWM output waveform at 305.18 Hz with timer 7. The high frequency oscillation (fosc) is set to be operated at 20 MHz.
Chapter 7 16-bit Timer VII - 26 16-bit Standard PWM Output (5) Select fosc at clock source by the TM7CK1-0 flag of the TM7MD1 register. Also, select 1/1 frequency (no division) at count clock source by the TM7PS1-0 flag. (6) Set "H" period of the PWM output to the timer 7 preset register 1 (TM7PR1).
VII - 27 Chapter 7 16-bit Timer 16-bit High Precision PWM Output 7-7 16-bit High Precision PWM Output (Cycle/Duty can be changed consecutively) The TM7IO pin outputs high precision PWM output, which i.
Chapter 7 16-bit Timer VII - 28 16-bit High Precision PWM Output Count Timing of High Precision PWM Output (When compare register 2 is x'0000'l) (Timer 7) Here is the count timing as the.
VII - 29 Chapter 7 16-bit Timer 16-bit High Precision PWM Output 7-7-2 Setup Example High Precision PWM Output Setup Example (Timer 7) The TM7IO output pin outputs the 1/4 duty PWM output waveform at 400 Hz with timer 7. Select fosc/2 (at fosc = 20 MHz) as a clock source.
Chapter 7 16-bit Timer VII - 30 16-bit High Precision PWM Output (5) Select fosc as clock source by the TM7CK1-0 flag of the TM7MD1 register. Also, select 1/2 dividing as count clock source by the TM7PS1- 0 flag. (6) Set the PWM output cycle to the timer 7 preset register 1 (TM7PR1).
VII - 31 Chapter 7 16-bit Timer 16-bit Timer Synchronous Output 7-8 16-bit Timer Synchronous Output 7-8-1 Operation When the binary counter of the timer reaches the set value of the compare register, the latched data is output from port 6 at the next count clock.
Chapter 7 16-bit Timer VII - 32 16-bit Timer Synchronous Output 7-8-2 Setup Example Synchronous Output Setup Example (Timer 7) Setup example that latched data of port 6 is output constantly (100 µs) by using timer 7 from the synchro- nous output pin is shown below.
VII - 33 Chapter 7 16-bit Timer 16-bit Timer Synchronous Output TM7BC counts up from x'0000'. If any data is written to the port 6 output register (P6OUT), TM7BC reaches the set value of TM7OC1 register and the synchronous output pin outputs data of port 7 in every time an interrupt request is generated.
Chapter 7 16-bit Timer VII - 34 16-bit Timer Capture 7-9 16-bit Timer Capture 7-9-1 Operation The value of a binary counter is stored to register at the timing of the external interrupt input signal, or the timing of writing operation with an arbitrary value to the capture register.
VII - 35 Chapter 7 16-bit Timer 16-bit Timer Capture with the automatic data transfer function (ATC1). In the transfer mode 5 of ATC1, set the address of the input capture register TM7ICL to the memory pointer 1.
Chapter 7 16-bit Timer VII - 36 16-bit Timer Capture Capture Operation that the writing to program is selected as a Trigger (Timer 7) A capture trigger can be generated by writing an arbitrary value to the input capture register (TM7IC), and at the same timing, the value of the binary counter can be stored to the input capture register.
VII - 37 Chapter 7 16-bit Timer 16-bit Timer Capture 7-9-2 Setup Example Capture Function Setup Example (Timer 7) Pulse width measurement is enabled by storing the value of the binary counter to the capture register at the interrupt generation edge of the external interrupt 0 input signal with timer 7.
Chapter 7 16-bit Timer VII - 38 16-bit Timer Capture TM7BC counts up from x'0000'. At the timing of the rising edge of the external interrupt 0 input signal, the value of TM7BC is stored to the TM7IC register.
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8.
Chapter 8 Time Base Timer / 8-bit Free-running Timer VIII - 2 Overview Table 8-1-1 Clock Source and Generation Cycle 8-1 Overview This LSI has a time base timer and a 8-bit free-running timer (timer 6).
VIII - 3 Chapter 8 Time Base Timer / 8-bit Free-running Timer Overview 8-1-2 Block Diagram Timer 6, Time Base Timer Block Diagram Figure 8-1-1 Block Diagram (Timer 6, Time Base Timer) 0 7 TM6CK0 T.
Chapter 8 Time Base Timer / 8-bit Free-running Timer VIII - 4 Control Registers 8-2 Control Registers Timer 6 consists of binary counter (TM6BC), compare register (TM6OC), and is controlled by mode register (TM6MD). Time base timer is controlled by mode register (TM6MD) and time base timer clear register (TBCLR), too.
VIII - 5 Chapter 8 Time Base Timer / 8-bit Free-running Timer Control Registers Timer 6 Binary Counter (TM6BC) Timer 6 Compare Register (TM6OC) Figure 8-2-1 Timer 6 Binary Counter (TM6BC : x&a.
Chapter 8 Time Base Timer / 8-bit Free-running Timer VIII - 6 Control Registers TM6CK3 0 TM6CK2 0 1 0 1 1 fs fx Timer 6 clock source fosc 0 0 1 1 0 1 TM6CK1 0 1 2 4 5 6 7 3 ( At reset : 0 0 0 0 0 0 0 .
VIII - 7 Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-bit Free-running Timer 8-3 8-bit Free-running Timer 8-3-1 Operation 8-bit Free-running Timer (Timer 6) The generation cycle of the timer interrupt is set by the clock source selection and the setting value of the compare register (TM6OC), in advance.
Chapter 8 Time Base Timer / 8-bit Free-running Timer VIII - 8 8-bit Free-running Timer 8-bit Free-running Timer as a 1 minute-timer, a 1 second-timer Table 8-3-2 shows the clock source selection and the TM6OC register setup, when a 8-bit free-running timer is used as a 1 minute-timer, a 1 second-timer.
VIII - 9 Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-bit Free-running Timer Count Timing of Timer Operation (Timer 6) Binary counter counts up with the selected clock source as a count clock. (A) When any data is written to the compare register as the TM6CLRS flag is "0", the binary counter is cleared to x'00'.
Chapter 8 Time Base Timer / 8-bit Free-running Timer VIII - 10 8-bit Free-running Timer (1) Set the TM6LRS flag of the timer 6 mode register (TM6MD) to "0". At that time, the initialization of the timer 6 binary counter (TM6BC) is enabled. (2) Clock source can be selected by the TM6CK3-1 flag of the TM6MD register.
VIII - 11 Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-bit Free-running Timer If the TM6CLRS flag of the TM6MD register is set to "0", TM6BC can be initialized in every rewriting of TM6OC register, but in that state the timer 6 interrupt is disabled.
Chapter 8 Time Base Timer / 8-bit Free-running Timer VIII - 12 Time Base Timer 8-4 Time Base Timer 8-4-1 Operation Time Base Timer (Time Base Timer) The Interrupt is constantly generated.
VIII - 13 Chapter 8 Time Base Timer / 8-bit Free-running Timer Time Base Timer Count Timing of Timer Operation (Time Base Timer) The counter counts up with the selected clock source as a count clock.
Chapter 8 Time Base Timer / 8-bit Free-running Timer VIII - 14 Time Base Timer Timer Operation Setup (Time Base Timer) An interrupt can be generated constantly with time base timer in the selected interrupt cycle. The inter- rupt generation cycle is as fosc × 1/2 13 (as 0.
Chapter 9 Watchdog Timer 9.
Chapter 9 Watchdog Timer IX - 2 Overview 9-1 Overview This LSI has a watchdog timer. This timer is used to detect software processing errors. It is controlled by the watchdog timer control register (WDCTR). And, once an overflow of watchdog timer is generated, a watchdog interrupt (WDIRQ) is generated.
IX - 3 Chapter 9 Watchdog Timer Control Registers 8 Figure 9-2-1 Watchdog Timer Control Register (WDCTR : x'03F02', R/W) 9-2 Control Registers The watchdog timer is controlled by the watchdog timer control register (WDCTR).
Chapter 9 Watchdog Timer IX - 4 Operation 9-3 Operation 9-3-1 Operation The watchdog timer counts system clock (fs) as a clock source. If the watchdog timer is overflowes, the watchdog interrupt (WDIRQ) is generated as an non maskable interrupt (NMI).
IX - 5 Chapter 9 Watchdog Timer Operation 8 WDT S 1 WDT S 0 W at ch dog t ime- ou t period 00 2 16 Xs y s t e m c l o c k 01 2 18 Xs y s t e m c l o c k 10 2 20 Xs y s t e m c l o c k 11 2 22 Xs y s t.
Chapter 9 Watchdog Timer IX - 6 Operation Watchdog Timer and CPU Mode The relation between this watchdog timer and CPU mode features are as follows ; (1) In NORMAL, IDLE, SLOW mode, the system clock is counted. (2) The counting is continued regardless of switching at NORMAL, IDLE, SLOW mode.
IX - 7 Chapter 9 Watchdog Timer Operation 8 9-3-2 Setup Example The watchdog timer detects errors. On the following example, the watchdog timer period is set to 2 18 × system clock, the lowest value for watchdog timer clear is set to 2 9 × system clock.
Chapter 9 Watchdog Timer IX - 8 Operation Interrupt Service Routine Setup (1) If the watchdog timer overflows, the non maskable interrupt is generated. Confirm that the WDIR flag of the non maskable interrupt control register (NMICR) is "1" on the interrupt service routine, and manage the suitable execution.
Chapter 10 Buzzer 10.
Chapter 10 Buzzer Overview X - 2 10-1 Overview This LSI has a buzzer. It can output the square wave, having a frequency 1/2 9 to 1/2 14 of the high speed oscillation clock, or by 1/2 3 to 1/2 4 of the low speed oscillation clock.
X - 3 Chapter 10 Buzzer Control Register DLYS1 DLYS2 DLYS0 Oscillation stabilization wait period selection 0 1 2 4 5 6 7 3 (At reset : 0 0 0 0 0 0 0 - ) DLYCTR - DLYS0 DLYS1 DLYS2 BUZS0 BUZS1 BUZS2 0 .
Chapter 10 Buzzer Operation X - 4 10-3 Operation 10-3-1 Operation Buzzer Buzzer outputs the square wave, having a frequency 1/2 9 to 1/2 14 of the high speed oscillation clock (fosc), or by 1/2 3 to 1/2 4 of the low speed oscillation clock (fx).
X - 5 Chapter 10 Buzzer Operation 10-3-2 Setup Example Buzzer outputs the square wave of 2 kHz from P06 pin. It is used 8.38 MHz as the high oscillation clock (fosc).
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Chapter 11 Serial Interface 0,1 11.
Chapter 11 Serial Interface 0, 1 XI - 2 Overview 11-1 Overview This LSI contains a serial interface 0 and 1 that can be used for both communication types of clock synchronous and UART (duplex). Also, the pins are changable to A (port 0) or B (port 7).
XI - 3 Chapter 11 Serial Interface 0, 1 Overview Table 11-1-1 Serial Interface 0, 1 Functions 11-1-1 Functions Table 11-1-1 shows functions of serial interface 0, 1.
Chapter 11 Serial Interface 0, 1 XI - 4 Overview 11-1-2 Block Diagram Serial Interface 0 Block Diagram Figure 11-1-1 Serial Interface 0 Block Diagram Reception shift register SBO0B/P70 SC0RIRQ Sta.
XI - 5 Chapter 11 Serial Interface 0, 1 Overview Serial Interface 1 Block Diagram Figure 11-1-2 Serial Interface 1 Block Diagram Reception shift register SC1RIRQ Start condition generation circuit.
Chapter 11 Serial Interface 0, 1 XI - 6 Control Registers 11-2 Control Registers 11-2-1 Registers Table 11-2-1 shows registers to control serial interface 0, 1.
XI - 7 Chapter 11 Serial Interface 0, 1 Control Registers 11-2-2 Serial Interface 0 Data Buffer Registers Serial Interface 0 has each 8-bit data buffer register for transmission, and for reception.
Chapter 11 Serial Interface 0, 1 XI - 8 Control Registers 11-2-3 Serial Interface 0 Mode Registers Serial Interface 0 Mode Register 0 (SC0MD0) Figure 11-2-3 Serial Interface 0 Mode.
XI - 9 Chapter 11 Serial Interface 0, 1 Control Registers Serial Interface 0 Mode Register 1 (SC0MD1) Figure 11-2-4 Serial Interface 0 Mode Register 1 (SC0MD1 : x'03F93', R/W) 0 1 2 4 5 .
Chapter 11 Serial Interface 0, 1 XI - 10 Control Registers Serial Interface 0 Mode Register 2 (SC0MD2) SC0BRKF flag is only for reading. Figure 11-2-5 Serial Interface 0 Mode Register 2 (SC0MD2 : .
XI - 11 Chapter 11 Serial Interface 0, 1 Control Registers Serial Interface 0 Mode Register 3 (SC0MD3) All flags are only for reading. Figure 11-2-6 Serial Interface 0 Mode Register 3 (SC0MD3 : x&.
Chapter 11 Serial Interface 0, 1 XI - 12 Control Registers Serial Interface 0 Port Control Register (SC0ODC) Figure 11-2-7 Serial Interface 0 Port Control Register (SC0ODC : x'03F96', R/.
XI - 13 Chapter 11 Serial Interface 0, 1 Control Registers Figure 11-2-8 Serial Interface 0 Tranfer Clock Selection Register (SC0CKS : x'03F97', R/W) Serial Interface 0 Transfer Clock Se.
Chapter 11 Serial Interface 0, 1 XI - 14 Control Registers 11-2-4 Serial Interface 1 Data Buffer Registers Serial Interface 1 has each 8-bit data buffer register for transmission, and for reception.
XI - 15 Chapter 11 Serial Interface 0, 1 Control Registers 11-2-5 Serial Interface 1 Mode Registers Serial Interface1 Mode Register 0 (SC1MD0) Figure 11-2-11 Serial Interface 1 Mod.
Chapter 11 Serial Interface 0, 1 XI - 16 Control Registers Serial Interface 1 Mode Register 1 (SC1MD1) Figure 11-2-12 Serial Interface 1 Mode Register 1 (SC1MD1 : x'03F9B', R/W) 0 1 2 4 .
XI - 17 Chapter 11 Serial Interface 0, 1 Control Registers Serial Interface 1 Mode Register 2 (SC1MD2) SC1BRKF flag is only for reading. Figure 11-2-13 Serial Interface 1 Mode Register 2 (SC1MD2 :.
Chapter 11 Serial Interface 0, 1 XI - 18 Control Registers Serial Interface 1 Mode Register 3 (SC1MD3) All flags are only for reading. Figure 11-2-14 Serial Interface 1 Mode Register 3 (SC1MD3 : x.
XI - 19 Chapter 11 Serial Interface 0, 1 Control Registers Serial Interface 1 Port Control Register (SC1ODC) Figure 11-2-15 Serial Interface 1 Port Control Register (SC1ODC : x'03F9E', R.
Chapter 11 Serial Interface 0, 1 XI - 20 Control Registers Figure 11-2-16 Serial Interface 1 Tranfer Clock Selection Register (SC1CKS : x'03F9F', R/W) Serial Interface1 Transfer Clock Se.
XI - 21 Chapter 11 Serial Interface 0, 1 Operation 11-3 Operation Serial Interface 0, 1 can be used for both clock synchronous and duplex UART. 11-3-1 Clock Synchronous Serial Interface Activation Factor for Communication Table 11-3-1 shows activation factors for communication.
Chapter 11 Serial Interface 0, 1 XI - 22 Operation Start Condition Setup The SCnSTE flag of the SCnMD0 register sets if a start condition is enabled or not. If a start condition is enabled, and received at communication, a bit counter is cleared to restart the communication.
XI - 23 Chapter 11 Serial Interface 0, 1 Operation Receive Bit Count and First Transfer Bit When the transfer bit count is 1 bit to 7 bits, the data storing method to the received data buffer RXBUFn is different depending on the first transfer bit selection.
Chapter 11 Serial Interface 0, 1 XI - 24 Operation SCnCE1 Received data input edge Transmission data output edge 1 0 Table 11-3-2 Transmission Data Output Edge and Received Data Input Edge Input Edge / Output Edge Setup The SCnCE1 to 0 flag of the SCnMD0 register set an output edge of the transmission data, an input edge of the received data.
XI - 25 Chapter 11 Serial Interface 0, 1 Operation Data Input Pin Setup 3 channels type (clock pin (SBT pin), data output pin (SBO pin), data input pin (SBI pin)) or 2 channels type (clock pin (SBT pin), data I/O pin (SBO pin)) can be selected as the communication.
Chapter 11 Serial Interface 0, 1 XI - 26 Operation Received Buffer Empty Flag When the reception is completed (the last data reception edge of the clock is input), data is stored to RXBUFn from the internal shift register, automatically.
XI - 27 Chapter 11 Serial Interface 0, 1 Operation Emergency Reset It is possible to shut down communication. For a forced reset, the SCnSBOS flag and the SCnSBIOS flag of the SCnMD1 register should be set to "0" (SBO pin : port, input data : "1" input).
Chapter 11 Serial Interface 0, 1 XI - 28 Operation Figure 11-3-5 Transmission Timing (falling edge, start condition is enabled) Figure 11-3-6 Transmission Timing (falling edge, start condition is disa.
XI - 29 Chapter 11 Serial Interface 0, 1 Operation Figure 11-3-7 Transmission Timing (rising edge, start condition is enabled) Figure 11-3-8 Transmission Timing (rising edge, start condition is disabled) T Clock (SBT pin) Output data (SBO pin) SCnTBSY Interrupt (SCnTIRQ) Transfer bit counter 012345 6 7 ∆ (Write data to TXBUFn) (at master) Tmax=1.
Chapter 11 Serial Interface 0, 1 XI - 30 Operation Reception Timing Figure 11-3-9 Reception Timing (rising edge, start condition is enabled) Figure 11-3-10 Reception Timing (rising edge, start con.
XI - 31 Chapter 11 Serial Interface 0, 1 Operation Figure 11-3-11 Reception Timing (falling edge, start condition is enabled) Figure 11-3-12 Reception Timing (falling edge, start condition is disabled) T Clock (SBT pin) Input data (SBI pin) SCnRBSY Interrupt (SCnTIRQ) Transfer bit counter 012345 6 7 ∆ (Write data to TXBUFn) (at master) Tmax=2.
Chapter 11 Serial Interface 0, 1 XI - 32 Operation Transmission / Reception Timing When transmission and reception are operated at the same time, set the SCnCE1 flag of the SCnMD0 register to "0" or "1".
XI - 33 Chapter 11 Serial Interface 0, 1 Operation Serial Interface 0 Pins Setup (3 channels, at reception) Table 11-3-7 shows the setup for synchronous serial interface pin with 3 channels (SBO0 pin, SBI0 pin, SBT0 pin) at reception.
Chapter 11 Serial Interface 0, 1 XI - 34 Operation Serial Interface 0 Pins Setup (3 channels, at transmission / reception) Table 11-3-8 shows the setup for synchronous serial interface pin with 3 lines (SBO0 pin, SBI0 pin, SBT0 pin) at transmission / reception.
XI - 35 Chapter 11 Serial Interface 0, 1 Operation Serial Interface 0 Pins Setup (2 channels, at reception) Table 11-3-10 shows the setup for synchronous serial interface pin with 2 channels (SBO0 pin, SBT0 pin) at reception. SBI0 pin can be used as a general port.
Chapter 11 Serial Interface 0, 1 XI - 36 Operation Serial Interface 1 Pins Setup (3 channels, at reception) Table 11-3-12 shows the setup for synchronous serial interface pin with 3 channels (SBO1 pin, SBI1 pin, SBT1 pin) at reception.
XI - 37 Chapter 11 Serial Interface 0, 1 Operation Serial Interface 1 Pins Setup (3 channels, at transmission / reception) Table 11-3-13 shows the setup for synchronous serial interface pin with 3 lines (SBO1 pin, SBI1 pin, SBT1 pin) at transmission / reception.
Chapter 11 Serial Interface 0, 1 XI - 38 Operation Serial Interface 1 Pins Setup (2 channels, at reception) Table 11-3-15 shows the setup for synchronous serial interface pin with 2 channels (SBO1 pin, SBT1 pin) at reception. SBI1 pin can be used as a general port.
XI - 39 Chapter 11 Serial Interface 0, 1 Operation 11-3-4 Setup Example Transmission / Reception Setup Example The setup example for clock synchronous serial communication with serial 0 is shown. Table 11-3-16 shows the conditions at transmission / reception.
Chapter 11 Serial Interface 0, 1 XI - 40 Operation Setup Procedure Description (6 ) Set the SC0LNG2-0 flag of the serial 0 mode register (SC0MD0) to "111" to set the transfer bit count "8 bits". (7 ) Set the SC0STE flag of the SC0MD0 register to "0" to disable start condition.
XI - 41 Chapter 11 Serial Interface 0, 1 Operation (15) Set the interrupt level. SC0TICR (x'3FF5') bp7-6 : SC0TLV1-0 = 10 (16) Enable the interrupt. SC0TICR (x'3FF5') bp1 : SC0TIE = 1 (17) Start serial transmission. Transmission data → TXBUF0 (x'3F91') Received data → input to SBI0A pin.
Chapter 11 Serial Interface 0, 1 XI - 42 Operation 11-3-5 UART Serial Interface Serial 0, 1 can be used for duplex UART communication. Table 11-3-17 shows UART serial interface functions.
XI - 43 Chapter 11 Serial Interface 0, 1 Operation Activation Factor for Communication At transmission, if any data is written to the transmission data buffer TXBUFn, a start condition is gener- ated to start transfer. At reception, if a start condition is received, communication is started.
Chapter 11 Serial Interface 0, 1 XI - 44 Operation Frame Mode and Parity Check Setup Figure 11-3-15 shows the data format at UART communication. parity bit stop bit start bit character bits 1 data.
XI - 45 Chapter 11 Serial Interface 0, 1 Operation Parity bit is to detect wrong bits with transmission / reception data. Table 11-3-20 shows kinds of parity bit. The SCnNPE, SCnPM1 to 0 flag of the SCnMD2 register set parity bit. Break Status Transmission Control Setup The SCnBRKE flag of the SCnMD2 register generates the break status.
Chapter 11 Serial Interface 0, 1 XI - 46 Operation Judgement of Break Status Reception Reception at break status can be judged. If all received data from start bit to stop bit is "0", the SCnBRKF flag of the SCnMD2 register is set and regard the break status.
XI - 47 Chapter 11 Serial Interface 0, 1 Operation Transmission/reception data polarity switching In UART communication, polarity of transmission/reception data cannot be switched. At the same time, setups of the SCnTRN, SCnREN flags of the SCnMD0 register are invalid.
Chapter 11 Serial Interface 0, 1 XI - 48 Operation The following items are same to clock synchronous serial. Reference as follows ; First Transfer Bit Setup Refer to : XI-21 Transmission Data .
XI - 49 Chapter 11 Serial Interface 0, 1 Operation Transmission Timing TXD pin SCnTBSY Interrupt (SCnTIRQ) parity bit stop bit stop bit ∆ write data to TXBUFn T TXD pin SCnTBSY Interrupt (SCnTIR.
Chapter 11 Serial Interface 0, 1 XI - 50 Operation Reception Timing RXD pin SCnRBSY Interrupt (SCnRIRQ) Parity bit Stop bit Stop bit ∆ input start condition Tmin=0.5 T T RXD pin SCRBSY Interrupt (SCRIRQ) stop bit stop bit ∆ input start condition Tmin=0.
XI - 51 Chapter 11 Serial Interface 0, 1 Operation Transfer Rate Baud rate timer (timer 2 and timer 4) can set any transfer rate. Tables 11-3-22, 23 show the setup example of the transfer rate. For detail of the baud rate timer setup, refer to chapter 6.
Chapter 11 Serial Interface 0, 1 XI - 52 Operation Table 11-3-24-1 UART Serial Interface Transfer Rate (decimal) 300 960 1200 2400 4800 - - 207 51 25 12 207 104 217 217 108 103 51 25 - 207 108 217 155.
XI - 53 Chapter 11 Serial Interface 0, 1 Operation Table 11-3-24-2 UART Serial Interface Transfer Rate (decimal) 9600 19200 28800 31250 38400 25 - - - - - - 26 - - - - - - 51 12 - - 12 54 77 103 25 25.
Chapter 11 Serial Interface 0, 1 XI - 54 Operation 11-3-6 Serial interface 0 UART Serial Interface Pin Setup Serial Interface 0 Pin Setup (1, 2 channels, at transmission) Table 11-3-25 shows the pins setup at UART serial interface 0 transmission.
XI - 55 Chapter 11 Serial Interface 0, 1 Operation Serial Interface 0 Pin Setup (1 channel, at reception) Table 11-3-27 shows the pin setup at UART serial interface 0 reception with 1 channel (TXD0 pin). The RXD0 pin is not used, so can be used as a port.
Chapter 11 Serial Interface 0, 1 XI - 56 Operation 11-3-7 Serial interface 1 UART Serial Interface Pin Setup Serial Interface 1 Pin Setup (1, 2 channels, at transmission) Table 11-3-29 shows the pins setup at UART serial interface 1 transmission.
XI - 57 Chapter 11 Serial Interface 0, 1 Operation Serial Interface 1 Pin Setup (1 channel, at reception) Table 11-3-31 shows the pin setup at UART serial interface reception with 1 channel (TXD1 pin). The RXD1 pin is not used, so can be used as a port.
Chapter 11 Serial Interface 0, 1 XI - 58 Operation 11-3-8 Setup Example Transmission / Reception Setup The setup example at UART transmission / reception with serial 0 is shown.
XI - 59 Chapter 11 Serial Interface 0, 1 Operation Setup Procedure Description (6 ) Select the start condition. SC0MD0 (x'3F92') bp3 : SC0STE = 1 (7 ) Select the first bit to be transfered. SC0MD0 (x'3F92') bp4 : SC0DIR = 0 (8 ) Control the output data.
Chapter 11 Serial Interface 0, 1 XI - 60 Operation Note : (6) to (7), (8) to (10), (11) to (13) can be set at once. (14) Set the SC0RIE flag of the SC0RICR register to "1", and set the SC0TIE flag ot the SC0TICR register to "1" to enable the interrupt request.
18 Chapter 12 Serial Interface 3 12.
XII - 2 Overview Chapter 12 Serial Interface 3 Table 12-1-1 Serial Interface 3 Functions List 12-1 Overview This LSI contains a serial interface 3 can be used for both communication types of clock synchronous and simple IIC (single master). 12-1-1 Functions Table 12-1-1 shows the functions of serial interface 3.
XII - 3 Overview Chapter 12 Serial Interface 3 12-1-2 Block Diagram Serial Interface 3 Block Diagram Figure 12-1-1 Serial Interface 3 Block Diagram SBO3/SDA/P51 SBI3/P50 SBT3/SCL/P52 M U X SC3IOM .
Control Registers Chapter 12 Serial Interface 3 XII - 4 12-2 Control Registers 12-2-1 Registers Table 12-2-1 shows the registers to control serial interface 3.
Control Registers Chapter 12 Serial Interface 3 XII - 5 1 4 14 12-2-2 Data Register Serial interface 3 has a 8-bit serial data register. Figure 12-2-1 Serial Interface 3 Transmit/Receive Shift Registe.
Control Registers Chapter 12 Serial Interface 3 XII - 6 12-2-3 Mode Registers Serial Interface 3 Mode Register 0 (SC3MD0) Figure 12-2-2 Serial Interface 3 Mode Register 0 (SC3MD0 : x'03FA8&ap.
Control Registers Chapter 12 Serial Interface 3 XII - 7 1 4 14 Serial Interface 3 Mode Register 1 (SC3MD1) Figure 12-2-3 Serial Interface 3 Mode Register 1 (SC3MD1 : x'03FA9', R/W) 0 1 2.
Control Registers Chapter 12 Serial Interface 3 XII - 8 Serial Interface 3 Control Register (SC3CTR) Figure 12-2-4 Serial Interface 3 Control Register (SC3CTR : x'03FAA', R/W) 0 1 2 4 5 .
Control Registers Chapter 12 Serial Interface 3 XII - 9 1 4 14 Serial Interface 3 Port Control Register (SC3ODC) Figure 12-2-5 Serial Interface 3 Port Control Register (SC3ODC : x'03FAE'.
Chapter 12 Serial Interface 3 Operation XII - 10 12-3 Operation This LSI contains a serial interface 3 that can be used for both communication types of clock synchronous and single master IIC. 12-3-1 Clock Synchronous Serial Interface Activation Factor for Communication Table 12-3-1 shows the activation factor for communication.
Chapter 12 Serial Interface 3 Operation XII - 11 First Transfer Bit Setup The first bit to be transferred can be set by the SC3DIR flag of the SC3MD0 register. MSB first or LSB first can be selected. Transmit /Receive Data Buffer Data register for transmission/reception is common.
Chapter 12 Serial Interface 3 Operation XII - 12 Clock Setup Clock source is selected from the dedicated prescaler by the SC3CKS register and timer 5 output. The dedicated prescaler is started by selecting "prescaler operation" by the PSCMD (x'03F6F') register.
Chapter 12 Serial Interface 3 Operation XII - 13 Forced Reset at Communication It is possible to shut down the communication. A forced reset is operated by setting both of the SC3SBOS flag and the SC3SBIS flag of the SC3MD1 register to "0" (the SBO3 pin function : port, input data : input "1").
Chapter 12 Serial Interface 3 Operation XII - 14 T Clock (SBT3 pin) Output data (SBO3 pin) SC3BSY Interrupt (SC3IRQ) Transfer bit counter 1 0 23456 7 at master Tmax=2.
Chapter 12 Serial Interface 3 Operation XII - 15 T Clock (SBT3 pin) Output data (SBO3 pin) SC3BSY Interrupt (SC3IRQ) Transfer bit counter 1 0 23456 7 at master Tmax=2.
Chapter 12 Serial Interface 3 Operation XII - 16 Reception Timing Figure 12-3-6 Reception Timing (Rising edge, Enable Start Condition) Figure 12-3-7 Reception Timing (Rising edge, Disable Start Condition) T Clock (SBT3 pin) Input data (SBI3 pin) SC3BSY interrupt (SC3IRQ) Transfer bit counter 1 0 23456 7 (Write data to SC3TRB) at master Tmax=2.
Chapter 12 Serial Interface 3 Operation XII - 17 Figure 12-3-9 Reception Timing (Falling edge, Disable Start Condition) Figure 12-3-8 Reception Timing (Falling edge, Enable Start Condition) T Clock (SBT3 pin) Input data (SBI3 pin) SC3BSY Interrupt (SC3IRQ) Transfer bit counter 1 0 23456 7 (Write data to SC3TRB) at master Tmax=1.
Chapter 12 Serial Interface 3 Operation XII - 18 Transmission/Reception Simultaneous timing When transmission and reception are operated at the same time, data is recieved at the opposite edge of the transmission clock. SBT3 pin SBI3 pin SBO3 pin Data is input at the rising edge of the clock.
Chapter 12 Serial Interface 3 Operation XII - 19 Pin Setup (3 channels, at transmission) Table 12-3-5 shows the pins setup at synchronous serial interface transmission with 3 channels (SBO3 pin, SBI3 pin, SBT3 pin).
Chapter 12 Serial Interface 3 Operation XII - 20 Pin Setup (3 channels, at reception) Table 12-3-6 shows the pins setup at synchronous serial interface reception with 3 channels (SBO3 pin, SBI3 pin, SBT3 pin).
Chapter 12 Serial Interface 3 Operation XII - 21 Pin Setup (3 channels, at transmission/reception) Table 12-3-7 shows the pins setup at synchronous serial interface transmission/reception with 3 channels (SBO3 pin, SBI3 pin, SBT3 pin).
Chapter 12 Serial Interface 3 Operation XII - 22 Pin Setup (2 channels, at transmission) Table 12-3-8 shows the pins setup at synchronous serial interface transmission with 2 channels (SBO3 pin, SBT3 pin). The SBI3 pin is not used, so that it can be used as a general port.
Chapter 12 Serial Interface 3 Operation XII - 23 Pin Setup (2 channels, at reception) Table 12-3-9 shows the pins setup at synchronous serial interface reception with 2 channels (SBO3 pin, SBT3 pin). The SBI3 pin is not used, so that it can be used as a general port.
Chapter 12 Serial Interface 3 Operation XII - 24 13-3-2 Setup Example Transmission/Reception Setup Example Here is the setup example for transmission/reception with serial interface 3.
Chapter 12 Serial Interface 3 Operation XII - 25 (6) Select the transfer bit count. SC3MD0 (x'3FA8') bp2-0 : SC3LNG2-0 = 111 (7) Select the start condition. SC3MD0 (x'3FA8') bp3 : SC3STE = 1 (8) Select the first transfer bit. SC3MD0 (x'3FA8') bp4 : SC3DIR = 0 (9) Select the transfer edge.
Chapter 12 Serial Interface 3 Operation XII - 26 (15) Start serial transmission. Transmission data → SC3TRB (x'3FAB') (15) Set the transmission data to the serial transmit/receive shift register SC3TRB. The internal clock is generated to start transmission/reception.
Chapter 12 Serial Interface 3 Operation XII - 27 12-3-3 Single Master IIC Interface Activation factor for Communication Set data (at transmission) or dummy data (at reception) to the transmit/receive shift register SC3TRB. Start condition and transfer clock are generated to start communication, regardless of transmission/ reception.
Chapter 12 Serial Interface 3 Operation XII - 28 Start Condition Setup At IIC communication, enable start condition by the SC3STE flag of the SC3MD0 register at the begin- ning of communication. The SC3STE flag of the SC3MD0 register can select if start condition is enabled or not.
Chapter 12 Serial Interface 3 Operation XII - 29 SDA SCL 12 . . 8 ACK bit reception clock (generated by switching the pin of software) ACK/ NACK Data transmission period (Hardware processing period) I.
Chapter 12 Serial Interface 3 Operation XII - 30 Clock Setup The transfer clock of IIC communication is the one that the clock source is divided by 3 inside of this serial. The clock source is selected from the dedicated prescaler and timer 5 output by the SC3CKS register.
Chapter 12 Serial Interface 3 Operation XII - 31 At communication, set Nch-open drain for pin's type, because the hardware switches if bus is used/released. And even at reception, select the SDA pin (the SBO3 pin) direction control to "output".
Chapter 12 Serial Interface 3 Operation XII - 32 Figure 12-3-16 Master Transmission Timing Master Transmission Timing SDA SCL Interrupt 12 . . . . 8 ACK 1 2 8 IICBSY Set data to SC3TRB Clear IICBSY flag (1) (2) (3) (4) (5) (6) Set data to SC3TRB ACK 8-bit transmission 8-bit transmission (1) Output start condition.
Chapter 12 Serial Interface 3 Operation XII - 33 Figure 12-3-17 Master Reception Timing Master Reception Timing SDA SCL Interrupt 12 . . . . 8 ACK 1 2 8 IICBSY Set data to SC3TRB Clear IICBSY flag (1) (2) (3) (4) (5) (6) Set data to SC3TRB ACK 8-bit transmission 8-bit reception [Set dummy data] (1) Output start condition.
Chapter 12 Serial Interface 3 Operation XII - 34 Pin Setup (2 channels, at transmission) Table 12-3-13 shows the pins setup at IIC serial interface transmission with 2 channels (SDA pin, SCL pin).
Chapter 12 Serial Interface 3 Operation XII - 35 Pin Setup (2 channels, at reception) Table 12-3-14 shows the pins setup at IIC serial interface reception with 2 channels (SDA pin, SCL pin).
Chapter 12 Serial Interface 3 Operation XII - 36 Figure 12-3-15 Conditions Single Master IIC Communication Setup (1) Select prescaler operation. PSCMD (x'3F6F') bp0 : PSCEN = 1 (2) Select the clock source. SC2CKS (x'3FAF') bp2-0 : SC3PSC2-0 = 100 bp3 = 0 (3) Control the pin type.
Chapter 12 Serial Interface 3 Operation XII - 37 Setup Procedure Description (5 ) Set ACK bit. SC3CTR (x'3FAA') bp0 : SC3ACKO = x bp1 : SC3ACKS = 1 (6) Select the communication type. SC3CTR (x'3FAA') bp2 : SC3CMD = 1 <Transmission setup> (7) Select the transmission/reception mode.
Chapter 12 Serial Interface 3 Operation XII - 38 (13) Select the transfer clock. SC3MD1 (x'3FA9') bp2 : SC3MST = 1 (14) Control the pin function. SC3MD1 (x'3FA9') bp4 : SC3SBOS = 1 bp5 : SC3SBIS = 1 bp6 : SC3SBTS = 1 bp7 : SC3IOM = 1 (15) Set the interrupt level.
Chapter 12 Serial Interface 3 Operation XII - 39 (19) Judge the ACK bit level. SC3CTR (x'3FAA') bp0 : SC3ACKO (20) Select the transfer bit count. SC3MD0 (x'3FA8') bp2-0 : SC3LNG2-0 = 0 (21) Select the start condition. SC3MD0 (x'3FA8') bp3 : SC3STE = 0 <The next data transmission is started.
Chapter 12 Serial Interface 3 Operation XII - 40 It is possible to shut down the communication. When the communication should be stopped by force, set the SC3SBOS and the SC3SBIS of the SC3MD1 register to "0". Setup for each flag should be done in order.
Chapter 13 Serial Interface 4 13.
XIII - 2 Overview Chapter 13 Serial Interface 4 Table 13-1-1 Serial interface 4 Functions List 13-1 Overview This LSI contains a serial interface 4, which is compatible with IIC serial interface (slave) communication. 13-1-1 Functions Table 13-1-1 shows the functions of serial interface 4.
XIII - 3 Overview Chapter 13 Serial Interface 4 13-1-2 Block Diagram Serial interface 4 Block Diagram Figure 13-1-1 Serial interface 4 Block Diagram P01/SDA P53/SDA M U X Transmission/reception Sh.
Control Registers Chapter 13 Serial Interface 4 XIII - 4 13-2 Control Registers 13-2-1 Registers Table 13-2-1 shows the registers to control serial interface 4.
Control Registers Chapter 13 Serial Interface 4 XIII - 5 1 4 14 13-2-2 Data Register Serial interface 4 has a 8-bit buffer registers for transmission/reception.
Control Registers Chapter 13 Serial Interface 4 XIII - 6 13-2-3 Mode Registers Serial interface 4 Addressing Register 0 (SC4AD0) Figure 13-2-3 Serial interface 4 Addressing Register 0 (SC4AD0 : x&.
Control Registers Chapter 13 Serial Interface 4 XIII - 7 1 4 14 Serial interface 4 Status Register (SC4STR) Figure 13-2-5 Serial interface 4 Status Register (SC4STR : x'03FAC', R) 0 1 2 .
Control Registers Chapter 13 Serial Interface 4 XIII - 8 Serial interface 4 Port Control Register 0 (SC4ODC0) Figure 13-2-6 Serial interface 4 Port Control Register 0 (SC4ODC0 : x'03F3F'.
Chapter 13 Serial Interface 4 Operation XIII - 9 13-3 Operation Activation and Termination Factors Set the SELI2C flag of the SC4AD1 register to "1" to activate this serial interface.
Chapter 13 Serial Interface 4 Operation XIII - 10 Busy Flag This serial interface contains 2 busy flags (SLVBSY, I2CBSY). The SLVBSY flag is set to "1" when address transmitted from master matches with the slave address. The I2CBSY flag is set to "1" during communication on IIC bus.
Chapter 13 Serial Interface 4 Operation XIII - 11 13-3-1 Setup Example of the Slave IIC Serial Interface Setup Example of the Data Transmission This section describes the setup example of slave transmission using serial interface 4. Table 13-3-2 shows the conditions for transmission routine.
Chapter 13 Serial Interface 4 Operation XIII - 12 (5) Set the slave address. SC4AD0 (x'3FA3') bp7-1 : I2CAD7-1 = 0110011 (6) IIC communication start (7) Data transmission/reception confirmat.
Chapter 14 Automatic Transfer Controller 14.
Chapter 14 Automatic Transfer Controller XIV - 2 Overview 14-1 Overview 14-1-1 ATC1 This LSI contains an automatic transfer controller (ATC) that uses direct memory access (DMA) to transfer the contents of the whole memory space (256 KB) using the hardware.
XIV - 3 Chapter 14 Automatic Transfer Controller Overview 13 14-1-2 Functions Table 14-1-1 and 14-1-2 provide a list of the ATC1 trigger factors and transfer modes.
Chapter 14 Automatic Transfer Controller XIV - 4 Overview 14-1-3 Block Diagram ATC1 Block Diagram Figure 14-1-1 ATC1 Block Diagram ATC1 Trigger Factor s DMA Transfer State Control TM7 Capture Trig.
Chapter 14 Automatic Transfer Controller Control Registers XIV - 5 13 14-2 Control Registers 14-2-1 Registers Table 14-2-1 shows the registers used to control ATC1.
Chapter 14 Automatic Transfer Controller Control Registers XIV - 6 ATC1 Control Register 0 (AT1CNT0) Figure 14-2-1 ATC1 Control Register 0 (AT1CNT0 : x'03FD0', R/W) AT1CNT0 FMODE AT1MD0 .
Chapter 14 Automatic Transfer Controller Control Registers XIV - 7 13 Figure 14-2-3 ATC1 Transfer Data Counter (AT1TRC : x'03FD2', R/W) ATC1 Control Register 1 (AT1CNT1) AT1IR2 AT1IR1 AT.
Chapter 14 Automatic Transfer Controller Control Registers XIV - 8 ATC1 Memory Pointer 0 (AT1MAP0) Figure 14-2-6 ATC1 Memory Pointer 0 : Upper 2 bits (AT1MAP0H : x'03FD5', R/W) Figure 14.
Operation Chapter 14 Automatic Transfer Controller XIV - 9 13 14-3 Operation 14-3-1 Basic Operations and Timing ATC1 is a DMA block that enables the hardware to transfer the whole memory space (256 KB). This section provides a description of and timing for the basic ATC1 operations.
Chapter 14 Automatic Transfer Controller Operation XIV - 10 Data transfer The basic ATC1 operation cycle is the "byte-data transfer cycle", in which ATC1 transfers a single byte of data. This operation consists of two instruction cycles, a load and a store cycle.
Operation Chapter 14 Automatic Transfer Controller XIV - 11 13 14-3-2 Setting the Memory Address Setting the transfer addresses to the memory pointers The address of the memory space for an automatically data transfer of ATC1 should be set in the both of memory pointer 0 (AT1MAP0) and memory pointer 1 (AT1MAP1).
Chapter 14 Automatic Transfer Controller Operation XIV - 12 14-3-3 Setting the Data Transfer Count Transfer data counter (AT1TRC) function You can preset the data transfer count is preset for ATC1. Set the value in the ATC1 transfer counter (AT1TRC).
Operation Chapter 14 Automatic Transfer Controller XIV - 13 13 14-3-4 Setting the Data Transfer Modes Data transfer modes There are two types of ATC1 transfers, standard and burst, and sixteen transfer modes. Set the transfer mode in ATC1 control register 0 (AT1CNT0).
Chapter 14 Automatic Transfer Controller Operation XIV - 14 Set the source address in 18-bit memory pointer 0 (AT1MAP0H, M, L), and set the destination I/O address in lower 8 bits of memory pointer 1(AT1MAP1L). The upper 10 bits of the I/O space address (x'03F') need not to be set in AT1MAP1H and AT1MAP1M.
Operation Chapter 14 Automatic Transfer Controller XIV - 15 13 Set the source I/O address in lower 8 bits of memory pointer 1 (AT1MAP1L), and set the destination address in 18-bit memory pointer 0 (AT1MAP0H, M, L). The upper 10 bits of the I/O space address (x'03F') need not to be set in AT1MAP1H and AT1MAP1M.
Chapter 14 Automatic Transfer Controller Operation XIV - 16 Figure 14-3-4 Transfer Mode 2 Set the source address in 18-bit memory pointer 0 (AT1MAP0H, M, L), and set the destination I/O address in lower 8 bits of memory pointer 1(AT1MAP1L). The upper 10 bits of the I/O space address (x'03F') need not to be set in AT1MAP1H and AT1MAP1M.
Operation Chapter 14 Automatic Transfer Controller XIV - 17 13 Set the source I/O address in lower 8 bits of memory pointer 1 (AT1MAP1L), and set the destination address in 18-bit memory pointer 0 (AT1MAP0H, M, L). The upper 10 bits of the I/O space address (x'03F') need not to be set in AT1MAP1H and AT1MAP1M.
Chapter 14 Automatic Transfer Controller Operation XIV - 18 14-3-9 Transfer Mode 4 In transfer mode 4, ATC1 automatically transfers two bytes (one word) of data from any memory space to the I/O space (special registers : x'03F00' - x'03FFF') every time an ATC1 activation request occurs.
Operation Chapter 14 Automatic Transfer Controller XIV - 19 13 14-3-10 Transfer Mode 5 In transfer mode 5, ATC1 automatically transfers two bytes (one word) of data from the I/O space (special registers : x'03F00' - x'03FFF') to any memory space every time an ATC1 activation request occurs.
Chapter 14 Automatic Transfer Controller Operation XIV - 20 14-3-11 Transfer Mode 6 In transfer mode 6, ATC1 automatically transfers one byte of data two times every time an ATC1 activation request occurs.
Operation Chapter 14 Automatic Transfer Controller XIV - 21 13 To execute a continuous serial transaction, you must pre-store the serial transmission data in the memory space that memory pointer 0 points, the transmission data must fill every other address in the space.
Chapter 14 Automatic Transfer Controller Operation XIV - 22 14-3-12 Transfer Mode 7 In transfer mode 7, ATC1 automatically transfers one byte of data two times every time an ATC1 activation request occurs.
Operation Chapter 14 Automatic Transfer Controller XIV - 23 13 In transfer mode 7, ATC1 executes a data byte transfer twice each time it is activated. However, the value in memory pointer 0 increments by one only after the first transfer ends.
Chapter 14 Automatic Transfer Controller Operation XIV - 24 14-3-13 Transfer Mode 8 In transfer mode 8, ATC1 automatically transfers one byte of data two times every time an ATC1 activation request occurs.
Operation Chapter 14 Automatic Transfer Controller XIV - 25 13 In transfer mode 8, ATC1 executes a data byte transfer twice each time it is activated. The value in memory pointer 0 increments by one each time a byte-length data transfer ends.
Chapter 14 Automatic Transfer Controller Operation XIV - 26 14-3-14 Transfer Mode 9 In transfer mode 9, ATC1 automatically transfers one byte of data two times every time an ATC1 activation request occurs.
Operation Chapter 14 Automatic Transfer Controller XIV - 27 13 In transfer mode 9, ATC1 executes a data byte transfer twice each time it is activated. However, the value in memory pointer 0 increments by one only after the first transfer ends.
Chapter 14 Automatic Transfer Controller Operation XIV - 28 14-3-15 Transfer mode A In transfer mode A, ATC1 automatically transfers one byte of data from any memory space to any other memory space every time an ATC1 activation request occurs.
Operation Chapter 14 Automatic Transfer Controller XIV - 29 13 14-3-16 Transfer Mode B In transfer mode B, ATC1 automatically transfers one byte of data from any memory space to any other memory space every time an ATC1 activation request occurs.
Chapter 14 Automatic Transfer Controller Operation XIV - 30 14-3-17 Transfer Mode C In transfer mode C, ATC1 automatically transfers one byte of data from any memory space to any other memory space every time an ATC1 activation request occurs.
Operation Chapter 14 Automatic Transfer Controller XIV - 31 13 14-3-18 Transfer Mode D In transfer mode D, ATC1 automatically transfers one byte of data from any memory space to any other memory space every time an ATC1 activation request occurs.
Chapter 14 Automatic Transfer Controller Operation XIV - 32 14-3-19 Transfer Mode E Transfer mode E is a burst mode. In this mode, when ATC1 is activated, it automatically transfers the number of data bytes set in the transfer data counter (AT1TRC) in one continuous operation.
Operation Chapter 14 Automatic Transfer Controller XIV - 33 13 14-3-20 Transfer Mode F Transfer mode F is a burst mode. In this mode, when ATC1 is activated, it automatically transfers the number of data bytes set in the transfer data counter (AT1TRC) in one continuous operation.
Chapter 14 Automatic Transfer Controller Setup Example XIV - 34 1 4 -4 Setup Example An example setup procedure, with a description of each step is as follows ; (1) Select the data transfer mode with the AT1MD flag in the AT1CNT0 register.
Setup Example Chapter 14 Automatic Transfer Controller XIV - 35 13 To activate ATC1 in the software, first complete steps (1) to (6), then set the AT1ACT flag in the AT1CNT0 register. After the AT1ACT flag is set, ATC1 is started and data transfer is started.
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Chapter 15 A/D Converter 15.
Chapter 15 A/D Converter Overview XV - 2 15-1 Overview This LSI has an A/D converter with 10 bits resolution. That has a built-in sample hold circuit, and software can switch channel 0 to 6 (AN0 to AN6) to analog input. As A/D converter is stopped, the power consump- tion can be reduced by a built-in ladder resistance.
Chapter 15 A/D Converter Overview XV - 3 15-1-2 Block Diagram Figure 15-1-1 A/D Converter Block Diagram MUX MUX A/D conversion data upper 8 bits A/D conversion data lower 2 bits Sample and hold A/D co.
Chapter 15 A/D Converter XV - 4 Control Registers 15-2 C on tro l R egi st er s A/D converter consists of the control register (ANCTRn) and the data storage buffer (ANBUFn). 15-2-1 Registers Table 15-2-1 shows the registers used to control A/D converter.
XV - 5 Chapter 15 A/D Converter Control Registers 15-2-2 Control Registers A/D Converter Control Register 0 (ANCTR0) Figure 15-2-1 A/D Converter Control Register 0 (ANCTR0 : x'03FB0', R/W) 0 as 800 ns < T AD ≤ 15.
Chapter 15 A/D Converter XV - 6 Control Registers A/D Converter Control Register 1 (ANCTR1) A/D Converter Control Register 2 (ANCTR2) Figure 15-2-2 A/D Converter Control Register 1 (ANCTR1 : x.
XV - 7 Chapter 15 A/D Converter Control Registers 15-2-3 Data Buffers A/D Conversion Data Storage Buffer 0 (ANBUF0) The lower 2 bits from the result of A/D conversion are stored to this register. A/D Conversion Data Storage Buffer 1 (ANBUF1) The upper 8 bits from the result of A/D conversion are stored to this register.
Chapter 15 A/D Converter Operation XV - 8 15-3 Operation Here is a description of A/D converter circuit setup procedure. (1) Set the analog pins. Set the analog input pin, set in (2), to "special function pin" by the port A input mode register (PAIMD).
Operation Chapter 15 A/D Converter XV - 9 Figure 15-3-1 Operation of A/D Conversion To read the value of the A/D conversion, A/D conversion should be done several times to prevent noise error by confirming the match of level by program, or by using the average value.
Chapter 15 A/D Converter Operation XV - 10 Sampling Time (Ts) of A/D Converter Setup The sampling time of A/D converter is set by the ANSH1 to 0 flag of the ANCTR0 register. The sampling time of A/D converter depends on external circuit, so set the right value by analog input impedance.
Operation Chapter 15 A/D Converter XV - 11 Built-in Ladder Resistor Control The ANLADE flag of the ANCTR0 register is set to "1" to send a current to the ladder resistance for A/ D conversion. As A/D converter is stopped, the ANLADE flag of the ANCTR0 register is set to "0" to save the power consumption.
Chapter 15 A/D Converter Operation XV - 12 Setup Procedure (1) Set the analog input pin. PAIMD (x'3F3C') bp0 : PAIMD0 = 1 PAPLUD (x'3F4A') bp0 : PAPLUD0 = 0 PADIR (x'3F3A') bp0 : PADIR0 = 0 (2 ) Select the analog input pin.
Operation Chapter 15 A/D Converter XV - 13 Setup Procedure Description (7 ) Set the ANLADE flag of the A/D converter control register 0 (ANCTR0) to "1" to send a current to the ladder resistance for the A/D conversion.
Chapter 15 A/D Converter Operation XV - 14 (1) Set the analog input pin that set in (2), to the special function pin by the port A input mode register (PAIMD). Also, set no pull-up/pull- down resistance by the port A pull-up/pull- down resistance control register (PAPLUD).
Operation Chapter 15 A/D Converter XV - 15 (7 ) Enable the interrupt by setting the ADIE flag of the ADICR register to "1". (8 ) Set the ANLADE flag of the A/D converter control register 0 (ANCTR0) to "1" to send a current to the ladder resistance for the A/D conversion.
Chapter 15 A/D Converter Operation XV - 16 15-3-3 Cautions A/D conversion can be damaged by noise easily, therefore, anti-noise measures should be taken ad- equately . Anti-noise measures To A/D input (analog input pin), add condenser near the V SS pins of micro controller.
Operation Chapter 15 A/D Converter XV - 17 To maintain high precision of A/D conversion, following instructions on use of A/D con- verter should be strictly kept. 1. Input impedance R of A/D input pin should be under 500 k Ω *1 . And connect the external capacitor C (over 1000 pF, under 1 µ F) *1 between Vss and the A/D input pin.
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18 Chapter 16 D/A Converter 16.
Chapter 16 D/A Converter XVI - 2 Overview Figure 16-1-1 D/A Converter Block Diagram 16-1 Overview This LSI has a built-in D/A converter with 8 bits solution. There are 2 output channels and 8-bit data registers for each channel. When the D/A converter is not used, the built-in ladder resistance can be set to OFF to save the power consumption.
Operation XVI - 3 Chapter 16 D/A Converter 16-2 Operation The D/A converter circuit setup procedure is as follows: (1 ) Set the analog pins. Set the analog input pin, set in (2), to "special function pin" by the port A input mode register (PAIMD).
Chapter 16 D/A Converter XVI - 4 Control Registers 16-3 C on tro l R egi st er s 16-3-1 Overview Table 16-3-1 shows the registers to control the D/A converter in MN101C77C.
XVI - 5 Chapter 16 D/A Converter Control Registers 16-3-2 Control Register (DACTR) This is the 8-bit readable/writable register that controls the D/A conversion.
Chapter 16 D/A Converter XVI - 6 Control Registers 16-3-3 Input Data Registers These readable/writable registers store the A/D converter data. D/A Converter Input Data Register 01 (DADR01) This register stores the D/A conversion data (for DA01 channel).
Setup Example XVI - 7 Chapter 16 D/A Converter 16-4 Setup Example Channel fixed D/A Converter Setup Example Conversion channel should be set to DA0.
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Chapter 17 Appendices 17.
Chapter 17 Appendices XVII- 2 Probe Switches 17-1 Probe Switches 17-1-1 PRB-MBB101C77-M - This prob e must be us ed with the follo wing boar ds. - Connec tor board : PX-CN101- M - MBB board: PRB-MBB10.
Chapter 17 Appendices Probe Switches XVII-3 17-1-2 PX-CN101-M This board can be used for any M BB models (produ ct No. PRB-MB B101 ∗∗∗ -M) of MN101 series. (Please visit our website for the latest information on the prod uct.) < How to connect > Make sure that the points marked are put together .
Chapter 17 Appendices XVII-4 Probe Switches 17-1-3 PRB-ADP101-64-M When connected to the target, use this board with MBB board. This board can be used wit h the following boards. (The product type is subject to change without prior notice. The latest information should be confirmed on our web si te.
Chapter 17 Appendices Probe Switches XVII-5 17-1-4 PRB-DMY101C77-M Dummy target boards dif fer depending upon the models. This b oard can be used for only 101C77 64PIN. When unconnected to the target, use this boa rd with the PRB-MBB101C77-M . Improper matching may cause any dam age to the ICE.
Chapter 17 Appendices XVII - 6 Special Function Registers List I/O Wait Setup Clock Switching Watchdog Time-out Period Setup Internal ROM/External Memory Switching X'3F00' X'3F01' .
XVII - 7 Chapter 17 Appendices Special Function Registers List P6 Synchronous Output Event Selection Bit Symbol /Initial Value /Description Port 6 Synchronous Output Selection Port 8 Input Data Port 2.
Chapter 17 Appendices XVII - 8 Special Function Registers List X'3F36' X'3F37' P7DIR X'3F38' P8DIR X'3F3C' PAIMD X'3F3E' P6IMD X'3F40' P0PLU.
XVII - 9 Chapter 17 Appendices Special Function Registers List Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 X'3F53' X'3F54' X'3F55' X'3F56' TM1OC7 TM1OC6 TM1OC5 TM.
Chapter 17 Appendices XVII - 10 Special Function Registers List Timer 7 Count Clock Selection Timer 7 Clock Source Selection Timer 7 Capture Trigger Selection X'3F70' X'3F71' X&apo.
XVII - 11 Chapter 17 Appendices Special Function Registers List Bit Symbol /Initial Value /Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X'3F98' X'3F99' X'3F9A&a.
Chapter 17 Appendices XVII - 12 Special Function Registers List Bit Symbol /Initial Value /Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X'3FAE' X'3FAF' X'3FB0&a.
XVII - 13 Chapter 17 Appendices Special Function Registers List X'3FD1' - - - BTSTP AT1IR3 AT1IR2 AT1IR1 AT1IR0 ATCNT1 Burst Transfer Enable flag ATC1 Activation Factor Selection XIV - 7 X&a.
Chapter 17 Appendices XVII - 14 Special Function Registers List X'3FF0' X'3FF1' X'3FF2' X'3FF9' X'3FFA' X'3FFC' ATC1LV1 ATC1LV0 - ATC1IE ATC.
XVII - 15 Chapter 17 Appendices Special Function Registers List X'3FA4' X'3FA5' X'3FAD' X'3FAC' X'3F3F' SC4ODC0 X'3F3D' SC4ODC1 X'3FF3&.
Chapter 17 Appendices XVII - 16 Instruction Set 1 7 -3 Instruction Set MN101C SERIES INSTRUCTION SET Group Data Move Instructions Mnemonic Operation Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes 1 23456789 1 0 1 1 Ext. MOV -- -- -- -- 21 1010 DnDm MOV imm8,Dm imm8 → Dm -- -- -- -- 42 1010 DmDm <#8.
XVII - 17 Chapter 17 Appendices Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes 1 23456789 1 0 1 1 exten- sion PUSH .
Chapter 17 Appendices XVII - 18 Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes 1 23456789 1 0 1 1 Exten sion *1 d4 sign-extension *2 d7 sign-extension *3 d11 sign-extension NOT Dn NOT _ Dn → Dn= 00 32 0010 10Dn 0010 ASR Dn ASR Dn.
XVII - 19 Chapter 17 Appendices Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes 1 23456789 1 0 1 1 Exten- sion *1 d4 sign-extension *2 d7 sign-extension BGT label Bcc if((VF^NF)|ZF=0),PC+6+d11(label)+H → PC -- -- -- -- 63 / 4 0011 0001 <d11 .
Chapter 17 Appendices XVII - 20 Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes 1 23456789 1 0 1 1 Exten- sion TBNZ (abs8)bp,label if(mem8(abs8)bp=1),PC+8+d11(label)+H → PC 00 8 6/7 0001 1bp.
XVII - 21 Chapter 17 Appendices Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes 1 23456789 1 0 1 1 Exten- sion Contorl instructions REP imm3 REP *1 imm3-1 → RPC --- --- --- --- 32 0001 1rep 0010 *1 no repeat whn imm3=0, (rep: imm3-1) RTS RTS mem8(SP) → (PC).
Chapter 17 Appendices XVII - 22 Instruction Map 17-4 Instruction Map 0 0 NOP RTS MOV #8,(io8) RTI CMP #8,(abs8)/(abs12) POP An ADD #8,Dm MOVW #8,DWm MOVW #8,Am 1 JSR d12(label) JSR d16(label) MOV #8,(.
XVII - 23 Chapter 17 Appendices Instruction Map 0 0 TBZ (abs8)bp,d7 TBZ (abs8)bp,d11 1 TBNZ (abs8)bp,d7 TBNZ (abs8)bp,d11 2 CMP Dn,Dm 3 ADD Dn,Dm 4 TBZ (io8)bp,d7 TBZ (io8)bp,d11 5 TBNZ (io8)bp,d7 TBN.
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Chapter 18 Flash EEPROM 18.
Chapter 18 Flash EEPROM XVIII - 2 Overview 18-1 Overview 18-1-1 Overview The MN101CF77G is equivalent to MN101C77C except its Mask ROM is substituted with 128 KB of flash EEPROM. Operating voltage of MN101CF77G is as follows. MN101CF77G Operating voltage: V DD =2.
XVIII - 3 Chapter 18 Flash EEPROM Overview Figure 18-1-1 Memory Map in Internal Flash EEPROM Figure 18-1-1 shows a memory map in Internal flash EEPROM.
Chapter 18 Flash EEPROM XVIII - 4 Overview 18-1-2 Differences between Mask ROM version and EPROM version Table 18-1-1 shows differences between 8-bit microcontroller MN101C77C (Mask ROM version), MN101CF77G (EPROM version) .
XVIII - 5 Chapter 18 Flash EEPROM Pin Descriptions Figure18-2-1 Pin Configuration ( LQFP064-P-1414 ) 18-2 Pin Descriptions MN101CF77G (TOP VIEW) 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 RXD0A/SBI0A/.
Chapter 18 Flash EEPROM XVIII - 6 Electrical Characteristics 18-3 Electrical Characteristics *1 Applied to any 100 ms period. *2 Connect at least one bypass capacitor of 0.1 µF or larger between the power supply pin and the ground for latch-up prevention.
XVIII - 7 Chapter 18 Flash EEPROM Electrical Characteristics 18-3-2 Operating Conditions *1 V PP =V DD exept during Flash EEPROM program/erase. *2 Operating tempreture during programming should be within 0 °C to +50 °C . [ NORMAL mode : fs=fosc/2, SLOW mode : fs=fx/2 ] MI N T YP MA X fo s c = < 20.
Chapter 18 Flash EEPROM XVIII - 8 Electrical Characteristics *1 - Measured under conditions of no load, or power down on analog blocks. (Pull-up resistance should be unconnected.
XVIII - 9 Chapter 18 Flash EEPROM Reprogramming Flow 18-4 Reprogramming Flow Figure 18-4-1 shows the flow for reprogramming (erasing and programming) the flash EEPROM.
Chapter 18 Flash EEPROM XVIII - 10 PROM writer mode 18-5 PROM writer mode Figure 18-5-1 Fixing a Device on the Adapter Socket and the Position of No.1 Pin In PROM writer mode, the CPU is halted for Internal flash EEPROM to be programed. The microcontroller is inserted into a dedicated adaptor socket, which connects to a PROM writer.
XVIII - 11 Chapter 18 Flash EEPROM PROM writer mode Pin Configuration for Socket Adaptor Figure 18-5-2 Pin Configuration for Socket Adaptor MN101CF77G (TOP VIEW) 60 59 58 57 56 55 54 53 52 51 50 4.
Chapter 18 Flash EEPROM XVIII - 12 Onboard Serial Interface Programming Mode x Onboard serial writer (YDC MODEL: AF200) x Flash programming connectors or pins for target board.
XVIII - 13 Chapter 18 Flash EEPROM Onboard Serial Interface Programming Mode 18-6-2 Circuit Requirements for the Target Board (in Clock Synchronous Communication using the YDC Serial Writer) This section describes the circuit requirements for the target board for onboard serial programming with the serial interface 0 using YDC serial writer.
Chapter 18 Flash EEPROM XVIII - 14 Onboard Serial Interface Programming Mode This section describes each memory space of Flash EEPROM. Load Program Area Fixed User Program Area Security Code Branch In.
XVIII - 15 Chapter 18 Flash EEPROM Onboard Serial Interface Programming Mode Use of YDC serial writer x You must write the load program to this LSI before installed in the target board. The load program usually comes with onboard serial writer. x Erase block 0 (load program) is write/erase-protected in the hardware during onboard programming mode.
Chapter 18 Flash EEPROM XVIII - 16 Onboard Serial Interface Programming Mode Pins V PP : 5.0 V power supply (for Flash EEPROM) V DD : MN101CF77G: 2.7 V to 3.
XVIII - 17 Chapter 18 Flash EEPROM Onboard Serial Interface Programming Mode Use of PanaX serial writer (DWIRE programming) x You need not to write load program in advance and also be able to use all space of the Flash EEPROM as user program area. x V PP pin must supply 5.
Chapter 18 Flash EEPROM XVIII - 18 Onboard Serial Interface Programming Mode x To connect resistors in series with communication pins (NRST, P53, P54) When resistors are connected in series with communication pins, signal spectrum speed drops affected by the load capacity.
MN101C77C/F77G LSI User's Manual February, 2004 1st Edition Issued by Matsushita Electric Industrial Co., Ltd. © Matsushita Electric Industrial Co.
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