Benutzeranleitung / Produktwartung DS87C530 des Produzenten Maxim
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1 of 47 REV: 070505 Note: Some revisions of t his device may incorporate deviations from publis hed specificati ons known as errata. Multiple revisions of any device may be si multaneously available through various s ales channels. For information about devic e errata, cl ick here: www .
DS87C530/DS83C530 EPROM/ROM M icrocontrollers with Real-Time Clock 2 of 47 ORDERING INFORMATION PART TEMP RANGE MAX CLOCK SPEED (MHz) PIN-PACKAGE DS87C530 -QCL 0 ° C to +70 ° C 33 52 PLCC DS87C530 -.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 3 of 47 DETAILED DESCRI PTION The DS87C530/DS83C530 EPROM/ROM microcontrollers with a real-time clock (RTC) are 8051- compatible microcontrollers based on the Dallas Semic onductor high-speed core.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 4 of 47 Figure 1. Block D iagram PIN DESCRIPTION PIN PLCC TQFP NAME FUNCTION 52 45 V CC +5V Processo r Power Supply 1, 25 18, 46 GND Processor Dig ital Circuit Gr ound 29 22 V CC2 +5V RTC Supp ly.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 5 of 47 PIN DESCRIPTION ( continued) PIN PLCC TQFP NAME FUNCTION 38 31 PSEN Program Store-Enab le Output. T his active-low signal is a chip enable for optional external ROM m emory.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 6 of 47 PIN DESCRIPTION ( continued) PIN PLCC TQFP NAME FUNCTION 30 23 P2.0 (AD8) 31 24 P2.1 (AD9) 32 25 P2.2 (AD10) 33 26 P2.3 (AD11) 34 27 P2.4 (AD12) 35 28 P2.5 (AD13) 36 29 P2.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 7 of 47 COMPATIBILIT Y The DS87C530/DS83C530 are fully sta tic, CMOS 8051-compatible microc ontrollers designed for high performance. While rem aining familiar to 8051 users, th e devices have many new features.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 8 of 47 The relative time of two instructions mig ht be different in the new architectur e than it was previously .
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 9 of 47 Table 1. Special Func tion Register Locations * Function s not prese nt in the 80C52 ar e in bold. REGIST ER BIT 7 BIT 6 BIT 5 B IT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS P0 P0.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 10 of 47 Table 1. Special Func tion Regi ster Locations (continued) * Function s not prese nt in the 80C52 ar e in bold.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 11 of 47 automatically to occur once per s econd, once per minute, once per h our, or once pe r day. Enabling interrupts with no match will genera te an interrupt 256 times per second.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 12 of 47 12.5pF crystal uses more power, giving a shorter batter y backed life, but produces a more robust oscillator. Bit 6 in the RTC Trim register (TR I M; 96h) must be pro grammed to specify the crystal type for the oscillator.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 13 of 47 space SRAM is read/wr ite accessible and is memor y mapped. This on-chi p SRAM is reached by the MOVX instruction. It is not used for executable memo r y. The scratchpad area is 256 b ytes of register mapped RAM and is identical to the RAM found on th e 80C52.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 14 of 47 device will immediately jump to external program execution because program code from 4k B to 16kB (1000h–3FFFh) is no long er located on-chip. This could result in code misalignm ent and execution of an invalid instruction.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 15 of 47 The on-chip data area is software sel ectable using 2 bits in the Power Management Register at location C4h. This selection is dynamicall y programmable. Thus access to the on-c hip area becomes t ransparent to reach off- chip devices at the same addresses.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 16 of 47 Using a Stre tch value between 1 and 7 ca uses the microcontrolle r to stretch the rea d/write strobe and all related timing . Also, setup and hold times are increased by 1 clock when using an y Str etch greater than 0.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 17 of 47 POWER M ANAGEMENT Along with the standard Idle and power-dow n (Stop) modes of the standard 80C52, the DS87C530/DS83C530 provide a new Powe r Management Mode. This mode allows the processor to continue functioning, yet to sa ve power compared with full ope ration.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 18 of 47 CRYSTAL-LES S PMM A major component of power consumption in PMM is the cry stal amplifie r circuit. The DS87C530/DS83C530 allow the user to sw itch CPU operation to an internal ring oscillator and turn off the crystal a mplifier.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 19 of 47 Switchback To return to a 4-clock rat e from PMM, software c an simply select the CD1 and CD0 clock control b its to the 4 clocks per c ycle state. Ho wever, the DS87C530/DS83C530 provide several hardwa re altern atives for automa tic Switchback.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 20 of 47 Crystal/Ring Operation The DS87C530/DS83C530 allow software to choose the clock source as an independent selection from the instruction cycle rate. The us er can select crystal-based or ring oscillator-based operation under software control.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 21 of 47 Table 6. PMM Control and Status Bit Summary NAME LOCAT ION FUNCTION RESET WRITE AC CESS XT/ RG EXIF.3 Control. XT/ RG =1, run s from crystal or external clock; XT/ RG =0, runs f ro m internal ring oscillator.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 22 of 47 Figure 5. Inv oking and Clearing PMM WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 23 of 47 IDLE MODE Setting the lsb of the Po wer Control register (PCON; 87h) invokes the Idle mode. I dle will leave internal clocks, serial ports and timers running. Power co nsum ption drops because the CPU is not active.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 24 of 47 The ring oscillator runs at approx imatel y 2MHz to 4MHz but will not be a pre cise value. Do not c onduct real-time precision opera tions (inc luding serial communication) durin g this ring period.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 25 of 47 PERIPHER AL OVERVIEW The DS87C530/DS83C530 provide several of the most commonly needed periph eral functions in microcomputer-based s ystems.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 26 of 47 read the PFI fla g at WDCON.4. A PFI condition sets this bit to a 1. The flag is independent of the interrupt ena ble and software must manually clear it. If the PFI is enabled and the bandgap select bit (BGS) is se t, a PFI will bring the device out of Stop mode.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 27 of 47 There are fiv e control bits i n special function re gisters that affe ct the W atchdog Timer and two status flags that re port to the user.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 28 of 47 TIMED- A CCES S PROTECTI ON It is useful to protect certain SFR bits from an accidental write operation. The Timed-Access procedure stops an errant C PU from accidentall y changin g these bits.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 29 of 47 DS87C530 SECURI TY OPTIONS The DS87C530 employs a stand ard three-level lo ck that restricts viewing of the EPROM contents. A 64- byte Encry ption Arra y allows the author ized user to verify memory by presenting the data in encry pted form.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 30 of 47 Table 9. EPROM Prog ramming Modes MODE RST PSEN ALE/ PROG EA /VPP P2.6 P2.7 P3.3 P 3.6 P3.7 Program Code Data H L PL 12.75V L H H H H Verify Code Dat a H L H H L L L H H Program Encryption Array Address 0- 3Fh H L PL 12.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 31 of 47 Figure 7. EPROM Pro gramming Configuration ROM-SPECIFIC FE ATURES (DS8 3C530) The DS83C530 supports a subset of the EPROM features found on the DS87C530. SECURITY OPTION S Lock Bits The DS83C530 employs a lock that re stricts viewing of the ROM cont ents.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 32 of 47 DS83C530 R OM Verification The DS83C530 memory contents can be ve rified us ing a standard EPROM programmer. Th e memory address to be verified is placed on the pins shown in Figure 7, and the programming control pins ar e set to the levels shown in Table 9.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 33 of 47 ABSOLUTE M AXIMUM R ATINGS Voltage Ra nge on Any Pin Relative t o Ground… ……………… ……………… …………….
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 34 of 47 DC ELECTRIC AL CHARACTERIST ICS (continued) (V CC = 4.5V to 5. 5V, T A = -40°C t o +85° C.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 35 of 47 AC ELECTRIC AL CHARACTERIST ICS (Note 1) 33MHz VARIAB LE CLOCK PARAMETER SY MBOL MIN MAX MIN MAX UNITS External Osc illator 0 33 0 33 Oscillator Frequency E xternal C rystal 1/t CL CL 1 33 1 33 MHz ALE Pulse Wid th t LHL L 40 1.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 36 of 47 MOVX CH ARACTERISTICS USIN G STRETCH M EMORY C YCLES VARIABLE CLOCK PARAMETER SYM B OL MIN M AX UNITS STRETCH 1.5t CLCL -5 t MCS =0 Data Access ALE Pulse Width t LHLL2 2t CLCL -5 ns t MCS >0 0.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 37 of 47 MOVX CH ARACTERISTICS USIN G STRETCH M EMORY C YCLES (continued) M2 M1 M0 MOVX CYCLES t MCS 0 0 0 2 machine cy cles 0 .
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 38 of 47 EXPLAN ATION OF A C SYM BOLS In an effort to remain compatible with the original 8051 famil y, this device specifies the same parameters as such devices, using the same s ymbols.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 39 of 47 EXTERNA L PROGRAM MEM ORY READ CYCLE EXTERN A L D ATA MEMORY READ CYCLE t VALL2 WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 40 of 47 DATA MEMOR Y WRITE CYCLE DATA MEMORY WRITE W ITH STRETCH = 1 t AVL L2 WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 41 of 47 DATA MEMORY WRITE W ITH STRETCH = 2 EXTERNA L CLOCK DRIVE WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 42 of 47 SERIAL PORT MODE 0 TIMING WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 43 of 47 POWER-CYCLE TIMING EPROM PROGRAM MING AND VERIFICATION WAVEFORM S WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .100 Y .COM.TW WW W .
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 44 of 47 PACKAGE INFORM ATION (The package drawing(s) in this dat a sheet may n ot reflect th e most curren t specificati ons. For the latest pac kage outline information, go to ww w.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 45 of 47 PACKAGE INFORM ATION (continu ed) (The package drawing(s) in this dat a sheet may n ot reflect th e most curren t specificati ons. For the latest pac kage outline information, go to ww w.
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 46 of 47 PACKAGE INFORM ATION (continu ed) (The pac kage dr awing(s ) in this data sh eet m ay not ref lect the m ost c urrent spec ific ations. For the la test pac kage outline inf orm ation, go t o www .
DS87C530/D S83C 530 EP ROM/ROM Microc ontrol lers with Rea l-T ime Clock 47 of 47 Maxim/Dallas S emiconductor cannot assu me responsibility for use of a ny circuitry other than circuitry entirel y embodied i n a Ma xim/Dall as Se micond uctor pr oduct.
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