Benutzeranleitung / Produktwartung ADuC812 des Produzenten Analog Devices
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REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use.
REV. B ADuC812 –2– FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . .
REV. B –3– ADuC812 ADuC812BS Parameter V DD = 5 V V DD = 3 V Unit Test Conditions/Comments ADC CHANNEL SPECIFICATIONS DC ACCURACY 3, 4 Resolution 12 12 Bits Integral Nonlinearity ± 1/2 ± 1/2 LSB typ f SAMPLE = 100 kHz ± 1.5 LSB max f SAMPLE = 100 kHz ± 1.
REV. B –4– ADuC812–SPECIFICA TIONS 1, 2 ADuC812BS Parameter V DD = 5 V V DD = 3 V Unit Test Conditions/Comments DAC AC CHARACTERISTICS Voltage Output Settling Time 15 15 µ s typ Full-Scale Sett.
REV. B –5– ADuC812 ADuC812BS Parameter V DD = 5 V V DD = 3 V Unit Test Conditions/Comments DIGITAL OUTPUTS Output High Voltage (V OH ) 2.4 V min V DD = 4.5 V to 5.5 V I SOURCE = 80 µ A 4.0 2.6 V typ V DD = 2.7 V to 3.3 V I SOURCE = 20 µ A Output Low Voltage (V OL ) ALE, PSEN , Ports 0 and 2 0.
REV. B ADuC812 –6– PIN CONFIGURATION 5 2 51 50 49 48 43 42 41 40 4 7 46 45 44 1 4 15 16 17 18 19 20 21 2 2 23 24 25 26 1 2 3 4 5 6 7 8 9 10 13 12 11 39 38 37 36 35 34 33 32 31 30 29 28 27 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) P0.7/AD7 P0.6/AD6 P0.
REV. B ADuC812 –7– PIN FUNCTION DESCRIPTIONS Mnemonic Type Function DV DD P Digital Positive Supply Voltage, 3 V or 5 V Nominal AV DD P Analog Positive Supply Voltage, 3 V or 5 V Nominal C REF I Decoupling Input for On-Chip Reference. Connect 0.1 µ F between this pin and AGND.
REV. B ADuC812 –8– Mnemonic Type Function PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses.
REV. B ADuC812 –9– ARCHITECTURE, MAIN FEATURES The ADuC812 is a highly integrated true 12-bit data acquisition system. At its core, the ADuC812 incorporates a high- perfor- mance 8-bit (8052-Compatible) MCU with on-chip reprogrammable nonvolatile Flash program memory control- ling a multichannel (8-input channels), 12-bit ADC.
REV. B ADuC812 –10– OVERVIEW OF MCU-RELATED SFR s Accumulator SFR ACC is the Accumulator register and is used for math opera- tions including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for accumulator-specific instructions refer to the Accumulator as A.
REV. B ADuC812 –11– SPECIAL FUNCTION REGISTERS All registers except the program counter and the four general purpose register banks, reside in the special function register (SFR) area. The SFR registers include control, configuration and data registers that provide an interface between the CPU and other on- chip peripherals.
REV. B ADuC812 –12– ADC CIRCUIT INFORMATION General Overview The ADC conversion block incorporates a fast, 8-channel, 12-bit, single supply A/D converter. This block provides the user with multichannel mux, track/hold, on-chip reference, calibration features and A/D converter.
REV. B ADuC812 –13– ADCCON1 – (ADC Control SFR #1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as detailed below. SFR Address: EFH SFR Power-On Default Value: 20H Table III. ADCCON1 SFR Bit Designations Bit Name Description ADCCON1.
REV. B ADuC812 –14– ADCCON2 – (ADC Control SFR #2) The ADCCON2 register controls ADC channel selection and conversion modes as detailed below. SFR Address: D8H SFR Power On Default Value: 00H I C D AA M DV N O C CV N O C S3 S C2 S C1 S C0 S C Table IV.
REV. B ADuC812 –15– Driving the A/D Converter The ADC incorporates a successive approximation (SAR) archi- tecture involving a charge-sampled input stage. Figure 7 shows the equivalent circuit of the analog input section. Each ADC conversion is divided into two distinct phases as defined by the position of the switches in Figure 7.
REV. B ADuC812 –16– ground, no amplifier can deliver signals all the way to ground when powered by a single supply. Therefore, if a negative supply is available, you might consider using it to power the front-end amplifiers.
REV. B ADuC812 –17– core. This mode allows the ADuC812 to capture a contiguous sample stream at full ADC update rates (200 kHz). A typical DMA Mode configuration example. To set the ADuC812 into DMA mode a number of steps must be followed. 1. The ADC must be powered down.
REV. B ADuC812 –18– the gain calibration coefficient is divided into ADCGAINH (6 bits) and ADCGAINL (8 bits).The offset calibration coefficient c o m pen- sates for dc offset errors in both the ADC and the input signal. Increasing the offset coefficient compensates for positive offset, and effectively pushes the ADC Transfer Function DOWN.
REV. B ADuC812 –19– Using the Flash/EE Program Memory T his 8K Byte Flash/EE Program Memory array is mapped into the lower 8K bytes of the 64K bytes program space addres- sa ble by the ADuC812 and will be used to hold user code in typical applications.
REV. B ADuC812 –20– ECON—Flash/EE Memory Control SFR This SFR acts as a command interpreter and may be written with one of five command modes to enable various read, pro- gram and erase cycles as detailed in Table VII: Table VII.
REV. B ADuC812 –21– USER INTERFACE TO OTHER ON-CHIP ADuC812 PERIPHERALS The following section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given.
REV. B ADuC812 –22– Using the D/A Converter The on-chip D/A converter architecture consists of a resistor string DAC followed by an output buffer amplifier, the func- tional equivalent of which is illustrated in Figure 18. Details of the actual DAC architecture can be found in U.
REV. B ADuC812 –23– SOURCE/SINK CURRENT – mA 3 0 5 10 15 OUTPUT VOLTAGE – V 2 1 0 Figure 21. Source and Sink Current Capability with V REF = V DD = 3 V To drive significant loads with the DAC outputs, external buff- ering may be required, as illustrated in Figure 22.
REV. B ADuC812 –24– WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset within a reasonable amount of time if the ADuC812 enters an erroneous state, possibly due to a programming error. The Watchdog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR.
REV. B ADuC812 –25– POWER SUPPLY MONITOR As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies (AV DD and DV DD ) on the ADuC812. It will indicate when either power supply drops below one o f fi ve user-selectable voltage trip points from 2.
REV. B ADuC812 –26– SERIAL PERIPHERAL INTERFACE The ADuC812 integrates a complete hardware Serial Peripheral Interface (SPI) on-chip. SPI is an industry standard s yn chronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.
REV. B ADuC812 –27– Table XII. SPICON SFR Bit Designations (continued) Bit Name Description 1 SPR1 SPI Bit-Rate Select Bits. 0 SPR0 These bits select the SCLOCK rate (bit-rate) in Master Mode as follows: SPR1 SPR0 Selected Bit Rate 00f OSC /4 01f OSC /8 10f OSC /32 1 1 fosc/64 In SPI Slave Mode, i.
REV. B ADuC812 –28– I 2 C-COMPATIBLE INTERFACE The ADuC812 supports a 2-wire serial interface mode which is I 2 C compatible. The I 2 C-compatible interface shares its pins with the on-chip SPI interface and therefore the user can only enable one or the other interface at any given time (see SPE in SPICON previously).
REV. B ADuC812 –29– 8051-COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary peripheral circuits that are also available to the user on-chip. These remaining functions are fully 8051-compatible and are controlled via standard 8051 SFR bit definitions.
REV. B ADuC812 –30– User configuration and control of all Timer operating modes is achieved via three SFRs, namely: TMOD, TCON: Control and configuration for Timers 0 and 1.
REV. B ADuC812 –31– 1 F T1 R T0 F T0 R T1 E I 1 1 T I 1 0 E I 1 0 T I 1 NOTE 1 These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins. Table XVII.
REV. B ADuC812 –32– Mode 2 (8-Bit Timer/Counter with Auto Reload) Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 28. Overflow from TL 0 not only sets TF0, but also reloads TL0 with the contents of T H0 , which is preset by software.
REV. B ADuC812 –33– T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default Value 00H Bit Addressable Yes 2 F T2 F X EK L C RK L C T2 N E X E2 R T2 T N C2 P A C Table XVIII. T2CON SFR Bit Designations Bit Name Description 7 TF2 Timer 2 Overflow Flag.
REV. B ADuC812 –34– Timer/Counter Operation Modes The following paragraphs describe the operating modes for t imer / counter 2. The operating modes are selected by bits in the T 2C O N SFR as shown in Table XIX.
REV. B ADuC812 –35– UART SERIAL INTERFACE T he serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can c om - mence reception of a second byte before a previously received byte has been read from the receive register.
REV. B ADuC812 –36– Mode 0: 8-Bit Shift Register Mode Mode 0 is selected by clearing both the SM0 and SM1 bits in t he S FR SCON. Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF.
REV. B ADuC812 –37– Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate a n d the value of SMOD as follows: Modes 1 and 3 Baud Rate = (2 SMOD /32) × ( Timer 1 Overflow Rate ) The Timer 1 interrupt should be disabled in this application.
REV. B ADuC812 –38– INTERRUPT SYSTEM The ADuC812 provides a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three Interrupt-related SFRs. IE: Interrupt Enable Register.
REV. B ADuC812 –39– IE2: Secondary Interrupt Enable Register SFR Address A9H Power-On Default Value 00H Bit Addressable No — — ——— — I M S P EI S E Table XXV. IE2 SFR Bit Designations Bit Name Description 7 — Reserved for Future Use.
REV. B ADuC812 –40– ADuC812 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design consider- ations that must be addressed when integrating the ADuC81 2 into any hardware system. Clock Oscillator The clock source for the ADuC812 can come either from an external source or from the internal clock oscillator.
REV. B ADuC812 –41– If access to more than 64K bytes of RAM is desired, a feature unique to the ADuC812 allows addressing up to 16M bytes of external RAM simply by adding an additional latch as illus trated in Figure 39. LATCH ADuC812 RD P2 ALE P0 WR LATCH SRAM OE A8 – A15 A0 – A7 D0 – D7 (DATA) WE A16 – A23 Figure 39.
REV. B ADuC812 –42– As an alternative to providing two separate power supplies, t h e user can help keep AV DD quiet by placing a small series resistor and/or ferrite bead between it and DV DD , and then decoupling AV DD separately to ground. An e x a m p le o f t h is c o n figuration is shown in Figure 44 .
REV. B ADuC812 –43– Grounding and Board Layout Recommendations As with all high resolution data converters, special attention m ust be paid to grounding and PC board layout of ADuC81 2-based designs in order to achieve optimum performance from the ADCs and DAC.
REV. B ADuC812 –44– C1+ V+ C1 – C2+ C2 – V – T2OUT R2IN V CC GND T1OUT R1IN R1OUT T1IN T2IN R2OUT ADM202 DV DD 27 34 33 31 30 29 28 39 38 37 36 35 32 40 47 46 44 43 42 41 52 51 50 49 48 45 DV DD 1k DV DD 1k 2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN) DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) 11.
REV. B ADuC812 –45– Note that the serial port debugger is fully contained on the ADuC812 device, (unlike “ROM monitor” type debuggers) and therefore no external memory is needed to enable in-system debug sessions.
REV. B ADuC812 –46– (AV DD = DV DD = 3.0 V or 5.0 V 10%. All specifications T A = T MIN to T MAX unless otherwise noted.) 12 MHz Variable Clock Parameter Min Typ Max Min Typ Max Unit Figure CLOCK INPUT (External Clock Driven XTAL1) t CK XTAL1 Period 83.
REV. B ADuC812 –47– 12 MHz Variable Clock Parameter Min Max Min Max Unit Figure EXTERNAL PROGRAM MEMORY t LHLL ALE Pulsewidth 127 2t CK –4 0 n s 5 2 t AVLL Address Valid to ALE Low 43 t CK –4 .
REV. B ADuC812 –48– 12 MHz Variable Clock Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY READ CYCLE t RLRH RD Pulsewidth 400 6t CK – 100 ns 53 t AVLL Address Valid after ALE Low 43 t.
REV. B ADuC812 –49– 12 MHz Variable Clock Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY WRITE CYCLE t WLWH WR Pulsewidth 400 6t CK – 100 ns 54 t AVLL Address Valid after ALE Low 43 .
REV. B ADuC812 –50– 12 MHz Variable Clock Parameter Min Typ Max Min Typ Max Unit Figure UART TIMING (Shift Register Mode) t XLXL Serial Port Clock Cycle Time 1.
REV. B ADuC812 –51– Parameter Min Max Unit Figure I 2 C-COMPATIBLE INTERFACE TIMING t L SCLOCK Low Pulsewidth 4.7 µ s5 6 t H SCLOCK High Pulsewidth 4.0 µ s5 6 t SHD Start Condition Hold Time 0.6 µ s5 6 t DSU Data Setup Time 100 ns 56 t DHD Data Hold Time 0 0.
REV. B ADuC812 –52– Parameter Min Typ Max Unit Figure SPI MASTER MODE TIMING (CPHA = 1) t SL SCLOCK Low Pulsewidth 330 ns 57 t SH SCLOCK High Pulsewidth 330 ns 57 t DAV Data Output Valid after SCL.
REV. B ADuC812 –53– Parameter Min Typ Max Unit Figure SPI MASTER MODE TIMING (CPHA = 0) t SL SCLOCK Low Pulsewidth 330 ns 58 t SH SCLOCK High Pulsewidth 330 ns 58 t DAV Data Output Valid after SCL.
REV. B ADuC812 –54– Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING (CPHA = 1) t SS SS to SCLOCK Edge 0 ns 59 t SL SCLOCK Low Pulsewidth 330 ns 59 t SH SCLOCK High Pulsewidth 330 ns 59 t D.
REV. B ADuC812 –55– Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING (CPHA = 0) t SS SS to SCLOCK Edge 0 ns 60 t SL SCLOCK Low Pulsewidth 330 ns 60 t SH SCLOCK High Pulsewidth 330 ns 60 t D.
REV. B –56– C00208–0–10/01(B) PRINTED IN U.S.A. ADuC812 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 52-Lead Plastic Quad Flatpack (S-52) TOP VIEW (PINS DOWN) PIN 1 1 40 52 26 27 13 14 39 SQ 0.557 (14.15) 0.537 (13.65) 0.398 (10.11) 0.
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