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Reference Number: 323370-001 Intel ® Xeon ® Processor 5600 Series Datasheet, Volume 2 March 2010.
2 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNE CTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPL IED, BY ESTOPPEL OR O THERWISE, TO ANY INTELLECTUAL PROPER TY RIGHTS IS GRANTED BY THIS DOCUMENT .
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 3 Contents 1I n t r o d u c t i o n ......... ........... .......... ........... .......... ........... .......... ........... ........... .......... ...... 7 1.1 References ........... .......
4 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 2.11.6 MC_CHANNEL_0_ SCHEDULER_PARAMS MC_CHANNEL_1_SC HEDULER_PARAMS MC_CHANNE L_2_SCHED ULER_PARAMS............ ............. .......... ........... ...... 52 2.11.7 MC_CHANNEL_0_PAGETA BLE_PARAMS2 MC_CHANNEL_1_PAGETABLE_PA RAMS2 MC_CHANNE L_2_PAGETABL E_PARAMS2 .
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 5 Figures Tables 1-1 References ........... .......... ........... .......... ........... .......... ........... .......... ........... .......... 7 2-1 Functions Spec ifically Handled by the Processor .
6 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 Revision History § Revision Description Date -001 Initial release. March 2010.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 7 Introduction 1 Introduction The Intel ® Xeo n ® processor 5600 series is the next generation DP server/workstation processor based on the Intel ® Xe o n ® Processor 5500 Series architecture, and utilizing 32 nm process technology .
Introduction 8 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 9 Register Description 2 Register Description The processor supports PCI configuration space accesses using the mechanism denoted as Configura.
Register Description 10 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 2.2 Platform Configuration Structure The processor contains 6 PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI bus assigned for the processor socket.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 11 Register Description DID of 2DA0h. Device 4, Function 1 cont ains the address registers for Integrated Memory Controller Channel 0 and resides at DID of 2DA1h. Device 4, Function 2 contains the rank registers for Integr ated Memory Controller Channel 0 and resides at DID of 2DA2h.
Register Description 12 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 Notes: 1. Applies only to processors with two Intel QPI links. 2. Applies only to process ors supporting sparing, mirroring and scrub bing RAS features.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 13 Register Description 2.4 Detailed Configuration Space Maps Table 2-2. Device 0, Function 0: Generic Non-core Reg isters DID VID 00h DESIRED.
Register Description 14 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 Table 2-3. Device 0, Function 1: System Address De coder Registers DID VID 00h SAD_DRAM_RULE_0 80h PCISTS PCICMD 04h S.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 15 Register Description Table 2-4. Device 2, Function 0: Intel QPI Link 0 Registers DID VID 00h 80h PCISTS PCICMD 0 4h 84h CCR RID 08h 88h HDR.
Register Description 16 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 Table 2-5. Device 2, Function 1: Intel QPI Physical 0 Registers DID VID 00h QPI_0_PH_PIS 80h PCISTS PCICMD 04h 84h CCR.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 17 Register Description Table 2-6. Device 2, Function 2: Mirror Port Link 0 Registers DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HD.
Register Description 18 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 Table 2-7. Device 2, Function 3: Mirror Port Link 1 Registers DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HD.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 19 Register Description Note: 1. Applies only to processors with two Intel QPI links. Table 2-8.
Register Description 20 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 Table 2-9. Device 2, Function 5: Intel QPI Physical 1 Registers DID VID 00h QPI_1_PH_PIS 80h PCISTS PCICMD 04h 84h CCR.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 21 Register Description Table 2-10. Device 3, Function 0: Integr ated Memory Controller Regi sters DID VID 00h 80h PCISTS PCICMD 04h 84h CCR R.
Register Description 22 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 Table 2-11. D evice 3, Function 1: Targ et Address Decoder Registe rs DID VID 00h T AD_DRAM_RULE_0 80h PCISTS PCICMD 0.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 23 Register Description Note: 1. Applies only to process ors supporting registere d DIMMs. Table 2-12.
Register Description 24 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 Table 2-13. D evice 3, Function 4: Integrated Me mory Controller Test Registers DID VID 00h MC _TEST_PH_PIS 80h PCISTS.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 25 Register Description Table 2-14. Device 4, Fun ction 0: Inte g rated Memory Controller Channel 0 Control Registers DID VID 00h MC_CHANNEL_0.
Register Description 26 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 Table 2-15. D evice 4, Function 1: Inte grated Memory Cont roller Channel 0 Address Registers DID VID 00h MC_SAG_CH0_0.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 27 Register Description Table 2-16. Device 4, Fun ction 2: Inte g rated Memory Controller Channel 0 Rank Registers DID VID 00h MC_RIR_WA Y_CH0.
Register Description 28 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 Table 2-17. D evice 4, Function 3: Inte grated Memory Cont roller Channel 0 Thermal Control Re gisters DID VID 00h MC_.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 29 Register Description Table 2-18. Device 5, Fun ction 0: Inte g rated Memory Controller Channel 1 Control Registers DID VID 00h MC_CHANNEL_1.
Register Description 30 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 Table 2-19. D evice 5, Function 1: Inte grated Memory Cont roller Channel 1 Address Registers DID VID 00h MC_SAG_CH1_0.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 31 Register Description Table 2-20. Device 5, Fun ction 2: Inte g rated Memory Controller Channel 1 Rank Registers DID VID 00h MC_RIR_WA Y_CH1.
Register Description 32 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 Table 2-21. D evice 5, Function 3: Inte grated Memory Cont roller Channel 1 Thermal Control Re gisters DID VID 00h MC_.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 33 Register Description Table 2-22. Device 6, Fun ction 0: Inte g rated Memory Controller Channel 2 Control Registers DID VID 00h MC_CHANNEL_2.
Register Description 34 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 Table 2-23. D evice 6, Function 1: Inte grated Memory Cont roller Channel 2 Address Registers DID VID 00h MC_SAG_CH2_0.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 35 Register Description Table 2-24. Device 6, Fun ction 2: Inte g rated Memory Controller Channel 2 Rank Registers DID VID 00h MC_RIR_WA Y_CH2.
Register Description 36 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 2.5 PCI Standard Registers These registers appear in every function for every device.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 37 Register Description 2.5.1 DID - Device Identification R egister This 16-bit register combined with the V e ndor Identification register uniquely identifies the Function within the processor .
Register Description 38 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 defined and is implementation dependent. Th is does not result in all of the power savings of a reduced number of core product, but does save more power than even the deepest sleep state .
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 39 Register Description 2.7 SAD - System Address Decoder Registers 2.7.1 SAD_M CSEG_BASE Global register for MCSEG address space. These are designed to look just like the cores SMRR type registers.
Register Description 40 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 2.7.4 SAD_MESEG_MASK Register for ME stolen r ange address space. Th ey are designed t o look just like the core SMRR type registers.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 41 Register Description 2.8.2 QPI_RMT_QPILP1_STAT_L0 QPI_RMT_QPILP1_STAT_L1 R emote’ s Intel QPI Parameter 1 V alue register . 2.8.3 MIP_PH_CTR_L0 MIP_PH_CTR_L1 Mirror P ort Physical Layer Control R egister .
Register Description 42 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 2.8.4 MIP_PH_PRT_L0 MIP_PH_PRT_L1 Mirror Port periodic retraining timing register .
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 43 Register Description 2.9.1 MC_SMI_DIMM_ERROR_STATUS SMI DIMM error threshold overflow status register . This bit is set when the per-DIMM error counter exceeds the specified threshold. The bit is reset by BIOS.
Register Description 44 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 2.9.3 MC_MAX_DOD Defines the MAX number of DIMMS, RANK S, BANKS, ROWS , COLS among all DIMMS populating the three channels. The Memory Init logic uses this register to cycle through all the memory addresses writing all 0's to initialize all locations.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 45 Register Description 2.9.4 MC_RD_CRDT_INIT These registers contain the initial read cred its available for issuing memory reads. T AD read credit counters are loaded with the corre sponding values at reset and anytime this register is written.
Register Description 46 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 2.9.5 MC_SCRUBADDR_HI This register pair contains part of the address of the last patrol scrub request issued. When running memtest, the failing address is logged in this register on memtest errors.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 47 Register Description 2.10.3 MC_SSRSTATUS Provides the status of the operation specified in MC_SSRCONTROL.
Register Description 48 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 2.11.2 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A MC_CHANNEL_2_RANK_TIMING_A This register contains par ameters that spec ify the rank timing used. All par ameters are in DCLK.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 49 Register Description 22:19 RW 0 tsrWrTRd. Minimum delay between a write followed by a read to the same ran k . 0000: 10 0001: 11 0010: 12 0011: 13 0100: 14 0101: 15 0110: 16 0111: 17 1000: 18 1001: 19 1010: 20 1011: 21 1100: 22 1101: 23 1110: 24 1111: 25 18:15 RW 0 tddRdTWr.
Register Description 50 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 2.11.3 MC_CHANNEL_0_REFRESH_TIMING MC_CHANNEL_1_REFRESH_TIMING MC_CHANNEL_2_REFRESH_TIMING This register contains parameters that specify th e refresh timings. Units are in DCLK.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 51 Register Description 2.11.4 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_2_CKE_TIMING This register contains parameters that spec ify the CKE timings. All units are in DCLK. 2.
Register Description 52 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 2.11.6 MC_CHANNEL_0_ SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULE R_PARAMS MC_CHANNEL_2_SCHEDULE R_PARAMS These are the par ameters used to control parameters within the scheduler .
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 53 Register Description 2.12 Memory Thermal Control 2.12.1 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1 MC_THERMAL_STATUS2 Status registers for the thermal throttling logic for each channel.
Register Description 54 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 2.12.3 MC_DDR_THERM1_COMMAND0 MC_DDR_THERM1_COMMAND1 MC_DDR_THERM1_COMMAND2 This register contains the command portion of the DDR_THERM2# pin functionality (i.e. what an assertion of the pin does).
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 55 Register Description 2.12.5 MC_DDR_THERM1_STATUS0 MC_DDR_THERM1_STATUS1 MC_DDR_THERM1_STATUS2 This register contains the status portion of the DDR_THERM2# pin functionality (that is, what is happening or has happened with respect to the pin).
Register Description 56 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 57 Functional Description 3 Functional Description This chapter describes the functional diff erences between the Intel X eon processor 5500 series and Intel Xeon processor 5600 series.
Functional Description 58 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 3.2 Supported RDIMM Memory Configurations 3.2.1 RDIMM 1.5 V Configurations Notes: 1. The Intel X eon processor 5600 series supports all Intel Xeo n processor 5500 series memory confi gurations.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 59 Functional Description 3.2.2 RDIMM 1.35 V Configurations Notes: 1. The Intel Xe on processor 5600 series supports all timings defined by the JEDEC standard. 2. All channels in a system will ru n at the fastest common frequency.
Functional Description 60 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 1. The Intel Xeon pro cessor 5600 series supports all Intel X eon processor 5500 series POR memory configurations. 2. Any combination of x8 and x16 UDIMMs, wi th 1Gb or 2Gb DRA M density, is supported.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 61 Functional Description 3.3.2 UDIMM 1.35V Configurations Notes: 1. The Intel Xe on processor 5600 series supports all timings defined by the JEDEC standard. 2. All channels in a system will ru n at the fastest common frequency.
Functional Description 62 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 3.5 Memory Error Signaling 3.5.1 Enabling SMI/NMI for Memory Corrected Errors The MC_SMI_CNTRL registe r has enables for SMI and NMI interrupts. Only one should be set.
Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2 63 Functional Description 3.7 2X Refresh The Intel X eon processor 5600 series supports 2X refresh via two mechanisms.
Functional Description 64 Intel ® Xeon ® Processor 5600 Series Datasheet Volume 2.
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