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Document Number: 316704-001 Intel ® Core TM 2 Duo processor and Mobile Intel ® GME965 Express Chipset Development Kit User Manual June 2007.
2 316704-001 / Developm ent Kit Use r’s Manual INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNE CTION WITH INTEL® PRODUCTS . NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
316704-001 / Developm ent Kit Us er’s Manual 3 Contents 1 About This Manual ............................................................................................6 1.1 Content Overview ..........................................................
4 316704-001 / Developm ent Kit Use r’s Manual Figures Figure 1. Developme nt Board Block Diagram....................................................... 24 Figure 2. Development Boar d Component Lo cations ...........................................
316704-001 / Developm ent Kit Us er’s Manual 5 Revision History Document Number Revision Number Description Revision Date 316704 001 Initial publi c release.
About This Manual 6 316704-001 / Developm ent Kit Use r’s Manual 1 About This Manual This user’s manual describes the use of the Intel ® Core TM 2 Duo processor and Mobile Intel ® GME965 Express Chipset development kit. Thi s manual has been written for OEMs, system evaluators, and embedded syst em developers.
About This Manual 316704-001 / Developm ent Kit Us er’s Manual 7 Table 1. Text Conventions Notation Defini tion # The pound symbol (#) appended to a si gnal name indicates that the signal is active low. (e.g., PRSNT1#) Variables Variables are shown in italics.
About This Manual 8 316704-001 / Developm ent Kit Use r’s Manual 1.3 Glossary of Terms and Acronyms Table 2 defines conventions and terminol ogy used throughout this document. Table 2. Terms and Acronyms Term/Acronym Definition Aggressor A network that transmits a coupled signal to another network.
About This Manual 316704-001 / Developm ent Kit Us er’s Manual 9 Term/Acronym Definition manufacturer’s conditions required for AC timing specifications; i.e., ringback, etc.) and the output pin of the driving agent crossing the switching voltage when the driver is driving a test load used to specify the driver’s AC timings.
About This Manual 10 316704-001 / Developm ent Kit Use r’s Manual Term/Acronym Definition System Bus The System Bus is the mi croprocessor bus of the processor. Setup Window The time between the beginni ng of Setup to Clock (TSU_MIN) and the arrival of a valid clock edge.
About This Manual 316704-001 / Developm ent Kit Us er’s Manual 11 Acronym Definition BIOS Basic Input/Output System CK-SSCD Spread Spectr um Differential Clock CMC Common Mode Choke CMOS Complementa.
About This Manual 12 316704-001 / Developm ent Kit Use r’s Manual Acronym Definition LOM LAN on Motherboard LPC Low Pin Count LS Low-speed. Refers to USB LVDS Low Voltage Differential Signaling mBGA.
About This Manual 316704-001 / Developm ent Kit Us er’s Manual 13 Acronym Definition VREG Voltage Regulator XDP eXtended Debug Port 1.4 Support Options 1.4.1 Electronic Support Systems Intel’s web site ( http://www.intel.com/ ) provide s up-to -date techn ical informa tion and product support.
About This Manual 14 316704-001 / Developm ent Kit Use r’s Manual Intel Literature Fulfi lment Center P.O. Box 5937 Denver, Colorado 80217-9808 USA Email a request to: intelsupport@hibbertgroup.
Getting Started 316704-001 / Developm ent Kit Us er’s Manual 15 2 Getting Started This chapter identifies the development ki t’s key components, features and specifications.
Getting Started 16 316704-001 / Developm ent Kit Use r’s Manual Development Board Implementation Comments PCI Express* Three x1 connectors One x16 connector Revision 1.1 compliant There are Five x1 PCI Express* slots but slots 2 and 4 are not intended for use with PCI Express* add-in cards.
Getting Started 316704-001 / Developm ent Kit Us er’s Manual 17 Development Board Implementation Comments Power Management ACPI Compliant S0 – Power On S3 – Suspend to RAM S4 – Suspend to Disk S5 – Soft Off M0 – All Wells powered M1 – Main Well down.
Getting Started 18 316704-001 / Developm ent Kit Use r’s Manual Note: While every care was taken to ensure the latest versions of drivers were provi ded on the enclosed CD at time of publicati on, newer revisions may be avail able. Updated drivers for Intel components can be found at: http://developer.
Getting Started 316704-001 / Developm ent Kit Us er’s Manual 19 VGA Monitor: Any standard VG A or multi-resolution monitor may be used. The se tup instructions in this chapter assume the use of a standard VGA monitor, TV, or fl at panel monitor. Keyboard: The development board can support either a PS/2 or USB style keyboard.
Getting Started 20 316704-001 / Developm ent Kit Use r’s Manual Other Devices and Adapters: The development board functions much like a standard desktop computer motherboard. Most PC-compatible peripherals can be attached and configured to work with the development board.
Getting Started 316704-001 / Developm ent Kit Us er’s Manual 21 Note: Ensure that the processor has been locked into the socket by turning the socket screw fully clockwise. Note: For pro per insta llation of the CPU therma l solution, ple ase refe r to Appendix A 5.
Theory of Operation 22 316704-001 / Developm ent Kit Use r’s Manual 3 Theory of Operation 3.1 Block Diagram Figure 1. Development Board Block Diagram 3.
Theory of Operation 316704-001 / Developm ent Kit Us er’s Manual 23 chassis. Internal and rear panel system I/O connectors are described i n Section 3.
Theory of Operation 24 316704-001 / Developm ent Kit Use r’s Manual • SDVO interface via PCI Express* x16 connector provides maximum displ ay flexibility o Can drive up to two display outputs 3.4.1.1 System Memory The development board supports DDR2 533/667 main memory.
Theory of Operation 316704-001 / Developm ent Kit Us er’s Manual 25 3.4.1.4 PCI Express x16 Slot The development board provides access to one x16 PCI Express* connector. Any industry standard x1 or x16 PCI Express* video adapter may be used with this interface .
Theory of Operation 26 316704-001 / Developm ent Kit Use r’s Manual 3.4.2.3 On-Board LAN The development board has one RJ-45 interface – at connector J5A1 - through which 10/100/1000 ethernet is available. The ethernet MAC is located i n the ICH8-M and the PHY is located externally in the 82566MM LAN Connect Interface (LCI) device.
Theory of Operation 316704-001 / Developm ent Kit Us er’s Manual 27 connector at J5A1. Four ports are routed to USB front panel headers at J6H3 and J6H4. The last is routed to the PCI-Express* docking connector at J9C1. There are Five UHCI Host Controllers and tw o EHCI Host Controllers.
Theory of Operation 28 316704-001 / Developm ent Kit Use r’s Manual Table 7. BIOS Location Strapping Options ICH8-M Signal GNT#0 SPI_CS1# BIOS Location 0 1 SPI 1 0 PCI 1 1 LPC (Default) Note: GNT#0 is configur able via jump er J8E2 . Further details on its loca tion can be found in Section 4.
Theory of Operation 316704-001 / Developm ent Kit Us er’s Manual 29 3.4.3 POST Code Debugger A Port 80-83 Add-in card can be plugged i nto to the development board at the TPM header (J9A1). This card decodes the LPC bus BIOS POST codes and displays them on four 7-segment LED displays.
Theory of Operation 30 316704-001 / Developm ent Kit Use r’s Manual State Description G0/S0/C3 Deep Sleep: DPSLP# signal active G0/S0/C4 Deeper Sleep: DPRSLP# signal active G1/S3 Suspend To RAM (all switched rails are turned off) G1/S4 Suspend To Disk G2/S5 Soft Off G3 Mechanical Off Table 10.
Theory of Operation 316704-001 / Developm ent Kit Us er’s Manual 31 Table 11. Sleep Signals and M-State Definition Signal SLP_S3# SLP_S4# SLP_S5# S4_STATE# SLP_M# S0/M0 High High High High High S3/M.
Theory of Operation 32 316704-001 / Developm ent Kit Use r’s Manual Table 12. Development Board Voltage Rails Component / Interface Voltage Plane Supply Rail Reference Designator CPU VR 5V +V5S +V5S.
Theory of Operation 316704-001 / Developm ent Kit Us er’s Manual 33 Component / Interface Voltage Plane Supply Rail Reference Designator GMCH 1.8V +V1.8 +V1.8_GMCH R5D1 GMCH 1.8V +V1.8_GMCH +V1.8_SM_CK R5D2 GMCH 1.8V +V1.8 +V1.8_TXLVDS R5U25 GMCH 1.
Theory of Operation 34 316704-001 / Developm ent Kit Use r’s Manual Component / Interface Voltage Plane Supply Rail Reference Designator Memory 1.8V +V1.8 +V1.8_DIMM1 R5B10 Memory 3.3V +V3.3M +V3.3M_DIMM0 R4C1 (0.022 Ω ) Memory 3.3V +V3.3M +V3.3M_DIMM1 R4B26 (0.
Theory of Operation 316704-001 / Developm ent Kit Us er’s Manual 35 Component / Interface Voltage Plane Supply Rail Reference Designator Panel LVDS 5V +V5S +V3.3S_LVDS_DDC R6U9* CK505 3.3V +V3.3M_CK505 VDD_CK505 R5G11 CK505 3.3V +V3.3S +V3.3S_DB800 R7C10 CK505 0.
Theory of Operation 36 316704-001 / Developm ent Kit Use r’s Manual Component / Interface Voltage Plane Supply Rail Reference Designator System ATX +V5A +V5_ATX R4J1* System ATX +V3.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 37 4 Hardware Reference This sec tion pr ovides r eferen ce inform ation on t he hard ware, inc luding loc ations of development board components, connector pinout informati on and jumper settings.
Hardware Reference 38 316704-001 / Developm ent Kit Use r’s Manual Table 13. Development Board Component Location Legend Reference Designator Function BT5H1 CMOS Battery J1C1 Reserved J1D1 XDP Conne.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 39 Reference Designator Function J7J4 PATA Connector J8A1 Reserved J8A2 Reserved J8B3 PCI Slot 3 J8B4 PCI Express Slot 3 J8D1 PCI Expr.
Hardware Reference 40 316704-001 / Developm ent Kit Use r’s Manual Figure 3. Back Panel Connector Locations n o p q r s t u Table 14. Back Panel Connector Definitions Item Description Ref Des Item D.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 41 Figure 4. D-Connector to Component Video Cable Figure 5. D-Connector to Composite Video Cable Figure 6. D-Connector to S-Video Cable 4.3 Configuration Settings Note: Do not move jumpers with the power on.
Hardware Reference 42 316704-001 / Developm ent Kit Use r’s Manual The unsupported jumpers must remain in their default posi tion or the operation of the development board is unpredictabl e. The development board is shipped wi th the jumpers and switches shunted in the default locati ons.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 43 Reference Designator Function Default Setting Optional Setti ng Override For each VID signal IN: Tied to logic low OUT: Tied to log.
Hardware Reference 44 316704-001 / Developm ent Kit Use r’s Manual Reference Designator Function Default Setting Optional Setti ng J3J1 Reserved OUT Do not alter jumper setting J3J2 Reserved OUT Do .
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 45 Reference Designator Function Default Setting Optional Setti ng H8 Programming NMI enabled programming J9H3 KBC Disable OUT: Normal operation, Keyboard Controller enabled IN: Keyboard Controller disabled J9H4 SMC MD0 IN: Normal operation.
Hardware Reference 46 316704-001 / Developm ent Kit Use r’s Manual 4.5 LEDs The development board has a number of LEDs. These LEDs provide status for vari ous functions on the development board. Figure 8 indicates the l ocation of the LEDs and Table 16 describes their function.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 47 Function Reference Designator VID 0 CR1B1 VID 1 CR1B2 VID 2 CR1B3 VID 3 CR1B4 VID 4 CR1B5 VID 5 CR1B6 VID 6 CR1B7 M0/M1 CR4H1 System Power Good CR5J1 Reserved CR8G1 4.6 Other Headers, Slots and Sockets 4.
Hardware Reference 48 316704-001 / Developm ent Kit Use r’s Manual d. J9H2 (1-2) (default: 1-X), disable 1 Hz Cl ock. 4. Attach an ATX power supply or AC to DC adapter to the system and power up the development board. 5. From the directory where you extracted the files, run the “kscfl ash ksc.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 49 Reference Designator Slot/Socket Description Detail J6H5 Front Panel Header Table 28 J6H3, J6H4 USB Header Table 29 4.
Hardware Reference 50 316704-001 / Developm ent Kit Use r’s Manual Pin Description Pin Description A11 PERST# B11 WAKE# Key A12 GND B12 RSVD A13 REFCLK+ B13 GND A14 REFCLK- B14 LANE 0 (T+) A15 GND B.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 51 Pin Description Pin Description A43 LANE 6 (R+) B43 GND A44 LANE 6 (R-) B44 GND A45 GND B45 LANE 7 (T+) A46 GND B46 LANE 7 (T-) A47.
Hardware Reference 52 316704-001 / Developm ent Kit Use r’s Manual Pin Description Pin Description A77 LANE 14 (R-) B77 GND A78 GND B78 LANE 15 (T+) A79 GND B79 LANE 15 (T-) A80 LANE 15 (R+) B80 GND A81 LANE 15 (R-) B81 PRST2# A82 GND B82 RSVD 4.6.2.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 53 Pin Description Pin Description A18 GND B18 GND End of x1 Connector A19 Reserved B19 SDVO_Green+ A20 GND B20 SDVO_Green- A21 SDVOB_.
Hardware Reference 54 316704-001 / Developm ent Kit Use r’s Manual Pin Description Pin Description A50 Reserved B50 N/C A51 GND B51 N/C A52 N/C B52 GND A53 N/C B53 GND A54 GND B54 N/C A55 GND B55 N/.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 55 Table 20. MEC Slot (J6B2) Pin Description Pin Description A1 N/C B1 12 V A2 12 V B2 12 V A3 12 V B3 Reserved A4 GND B4 GND A5 N/C B5 N/C A6 N/C B6 N/C A7 N/C B7 GND A8 N/C B8 3.3 V A9 3.
Hardware Reference 56 316704-001 / Developm ent Kit Use r’s Manual Pin Description Pin Description End of x4 Connector A33 Reserved B33 N/C A34 GND B34 N/C A35 N/C B35 GND A36 N/C B36 GND A37 GND B3.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 57 Pin Description Pin Description A66 GND B66 SDVOB_Clk+ A67 GND B67 SDVOB_Clk- A68 N/C B68 GND A69 N/C B69 GND A70 GND B70 SDVOB_Blu.
Hardware Reference 58 316704-001 / Developm ent Kit Use r’s Manual Pin Description Pin Description Key A12 GND B12 RSVD A13 REFCLK+ B13 GND A14 REFCLK- B14 LANE 0 (T+) A15 GND B15 LANE 0 (T-) A16 LANE 0 (R+) B16 GND A17 LANE 0 (R-) B17 PRSNT2* A18 GND B18 GND 4.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 59 4.6.2.6 SATA Pinout Up to three SATA devices may be suppo rted by the SATA connectors on the development board. Table 23 describes the SATA ‘Di rect Connect’ connector and Table 24 describes the SATA ‘Cable Connect’ connectors.
Hardware Reference 60 316704-001 / Developm ent Kit Use r’s Manual Connector J2B3 is used to power the CPU fa n. Connectors J2C1 and J2F1 are not used in the default operation of the devel opment board. Table 26. Fan Connectors (J2B3, J2C1) Pin Signal 1 +V 2 TACH 3 GND Table 27.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 61 16 +V5 5 volt suppl y 4.6.2.9 USB Headers (J6H3, J6H4) The USB headers implement 4 additi onal USB ports on the development board. Connector J6H3 implements ports 7 and 8 and connector J6H4 impl ements ports 2 and 4.
Hardware Reference 62 316704-001 / Developm ent Kit Use r’s Manual Appendix A . Heatsink Installation Instructions It is necessary for the Intel ® Core TM 2 Duo processor to have a thermal solution attache d to it in order to keep it wit hin its ope rating temperat ure.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 63 Figure 10. Backplate Pins 4. Clean the die of the processor with i sopropyl alcohol before the heatsink i s attached to the processor. This ensures that the surface of the die is cl ean.
Hardware Reference 64 316704-001 / Developm ent Kit Use r’s Manual Figure 11. Applying the Thermal Grease 6. Pick up the heatsink and squeeze the activati on arm until it comes in contact with the ba se plate that is at tached to the he atsink base.
Hardware Reference 316704-001 / Developm ent Kit Us er’s Manual 65 7. While keeping the acti vation arm compressed, place the heatsink over the pi ns of the heatsink backplate. Lower the heatsink until the lugs have inserted into the base of the heatsink.
Hardware Reference 66 316704-001 / Developm ent Kit Use r’s Manual Figure 14. Plugging in the Fan Figure 15. Completed Assembly.
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