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Intel ® 815 Chipset: Graphics Controller Programmer’s Reference Manual (PRM) July 2000 Order Num ber: 298237-001 R.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 2 Information in this document i s provided in connection with Intel products. No license, express or implied, by estoppel or oth erwise, to any intellectual property rights is granted by this document.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 3 Contents 1. Introduction ................................................................................................................... ............. 15 1.1. Term inology ...............
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 4 6.2.2. Source Data ................................................................................................. 58 6.2.3. Monochrom e Source Data ........................................
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 5 9.4.5. AR12 Mem ory Plane Enable Register .................................................... 104 9.4.6. AR13 Horizontal Pixel Panning Register ......................................
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 6 10. Programm ing Interf ace .......................................................................................................... ... 141 10.1. Reserved Bits and Sof tware Compatibility .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 7 12.2.6. TEXT _Im m ediate_BLT ............................................................................. 169 12.2.7. COLOR_BLT .............................................................
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 8 13.9. GFXRENDERST ATE_MAP_LO D_LIMITS .................................................................. 224 13.10. GFXRENDERST ATE_MAP_LO D_CONTROL ..........................................
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 9 15.4.3.3. HORZ_PH—Horizontal Phase Register ....................................... 279 15.4.3.4. INIT_PH—Initial Phas e Register .................................................. 280 15.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 10 16.2.5. ISR—Interrupt Status Register .................................................................. 326 16.2.6. Error Identity, Mask and Status Regis ters ............................
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 11 Figures Figure 1. Intel â 815 Chipset System Block Diagram ......................................................... 18 Figure 2. Intel ® 82815 Chipset GMCH Block Diagram .................
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 12 Tables Table 1. Supported System Bus and System Mem ory Bus Frequencies ......................... 22 Table 2. Mem ory-Mapped Registers .......................................................
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 13 Rev ision History Rev. Descripti on Date 1.0 • Ini tial Releas e July 2000.
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Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 15 1. Introduction The In te l â 815 ch ipset is a high ly f lexible chips et designed to ex tend from the basic graph ics/mu ltimedia PC platform up to the m ainstream perform ance desk top platform.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 16 Term Description MCH The Memory Controll er Hub com ponent that c ontains t he process or interfac e, DRAM controll er, and AGP i nterfac e. The MCH comm unic ates with the I CH over a proprietary int erconnect c alled the hub i nterface (previ ously known as HubLink).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 17 2. Intel ® 815 Chipset Overview The chipset consists of an Intel ® 82815 chipset G raphics an d Memory Control ler Hub (GMC H), an I/O Controller Hub (IC H) for the I/O su bsys tem, an d a Firmw are* Hub (FWH).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 18 Figure 1. Intel â â â â 815 Chipset System Block Diagram System Bus (66/100/133 MHz) PCI Bus PCI Slots (ICH=6 Req/G nt pairs) 815_SysBl.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 19 • Support f or a sing le processor conf igu ration • 64-bit A GTL+ based Sy stem Bus Interf ace at 66/100/133 MHz • 32-bit H ost A dd.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 20 • 370-pin sock et (PGA370). The PGA 370 is a zero in sertion force (ZIF) s ocket th at a processor in the FC-PGA packag e will u se to interface w ith a sy stem board.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 21 Display Cache Interface The GMCH su pports a Display Cach e SDRA M controller w ith a 32-bit 133 MHz S DRAM array . The DRA M type s upported is indus try s tandard Sy nch ronous DR AM (SD RAM) li ke that of the s yst em mem ory.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 22 2.2.6. Sy stem Clocking The In te l ® 82815 ch ipset GMCH h as a new ty pe of clock ing arch itecture. It h as inte grated SDRA M buff ers that run at eit her 100 or 133 MHz, indepen dent of t he sy stem bus f requency .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 23 Figure 3. Conceptual Pla tform PCI Configuration Diagra m Processo r PCI Co nfi gura tion Window in I/O Space Hub Inter face DRAM* Con trol.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 24 To support a PCI g raphics dev ice, the Int el ® 815 chipset s imply pass es all of th at device’ s cycl es to the hub interf ace as it w ould for any other PCI dev ice.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 25 2.3.1.2. Sy stem Startup The In te l ® 815 ch ipset has m ultiple poss ible device m odes. The selection of w h ich mode w ill be auto- detected is represented in the followin g flow chart.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 26 2.3.1.3. Software Start-Up Sequence The following sequence of events w ill occur durin g the initialization of an Intel ® 815 ch ipset- based system : 1. The ICH asserts P CIRST# either in response to an initial assertion of PWROK or a write to an I/O Port.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 27 14. During PCI enumeration, th e system BIOS will identify and initialize the prim ary display device. The selection of the primary display device is ty pically OEM dependent. A n OEM may use a BIOS setup question to allow the sy stem us er to select the primary display device.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 28 3. After the conclu sion of the graphics driver startup code the internal g raphics functions w ill be ready for ru n-tim e activity an d comm ands can be written in to the ring buf fer. 2.3.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 29 3. System Address M ap This chapter provides address m aps of th e graphics con troller (GC) I/O and m em ory- mapped reg isters. Individual register bit f ield descriptions are provided in the f ollowing ch apters.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 30 3.1. Memory and I/O Space Registers Thi s sectio n pr ovide s a high-le vel re gister map (re gister group ings pe r functio n). T he memory and I/O maps for the GC regi sters are show n in the follow ing figu re.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 31 • VGA an d Extend ed VGA Control Regis ters (00000h − − − − 00FFFh). These regist ers are located in both I/O space and m em ory space.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 32 3.2. GC Register Memory A ddress Map All GC registers are m em ory-m apped. In addition, the VGA and Extended VGA registers are I/O ma pped.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 33 Table 2. Memo ry-Mapp ed Registers A ddress Offset Sy mbol Register Name A ccess 020C0h INSTP M Inst ruction P arser Mode Register R/W 020C.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 34 Table 2. Memo ry-Mapp ed Registers A ddress Offset Sy mbol Register Name A ccess Overlay Registers (30000h − − − − 03FFFFh) (For ad.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 35 Table 2. Memo ry-Mapp ed Registers A ddress Offset Sy mbol Register Name A ccess BLT Engine Status (40000h − − − − 4FFFFh) (Softwar.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 36 Table 2. Memo ry-Mapp ed Registers A ddress Offset Sy mbol Register Name A ccess LCD/TV-Out Registers (60000h–6FFFFh) LCD/TV-Out 60000h.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 37 3.3.1. VGA and Extended VGA I/O and Memor y Regi ster M ap Table 3. I/O and Memory Register Map A ddress Register Name (Read) Register Name.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 38 3.4. Indirect VGA and Extended VGA Register Indices Programm ing an index v alue into the appropriate SR X, GRX, ARX, or C RX register in directly access es the registers listed in this section.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 39 Table 6. 2D A tt ribute Cont roller Registers (3C0h / 3C1h ) Index Sym Register Name 00h AR00 Palette Regi ster 0 01h AR01 Palette Regi ste.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 40 Index Sym Register Name 0Fh CR0F Text Cursor Location Low 10h CR10 Vertical Sync St art 11h CR11 Vertical Sync End 12h CR12 Vertical Displa.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 41 3.4.1. Graphics A ddress Translation The In te l ® 815 ch ipset uses a log ical mem ory-addressi ng concept f or accessing graphics data.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 42 Figure 8. GTT M apping Virtual Graphics Memory Base Base + 64 MB TOM Base + 32 MB 64 KB 0 64 MB Graphics Engine Address Space Graphics Tran.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 43 4. Graphics Translation Table (GTT) Range Definition Address Off set: 10000h–FFFFh Default Value: Page table range 64 KB Acces s: aligned.
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Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 45 5. Basic Initialization Procedures 5.1. Initialization Sequence The initialization of graphics driver resources can be broken dow n into three categories: hardw are detection, frame buf fer initialization, and hardw are register initialization.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 46 Once the operating sy stem h as identified the device, it can load the appropriate dr iver.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 47 5.4. Hardw are Register Initialization 5.4.1. Color vs. M onochrome M onitor s The mapping and initialization of some hardw are registers depends in part on wh ether the graphics adapter is attached to a monochrom e or color monitor.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 48 5.6. Sav ing the Hardw are State Note that the VGA register u nlockin g protocol m ust be perform ed in order to access som e of the reg isters described below .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 49 5.7. Restoring the Hardw are State The graphics adapter s tate shou ld be restored by perf ormi ng the f ollowi ng steps . Note some of the syn chronization operations, especially those that ensu re that the local mem o ry is idle during the state restore.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 50 • Other registers that sh ould restore o nly certain bits from the sav ed-state values: Bit Blit Control MM 0x7000c Read the current valu e of the Bit Blit Control Register. Clear the bits pertaining to the Color Expansion Mode (bits 5:4).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 51 Wat ermark a nd Bur stlengt h Contro l MM 0 x20D 8 Read the curren t value of the Watermark and Burstleng th Control R egister. Clear th e burst l ength and w atermark bit s (bits 22: 20, 17:12, 10:8 and 5:0).
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Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 53 6. Blt Engine Programming 6.1. BLT Engine Programming Considerations 6.1.1. When the Source and Destination Locations Overlap It is possible to have BLT o perations in w hich the locations of the sou rce and destination data overlap.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 54 Figure 9. Source Cor ruption in BLT w ith Overlapping Sour ce and Destination Loca tions (i) Source Destination (a) Source Destination b_blt2.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 55 The BLT engine can alter the order in w hich source data is read and destination data is w ritten wh en necessary to avoid source data corruption problem s w hen th e source and destin ation locations ov erlap.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 56 The figure below illu strates how th is feature of the BLT engin e can be used to perform the sam e BLT operation as was illustrated in th e figure above, w hile avoiding th e corruption of source data.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 57 6.2. Basic Graphics Data Considerations 6.2.1. Contiguous vs. Discontinuous Gr aphics Data Graphics data st ored in mem ory, particularly in the f rame buf fer of a g raphics sy stem, has org anizational chara cter istic s that oft en dist inguish it fro m other varie ties o f data.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 58 Figure 13. Representation o f On-Screen 6x4 Array of Pixels in the Frame Buff er Note: Drawing is not to scale (0, 0) (0, 479) (639, 479) (639, 0) b_blt6.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 59 If the color sou rce data resides w ithin th e frame bu ffer or m ain mem ory graph ics mem ory, then the Source Addres s Regist er, specified in th e comm and packets is used to specify the address of the sou rce.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 60 mon ochrome s ource data can be set in th e source expans ion foregroun d color register and th e source expa nsion ba ckgro und co lor registe r. The BLT Engine requires that the bit align ment of each scan lin e’s w orth of m o nochrom e source data be specified.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 61 Figure 15. 8bpp Pattern Data -- Occ upies 64 By tes (8 quadwords) b_blt9.vsd 0 Pixel (0, 7) Pixel (7, 7) Pixel (0, 0) Pixel (7, 0) 63 57 56 48 47 40 39 24 23 32 31 16 15 8 7 00h 28h 08h 10h 18h 20h 30h 38h Figure 16.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 62 Figure 18. 2bpp Pattern Data -- Occupies 256 Bytes (32 quadwords) b _ blt10.vsd 0 Pixel ( 3, 0 ) Pixe l ( 7, 7 ) Pixel ( 0, 0 ) Pixe l ( 4,.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 63 6.3. BLT Programming Examples 6.3.1. Pattern Fill -- A Very Simple BLT In this example, a rec tangular ar ea on the scre en is to be filled with a color patte rn stored as pattern d ata in off-scr een memory.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 64 Figure 20. Pattern Data for Example Pattern Fill BLT b_blt22.vs d 63 0 100000h 100008h 100010h 100018h 100020h 100028h 100030h 100038h (0, .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 65 Figure 21. Results of Example Pattern Fill BLT b_blt21.vs d Scan Lines 128 Through 191 128, 128 Note: Drawing is not to scale (0, 0) (0, 76.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 66 6.3.2. Dr aw ing Char acters Using a Font Stored i n Sy stem M emory In this ex ample BLT operation, a low ercase letter “f” is to be draw n in black on a display with a gray backgrou nd.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 67 monoch rome BLT operand following the BLT_T EXT comman d. The BLT engin e will receiv e this data through the c ommand stream and use it as the source d ata fo r this BLT oper ation.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 68 This BLT o peration does not use the values in the Pattern A ddress Register, the Source Expansion Bac kground Color Registe r, or the Sour ce E xpansio n Fore ground Color Register . Figure 24.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 69 7. Initialization Registers To function, all registers described in this section mu st be pro gram med for the In tel ® 815 chips et fam ily of products.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 70 Bit Descripti on 7:6 Graphics Mode Sel ect (GMS). This fiel d is used t o enable/dis able the Internal Graphics devi ce and select the am ount of Main Memory t hat is “S tolen” to s upport the I nternal Graphics device in V GA (non-linear) m ode only.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 71 Bit Descripti on 1 SMM Space Locked (D_LCK). W hen D_LCK is set to 1 t hen D_LCK, GMS, US MM, and the mos t signif icant bit of LSMM becom e read only. D_LCK c an be set t o 1 via a normal configurat ion space write but can only be c leared by a reset.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 72 7.3. Display , I/O, GPIO, Clock, LCD, and Pixel Pipeline Registers These registers are described elsew here in th is docum ent. Refer to th e appropriate sections of this PRM for detailed bit/field descriptio ns.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 73 7.4. 2D Graphics Controller Registers (3CEh / 3CFh) Refer to Chapter 9, “VGA an d Extended VGA Registers” for detailed bit/field descriptions. Index Sym Register Name 10h GR10 Address Mapping 11h GR11 Page Select or 7.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 74 7.6. Initialization Values for VGA Registers Mode -> 0 0* 0+ 1 1* 1+ 2 2* 2+ 3 3* 3+ 7 7+ 132 col 132 col R e g i s t e r O p t 1 O p t .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 75 Mode -> 0 0* 0+ 1 1* 1+ 2 2* 2+ 3 3* 3+ 7 7+ 132 col 132 col R e g i s t e r O p t 1 O p t 2 GR01 00h 00h 00h 00h 00h 00h 00h 00h 00h 00.
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Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 77 8. Frame Buffer Access The VGA fram e buff er is located at A000h -BFFFh. This is the s tandard VGA f rame bu ffer address . The phy sical location of the f rame bu ffer is at the top of main me mory .
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Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 79 9. VGA and Extended VGA Registers This chapter describes the registers and the functional operation notations f or the observable registers in the 2D section. Each register is docum ented and the various bit settings defined.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 80 9.1.1. ST00 Input Status 0 I/O (and Mem ory Offset) Address: 3C2h Default: 00h Attributes: Read Only 7 6 5 4 3 0 CRT Int Reserved (00) RGB Cm p / Sen Reserved (0000) Bit Descripti ons 7 CRT Interrupt Pending.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 81 9.1.2. ST01 Input Status 1 I/O (and Mem ory Offs et) Address: 3BAh/3DAh Default: 00h Attributes: Read Only The address selection is dependent on CG A or MDA em ulation mode as s elected via the MSR register.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 82 9.1.3. FCR Feature Control I/O (and Mem ory Offs et) Address: 3BAh/3DAh W r ite; 3CAh Read Default: 00h Attributes: See Address above The address selection f or reads is dependent on CGA or MDA emu lation m ode as selected via th e MSR register.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 83 9.1.4. MSR Mi scellaneous Output I/O (and Mem ory Offset) Address: 3C2h W rite; 3CCh Read Default: 00h Attributes: .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 84 Table 8. CRT Display Sync Polarities V H Display Hori zontal Frequency Vertical Frequency P P >480 Line Variable Vari able P P 200 Line 15.7 KHz 60 Hz N P 350 Line 21.8 KHz 60 Hz P N 400 Line 31.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 85 9.2.2. SR00 Sequencer Reset I/O (and Mem ory Offs et) Address: 3C5h( Index=00h) Default: 00h Attributes: Read/W rite 7 2 1 0 Reserved (000000) Reserved (scra tch bit) Reserved (scra tch bit) Bit Descripti ons 7:2 Reserved .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 86 9.2.3. SR01 Clocking M ode I/O (and Mem ory Offs et) Address: 3C5h ( Index=01h) Default: 00h Attributes: Read/W rite 7 6 5 4 3 2 1 0 Reserved (00) Screen Off Shift 4 Dot Clock Divide Shift Load Res erved (0) 8/9 Dot Clocks Bit Descripti ons 7:6 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 87 9.2.4. SR02 Plane/Map M ask I/O (and Mem ory Offs et) Address: 3C5h ( Index=02h) Default: 00h Attributes: Read/W rite 7 4 3 0 Reserved Mem ory Planes P rocess or W rite Ac cess Enable.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 88 9.2.5. SR03 Character Font I/O (and Mem ory Offs et) Address: 3C5h (index=03h) Default: 00h Attributes: Read/W rite 7 6 5 4.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 89 9.2.6. SR04 Memor y M ode Register I/O (and Mem ory Offs et) Address: 3C5h ( index=04h) Default: 00h Attributes: Read/W rite 7 4 3 2 1 0 Reserved (0000) Chain 4 Odd/Even E xtended Mem ory Reserved (0) Bit Descripti on 7:4 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 90 9.2.7. SR07 Horiz ontal Character Counter Reset I/O (and Mem ory Offs et) Address: 3C5h ( index=07h) Default: 00h Attribute.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 91 9.3.2. GR00 Set/Reset Register I/O (and Mem ory Offs et) Address: 3CF h (index=00h) Default: 0Uh (U=Undefined) Attributes: Read/W rite 7 4 3 2 1 0 Reserved (0000) Set/Res et Plane 3 Set/Res et Plane 2 Set/Re set Plane 1 Set/Re set Plane 0 Bit Descripti on 7:4 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 92 9.3.4. GR02 Color Compare Register I/O (and Mem ory Offs et) Address: 3CF h (Index=02h) Default: 0Uh (U=Undefined) Attribut.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 93 9.3.6. GR04 Read Plane Select Register I/O (and Mem ory Offs et) Address: 3CF h (Index=04h) Default: 0Uh (U=Undefined) Attributes: Read/W rite 7 2 1 0 Reserved (000000) Read P lane Selec t Bit Descripti on 7:2 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 94 Bit Descripti on 6:5 Shift Register Control. In standard VGA m odes, pi xel data is trans ferred from the 4 graphics mem ory planes to t he palette vi a a set of 4 s erial output bits.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 95 Bit Descripti on 4 Odd/Even Mode. 0 = Addres ses s equentially acc ess dat a within a bit m ap, and the c hoice of which m ap is ac cessed i s made ac cording to t he value of the P lane Mask Regis ter (SR02).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 96 9.3.8. GR06 Mi scellaneous Regi ster I/O (and Mem ory Offs et) Address: 3CF h (Index=06h) Default: 0Uh (U=Undefined) Attributes: Read/W rite 7 4 3 2 1 0 Reserved (0000) Memory Map Mode Chain Odd/Even Graphics / Text Mode Bit Descripti on 7:4 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 97 9.3.9. GR07 Color Don’ t Care Register I/O (and Mem ory Offs et) Address: 3CF h (Index=07h) Default: 0Uh (U=Undefined) At.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 98 9.3.11. GR10 A ddress M apping I/O (and Mem ory Offs et) Address: 3CF h (Index=10h) Default: 00h Attributes: R/W 7 5 4 3 2 1 0 Reserved Paging to LM VGA Buffer / Mem ory Map Pack ed Mode Enable Linear Mapping Page Mapping Bit Description 7:5 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 99 Table 9. VGA Address Range GR10 [2] GR10 [1] GR10 [0] Note 1 A ddress Range (see note 2) A 0000-A FFFF Range (No GTT) B0, B8 Ranges (No GTT.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 100 9.3.13. GR[14:1F] Softw are Flags I/O (and Mem ory Offs et) Address: 3CFh (Index=14h-1f h) Default: 00 Attribute: R/W Bit Description 7:0 S oftware Flags. Us ed as sc ratch pad s pace in BI OS.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 101 9.4. A ttribute Controller Registers Unlike the other sets of indexed registers, the attr ibute controller registers are no t accessed through a schem e employ ing entirely separate index an d data ports.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 102 9.4.2. A R[00:0F] Palette Registers [0:F] I/O (and Mem ory Offs et) Address: Read at 3C1h and W rite at 3C0h; (index=00h- 0Fh) Default: 00UU UUUUb (U=Undefined) Attributes: Read/W rite 7 6 5 0 Reserved Palet te Bits P[5:0] Bit Descripti on 7:6 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 103 Bit Descripti on 5 Pixel Panning C ompatibility . 0 = Sc roll both the upper and l ower screen regions horizontal ly as spec ified in t he Pixel Panning Register (A R13). 1 = Sc roll only the upper s creen region horizontal ly as spec ified in t he Pixel Panning Regis ter (AR13).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 104 9.4.4. A R11 Overscan Color Register I/O (and Mem ory Offs et) Address: Read at 3C1h and W rite at 3C0h; (index=11h) Default: UUh (U=Undefined) Attributes: Read/W rite Bit Descripti on 7:0 Overscan.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 105 9.4.6. A R13 Horiz ontal Pixel Panni ng Register I/O (and Mem ory Offs et) Address: Read at 3C1h and W rite at 3C0h; (index=13h) Default: 0Uh (U=Undefined) Attributes: Read/W rite 7 4 3 0 Reserved (0000) Horizontal P ixel Shift Bit Descripti on 7:4 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 106 9.4.7. A R14 Color Select Register I/O (and Mem ory Offs et) Address: Read at 3C1h and W rite at 3C0h; (index=14h) Default: 0Uh (U=Undefined) Attributes: Read/W rite 7 4 3 2 1 0 Reserved (0000) P7 P6 Alt P 5 Alt P4 Bit Descripti on 7:4 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 107 used to c hoose the co lor da ta positio n that is to be written to through the same data p ort. T his arrangem ent allow s the sam e data port to b e used for reading f rom and w r iting to tw o different color data positions.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 108 9.5.2. DA CSTATE DA C State Register I/O (and Mem ory Offset) Address: 3C7h Default: 00h Attributes: Read Only 7 2 1 0 Reserved (000000) DAC Stat e Bit Descripti on 7:2 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 109 9.5.5. DA CDATA Palette Data Register I/O (and Mem ory Offset) Address: 3C9h Default: Undef ined Attributes: Read/W rite Bit Descripti on 7:0 Pal ette Data.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 110 Figure 25 Display Fields and Dimens ions CRxx Control Registers crt_reg.vsd Blank (V ertical B ack Porc h) Vertical Top B orde r Blank (Ve.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 111 9.6.2. CR00 Horiz ontal Total Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=00h) Default: 00h Attributes: Read/W rite (G roup 0 Protection) This register is u sed to specify the total leng th of each s can line.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 112 9.6.5. CR03 Horiz ontal Blanki ng End Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=03h) Default: 1UUU UUUU.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 113 9.6.7. CR05 Horiz ontal Sy nc End Regi ster I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=05h) Default: 00h Attribut.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 114 9.6.8. CR06 Vertical Total Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=06h) Default: 00h Attributes: Read/W rite (G roup 0 Protection) Bit Descripti on 7:0 Vertical Tota l Bits [7:0] .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 115 Bit Descripti on 6 Vertical Displ ay E nable End Bit 9. The vertical display enable end i s a 10-bit or 12-bi t value that specif ies the num ber of t he last s can line within t he acti ve display area.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 116 Bit Descripti on 3 Vertical Blanki ng Start Bit 8. The vert ical blank ing start is a 10-bit or 12-bit value that speci fies t he beginning of t he vertical bl anking period relat ive to the begi nning of the ac tive displ ay area.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 117 Bit Descripti on 0 Vertical Total Bi t 8. The vertic al total i s a 10-bit or 12-bi t value that s pecif ies the t otal num ber of scan lines. This incl udes the s can lines bot h inside and out side of t he active di splay area.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 118 9.6.11. CR09 Maximum Scan Line Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=09h) Default: 00h Attributes: Read/W rite 7 6 5 4 0 Double Scanning Line Cmp Bit 9 Vert Blnk Start Bit 9 Starti ng Row Scan Count Bit Descripti on 7 Double Scanning Enable.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 119 9.6.12. CR0A Text Cursor Start Register I/O (and Mem ory Offs et) Address : 3B5h/3D5h (index=0Ah) Default: 00UU UUUUb (U=U.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 120 9.6.14. CR0C Start A ddress High Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=0Ch) Default: Undef ined Attributes: Read/W rite Bit Descripti on 7:0 Start Address Bits [15:8] or [17:10].
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 121 9.6.15. CR0D Start A ddress Low Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=0Dh) Default: Undef ined Attributes: Read/W rite Bit Descripti on 7:0 Start Address Bits [7:0] or [9:2].
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 122 9.6.17. CR0F Text Cursor Locati on Low Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=0Fh) Default: Undef in.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 123 9.6.19. CR11 Vertical Sy nc End Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=11h) Default: 0U00 UUUUb (U=U.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 124 9.6.20. CR12 Vertical Display Enable End Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=12h) Default: Undef ined Attributes: Read/W rite Bit Descripti on 7:0 Verti cal Display Enable End Bits [7:0].
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 125 9.6.22. CR14 Underli ne Location Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=14h) Default: 0UUU UUUUb (U=Undefined) Attributes: Read/W rite 7 6 5 4 0 Reserved (0) DW ord Mode Count By 4 Underline Locat ion Bit Descripti on 7 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 126 9.6.23. CR15 Vertical Blanking Start Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=15h) Default: Undef ined Attributes: Read/W rite Bit Descripti on 7:0 Verti cal Blanking S tart Bits [7:0].
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 127 9.6.25. CR17 CRT Mode Contr ol I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=17h) Default: 0UU0 UUUUb (U=Undefined) .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 128 Bit Descripti on 3 Count By 2. This bit is used in c onjunct ion with bit 5 of t he Underline Locat ion Register (CR14) t o select the n umber o f chara cter clo cks are r equired to caus e the m emory addres s counter t o be increm ented.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 129 Table 10. M emory A ddress Counter Address Bits [15:0] By te Mode CR14 bit 6=0 CR17 bit 6=1 CR17 bit 5=X Word M ode CR14 bit 6=0 CR17 bit .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 130 Table 11. Frame Buf fer A ddress Decoder CR17 bit 1=1 CR17 bit 1=1 CR17 bit 1=0 CR17 bit 1=0 CR17 bit 0=1 CR17 bit 0=0 CR17 bit 0=1 CR17 b.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 131 9.6.26. CR18 Line Compare Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=18h) Default: Undef ined Attributes: Read/W rite Bit Descripti on 7:0 Li ne Compare Bi ts [7:0].
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 132 9.6.28. CR24 Test Register for Toggl e State of A ttribute Control ler Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=24h) Default: 00h Attributes: Read Only 7 6 0 Toggle Status Reserved (0000000) Bit Descripti on 7 Toggle Stat us.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 133 9.6.30. CR31 Extended Vertical Display End Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=31h) Default: 00h Attributes: Read/W rite 7 4 3 0 Reserved (0000) Vertical Di splay End B its 11: 8 Bit Descripti on 7:4 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 134 9.6.31. CR32 Extended Vertical Sy nc Start Regi ster I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=32h) Default: 00h Attributes: Read/W rite 7 4 3 0 Reserved (0000) Vert ical S ync Start Bits 11:8 Bit Descripti on 7:4 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 135 9.6.32. CR33 Extended Vertical Blanking Start Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=33h) Default: 00h Attributes: Read/W rite 7 4 3 0 Reserved (0000) Vertic al Blank ing Start B its 11: 8 Bit Descripti on 7:4 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 136 9.6.33. CR35 Extended Horiz ontal Total Time Regi ster I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=35h) Default: 00h Attributes: Read/W rite 7 1 0 Reserved (0000000) Ext Horiz Total Bit Descripti on 7:1 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 137 9.6.35. CR40 Extended Start A ddress Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=40h) Default: 00h Attributes: Read/W rite 7 6 5 0 Start A ddr Enable Reserved (0) Start A ddress B its 23: 18 Bit Descripti on 7 Extended Mode Start Address Enable.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 138 9.6.36. CR41 Extended Offset Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=41h) Default: 00h Attributes: Read/W rite 7 4 3 0 Reserved (0000) Offs et Bits 11:8 Bit Descripti on 7:4 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 139 9.6.38. CR70 Interlace Control Register I/O (and Mem ory Offs et) Address: 3B5h/3D5h (index=70h) Default: 00h Attributes: Read/W rite 7 6 0 Interl ace Enable CRT Half-Line Val ue Bit Descripti on 7 Interlace Enabl e.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 140 9.6.40. CR81 Reserved I/O (and Mem ory Offs et) Address: 3B5h/3D5h(index 81h) Default: 00h Attributes Read/W rite This register is not present in 2D. 7 0 Reserved (00000000) Bit Descripti on 7:0 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 141 10. Programming Interface The Graphics Con troller (GC) contains an extens ive set of reg isters and in struction s (also referred to as “Com mands” ) for controll ing 2D, 3D , and video operati ons.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 142 10.3. GC Register Programming All of th e GC regist ers (except for the PCI C onfigu ration registers ) are mem o ry m apped. T he base address of this 512 K B mem o ry block is prog ramm ed in the MMA DR PCI C onfig uration register.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 143 10.4.3. Instruction Parser The follow ing fig ure show s a high-lev el diagram of the GC in struction in terface.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 144 10.4.4. Ring Buffers (RB) The GC pr ovide s two Ring Buffe r (RB ) mechanisms thr ough which instruc tions ca n be p assed to the Instru ction Parser.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 145 • Head Wrap Cou nt: This field is in cremen ted by the IP every time the Head Off set w raps back to the start of the buf fer.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 146 Softw are is required to use some m echanism to track instruction execu tion progress to determine the free space in the RB.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 147 10.4.6. Instruction A r bitration The Instru ction Parser s upports u p to four s ources of pen ding instru ctions: tw o Ring Buff ers and tw o Batch Buf fer sequ ences (one batch buff er per ring bu ffer).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 148 buff ers, and the im pact on latency an d perform ance, shou ld be caref ully cons idered by softw are developers. 10.4.6.3. Instruction A rbitration Points The IP performs arbitration for instruction ex ecution at the follow ing points: • Continuo usly when idle (i.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 149 10.5. Instruction Format GC instructions are defin ed with v arious formats. The first DWord of all instructions is called the h eader DWord.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 150 10.5.3. 3D Instructions The 3D inst ructions are used to program the 3D pipeline s tate and perf orm 3D, S tretch Blt , and MotionComp operations. All 3D state instru ctions are of fixed leng th, w hile the rendering in structions are all variable length .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 151 Table 13. Grap hics Contro ller Instructio ns Client Instruction 00h–Comm and Parser GFXCMDPARSER_NOP_IDENTIFI CATION GFX CMD PARSER_BR .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 152 Table 13. Grap hics Contro ller Instructio ns Client Instruction 03h–Rendering Proces sor GFXPRIMITIVE GFXBLOCK GFXR ENDERSTATE_VERTEX _.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 153 11. Instruction Parser Instructions 11.1. Introduction The Graphics Cont roller (GC) contains an extensiv e set of ins truction f or controlling 2D an d 3D operations. This section describes the program mer’s in terface to these in structions.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 154 11.2.2. GFXCMDPA RSER_BREA KPOINT_INTERRUPT This instruction w ill generate a breakpoint interrupt an d cause the parser to stop until the interrupt is cleare d by writing the Interrup t Identity Register.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 155 11.2.4. GFXCMDPARSER_WA IT_FOR_EVENT This instruction can be used to pause instruction stream processing un til a specific event occurs. Only one event can be specified -- specifyin g mu ltiple events is UNDEFINED.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 156 11.2.5. GFXCMDPARSER_FLUSH This instruction w ill flush all drawing engines an d the frame buf fer cache (a.k.a. local cach e). In addition, it will conditionally invalidate the m ap cache.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 157 11.2.7. GFXCMDPARSER _DEST_BUFFER_INFO The GFXCMDPARSER DEST_ BUFFER_INFO instruction is used to specify th e information about the destination buffer.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 158 11.2.8. GFXCMDPARSER _FRONT_BUFFER_INFO The GFXCMDPARSER _FRONT _BUFFER_INFO instruction is used to initialize the base address of the scene to be dis play by the Display Engine (DE) (a.k .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 159 11.2.9. GFXCMDPARSER _Z_BUFFER_INFO This instru ction is us ed to specify the base address an d pitch of the Z buff er surf ace used by the 3D Rendering engine.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 160 11.2.11. GFXCMDPARSER_A RB_ON_OFF The GFXCMDPARSER_A RB_ON_OFF instru ction is used to in form th e input interf ace to turn on/of f all the rings except the ring that th is instruction is execu ted from.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 161 11.2.14. GFXCMDPARSER_LOA D_SCA N_LINES_EXCL This instruction is used to initialize the scan lin e win dow registers in th e Display engin e.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 162 11.2.17. GFXCMDPARSER_BA TCH_BUFFER The GFXCMDPARSER_BA TCH_BUFFER instruction is used to inf orm the in put interface to pars e an instruction buff er. The address o n the instru ction buffers is in graphics m emory that should tran slate to a phy sical address in m ain mem ory.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 163 12. 2D Instructions This chapter contain s the 2D graphi cs controller inst ructions. For each in struction the form at specifies the fun ctionality of a fi eld. When an instruction does not require a field, it is ignored.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 164 12.2.1. SETUP_BLT The setup instruction supplies comm on setup information in cluding clipping coordinates used exclusively with the follow ing 3 instructions: 1. PIXEL_BLT (PB) - 1 pixel w rite with th e coordinate and solid pattern s upplied for each pix el to be written.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 165 DWord Bi t Description 0 = BR00 31:29 Cl ient : 02h – 2D Process or 28:22 Instruction T arget (Opcode) : 00h 21:05 Reserved. Must be Zero 0 04:00 Dword Length : 06h 1 = BR01 31 Reserved. Must be Zero 30 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 166 12.2.2. SETUP_MONO_PATTERN_SL_BLT This setup instruction supplies common setu p information inclu ding clipping coordinates used exclusively with the follow ing instru ction: • SCA NLINE_BL T (SLB) - 1 scan l ine of m onochrome pat tern and des tination are the only operands allowed.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 167 12.2.3. PIXEL_BLT The Destination X coordinate and Destination Y Address is compared with th e ClipRect registers.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 168 12.2.5. TEXT_BLT All m onochrome source scan lines and pixels that f all with in the ClipRect Y addresses and X coo rdinates are written (ignoring the raster operation) to (Destination Y Address + Destination X coordinate * by tes per pixel).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 169 12.2.6. TEXT_Immediate_BLT This instructi on allo ws the Driver to se nd dat a thro ugh the instr uction st ream, which eliminate s the re ad latency of reading a source from m emory. This allows graphics primitives su ch as Text to execute mu ch faster.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 170 12.2.7. COLOR_BLT COLOR_BLT is the simplest BLT operation. It pe rforms a color fill to the destination (with a possible ROP). T he only operand is the destination operand, which is w ritten dependent on the raster operation.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 171 12.2.8. PA T_BLT PAT_BLT is used w hen there is no source and th e color pattern is not trivial (is not a solid colo r only). The w hole color pattern (8 x 8 pix els = 16, 32, or 64 DWs) is read at the begi nnin g of th e BLT and stored in the Textu re Cache.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 172 12.2.9. MONO_PAT _BLT MONO_PAT_B LT is used w hen there is no source and the m o nochrom e pattern is not trivial (is not a solid color only).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 173 12.2.10. SRC_COPY_BLT This BLT instruction perform s a color source copy w here the only operands involved is a color sou rce and destination of the sam e bit width.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 174 12.2.11. MONO_SRC_COPY_BLT This BLT instruction perform s a mon ochrome s ource copy w here the only operands involv ed is a mon ochrome s ource and destination . The source and destination operands cannot ov erlap, wh ich m eans that the X direction m ust alway s be forward.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 175 DWord Bi t Description 4 31:16 Reserved. Must be Zero 4 = BR11 15:00 Number of Monochrome Source Quadw ords - 1: (1 to 64k Quadwords = 64 .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 176 DWord Bi t Description 0 = BR00 31: 29 Client : 02h – 2D Proces sor 28:22 Instruction T arget (Opcode) : 61h 21:20 Reserved. Must be Zero 19:17 Monochrome source data bit position of the fi rst pixel wi thin a by te per scan line.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 177 12.2.13. FULL_BLT The full BLT is the most com prehensive BLT instruction. It provides the ability to specify all 3 operands: destin ation, source, and pattern . The source and pattern operan ds are the sam e bit wi dth as the destination operand.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 178 DWord Bi t Descripti on 3 = BR09 31: 00 Destination A ddress: Addres s of the f irst byt e to be written (25:00 are im plement ed in Intel ® 810 chipset ) 31:14 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 179 DWord Bi t Description 0 = BR00 31:29 Cl ient : 02h – 2D Process or 28:22 Instruction Target (Opcode) : 46h 21:20 Reserved. Must be Zero 19:17 M onochrome source data bit positi on of the first pixel w ithin a by te per scan line.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 180 12.2.15. FULL_MONO_PATTERN_BLT The full BLT is the most com prehensive BLT instruction. It provides the ability to specify all 3 operands: dest ination, source, and pattern . The pattern operan d is mon ochrom e and the s ource operand is the sam e bit width as the destination operand.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 181 DWord Bi t Description 2 = BR14 31:16 Destinati on Height (in scan lines): (28:16 are im plement ed in Intel ® 810 chipset ) 15:00 Destin.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 182 12.2.16. FULL_MONO_PATTERN_MONO_SRC_BLT The full BLT provides the ability to specify all 3 operands: destination, source, and pattern. The pattern and source operan ds are mon ochrom e. The monochrom e pattern is loaded from th e instruction stream .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 183 DWord Bi t Description 1 = BR13 31 Solid Pattern Sele ct: (1 = solid patt ern; 0 = no solid pat tern) 30 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 184 12.3. BLT Engine Instruction Definitions This section describes the BLT Engine in struction f ields. These description s are in the f ormat of reg ister description s. For debug purposes, t he read-onl y addres ses in dicated provide BL T Engine s tatus.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 185 Bit Descripti ons 13 T ext BLT. Current Opcode is Text BLT. 12 Scan Line B LT. Current Opcode is Sc an Line BLT. 11 Pixel BLT. Current Opcode is P ixel BLT. 10:8 Destinati on Transparency M ode.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 186 12.3.2. BR01—Setup BLT Raster OP, Control, and Destination Offset Memor y Of fset Addres s: 40004h Default: 0000 xxxx Attributes: RO; DW ord ac cessible BR01 contains the contents of th e last Setup instruction DWord 1.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 187 Bit Descripti ons 28 Monochrome Pattern Transparency M ode. This bit applies onl y when the pattern data is monoc hrome.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 188 12.3.3. BR02—Clip Rectangle Y1 A ddress Memor y Of fset Addres s: 40008h Default: None Attributes: RO; DW ord ac cessible BR02 is loaded by either th e SETUP _BLT or SETUP_ MONO_PATT ERN_SL_BLT instructions and is used w ith PIXEL_BLT, SCANLINE_BL T, or T EXT_BLT instructions .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 189 12.3.5. BR04—Clip Rectangle X1 and X2 Memor y Of fset Addres s: 40010h Default: None Attributes: RO; DW ord ac cessible BR04 is loaded by either th e SETUP _BLT or SETUP_ MONO_PATT ERN_SL_BLT instructions and is used with P IX EL_B LT , SCAN LINE _B LT, or TE XT _B LT i nstruc tio ns.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 190 12.3.6. BR05—Setup Expansion Background Col or Memor y Of fset Addres s: 40014h Default: None Attributes: RO; DW ord ac cessible 31 24 23 0 Reserved. Must be Zero Setup E xpansion Back ground Color Bits [23:0] Bit Descripti ons 31:24 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 191 12.3.8. BR07—Setup Color Pattern A ddress Memor y Off set Addres s: 4001Ch Default: None Attributes: RO; DW ord ac cessible 31 26 25 16 Reserved. Must be Zero S etup Color Patt ern Address Bits [25:16] 15 6 5 0 Setup Color P attern Addres s Bit s [15: 6] Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 192 12.3.9. BR08—Destination X1 and X2 Memor y Of fset Addres s: 40020h Default: None Attributes: RO; DW ord ac cessible BR08 is loaded by eith er PIXEL_BLT , SCANLINE_BLT, or TEXT _BLT instructions.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 193 12.3.10. BR09—Destination A ddress and Destination Y1 Address Memor y Of fset Addres s: 40024h Default: None Attributes: RO; DW ord ac cessible 31 26 25 0 Rese rved . Must be Zero Destinat ion and Desti nation Y1 and Y A ddress B its [ 25:0] Bit Descripti ons 31:26 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 194 12.3.12. BR11—BLT Sour ce Pitch (Offset) or M onochrome Sour ce Quadw ords Memor y Off set Addres s: 4002Ch Default: None Attributes: RO; DW ord ac cessible 31 14 13 0 Reserved Source Pi tch (Off set) or Monochrome S ource Quadwords Bit Descripti ons 31:14 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 195 12.3.13. BR12—Source A ddress Memor y Of fset Addres s: 40030h Default: None Attributes: RO; DW ord ac cessible 31 26 25 0 Rese rved . Must be Zero Source Addres s Bit s [25: 0] Bit Descripti ons 31:26 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 196 12.3.14. BR13—BLT Raster OP, Control, and Destination Pitch Memor y Of fset Addres s: 40034h Default: 0000 xxxx Attributes: RO; DW ord a.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 197 Bit Descripti ons 28 M onochrome Pattern Transparency M ode. This bit applies only when the patt ern data is monoc hrome.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 198 12.3.15. BR14—Destination Width & Height Memor y Of fset Addres s: 40038h Default: None Attributes: RO; DW ord ac cessible BR14 contains the values for the heigh t and w idth of th e data to be BLT.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 199 12.3.16. BR15—Color Pattern A ddress Memor y Off set Addres s: 4003Ch Default: None Attributes: RO; DW ord ac cessible 31 26 25 16 Reserved. Must be Zero Color Patt ern Address Bits [25:16] 1 5 6 5 0 Color Patt ern Address B its [ 15:6] Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 200 12.3.17. BR16—Pattern Expansion Background & Sol id Pattern Color Memor y Of fset Addres s: 40040h Default: None Attributes: RO; DW ord ac cessible 31 24 23 0 Reserved. MBZ Pattern Expansion Bac kground Color Bi ts [23: 0] Bit Descripti ons 31:24 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 201 12.3.19. BR18—Source Expansion Background, and Destination Col or Memor y Of fset Addres s: 40048h Default: None Attributes: RO; DW ord ac cessible 31 24 23 0 Reserved. Must be Zero S ource Expansion Bac kground Color Bi ts [23: 0] Bit Descripti ons 31:24 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 202 12.3.21. S_SLA DD—Source Scan Line Address Memor y Of fset Addres s: 40074h Default: None Attributes: RO; DW ord ac cessible 31 26 25 0 Rese rved . Must be Zero Source Sc an Line Address Bits [25:0] Bit Descripti ons 31:26 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 203 12.3.23. D_SLRA DD—Destination Scan Line Read Address Memor y Off set Addres s: 4007Ch Default: None Attributes: RO; DW ord ac cessible 31 26 25 0 Rese rved . Must be Zero Destinat ion Scan Li ne Read Address B its [ 25:0] Bit Descripti ons 31:26 Reserved.
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Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 205 13. Rendering Engine Instructions This chapter describes the 3D instructions and motion com pensation instruction that controls the Graphics cont roller (GC) rendering en gine.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 206 13.1.3. Position Mask In Variable vertex f ormat, a position m ask is sent to indicate the present of X, Y, Z , and 1/W parameters. If 1/W (RHW) is declared not presen t in the vertex packet, hardw are forces 1/w equal to 1.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 207 13.1.6. Variabl e Length Vertex Formats for Render ing Instr uctions The GC support s variable l ength vertex f ormats . These form ats are determ ined, by enabl e bits contai ned in the variable leng th vertex f ormat (VLVF) instru ctions.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 208 13.1.7. GFXVERTEX Rendering Processor instructions include data per vertex . The vertex data form at is the sam e for these instructions. GFXVERTEX is not an instru ction, but a definition of this vertex data format.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 209 13.2. GFXRENDERSTA TE_VERTEX_FORMA T Flexible Vertex Form at Packet DWord Bi t Description 0 31:29 Clie nt : 03h – Render Proces sor 28:24 3DState24 : 05h 23:12 Reserved : 00h 11:8 Texture Coordinate C ount: This f ield identi fies how many c oordinates are pres ent in the vertex.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 210 13.3. GFXBLOCK The GFXBLOCK instruction is used w ith Motion Compensation. It is a variable leng th instruction, w hich contain s intra-coded/correction data at the end of th e instruction .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 211 DWord Bi ts Description 1 22 Cb Block Pattern: Enable/dis able intra-c oded/correc tion data for t he Cb block 21:18 Reserved: 00h 17:16 H.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 212 DWord Bi ts Description 2 31:26 Reserved: 00h 25:16 H orizontal Origin: An unsi gned integer spec ifying bot h the upper-left pixel of the destinat ion block and the origin of t he mot ion vectors in the referenc e frame(s ).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 213 13.3.1. Motion Vector Format The motion vectors provided in the GFXBLOCK instruction have th e followin g format.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 214 13.5. GFXRENDERSTA TE_MA P_TEXELS The Map ping Engi ne is ca pab le o f genera ting at most two texels p er p ixel. The texel s may be obt ained from tw o separate m aps or the sam e m ap usin g diff erent u ,v coordinat es.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 215 13.6. GFXRENDERSTA TE_MA P_COORD_SETS The Mapping En gine is capable of g enerati ng at m ost two m ap coordinate sets (u and v addres ses) per pixel. Each output texel m ay be related to sepa rate coordinate sets or to the same coordinate set, as show n below.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 216 DWord Bi t Descripti on 0 31:29 Client : 03h – Rendering Engine 28:24 3DS tate16 : 1Ch 23:19 Opcode : 1h 18:17 Reserved: 00h (Additi onal Coordinate Set s) 16 Update Coordinate Set Index : The valid range is 0–1.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 217 13.7. GFXRENDERSTA TE_MA P_INFO The Mapping Engine is capable of fetch ing texels f rom at most tw o maps per pixel. This instruction specifies the attributes relating to the location and format of th e map.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 218 Discrete Device Integrated Device Base A ddress Bi ts [31:26] Utilize Fe nce Registers Fence Range Hit Tiled Surface Til e Wal k Surface .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 219 DWord Bi t Descripti on 0 31:29 Cli ent : 03h – Rendering Engi ne 28:24 3DstateM W : 1Dh 23:16 Opcode : 0h 15:0 DWORD_LENGTH : 2h 1 31:29 Reserved: 00h 28 Update Map Index : The vali d range is 0–1.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 220 DWord Bi t Descripti on 1 18 Color S pace Conversion Enable: 0 = Do not perform conversi on. 1 = Perform color s pace convers ion assum ing bias ed chromananc e values. 17 Vertical Line Stride: The num ber of lines to ski p between logically adjac ent lines.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 221 DWord Bi t Descripti on 2 31 Dimensions are Powers of 2: This field s pecifies whether the following Height and Wid t h fields of the m ap are spec ified as the log 2 of t he actual dim ension or as the actual hei ght or width.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 222 13.8. GFXRENDERSTA TE_MA P_FILTER The Mapping Engine is capable of fetchin g texels/pixels from at most tw o maps per pixel. This instruction specifies the f ilter settings associated w ith specified map.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 223 DWord Bi t Description 0 31:29 Client : 03h – Rendering Engine 28:24 3DS tate16 : 1Ch 23:19 Opcode : 2h 18:17 Reserved: 00h (Additi onal Maps) 16 Update Map Index : The vali d range is 0–1.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 224 13.9. GFXRENDERSTA TE_MA P_LOD_LIMITS The limits of the Level of Detail calculation can be con trolled w ithin GC for each Map. These values are specified in the follow ing instruction as f ollows.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 225 13.10. GFXRENDERSTA TE_MA P_LOD_CONTROL The Level-of -Detail dither w eight and bias can be ass ociated with each map u sing th e followi ng instruction.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 226 13.11. GFXRENDERSTA TE_MA P_PA LETTE_LOA D The Texture Palette i s loaded usi ng th e follow ing i nstru ction. Al l 256 entries of the tex ture palett e mu st be loaded every time th is comm and packet is sent.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 227 13.12. GFXRENDERSTA TE_MA P_COLOR_BLEND_STA GES The Renderin g Engi ne support s three m ap color blend s tages f or the red, green, an d blue ch annels.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 228 Dword Bit Description 0 31:29 Cli ent : 03h – Rendering Engi ne 28:24 3DS tate24 : 00h 23:22 Reserved: 00h (Addit ional Blending S tages) 21:20 Update Blending Stage Index : The valid range is 0–2.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 229 Dword Bit Description 0 6 Invert C olor A rg2: 0 = Do not Invert A rgument 1 = Invert Argum ent 5 Color Operati on Mask : 0 = Do not update; 1 = Update 4:0 Col or Operation: Vali d values are : 00h = The user m ust explicit ly disable eac h blend stage t hat is not us ed.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 230 13.13. GFXRENDERSTA TE_MA P_A LPHA _BLEND_STA GES The Renderin g Engin e supports three m ap color blend st ages for th e alpha chan nel.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 231 The settings f or these stages are s pecified in the f ollowin g instruction . DWord Bi t Description 0 31:29 Cli ent : 03h – Rendering Engi ne 28:24 3DS tate24 : 01h 23:22 Reserved: 00h (Addit ional Blending S tages) 21:20 Update Blending Stage Index : The valid range is 0–2.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 232 DWord Bi t Description 0 4:0 A lpha Operation: Valid val ues are : 00h = Reserved (Enable/Dis able of s tage is program med i n the Color .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 233 13.15. GFXRENDERSTA TE_COLOR_CHROMA _KEY ColorKey and Chrom aKey are terms used to describe tw o methods of remov ing a specif ic color or range of colors from a m ap that is applied to a p rimitiv e.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 234 The In te l ® 810 ch ipset im plementati on of Blen d color/chrom a key m ode is, again , diff erent than w hat Microsoft eventually d efined for DX7* .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 235 13.16. GFXRENDERSTA TE_SRC_DST_BLEND_MONO The state variable Specular_RGB_Enable is set in th e graphics comm and GFXRENDERSTATE_ SRC_DST_B LEND_MONO.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 236 The Zero blend f actor is : Ro ut = 0 Gout = 0 Bout = 0 Aout = 0 The One blend factor is : Rout = Rin Gout = Gin Bout = Bin Aout = Ain The.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 237 Bit Description 31:29 Client : 03h – Rendering Proc essor 28:24 3DS tate24 : 08h 23:16 Reserved : 00h 15 Specular RGB S tate Mask : 0 = Do Not Update 1 = Update 14 Specular RGB E nable : 0 = Disable (def ault) 1 = Enable Controls s pecular col or interpolati on.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 238 13.17. GFXRENDERSTA TE_Z_BIA S_A LPHA _FUNC_REF DWord Bi t Description 0 31:29 Client : 03h – Render Process or 28:24 3DS tate24NP (Non-.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 239 13.18. GFXRENDERSTA TE_LINE_WIDTH_CULL_SHA DE_ MODE The provoking vertex ref ers to the vertex that selected the f lat shaded color for the primitive. In th e OpenGL* specification, the third/second (triangle/lin e) vertex should us ed.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 240 DWord Bi t Description 0 31:29 C lient : 03h – Render Process or 28:24 3DState24 : 02h 23 Reserved 22:21 Reserved 20 Z Function State Ma.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 241 13.19. GFXRENDERSTA TE_BOOLEA N_ENA _1 Dword Bit Description 0 31:29 Client : 03h – Render P rocess or 28:24 3DState24 : 03h 23:20 Reser.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 242 13.20. GFXRENDERSTA TE_BOOLEA N_ENA _2 DWord Bi t Description 0 31:29 C lient : 03h – Render Process or 28:24 3DState24 : 04h 23:18 Rese.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 243 13.21. GFXRENDERSTA TE_FOG_COLOR The GFXRENDERST ATE_FOG_COLOR state instruction form at is: DWord Bi t Descri ption 0 31:29 Client : 03h – Render Process or 28:24 3DState24NP (Non-pi pelined) : 15h 23:19 Fog Color Red : Bits 7:3 of t he red fog color c omponent.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 244 DWord Bi ts Description 0 31:29 Client : 03h – Rendering Engine 28:24 3DStateM WNP (Non-pipelined) : 1Dh 23:16 Opcode : 80h 15:0 DW ORD_LENGTH : 3 1 31 Draw ing/Sci ssor Rectangle clipping E nable (for validati on purpose only).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 245 13.23. GFXRENDERSTA TE_SCISSOR_ENA BLE Only inclusiv e mode sc issorin g is su pported. Pixel Ali gned Drawi ng W i ndow Pi xel Al igned C.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 246 13.24. GFXRENDERSTA TE_SCISSOR_RECTA NGLE_INFO The coordinate in this instruction packet is relative to th e origin (upper left corner, DWord #4) o f the draw ing rectangl e defined in th e GFXRENDERSTATE_DRAWING_RECTANGL E_INFO packet.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 247 13.25. Stipple Pattern The stipple pattern is a 4x4 b it mem o ry th at serves as pixel w rite mask. When stipple is enabled, the frame bu ffer w ill only be updated w ith pixels that have 1’s in their associated stipple pattern memory locations.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 248 13.26. GFXRENDERSTA TE_A NTI_A LIA SING The Anti-aliasing packet defines the anti- aliasing enable, bounding-box ex pansion, line anti-aliasing region, poly gon anti-aliasin g region , and edge fl ag enable State variables .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 249 13.27. GFXRENDERSTA TE_PROVOKING_VTX_PIXELIZA TION _RULE The provoking vertex state variables provide the flexibility of selecting th e flat-shaded vertex f or the first triangle/line of a primitive packet.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 250 DWord Bi ts Description 0 31:29 Cl ient : 03h – Rendering Engine 28:24 3DS tate24 : 07h 23:13 Reserved: 0000h 12 Small Triangle Filter Enable M ask : 1 = Update ; 0 = Do Not Updat e 11 Small Triangle Fi lter Enable: I f Set then Sm all Triangles i.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 251 13.28. GFXRENDERSTA TE_DEST_BUFFER_VA RIA BLES The GFXRENDERSTAT E_DEST _BUFFER_VARIABLES instruction is us ed to specify the inform ation about the destination buffer. This inf ormation is us ed to initialize rendering hardw are parameters .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 252 DWord Bi t Description 1 31:24 Reserved: 00h 23:20 Desti nation Origi n Horizontal Bi as: This i s an unsigned val ue (0.4) that i s used to bias the ori gin of the X values ass ociated with t he vertices of a prim itive.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 253 13.29. Programming Hints/Rules The following provides pr ogramm ing hints/rules for 3D, Motion Compensation , and Stretch Blitter operations.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 254 3D ins truction GFXRENDER STATE_BOOLEA N_EN_2. To ensure proper h ardwa re operation, softw are must f ollow up w ith the GFXCMDPARSER_FLUSH instru ction to cause the hardw are to flu sh th e 3D pipeline.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 255 • Z buf ferin g is n ot support ed (Z_en i s overloaded to 0). • State va riables th at have a con text1 are: blen d_en, dest_bl end(3:0), src_blen d(3:0), xoff set(11:0), yof fset(11:0), all Dest Buf fer form at variable packet, all Map Info packet, Map Cach e enable.
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Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 257 14. Clock Control Registers The clock control registers are accessed by w riting to the m emory mapped address offset. The In te l ® 815 ch ipset has three PLL s to gen erate all the cl ocks.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 258 Example Programm ing Sequence (DCLK2) 1. Write the Display Clock 2 Divisor register w ith the M-REG valu e and N-REG value. 2. Write the clock 2 b yte of th e Display & L CD Clock Divisor Select Register w ith the P-REG value.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 259 14.3. DCLK_1D—Display Clock 1 Div isor Register Address O ff set: 06004h–06007h Default Value: 00100053h Attribute: R/W Size: 32 bits .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 260 14.4. DCLK_2D—Display Clock 2 Div isor Register Address O ff set: 06008h–0600Bh Default Value: 00030013h Attribute: R/W Size: 32 bits .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 261 14.5. LCD_CLKD—LCD Clock Divisor Register Address O ffs et: 0600Ch–0600Fh Default Value: 00030013h Attribute: R/W Size: 32 bits The LC.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 262 14.6. DCLK_0DS—Display & LCD Clock Div isor Select Register Address O ff set: 06010h–06013h Default Value: 40404040h Attributes: R/W Size: 32 bits Display clock i {i=0 to 2} becomes effective af ter program min g the appropriate byte i {i = 0 to 2}in this register.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 263 Bit Description 22:20 Post Divisor Sel ect clock 2. 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 (default ) 101 = Divide by 32 11x = Reserved 19 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 264 14.7. PWR_CLKC—Pow er Management and Miscellaneous Clock Control Address O ff set: 6014h–06017h Default Value: 0000 0101 h Attribute: .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 265 15. Overlay Registers This chapter contain s the Overlay and Gam ma C orrection registers and an Overlay instruction. The current g raphics controller im plements one ov erlay th at is referred to as Overlay 0.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 266 Table 16. Ov erlay Register/Instruct ion Catego ries Register/Instructi on Category Mem . A ddress Offset Comment Overlay 0 Regist er Update Address (OV0ADD) 30000h • Us ed to update Overlay 0 regis ters.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 267 15.1. OV0A DD—Ov erlay 0 Register Update A ddress Register Memor y Address Off set: 30000h–30003h Default Value: 00000000 Access: R /W Size: 32 bits This register provides a physical m emory address that will be us ed on the next register u pdate for Overlay 0.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 268 15.2. DOV0STA —Display /Overlay 0 Status Register Memor y Address Off set: 30008h–3000Bh Default Value: 0000 5000h Access: R O Size: 32 bits This read-only register in dicates the statu s for the overlay .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 269 Bit Descripti on 20:19 Overlay 0 Current Buffer/Field. This f ield indic ates t he Current Buff er. Updated at di splay VB LANK before the int errupt, thi s fiel d is only valid when in field (interlac ed) mode.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 270 These registers determine th e characteristics of the gam ma correction for the overlay data. Each register is 32 bits wide. The registers are w ritten to and read from together w hen accessed from the PCI.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 271 15.3.1.2. Mathematical Gamma Correction For Ov erlay Gamm a correction is a function that corrects for non -linearity betw een display phosphor brigh tness as a fun ction of electron beam current.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 272 As show n, the inputs to the function are: • PCI Regis ter Bus: The chip in ternal PCI data bus an d the appropriate regist er decodes f.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 273 The following g ives a more detailed description of the algorithm . A line w ith tw o coord inate points as (x1, y 1) and (x2, y 2 ) can b.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 274 15.4. Memory Offset Registers 15.4.1. Overlay Buffer Pointer Registers These regist ers provide address poin ters into th e sys tem m emory or L ocal mem o ry buffer areas . The buff ers m ust be QWord aligne d.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 275 15.4.1.2. OBUF_1Y—Overlay Buffer 1 Y Pointer Register Memor y Address Off set: 04h (R/W ) On-chip Reg.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 276 15.4.1.4. OBUF_0V—Overlay Buffer 0 V Pointer Register Memor y Address O ff set: 0Ch (R/W ) On-chip Reg.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 277 15.4.1.6. OBUF_1V—Overlay Buffer 1 V Pointer Register Memor y Address Off set: 14h (R/W ) On-chip Reg.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 278 15.4.3. Overlay Initial Phase Registers Provides a spatial sub-pixel accurate adjustment. This value is alw ays a f ractional positive number that wh en combined w ith the subtract one from initial phase bit, the possible range for in itial phase becomes - 1<phase<1.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 279 15.4.3.2. UV_VPH—UV Vertical Phase Register Memor y Address Off set: 20h (R/W ) On-chip Reg.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 280 15.4.3.4. INIT_PH—Initial Phase Register Memor y Address Off set: 28h (R/W ) On-chip Reg. Mem Addr O ffs et: 30128h (RO ; debug path) Default Value: 00h Access : s ee address of fset above Size: 32 bits 31 6 5 0 Reserved Init ial Phas e minus one Bit Descripti on 31:6 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 281 15.4.4. Overlay Desti nation Window Position/Size Regi sters These registers allow f or the positioning of the overlay data relative to the graphics display or the secondary display active region.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 282 15.4.5. Overlay Source Size Registers These regist ers provide inf ormation to th e overlay engin e on w hat data needs to be f etched from memory .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 283 15.4.5.2. SWIDQW—Source Width In QWords Register Memor y Address Off set: 38h (R/W ) On-chip Reg.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 284 15.4.5.3. SHEIGHT—Source Height Register Memor y Address O ff set: 3Ch (R/W ) On-chip Reg.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 285 15.4.6. Overlay Scale Factor Registers These registers provide the scaling inform ation that is u sed to specify the am ount of vertical and horizontal scaling.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 286 15.4.6.2. UVSCA LE—UV Scale Factor Register Memor y Address Off set: 44h (R/W ) On-chip Reg.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 287 15.4.7. Overlay Color Correction Registers Used for YUV sources only. A djustments are m ade before the RGB conversion. 15.4.7.1. OV0CLRC0—Overlay 0 Color Correction 0 Register Memor y Address Off set: 48h (R/W ) On-chip Reg.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 288 15.4.8. Overlay Destination Color Key Registers Used for YUV sources only. A djustments are m ade before the RGB conversion. 15.4.8.1. DCLRKV—Destination Co lor Key Value Register Memor y Address Off set: 50h (R/W ) On-chip Reg.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 289 15.4.8.2. DCLRKM—Destinat ion Color Key Mask Register Memor y Address Off set: 54h (R/W ) On-chip Reg.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 290 15.4.9. Overlay Source Color Key Registers There is an overlay source key per overlay stream, w hich is used on a pix el basis. The Source comparison occu rs after the h orizontal zoomin g, but in th e YUV formats bef ore the color space conversion.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 291 15.4.9.2. SCLRKVL—Source Color Key Value Low Register Memor y Address O ff set: 5Ch (R/W ) On-chip Reg.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 292 Bit Descripti on 31 Source Constant A lpha Blend Enable. 1 = Enable Sourc e Alpha Blendi ng when the logical OR of t he Source Key Mas k Enables are asserted within the Alpha B lend W indow, and the c omparis on indicat es that the overlay is t o be displayed.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 293 15.4.10. Overlay Configuration Registers There is only 1 Overlay Config uration regis ter wh ich controls both overlay stream s. It is read from mem ory with Overlay 0 register loads du ring Vertical Blank .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 294 15.4.11. OV0CMD—Overlay Command Register Memor y Address Off set: 68h (R/W ) On-chip Reg. Mem Addr O ffs et: 30168h (RO ; debug path) Default Value: 00h Access : s ee address of fset above Size: 32 bits This register provides the data the overlay eng ine needs to begin w ork.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 295 Bit Descripti on 31 Select top overlay . Reserved for f uture im plem enations 30:28 Vertical Chrom inance Filter.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 296 Bit Descripti on 15:14 4:2: 2 By te Order. Aff ects the byte order for 4: 2:2 data. For ot her data form ats t hese bits should be set to ze ro. 00 = Normal 01 = UV Swap 10 = Y Swap 11 = Y and UV swap 13:10 Source Format.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 297 Bit Descripti on 5 Display/Flip T y pe. This bit af fect s the buff er addressing us ed for buff er display and the us e of the initial vertical phas e.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 298 15.4.12. Overlay Alpha Blend Window Posi tion/Siz e Registers These registers allow f or the alpha blending of a subsection of th e overlay w indow positioning of the overlay data relative to the g raphics display or the secondary display active region.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 299 15.4.12.2. A W INSZ—A lpha Blend W indow Size Register Memor y Address Off set: 74h (R/W ) On-chip Reg.
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Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 301 16. Instruction, M emory, and Interrupt Control Registers 16.1. Instruction Control Registers 16.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 302 Bit Descripti on 31:26 Reserved for address bits 31 downto 26 25:19 Fence Lower Bound : Memory address bits 25 downto 19 (Must be size aligned) 18:15 Reserved 14:13 Reserved: MBZ (“00” ) 12 Tile walk 0 = X Major 1= Y Major.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 303 16.1.2. PGTBL_CTL—Page Table Control Regi ster Address O ff set: 02020h Default Value: 00000000h Access : Read/W rite Size: 32 bits This register en ables/disables th e page table mech anism and w hen en abled, also sets the base addres s of the 4 KB alig ned page table.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 304 16.1.3. PGTBL_ER—Page Table Error Register Address O ff set: 02024h (identical f unctionality in Device 0 at EC–EFh) Default Value: 0000 0000h Acces s: Read Only Size: 32 bits This register sto res information pertaining to page table error interrupts.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 305 Bit Descripti on 2:0 E rror Ty pe: 000 = Invalid Table 001 = Invalid P age table entry 010 = Incorrec t target for Displ ay surfac e (Request to l m if the surf ace start ed in mm or vic e versa)/Overl ay surface (Reques t to l m).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 306 16.1.4. PGTBL_ERRMSK—Page Table Error M ask Register Address O ff set: 02028h (identical f unctionality in Device 0 at F0–F3h) Default Value: 0000 0000h Access : Read/W rite Size: 32 bits This register is new to the Intel ® 815 ch ipset (i.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 307 Bit Descripti ons 31:9 Reserved. 8 Buffer Uni t Page Table Error Mask. 0 = Not Masked (def ault) 1 = M asked 7 Com mand Streamer DM A P age Table Error Mask. 0 = Not Masked (def ault) 1 = M asked 6 Overl ay P age Table Error Mask.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 308 16.1.5. RINGBUF—Ring Buffer Registers Address O ff set: 02030h – 0207Fh 02030h – 0203Fh: Low Priority Ring 02040h – 0204Fh: Interr.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 309 Dword Offset Bit Description 0 31:21 Reserved. 20:3 Ta il Pointer : Programmabl e Qword Offset in t he ring buffer (20: 3 is used by t he hardware).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 310 16.1.6. HWS_PGA —Hardw are Status Page A ddress Register Address O ff set: 02080h Default Value: 1FFFF000h. Access : Read/W rite Size: 32 bits Hardw are statu s page ph ysi cal address. The prog ramm ed address shoul d be 4 KB alig ned.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 311 16.1.7. IPEIR—Instr uction Parser Err or Identifi cation Register (debug) Address O ff set: 02088h Default Value: 0000h Acces s: Read Only Size: 32 bits This register is used to help identify th e instruction packet that g enerates an invalid instru ction interrupt to the p rocessor.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 312 16.1.9. INSTDONE—Instruction Stream Interface Done Register Address O ff set: 02090h Default Val ue: FFFF FFFFh Acces s: Read only . Size: 32 bits This read only regi ster r epo rts engi ne do ne signals.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 313 Bit Descripti on 4 Render Engine Done 3 Batch Done 2 Reserved 1 Intr. Ri ng Empt y or Disabled 0 Low Priority Ring Em pty or Dis abled 16.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 314 16.1.11. INSTPM—Instruction Parser M ode Register Address O ffs et: 020C0h Default Value: 00h Access : Read/W rite Size: 8 bits The bits in this register control the operation of the In struction Parser.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 315 16.1.12. I NSTPS—Instruction Parser State Register (debug) Address O ffs et: 020C4h Default Value: 0000h Acces s: Read Only Size: 32 bits This register contains the state code of the Instruction Parser in the CSI.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 316 Bit Description 11:10 CS DMA State Machine: Is respons ible for t he control of the DMA FIFO. I t get request s from the arbitration s tate m achine. It m anages the FI FO so that reques ts are only m ade when there is s pace in the FIFO.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 317 16.1.13. BBP_PTR—Batch Buffer Parser Poi nter Register (debug) Address O ffs et: 020C8h Default Value: 00000000h Acces s: Read Only Size: 32 bits This regis ter contain s the of fset f rom the batch bu ffe r start address of th e DWord bei ng pars ed by th e Instru ction Parser.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 318 16.1.15. A BB_END—Active Batch Buffer End A ddress Regi ster (debug) Address O ffs et: 020D0h Default Value: 00000000h Acces s: Read Only Size: 32 bits This register is loaded with the end address of the Batch Buf fer requ est.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 319 16.1.17. M EM _M ODE—Memor y Inter face Mode Regi ster (debug) Address O ffs et: 020DCh Default Value: 00000000h Access : Read/W rite Si.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 320 16.2. Interrupt Control Registers The interrupt control registers described be low all sh are the same bit definition.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 321 Bit Description 9 Overlay 0 Flip Pending. S tatus bi t is s et to refl ect a pending f lip when the parser parses a flip pac ket and clear.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 322 16.2.1. HWSTA M—Hardw are Status M ask Register Address O ff set: 02098h Default Val ue: FFFFh Access : Read/W rite Size: 16 bits This register h as the sam e format as the In terrupt Control Re gisters.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 323 16.2.2. IER—Interrupt Enable Register Address O ff set: 020A0h Default Value: 0000h Access : Read/W rite Size: 16 bits Individual enables f or each interrupt described above.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 324 16.2.3. IIR—Interrupt Identity Register Address O ff set: 020A4h Default Value: 0000h Access : Read/W rite Clear Size: 16 bits The individual interrupt(s), w hich occurred, are determined via th is register.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 325 16.2.4. IMR—Interrupt M ask Register Address O ff set: 020A8h Default Val ue: FFFFh Access : Read/W rite Size: 16 bits An interru pt that is mask ed by this register w ill not ap pear in the Interrupt Identity Register and w ill not generate an in terrupt.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 326 16.2.5. ISR—Interrupt Status Register Address O ff set: 020ACh Default Value: 0100h (probably still not quite correc t value) Acces s: Read Only Size: 16 bits This register cont ains the non -persistent v alue of the s ignals cau sing each in terrupt.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 327 16.2.6. Error Identity , M ask and Status Registers The Error Identity, Mask, and Statu s registers have th e followin g bit descriptions.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 328 16.2.6.2. Resetting the Page Table Error The page table error will be reset every time a w rite cycle is g enerated to bit 15 of the Interrupt Identity register (IIR ), independent of th e setting of the bit in the IMR or the IER.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 329 16.2.6.3. EIR—Error Identity Register Address O ff set: 020B0h Default Value: 00h Access : Read/W rite Clear Size: 16 bits 15 6 5 4 3 2 .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 330 16.2.6.5. ESR—Error Status Register Address O ff set: 020B8h Default Value: F Fh Acces s: Read Only Size: 16 bits 15 6 5 4 3 2 1 0 Reser.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 331 16.3. Display Interface Control 16.3.1. FW_BLC—FIFO Watermar k and Burst Length Control Address O ffs et : 020D8h Default Value: 22 31 73 17h Access : Read/W rite Size: 32 bits These control values only apply to HIRes modes of operation.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 332 Bit Description 31:28 O v e r l a y D e l ay T i m e r 1 . Is used to ins ert waits s tates i n between sets of YUVY request s to MM. The value in this register i s m ultiplied by 16 t o determ ine the wait st ate cloc k count .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 333 17. LCD / TV-Out Register Description During LCD or T V-Out m ode, the BIOS will program the f ollowing L CD / TV-Out registers. These registers are 32-bit mem ory mapped. These reg isters are not dou ble buff ered and take ef fect w hen loaded.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 334 17.2. HBLA NK—Horizontal Blank Register Address O ff set: 60004h Default Value: 00000000h Access : Read/W rite Size: 32 bits 31 28 27 16 Reserved Horizontal B lank End 15 12 11 0 Reserved Horizontal Blank S tart Bit Descripti on 31:28 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 335 17.3. HSYNC—Horizontal Sync Register Address O ff set: 60008h Default Value: 00000000h Access : Read/W rite Size: 32 bits 31 28 27 16 Reserved Horizontal Sync End 15 12 11 0 Reserved Horizontal Sync St art Bit Descripti on 31:28 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 336 17.4. VTOTA L—Vertical Total Register Address O ffs et: 6000Ch Default Value: 00000000h Access : Read/W rite Size: 32 bits 31 28 27 16 Reserv ed Ver tical Total Display Pixe ls 15 11 10 0 Reserv ed Ve rtical Active Displa y Pix els Bit Descripti on 31:28 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 337 17.5. VBLA NK—Vertical Blank Register Address O ff set: 60010h Default Value: 00000000h Access : Read/W rite Size: 32 bits 31 28 27 16 Reserved Vert ical Blank End 15 12 11 0 Reserved Vert ical Blank Start Bit Descripti on 31:28 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 338 17.6. VSYNC—Vertical Sync Register Address O ff set: 60014h Default Value: 00000000h Access : Read/W rite Size: 32 bits 31 28 27 16 Reserved Vert ical Sync End 15 12 11 0 Reserved Vert ical S ync S tart Bit Descripti on 31:28 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 339 17.7. LCDTV_C—LCD/TV-Out Control Register Address O ff set: 60018h Default Value: 00000000h Access : Read/W rite Size: 32 bits 31 30 29 .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 340 Bit Descripti on 28 FP VESA VGA Mode 0 = Disable. Us e the LCD / TV Timing Generat or. VGA S ync Polarit y is ignored. FP Sync Polarit y is used. Centeri ng can be enabled for f ixed resolution flat panels or TVs .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 341 Bit Descripti on 8 FPHSYNC Output Control. 1 = Tristat es the FPHSY NC pin. 0 = FPHSYNC is active unl ess LCD / TV Out Enable is deassert ed. 7 Border E nable. 1 = Border to the LCD / TV encoder is enabled.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 342 17.8. OVRA CT—Ov erlay A ctiv e Register Address O ffs et: 6001Ch Default Value: 00000000h Access : Read/W rite Size: 32 bits 31 27 26 16 Reserved Overlay Active End 15 12 11 0 Reserved Overlay Act ive Start Bit Descripti on 31:27 Reserved.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 343 18. Local M emory Interface 18.1. DRT—DRA M Row Ty pe Address of fs et : 03000h Default value : 00h Access : Read / write Size : 8 bit This 8-bi t register i dentifi es w hether or n ot the local m emory is populate d.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 344 18.2. DRA MCL—DRA M Control Low Address of fs et : 03001h Default value : 17h Access : Read / write Size : 8 bit 7 5 4 3 2 1 0 Reserved Paging Mode Control RAS-to- CAS Override CAS# Latency RAS# Rimi ng RAS# Precharge Timing Bit Descripti on 7:5 Reserved 4 Paging Mode Control (PMC).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 345 18.3. DRA MCH—DRA M Control High Address of fs et : 03002h Default value : 08h Access : Read / write Size : 8 bit 7 5 4 3 2 0 Reserved DRAM Refresh Rate Special Mode Sel ect Bit Descripti on 7:5 Reserved 4:3 DRAM Refresh Rate (DRR).
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Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 347 19. I/O Control Registers 19.1. HVSYNC—HSYNC/VSYNC Control Register Address O ff set: 05000h Default Value: 00000000h Size: 32 bits Attribute: R/W Bits 19:16 are for DPMS and DDC Sy nc Select.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 348 19.2. GPIO Registers 19.2.1. GPIOA General Pur pose I/O Contr ol Register A Address of fs et : 05010h Default value : 00h,.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 349 Bit Description 8 DDDA Direction M ask—R/W : This i s a m ask bit to determ ine whether the GPIO DIRECTION V A L UE bit shoul d be written into the regi ster. 0 = Do NOT write DDDA Direct ion Value bit (default).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 350 19.2.2. GPIOB General Pur pose I/O Contr ol Register B Address of fs et : 05014h Default value : 00h, 00h, 000U0000b, 000U.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 351 Bit Description 8 LTVDA Direction M ask—R/W : This is a m ask bit to determ ine whether the GPIO DIRECTION VA LUE bit should be written int o the regist er. 0 = Do NOT write LTVDA Direct ion Value bit (default).
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Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 353 20. Display And Cursor Registers The follow ing are cu rsor, display, an d pixel pipe regis ters in address range 70000h–7FFFFh .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 354 20.2. DISP_SLC—Display Scan Line Count Range Compare Memor y Of fset Addres s: 70004h Default: 0000h Attributes: Read only The Top and B.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 355 20.3. Pixel Pipeline Control 20.3.1. PIXCONF—Pixel Pipeline Configuration Memor y Of fset Addres s: 70008h Default: 00000000h Attributes.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 356 Bit Descripti ons 19:16 Display Color Mode. 0000 = CRT standard VG A text and graphics mode and 1-bit /2-bit/4-bi t pack ed graphics m ode (Default). 0001 = Reserved. 0010 = CRT 8-bit pack ed extended graphics m ode.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 357 Bit Descripti ons 0 GUI Mode. 0 = Standard VGA and extended 4 bpp/16 color resolutions (default). Can s till acc ess m emory in linear mode. 1 = High Resolut ion (i.e., not VGA or extended planar).
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 358 20.3.4. DPLYBA SE—Display Base A ddress Register Memor y Of fset Addres s: 70020h Default: 0000h Attributes: Read/W rite The display can be read from g raphics mem ory. This register is the display staging reg ister wh en w ritten.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 359 20.3.5. DPLYSTA S—Display Status Select Register Memor y Of fset Addres s: 70024h Default: 0000h Attributes: Read/W rite This register selects the proper events to be signaled to the Interrupt Control Register in th e comm and stream .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 360 Bit Descripti ons 23:18 Reserved. 17 Verti cal Blank Enabl e. 0 = Vertic al Blank S tatus Disabled 1 = Vertic al Blank S tatus E nabled 16 Overlay Registers Upated Enable.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 361 20.4. Hardw are Cursor The hardware cursor registers are memory m apped and accessible through 3 2 bit accesses. 20.4.1. CURCNTR—Cursor Contr ol Register Memor y Of fset Addres s: 70080h Default: 0000h Attributes: Read/W rite This register is double buff ered.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 362 20.4.2. CURBA SE—Cur sor Base A ddress Register Memor y Of fset Addres s: 70084h Default: 0000h Attributes: Read/W rite The cursor can on ly be read f rom Sy stem me mory . This register is double buf fered.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 363 21. Appendix A: M ode Parameters This appendix contain s the regi ster program ming i nform ation on a per-m ode basis. Ref er to the appropriate table for the specif ic values to u se in order to correctly program the graphics adapter for the desired m ode and frequen cy com b ination.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 364 Parameters for Screen Resolu tion/Refresh Rate: 320x200_70Hz = Dot Clock Value 25 // 25. 175-MHz Dot Clock M Value 0x0013 N Value 0x 0003 .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 365 Parameters for Screen Resolu tion/Refresh Rate: 320x240_70Hz = Dot Clock Value 31 //31-MHz Dot Cloc k M Value 0x0013 N Value 0x 0002 P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 366 Parameters for Screen Resolu tion/Refresh Rate: 352X480_70Hz = Dot Clock Value 15 //15.68-MHz Dot Clock M Value 0x000D N Value 0x 0001 P V.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 367 Parameters for Screen Resolu tion/Refresh Rate: 352X576_70Hz = Dot Clock Value 19 //19-MHz Dot Cloc k M Value 0x0011 N Value 0x 0004 P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 368 Parameters for Screen Resolu tion/Refresh Rate: 400x300_70Hz = Dot Clock Value 49 //49-MHz Dot Cloc k M Value 0x001F N Value 0x 0006 P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 369 Parameters for Screen Resolu tion/Refresh Rate: 512X384_70Hz = Dot Clock Value 82 //82-MHz Dot Cloc k M Value 0x0027 N Value 0x 000A P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 370 Parameters for Screen Resolu tion/Refresh Rate: 640x350_85Hz = Dot Clock Value 31 //31.5-MHz Dot Clock M Value 0x0013 N Value 0x 0002 P Va.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 371 Parameters for Screen Resolu tion/Refresh Rate: 640x400_70Hz = Dot Clock Value 25 //25.175-MHz Dot Clock M Value 0x0013 N Value 0x 0003 P .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 372 Parameters for Screen Resolu tion/Refresh Rate: 640x400_85Hz = Dot Clock Value 31 //31.5-MHz Dot Clock M Value 0x0013 N Value 0x 0002 P Va.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 373 Parameters for Screen Resolu tion/Refresh Rate: 640x480_60Hz = Dot Clock Value 25 //25.175-MHz Dot Clock M Value 0x0013 N Value 0x 0003 P .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 374 Parameters for Screen Resolu tion/Refresh Rate: 640x480_70Hz = Dot Clock Value 28 //28-MHz Dot Cloc k M Value 0x0053 N Value 0x 0010 P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 375 Parameters for Screen Resolu tion/Refresh Rate: 640x480_72Hz = Dot C lock Value 31 //31.5- MHz Dot C lock M Value 0x0013 N Value 0x 0002 P.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 376 Parameters for Screen Resolu tion/Refresh Rate: 640x480_75Hz = Dot Clock Value 31 //31.5-MHz Dot Clock M Value 0x0013 N Value 0x 0002 P Va.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 377 Parameters for Screen Resolu tion/Refresh Rate: 640x480_85Hz = Dot Clock Value 36 //36-MHz Dot Cloc k M Value 0x0010 N Value 0x 0001 P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 378 Parameters for Screen Resolu tion/Refresh Rate: 720x400_85Hz = Dot Clock Value 35 //35.5-MHz Dot Clock M Value 0x0045 N Value 0x 000A P Va.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 379 Parameters for Screen Resolu tion/Refresh Rate: 720x480_60Hz = Dot Clock Value 28 //28.322-MHz Dot Clock M Value 0x0053 N Value 0x 0010 P .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 380 Parameters for Screen Resolu tion/Refresh Rate: 720x480_75Hz = Dot Clock Value 35 //35-MHz Dot Cloc k M Value 0x0021 N Value 0x 0004 P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 381 Parameters for Screen Resolu tion/Refresh Rate: 720x480_85Hz = Dot Clock Value 40 //40-MHz Dot Cloc k M Value 0x0008 N Value 0x 0001 P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 382 Parameters for Screen Resolu tion/Refresh Rate: 720x576_60Hz = Dot Clock Value 33 //33-MHz Dot Cloc k M Value 0x0014 N Value 0x 0002 P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 383 Parameters for Screen Resolu tion/Refresh Rate: 720x576_75Hz = Dot Clock Value 43 //43-MHz Dot Cloc k M Value 0x0029 N Value 0x 000A P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 384 Parameters for Screen Resolu tion/Refresh Rate: 720x576_85Hz = Dot Clock Value 49 //49.5-MHz Dot Clock M Value 0x001F N Value 0x 0006 P Va.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 385 Parameters for Screen Resolu tion/Refresh Rate: 800x600_56Hz = Dot Clock Value 36 //36-MHz Dot Cloc k M Value 0x0010 N Value 0x 0001 P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 386 Parameters for Screen Resolu tion/Refresh Rate: 800x600_60Hz = Dot Clock Value 40 //40-MHz Dot Cloc k M Value 0x0008 N Value 0x 0001 P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 387 Parameters for Screen Resolu tion/Refresh Rate: 800x600_70Hz = Dot Clock Value 45 //45-MHz Dot Cloc k M Value 0x0054 N Value 0x 0015 P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 388 Parameters for Screen Resolu tion/Refresh Rate: 800x600_72Hz = Dot Clock Value 50 //50-MHz Dot Cloc k M Value 0x0017 N Value 0x 0004 P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 389 Parameters for Screen Resolu tion/Refresh Rate: 800x600_75Hz = Dot Clock Value 49 //49.5-MHz Dot Clock M Value 0x001F N Value 0x 0006 P Va.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 390 Parameters for Screen Resolu tion/Refresh Rate: 800x600_85Hz = Dot Clock Value 56 //56.25-MHz Dot Clock M Value 0x0049 N Value 0x 000E P V.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 391 Parameters for Screen Resolu tion/Refresh Rate: 854X480_60Hz = Dot Clock Value 43 //43-MHz Dot Cloc k M Value 0x0029 N Value 0x 000A P Val.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 392 Parameters for Screen Resolu tion/Refresh Rate: 854X480_75Hz = Dot Clock Value 41 //41.54-MHz Dot Clock M Value 0x002B N Value 0x 000B P V.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 393 Parameters for Screen Resolu tion/Refresh Rate: 854X480_85Hz = Dot C lock Value 48 //Dot Cl ock M Value 0x000A N Value 0x 0001 P Value 0x3.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 394 Parameters for Screen Resolu tion/Refresh Rate: 1024X768_60Hz = Dot Clock Value 65 //65-MHz Dot Cloc k M Value 0x003F N Value 0x 000A P Va.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 395 Parameters for Screen Resolu tion/Refresh Rate: 1024X768_70Hz = Dot Clock Value 75 //75-MHz Dot Cloc k M Value 0x0017 N Value 0x 0002 P Va.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 396 Parameters for Screen Resolu tion/Refresh Rate: 1024X768_75Hz = Dot Clock Value 78 //78.75-MHz Dot Clock M Value 0x0050 N Value 0x 0017 P .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 397 Parameters for Screen Resolu tion/Refresh Rate: 1024X768_85Hz = Dot Clock Value 94 //94.5-MHz Dot Clock M Value 0x003D N Value 0x 000E P V.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 398 Parameters for Screen Resolu tion/Refresh Rate: 1152X864_60Hz = Dot Clock Value 80 //80-MHz Dot Cloc k M Value 0x0008 N Value 0x 0001 P Va.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 399 Parameters for Screen Resolu tion/Refresh Rate: 1152X864_70Hz = Dot Clock Value 96 //96-MHz Dot Cloc k M Value 0x000A N Value 0x 0001 P Va.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 400 Parameters for Screen Resolu tion/Refresh Rate: 1152X864_72Hz = Dot Clock Value 99 //99-MHz Dot Cloc k M Value 0x001F N Value 0x 0006 P Va.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 401 Parameters for Screen Resolu tion/Refresh Rate: 1152X864_75Hz = Dot Clock Value 108 //108-MHz Dot Cloc k M Value 0x0010 N Value 0x 0002 P .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 402 Parameters for Screen Resolu tion/Refresh Rate: 1152X864_85Hz = Dot Clock Value 121 //121-MHz Dot Cloc k M Value 0x006D N Value 0x 0014 P .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 403 Parameters for Screen Resolu tion/Refresh Rate: 1280x720_60Hz = Dot Clock Value 74 //74-MHz Dot Cloc k M Value 0x0023 N Value 0x 0004 P Va.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 404 Parameters for Screen Resolu tion/Refresh Rate: 1280x720_75Hz = Dot Clock Value 96 //96-MHz Dot Cloc k M Value 0x000A N Value 0x 0001 P Va.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 405 Parameters for Screen Resolu tion/Refresh Rate: 1280x720_85Hz = Dot Clock Value 110 //110-MHz Dot Cloc k M Value 0x0035 N Value 0x 000A P .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 406 Parameters for Screen Resolu tion/Refresh Rate: 1280x960_60Hz = Dot Clock Value 108 //108-MHz Dot Cloc k M Value 0x0010 N Value 0x 0002 P .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 407 Parameters for Screen Resolu tion/Refresh Rate: 1280x960_75Hz = Dot Clock Value 129 //129-MHz Dot Cloc k M Value 0x0029 N Value 0x 0006 P .
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 408 Parameters for Screen Resolu tion/Refresh Rate: 1280x960_85Hz = Dot Clock Value 148 //148.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 409 Parameters for Screen Resolu tion/Refresh Rate: 1280x1024_60Hz = Dot Clock Value 108 //108-MHz Dot Cloc k M Value 0x0010 N Value 0x 0002 P.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 410 Parameters for Screen Resolu tion/Refresh Rate: 1280x1024_70Hz = Dot Clock Value 129 //128.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 411 Parameters for Screen Resolu tion/Refresh Rate: 1280x1024_72Hz = Dot Clock Value 132 //132-MHz Dot Cloc k //NOTI NVES A M Value 0x0014 N V.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 412 Parameters for Screen Resolu tion/Refresh Rate: 1280x1024_75Hz = Dot Clock Value 135 //135-MHz Dot Cloc k M Value 0x002B N Value 0x 0006 P.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 413 Parameters for Screen Resolu tion/Refresh Rate: 1280x1024_85Hz = Dot Clock Value 157 //157.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 414 Parameters for Screen Resolu tion/Refresh Rate: 1600x900_60Hz = Dot Clock Value 119 //Dot Cl ock M Value 0x006B N Value 0x 0014 P Value 0x.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 415 Parameters for Screen Resolu tion/Refresh Rate: 1600x900_75Hz = Dot Clock Value 152 //Dot Cl ock M Value 0x0011 N Value 0x 0004 P Value 0x.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 416 Parameters for Screen Resolu tion/Refresh Rate: 1600x900_85Hz = Dot Clock Value 175 //Dot Cl ock M Value 0x0031 N Value 0x 000C P Value 0x.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 417 Parameters for Screen Resolu tion/Refresh Rate: 1600x1200_60Hz = Dot Clock Value 162 //162-MHz Dot Cloc k M Value 0x0019 N Value 0x 0006 P.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 418 Parameters for Screen Resolu tion/Refresh Rate: 1600x1200_65Hz = Dot Clock Value 175 //175.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 419 Parameters for Screen Resolu tion/Refresh Rate: 1600x1200_70Hz = Dot Clock Value 189 //189-MHz Dot Cloc k M Value 0x003D N Value 0x 000E P.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 420 Parameters for Screen Resolu tion/Refresh Rate: 1600x1200_72Hz = Dot Clock Value 195 //195-MHz Dot Cloc k M Value 0x003F N Value 0x 000E P.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 421 Parameters for Screen Resolu tion/Refresh Rate: 1600x1200_75Hz = Dot Clock Value 202 //202.
Intel® 815 Chipset: G raphics Contr oller PRM, Rev 1.0 R 422 Parameters for Screen Resolu tion/Refresh Rate: 1600x1200_85Hz = Dot Clock Value 229 //229.
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Ein wichtiger Punkt beim Kauf des Geräts Intel 815 (oder sogar vor seinem Kauf) ist das durchlesen seiner Bedienungsanleitung. Dies sollten wir wegen ein paar einfacher Gründe machen:
Wenn Sie Intel 815 noch nicht gekauft haben, ist jetzt ein guter Moment, um sich mit den grundliegenden Daten des Produkts bekannt zu machen. Schauen Sie zuerst die ersten Seiten der Anleitung durch, die Sie oben finden. Dort finden Sie die wichtigsten technischen Daten für Intel 815 - auf diese Weise prüfen Sie, ob das Gerät Ihren Wünschen entspricht. Wenn Sie tiefer in die Benutzeranleitung von Intel 815 reinschauen, lernen Sie alle zugänglichen Produktfunktionen kennen, sowie erhalten Informationen über die Nutzung. Die Informationen, die Sie über Intel 815 erhalten, werden Ihnen bestimmt bei der Kaufentscheidung helfen.
Wenn Sie aber schon Intel 815 besitzen, und noch keine Gelegenheit dazu hatten, die Bedienungsanleitung zu lesen, sollten Sie es aufgrund der oben beschriebenen Gründe machen. Sie erfahren dann, ob Sie die zugänglichen Funktionen richtig genutzt haben, aber auch, ob Sie keine Fehler begangen haben, die den Nutzungszeitraum von Intel 815 verkürzen könnten.
Jedoch ist die eine der wichtigsten Rollen, die eine Bedienungsanleitung für den Nutzer spielt, die Hilfe bei der Lösung von Problemen mit Intel 815. Sie finden dort fast immer Troubleshooting, also die am häufigsten auftauchenden Störungen und Mängel bei Intel 815 gemeinsam mit Hinweisen bezüglich der Arten ihrer Lösung. Sogar wenn es Ihnen nicht gelingen sollte das Problem alleine zu bewältigen, die Anleitung zeigt Ihnen die weitere Vorgehensweise – den Kontakt zur Kundenberatung oder dem naheliegenden Service.
