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80C186EA/80C188EA, 80L186EA/80L188EA 80C186EA/80C188EA AND 80L186EA/80L188EA 16-Bit High Integration Embedded Processor CONTENTS PAGE INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ.
80C186EA/80C188EA, 80L186EA/80L188EA NOTE: Pin names in parentheses apply to the 80C186EA/80L188EA Figure 1. 80C186EA/80C188EA Block Diagram 272432 – 2 3 3.
80C186EA/80C188EA, 80L186EA/80L188EA INTRODUCTION Unless specifically noted, all references to the 80C186EA apply to the 80C188EA, 80L186EA, and 80L188EA. References to pins that differ between the 80C186EA/80L186EA and the 80C188EA/ 80L188EA are given in parentheses.
80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 3 (A) Crystal Connection NOTE: The L 1 C 1 network is only required when using a third-overtone crystal.
80C186EA/80C188EA, 80L186EA/80L188EA PCB Function Offset 00H Reserved 02H Reserved 04H Reserved 06H Reserved 08H Reserved 0AH Reserved 0CH Reserved 0EH Reserved 10H Reserved 12H Reserved 14H Reserved .
80C186EA/80C188EA, 80L186EA/80L188EA PCB Function Offset 20H Interrupt Vector 22H Specific EOI 24H Reserved 26H Reserved 28H Interrupt Mask 2AH Priority Mask 2C In-Service 2E Interrupt Request 30 Inte.
80C186EA/80C188EA, 80L186EA/80L188EA 80C187 Interface (80C186EA Only) The 80C187 Numerics Coprocessor may be used to extend the 80C186EA instruction set to include floating point and advanced integer instructions. Connecting the 80C186EA RESOUT and TEST / BUSY pins to the 80C187 enables Numerics Mode operation.
80C186EA/80C188EA, 80L186EA/80L188EA PACKAGE INFORMATION This section describes the pins, pinouts, and thermal characteristics for the 80C186EA in the Plastic Leaded Chip Carrier (PLCC) package, Shrink Quad Flat Pack (SQFP), and Quad Flat Pack (QFP) pack- age.
80C186EA/80C188EA, 80L186EA/80L188EA Table 2. Pin Description Nomenclature Symbol Description P Power Pin (Apply a V CC Voltage) G Ground (Connect to V SS ) I Input Only Pin O Output Only Pin I/O Inpu.
80C186EA/80C188EA, 80L186EA/80L188EA Table 3. Pin Descriptions Pin Pin Input Output Description Name Type Type States V CC P POWER connections consist of six pins which must be shorted externally to a V CC board plane. V SS G GROUND connections consist of five pins which must be shorted externally to a V SS board plane.
80C186EA/80C188EA, 80L186EA/80L188EA Table 3. Pin Descriptions (Continued) Pin Pin Input Output Description Name Type Type States A18:16 O H(Z) These pins provide multiplexed Address during the address phase of the bus cycle. Address bits 16 through 19 are A19/S6 – A16 R(Z) presented on these pins and can be latched using ALE.
80C186EA/80C188EA, 80L186EA/80L188EA Table 3. Pin Descriptions (Continued) Pin Pin Input Output Description Name Type Type States WR/QS1 O H(Z) WRite output signals that data available on the data bus are to be written into the accessed memory or I/O device.
80C186EA/80C188EA, 80L186EA/80L188EA Table 3. Pin Descriptions (Continued) Pin Pin Input Output Description Name Type Type States MCS0/PEREQ I/O A(L) H(1) These pins provide a multiplexed function.
80C186EA/80C188EA, 80L186EA/80L188EA 80C186EA PINOUT Tables 4 and 5 list the 80C186EA pin names with package location for the 68-pin Plastic Leaded Chip Carrier (PLCC) component. Figure 9 depicts the complete 80C186EA/80L186EA pinout (PLCC pack- age) as viewed from the top side of the component (i.
80C186EA/80C188EA, 80L186EA/80L188EA Table 5. PLCC Package Location with Pin Names Location Name 1 AD15 (A15) 2 AD7 3 AD14 (A14) 4 AD6 5 AD13 (A13) 6 AD5 7 AD12 (A12) 8 AD4 9V CC 10 AD11 (A11) 11 AD3 .
80C186EA/80C188EA, 80L186EA/80L188EA Table 6. QFP (EIAJ) Pin Names with Package Location Address/Data Bus Bus Control Processor Control I/O Name Location Name Location Name Location Name Location AD0 .
80C186EA/80C188EA, 80L186EA/80L188EA Table 7. QFP (EIAJ) Package Location with Pin Names Location Name Location Name Location Name Location Name 1 AD15 (A15) 21 S2 41 MCS1/ERROR 61 DRQ0 2V CC 22 S1 42 MCS2 62 V SS 3 A16 23 S0 43 MCS3/NCS 63 N.
80C186EA/80C188EA, 80L186EA/80L188EA Table 8. SQFP Pin Functions with Package Location AD Bus AD0 1 AD1 3 AD2 6 AD3 8 AD4 12 AD5 14 AD6 16 AD7 18 AD8 (A8) 2 AD9 (A9) 5 AD10 (A10) 7 AD11 (A11) 9 AD12 (.
80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 7 Figure 7. Shrink Quad Flat Pack (SQFP) Pinout Diagram NOTES: 1. XXXXXXXXD indicates the Intel FPO number.
80C186EA/80C188EA, 80L186EA/80L188EA ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings * Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65 § Ct o a 150 § C Case Temperature under Bias ÀÀÀ b 65 § Ct o a 150 § C Supply Voltage with Respect to V SS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 0.
80C186EA/80C188EA, 80L186EA/80L188EA DC SPECIFICATIONS (80C186EA/80C188EA) Symbol Parameter Min Max Units Conditions V CC Supply Voltage 4.5 5.5 V V IL Input Low Voltage for All Pins b 0.5 0.3 V CC V V IH Input High Voltage for All Pins 0.7 V CC V CC a 0.
80C186EA/80C188EA, 80L186EA/80L188EA DC SPECIFICATIONS (80L186EA/80L188EA) Symbol Parameter Min Max Units Conditions V CC Supply Voltage 2.7 5.5 V V IL Input Low Voltage for All Pins b 0.5 0.3 V CC V V IH Input High Voltage for All Pins 0.7 V CC V CC a 0.
80C186EA/80C188EA, 80L186EA/80L188EA I CC VERSUS FREQUENCY AND VOLTAGE The current (I CC ) consumption of the processor is essentially composed of two components; I PD and I CCS .
80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS AC CharacteristicsÐ80C186EA25/80C186EA20/80C186EA13 Symbol Parameter Min Max Min Max Min Max Units Notes INPUT CLOCK 25 MHz (12) 20 MHz 13 MHz T F CLKIN Frequency 0 50 0 40 0 26 MHz 1 T C CLKIN Period 20 % 25 % 38.
80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS (Continued) AC CharacteristicsÐ80C186EA25/80C186EA20/80C186EA13 Symbol Parameter Min Max Min Max Min Max Units Notes SYNCHRONOUS INPUTS 25 MHz (.
80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS AC CharacteristicsÐ80L186EA13/80L186EA8 Symbol Parameter Min Max Min Max Units Notes INPUT CLOCK 13 MHz 8 MHz T F CLKIN Frequency 0 26 0 16 MHz 1 T C CLKIN Period 38.
80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS AC CharacteristicsÐ80L186EA13/80L186EA8 Symbol Parameter Min Max Min Max Units Notes SYNCHRONOUS INPUTS 13 MHz 8 MHz T CHIS TEST, NMI, INT3:0, T.
80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS (Continued) Relative Timings (80C186EA25/20/13, 80L186EA13/8) Symbol Parameter Min Max Unit Notes RELATIVE TIMINGS T LHLL ALE Rising to ALE Falli.
80C186EA/80C188EA, 80L186EA/80L188EA AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 8. See the Derating Curves section to see how timings vary with load capacitance. Specifications are measured at the V CC /2 crossing point, unless otherwise specified.
80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 10 NOTE: 20% V CC k Float k 80% V CC Figure 10. Output Delay and Float Waveform 272432 – 11 NOTE: RESIN measured to CLKIN, not CLKOUT Figure 11.
80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 12 NOTES: 1. T DXDL for write cycle followed by read cycle. 2. Pin names in parentheses apply to tthe 80C188EA.
80C186EA/80C188EA, 80L186EA/80L188EA DERATING CURVES 272432 – 13 Figure 13. Typical Output Delay Variations Versus Load Capacitance 272432 – 14 Figure 14. Typical Rise and Fall Variations Versus Load Capacitance RESET The processor performs a reset operation any time the RESIN pin is active.
80C186EA/80C188EA, 80L186EA/80L188EA Figure 15. Powerup Reset Waveforms 272432 – 15 NOTES: 1. CLKOUT synchronization occurs approximately 1 (/2 CLKIN periods after RESIN is sampled low.
80C186EA/80C188EA, 80L186EA/80L188EA Figure 16. Warm Reset Waveforms 272432 – 16 NOTES: 1. CLKOUT resynchronization occurs approximately 1 (/2 CLKIN periods after RESIN is sampled low. If RESIN is sampled low while CLKOUT is transitioning high, then CLKOUT will remain high for two CLKIN periods.
80C186EA/80C188EA, 80L186EA/80L188EA BUS CYCLE WAVEFORMS Figures 17 through 23 present the various bus cycles that are generated by the processor. What is shown in the figure is the relationship of the various bus signals to CLKOUT.
80C186EA/80C188EA, 80L186EA/80L188EA 272432-18 NOTES: 1. During the data phase of the bus cycle, A19/S6 is driven high for a DMA cycle. 2. Pin names in parentheses apply to the 80C188EA.
80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 19 NOTES: 1. The processor drives these pins to 0 during Idle and Powerdown Modes. 2. Pin names in parentheses apply to the 80C188EA.
80C186EA/80C188EA, 80L186EA/80L188EA NOTES: 272432 – 20 1. INTA occurs one clock later in Slave Mode. 2. Pin names in parentheses apply to the 80C188EA.
80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 21 NOTE: 1. Pin names in parentheses apply to the 80C188EA. Figure 21. HOLD/HLDA Waveform 40 40.
80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 22 NOTE: 1. Pin names in parentheses apply to the 80C188EA. Figure 22. DRAM Refresh Cycle During Hold Acknowledge 41 41.
80C186EA/80C188EA, 80L186EA/80L188EA 272432 – 23 NOTES: 1. Generalized diagram for READ or WRITE. 2. ARDY low by either edge causes a wait state. Only rising ARDY is fully synchronized. 3. SRDY low causes a wait state. SRDY must meet setup and hold times to ensure correct device operation.
80C186EA/80C188EA, 80L186EA/80L188EA 80C186EA/80C188EA EXECUTION TIMINGS A determination of program exeuction timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions.
80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY Function Format 80C186EA 80C188EA Comments Clock Clock Cycles Cycles DATA TRANSFER MOV e Move: Register to Register/Memory 1000100w m o dr .
80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA Comments Clock Clock Cycles Cycles DATA TRANSFER (Continued) SEGMENT e Segment Override: CS 0.
80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA Comments Clock Clock Cycles Cycles ARITHMETIC (Continued) IMUL e Integer multiply (signed): 1.
80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA Comments Clock Clock Cycles Cycles LOGIC (Continued) XOR e Exclusive or: Reg/memory and regis.
80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA Comments Clock Clock Cycles Cycles CONTROL TRANSFER (Continued) RET e Return from CALL: Withi.
80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA Comments Clock Clock Cycles Cycles PROCESSOR CONTROL CLC e Clear carry 11111000 2 2 CMC e Com.
80C186EA/80C188EA, 80L186EA/80L188EA REVISION HISTORY Intel 80C186EA/80L186EA devices are marked with a 9-character alphanumeric Intel FPO number un- derneath the product number.
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