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Document Number: 320835 -003 Intel ® Core™ i7-900 Desktop Processor Extreme Edition Series and Intel ® Core™ i7-900 Desktop Processor Series Datasheet, Volume 2 October 2009.
2 Datasheet INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNE CTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR O THERWISE, TO ANY INTELLECTUAL PROPER TY RIGHTS IS GRANTED BY THIS DOCUMENT .
Datasheet 3 Contents 1I n t r o d u c t i o n ....... ........... ........ ........... ........ ........... ........ ........... ........ ........ ........... ...... 11 1.1 Terminology ......... .......... ......... .......... ........ ........... ...
4 Datasheet 2.9.2 TA D_INTERLEAVE_ LIST_0, TAD_INTERLEAVE_L IST_1 TAD_INTERLEAVE_LIST_2, TAD_INTERLEAVE_LIST_ 3 TAD_INTERLEAVE_LIST_4, TAD_INTERLEAVE_LIST_ 5 TAD_INTERL EAVE_LIST_ 6, TAD_INTERLE AVE_LIST_7 ........... ........... ..........58 2.10 Integrated Memory Controller Channel Control Registers .
Datasheet 5 2.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_ RD MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_ RD MC_CHANNEL_2_ODT_MATRIX_RANK_ 0_3_RD....... ................... ............... 73 2.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_ RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_ RD MC_CHANNEL_2_ODT_MATRIX_RANK_ 4_7_RD.
6 Datasheet 2.10.39 Error Injection Imple mentation ..................... ........... .......... ........... ..........83 2.11 Integrated Memory Controller Channel Address Registers ........... .......... ........... ........84 2.11.1 MC_DOD_CH0_0, MC_DOD_CH0_1, MC_DOD _CH0_2 .
Datasheet 7 MC_RIR_WAY_CH2_6, MC_RIR_WAY_ CH2_7 MC_RIR_WAY_CH2_8, MC_RIR_WAY_ CH2_9 MC_RIR_WAY_CH2_10, M C_RIR_WAY_CH2_11 MC_RIR_WAY_CH2_12, M C_RIR_WAY_CH2_13 MC_RIR_WAY_CH2_14, M C_RIR_WAY_CH2_15 MC.
8 Datasheet Tables 1-1 Reference s................ ........ ........... ........ ........ ........... ........ ........... ........ ........... .... 13 2-1 Functions Specifically Handled by the Processor ............. ........... ........ ........... .
Datasheet 9 Revision History Revision Number Descriptio n Date -001 • Initial release. November 2008 -002 • Updated section 2.2 and T able 2.3. November 2008 -003 • Updated document title and In.
10 Datasheet.
Datasheet 11 Introduction 1 Introduction The Intel ® Core™ i7-900 desktop processor Extreme Edition series and Intel ® Core™ i7-900 desktop processor series are intended for high performance high-end desktop, Uni-processor (UP) server , and workstatio n systems.
Introduction 12 Datasheet security of the system. See the Intel Architecture Software Developer's Manual for more detailed information. Refer to h ttp://developer .
Datasheet 13 Introduction • Unit Interval (UI) — Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whe ther it be a rising edge or a falling edge. If a number of edges are collected at instances t 1 , t 2 , t n ,.
Introduction 14 Datasheet.
Datasheet 15 Register Description 2 Register Description The processor supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism in the PC I specification as defined in the PCI Local Bus Specification, Revision 2.
Register Description 16 Datasheet 2.2 Platform Configuration Structure The processor contains 6 PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI bus assigned for the processor socket.
Datasheet 17 Register Description at DID of 2C22h. Devic e 4, Function 3 contains the thermal control registers for Integrated Memory Controller Channel 0 and resides at DID of 2C23h.
Register Description 18 Datasheet 2.4 Detailed Configuration Space Maps Table 2-2. Device 0, Function 0: Generic Non-core Register s DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR 0Ch 8Ch 1.
Datasheet 19 Register Description Table 2-3. Device 0, Func tion 1: System Address De coder Registers DID VID 00h SAD_DRAM_RULE_0 80h PCISTS PCICMD 04h SAD_DRAM_RULE_1 84h CCR RID 08h SAD_DRAM_RULE_2 .
Register Description 20 Datasheet Table 2-4. Device 2, Function 0: Intel QPI Link 0 Re gisters DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR 0Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h.
Datasheet 21 Register Description Table 2-5. Device 2, Function 1: Intel QPI Physical 0 Registers DID VID 00h 80h PCISTS PCICMD 0 4h 84h CCR RID 08h 88h HDR 0Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h.
Register Description 22 Datasheet Table 2-6. Device 3, Function 0: Inte grated Memory Controller Registers DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR 0Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch.
Datasheet 23 Register Description Table 2-7. Device 3, Func tion 1: Target Address Decoder Registers DID VID 00h T AD_DRAM_RULE_0 80h PCISTS PCICMD 04h T AD_DRAM_RULE_1 84h CCR RID 08h T AD_DRAM_RULE_.
Register Description 24 Datasheet Table 2-8. Device 4, Function 0: Inte grated Memory Cont roller Channel 0 Control Registers DID VID 00h MC_CHANNEL_0_RANK_TIMING_A 80h PCISTS PCICMD 04h MC_CHANNEL_0_.
Datasheet 25 Register Description Table 2-9. De vice 4, Func tion 1: Integ rated Memory C ontrolle r Channel 0 Address Registers DID VID 00h MC_SAG_CH0_0 80h PCISTS PCICMD 04h MC_SAG_CH0_1 84h CCR RID.
Register Description 26 Datasheet Table 2-10. D evice 4, Function 2: Inte grated Memory Cont roller Channel 0 Rank Registers DID VID 00h MC_RIR_WA Y_CH0_0 80h PCISTS PCICMD 04h MC_RIR_WA Y_CH0_1 84h C.
Datasheet 27 Register Description Table 2-11. Device 4, Fun ction 3: Inte g rated Memory Controller Channel 0 Thermal Control Registers DID VID 00h MC_COOLING_COEF0 80h PCISTS PCICMD 04h MC_CLOSED_LOO.
Register Description 28 Datasheet Table 2-12. D evice 5, Function 0: Inte grated Memory Cont roller Channel 1 Control Registers DID VID 00h MC_CHANNEL_1_RANK_TIMING_A 80h PCISTS PCICMD 04h MC_CHANNEL_.
Datasheet 29 Register Description Table 2-13. Device 5, Fun ction 1: Inte g rated Memory Controller Channel 1 Address Registers DID VID 00h MC_SAG_CH1_0 80h PCISTS PCICMD 04h MC_SAG_CH1_1 84h CCR RID .
Register Description 30 Datasheet Table 2-14. D evice 5, Function 2: Inte grated Memory Cont roller Channel 1 Rank Registers DID VID 00h MC_RIR_WA Y_CH1_0 80h PCISTS PCICMD 04h MC_RIR_WA Y_CH1_1 84h C.
Datasheet 31 Register Description Table 2-15. Device 5, Fun ction 3: Inte g rated Memory Controller Channel 1 Thermal Control Registers DID VID 00h MC_COOLING_COEF1 80h PCISTS PCICMD 04h MC_CLOSED_LOO.
Register Description 32 Datasheet Table 2-16. D evice 6, Function 0: Inte grated Memory Cont roller Channel 2 Control Registers DID VID 00h MC_CHANNEL_2_RANK_TIMING_A 80h PCISTS PCICMD 04h MC_CHANNEL_.
Datasheet 33 Register Description Table 2-17. Device 6, Fun ction 1: Inte g rated Memory Controller Channel 2 Address Registers DID VID 00h MC_SAG_CH2_0 80h PCISTS PCICMD 04h MC_SAG_CH2_1 84h CCR RID .
Register Description 34 Datasheet Table 2-18. D evice 6, Function 2: Inte grated Memory Cont roller Channel 2 Rank Registers DID VID 00h MC_RIR_WA Y_CH2_0 80h PCISTS PCICMD 04h MC_RIR_WA Y_CH2_1 84h C.
Datasheet 35 Register Description Table 2-19. Device 6, Fun ction 3: Inte g rated Memory Controller Channel 2 Thermal Control Registers DID VID 00h MC_COOLING_COEF2 80h PCISTS PCICMD 04h MC_CLOSED_LOO.
Register Description 36 Datasheet 2.5 PCI Standard Registers These registers appear in every function for every device. Note: Reserved bit locations are n ot shown in the following register tables. 2.5.1 VID - Vendor Identification Register The VID Register contains the v endor identification number .
Datasheet 37 Register Description 2.5.3 RID - Revision Id entification Register This register contains the revision num ber of the processor . The R evision ID (RID) is a traditional 8-bit R ead Only (RO) register located at offset 08h in the standard PCI header of every PCI/PCI Express compatible device and function.
Register Description 38 Datasheet 2.5.5 HDR - Header Type Register This register identifies the header layout of the configur ation space . 2.5.6 SID/SVID - Subsystem Identity/Subsystem Vendor Identification Register This register identifies the manufacturer of the system.
Datasheet 39 Register Description 2.5.7 PCICMD - Command Register This register defines the PCI 3. 0 compatible command register values applicable to PCI Express space.
Register Description 40 Datasheet 2.5.8 PCISTS - PCI Status Register The PCI Status register is a 16-bit status register that reports the occurrence of various error events on this device's PCI interface.
Datasheet 41 Register Description 2.6 SAD - System Address Decoder Registers 2.6.1 SAD_PAM0123 This register is for legacy device 0, function 0 at 90h-93h address space. 4R O T B D Capability List (CLIST) This bit is hardwired to 1 to indicate to the configur ation software that this device/function implements a list of new ca pabilities.
Register Description 42 Datasheet 25:24 RW 0 PAM3_LOENABLE. 0D0000h-0D3FFFh Attribute (LO ENABLE). This field controls the steerin g of read and write cycles that addr ess the BIOS area from 0D0000h to 0D3FFFh. 00 = DRAM Disabled: All accesses are d irected to ESI.
Datasheet 43 Register Description 2.6.2 SAD_PAM456 Re gister for legacy device 0, funct ion 0 94h-97h address space. Device: 0 Function: 1 Offset: 44h Access as a Dword Bit Type Reset Value Descript ion 21:20 RW 0 PAM6_HIENABLE. 0EC000h-0EFFFFh A ttribute (HIENABLE).
Register Description 44 Datasheet 2.6.3 SAD_HEN Register for legacy Hole Enable. 2.6.4 SAD_SMRAM Register for legacy 9Dh address space. Note both IOH and non-core have this now . Device: 0 Function: 1 Offset: 48h Access as a Dword Bit Type Reset Value Description 7R W 0 HEN: Hole Enable This field enables a memory hole in DRAM space.
Datasheet 45 Register Description 2.6.5 S AD_PCIEXBAR Global register for PCIEXBAR address space. 2.6.6 SAD_DRAM_RULE_0, SAD_DRAM_RULE_1, SAD_DRAM_RULE_2, SAD_DRAM_RULE_3 SAD_DRAM_RULE_4, SAD_DRAM_RULE_5 SAD_DRAM_RULE_6, SAD_DRAM_RULE_7 This register provides SAD DRAM rules.
Register Description 46 Datasheet 2.6.7 SAD_INTERLEAVE_LIST_0, SAD_INTERLEAVE_LIST_1 SAD_INTERLEAVE_LIST_2, SAD_INTERLEAVE_LIST_3 SAD_INTERLEAVE_LIST_4, SAD_INTERLEAVE_LIST_5 SAD_INTERLEAVE_LIST_6, SAD_INTERLEAVE_LIST_7 This register provides SAD DRAM packag e assignments.
Datasheet 47 Register Description 2.7 Intel QPI Link Registers 2.7.1 QPI_QPILCL_L0, QPI_QPILCL_L1 This register provides Intel QPI Link Control. 2.8 Integrated Memory Controller Control Registers The registers in this section apply only to processors supporting registered DIMMs.
Register Description 48 Datasheet 8R W 0 CHANNEL0_ ACTIVE When set, indicate MC cha nnel 0 is active. This bit is controlled (set/reset) by software only . This bit is required to be set for an y active channel when INIT_DONE is set by software. Channel 0 AND Channel 1 activ e must both be set for a lockstep or mirrored pair .
Datasheet 49 Register Description 2.8.2 MC_STATUS This register is the MC primary status register . Device: 3 Function: 0 Offset: 4Ch Access as a Dword Bit Type Reset Value Description 4R O 1 ECC_ENABLED . ECC is enabled. 2R O 0 CHANNEL2 _DISABLED Channel 2 is disabled.
Register Description 50 Datasheet 2.8.3 MC_SMI_SPARE_D IMM_ERROR_STATUS SMI sparing DIMM error threshold overflow status register . This bit is set when the per- DIMM error counter exceeds the specified threshold.
Datasheet 51 Register Description 2.8.4 MC_SMI_SPARE_CNTRL System Man agement Interrupt and Spare control register . 2.8.5 MC_RESET_CONTROL DIMM R eset enabling controls. Device: 3 Function: 0 Offset: 54h Access as a Dword Bit Type Reset Value Description 16 RW 0 INTERRUPT_SELECT_NMI 1 = Enable NMI signalin g.
Register Description 52 Datasheet 2.8.6 MC_CHANNEL_MAPPER Channel mapping register . The sequence of operations to update this register is: Read MC_Channel_Mapper register Compare data read to data to be written. If different, then write. Poll MC _Channel_Mapper register until th e data read matches data written.
Datasheet 53 Register Description 2.8.7 MC_MAX_DOD This reg iste r de fin es t he MA X num ber of D IMM S, RAN KS, BA NKS, ROW S, COL S amo ng all DIMMS populating the three channels. The Memory Init logic uses this register to cycle through all the memory addresses writing all 0's to initialize all locations.
Register Description 54 Datasheet 2.8.8 MC_RD_CRDT_INIT These registers contain the initial read credits av ailable for issuing memory reads. T AD read credit counters are loaded with the corresponding v alue s at reset and anytime this register is written.
Datasheet 55 Register Description 2.8.9 MC_CRDT_WR_THLD This is the Memory Controller W rite Credit Thresholds register . A W r ite threshold is defined as the number of credits reserved fo r this priority (or higher) request.
Register Description 56 Datasheet 2.8.11 MC_SCRUBA DDR_HI This register pair contains part of the address of the last patrol scrub request issued. When running memtest, the failing address is logged in this register on memtest errors. Software can write the next address into th is register .
Datasheet 57 Register Description 2.9 TAD – Target Address Decoder Registers 2.9.1 TAD_DRAM_RULE_0, TAD_DRAM_RULE_1 TAD_DRAM_RULE_2, TAD_DRAM_RULE_3 TAD_DRAM_RULE_4, TAD_DRAM_RULE_5 TAD_DRAM_RULE_6, TAD_DRAM_RULE_7 T AD DRAM rules. Address map for channe l determination within a package.
Register Description 58 Datasheet 2.9.2 TAD_INTERLEAVE_LIST_0, TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_2, TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_4, TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_6, TAD_INTERLEAVE_LIST_7 T AD DRAM package assignments.
Datasheet 59 Register Description 2.10 Integrated Memory Controller Channel Control Registers 2.10.1 MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_1_DIMM_RESET_CMD MC_CHANNEL_2_DIMM_RESET_CMD Integrated Memory Controller DIMM reset co mmand register . This register is used to sequence the reset signals to the DIMMs.
Register Description 60 Datasheet 2.10.2 MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_1_DIMM_INIT_CMD MC_CHANNEL_2_DIMM_INIT_CMD Integrated Memory Controller DIMM initialization command register . This register is used to sequence the channel through the physical lay er training required for DDR.
Datasheet 61 Register Description 2.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_1_DIM M_INIT_PARAMS MC_CHANNEL_2_DIM M_INIT_PARAMS Initialization sequence parameters are stored in this register . Each field is 2^n count. Device: 4, 5, 6 Function: 0 Offset: 58h Access as a Dword Bit Type Reset Value Description 26 RW 0 DIS_3T.
Register Description 62 Datasheet 2.10.4 MC_CHANNEL_0_ DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS MC_CHANNEL_2_DIMM_INIT_STATUS The initialization state is stored in this register . This register is cleared on a new training command. Device: 4, 5, 6 Function: 0 Offset: 5Ch Access as a Dword Bit Type Reset Value Descript ion 9R O 0 RCOMP_CMPLT.
Datasheet 63 Register Description 2.10.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD MC_CHANNEL_2_DDR3CMD DDR3 Configuration C ommand. This register is used to issue commands to the DIMMs such as MRS commands. The register is used by setting one of the *_V ALID bits along with the appropriate address and destinat ion RANK.
Register Description 64 Datasheet 2.10.6 MC_CHANNEL_0_REFR ESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT This register supports Self Refresh and Thermal Throttle functions.
Datasheet 65 Register Description 2.10.8 MC_CHANNEL_0_MRS_VALUE_2 MC_CHANNEL_1_MRS_VALUE_2 MC_CHANNEL_2_MRS_VALUE_2 The initial MRS register values for MR2.
Register Description 66 Datasheet 2.10.10 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A MC_CHANNEL_2_RANK_TIMING_A This register contains par ameters that spec ify the ran k timing used. All parameters are in DCLK. Device: 4, 5, 6 Function: 0 Offset: 80h Access as a Dword Bit Type Reset Value Description 28:26 RW 0 tddWrTRd.
Datasheet 67 Register Description 18:15 RW 0 tddRdTWr. Minimum delay be tween Read followed by a Write to different DI MMs. 0000 = 2 0001 = 3 0010 = 4 0011 = 5 0100 = 6 0101 = 7 0110 = 8 0111 = 9 1000 = 10 1001 = 11 1010 = 12 1011 = 13 1100 = 14 14:11 RW 0 tdrRdTWr.
Register Description 68 Datasheet 6:4 RW 0 tddRdTRd. Minimum delay between reads t o different DIMMs. 000 = 2 001 = 3 010 = 4 011 = 5 100 = 6 101 = 7 110 = 8 111 = 9 3:1 RW 0 tdrRdTRd. Minimum delay between reads t o different r anks on the same DIMM.
Datasheet 69 Register Description 2.10.11 MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_1_RANK_TIMING_B MC_CHANNEL_2_RANK_TIMING_B This register contains parameters that spec ify the r ank timing used. All parameters are in DCLK. Device: 4, 5, 6 Function: 0 Offset: 84h Access as a Dword Bit Type Reset Value Description 20:16 RW 0 B2B_CAS_DELA Y.
Register Description 70 Datasheet 2.10.12 MC_CHANNEL_0_BANK_TIMING MC_CHANNEL_1_BANK_TIMING MC_CHANNEL_2_BANK_TIMING This register contains parameters that specify the bank timing parameters. These values are in DCLK. The values in these regi sters are encod ed where note d.
Datasheet 71 Register Description 2.10.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_2_CKE_TIMING This register contains parameters that spec ify the CKE timings. All units are in DCLK. 2.10.15 MC_CHANNEL_0_ZQ_TIMING MC_CHANNEL_1_ZQ_TIMING MC_CHANNEL_2_ZQ_TIMING This register contains parameters that sp ecify ZQ timing.
Register Description 72 Datasheet 2.10.16 MC_CHANNEL_0_RCOMP_PARAMS MC_CHANNEL_1_RCOMP_PARAMS MC_CHANNEL_2_RCOMP_PARAMS This register contains paramete rs that specify Rcomp timings. 2.10.17 MC_CHANNEL_0_ODT_PARAMS1 MC_CHANNEL_1_ODT_PARAMS1 MC_CHANNEL_2_ODT_PARAMS1 This register contains parameters that sp ecify ODT timings.
Datasheet 73 Register Description 2.10.18 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_1_ODT_PARAMS2 MC_CHANNEL_2_ODT_PARAMS2 This register contains parameters that specify F orcing OD T on Spe cific ranks. This register is used in debug only and not during normal operation.
Register Description 74 Datasheet 2.10.20 MC_CHANNEL_0_OD T_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD This register contains the OD T activation matrix for RANKS 4 to 7 for R eads.
Datasheet 75 Register Description 2.10.23 MC_CHANNE L_0_WAQ_PARAMS MC_CHANNEL_1_WAQ_PARAMS MC_CHANNEL_2_WAQ_PARAMS This register contains parameters that specify settings for the W rite Address Queue. Device: 4, 5, 6 Function: 0 Offset: B4h Access as a Dword Bit Type Reset Value Description 29:25 RW 6 PRECASWRTHRESHOLD .
Register Description 76 Datasheet 2.10.24 MC_CHANNEL_0_ SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULE R_PARAMS MC_CHANNEL_2_SCHEDULE R_PARAMS These are the par ameters used to control par ameters within the scheduler .
Datasheet 77 Register Description 2.10.26 MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_1_TX_BG_SETTINGS MC_CHANNEL_2_TX_BG_SETTINGS These are the parameters used to set the Start Scheduler for TX clock crossing.
Register Description 78 Datasheet 2.10.28 MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS MC_CHANNEL_2_EW_BGF_SETTINGS These are the par ameters used to set the early warning RX clock crossing BGF .
Datasheet 79 Register Description 2.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1 MC_CHANNEL_1_PAG ETABLE_PARAMS1 MC_CHANNEL_2_PAG ETABLE_PARAMS1 These are the parameters used to control par ame ters for page closing policies.
Register Description 80 Datasheet 2.10.33 MC_TX_BG_CMD_DAT A_RATIO_SETTINGS_CH0 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH2 Channel Bubble Generator r atios for CMD and DA T A.
Datasheet 81 Register Description 2.10.36 MC_CHANNEL_0_ADDR_MATCH MC_CHANNEL_1_ADDR_MATCH MC_CHANNEL_2_ADDR_MATCH This register specifies the intended addre ss or address range where ECC errors will be injected. It can be set to match memory address on a per channel basis.
Register Description 82 Datasheet 2.10.37 MC_CHANNEL_0_ECC_ERROR_MASK MC_CHANNEL_1_ECC_ERROR_MASK MC_CHANNEL_2_ECC_ERROR_MASK This register contains mask bits for the memory controller and specifies at which ECC bit(s) the error injection should occur .
Datasheet 83 Register Description 2.10.39 Error Injection Implementation The usage model is to program the MC_CHANNEL_X_ADDR_MA TCH and MC_CHANNEL_X_ECC_ERROR_MASK register s before writing the command in MC_CHANNEL_X_ECC_ERROR_INJECT register .
Register Description 84 Datasheet 2.11 Integrated Memory Controller Channel Address Registers 2.11.1 MC_DOD_CH0_0, MC _DOD_CH0_1, MC_DOD_CH0_2 Channel 0 DIMM Organization Descriptor Register . Device: 4 Function: 1 Offset: 4 8h, 4Ch, 50h Access as a Dword Bit Type Reset Value Description 12:10 RW 0 RANKOFFSET .
Datasheet 85 Register Description 2.11.2 MC_DOD_CH1_0, MC_DOD_CH1_1, MC_DOD_CH1_2 Channel 1 DIMM Organization Descriptor R egister . Device: 5 Function: 1 Offset: 48h, 4Ch, 50h Access as a Dword Bit Type Reset Value Description 12:10 RW 0 RANKOFFSET .
Register Description 86 Datasheet 2.11.3 MC_DOD_CH2_0, MC _DOD_CH2_1, MC_DOD_CH2_2 Channel 2 DIMM Organization Descriptor Register . Device: 6 Function: 1 Offset: 48h, 4Ch, 50h Access as a Dword Bit Type Reset Value Description 12:10 RW 0 RANKOFFSET .
Datasheet 87 Register Description 2.11.4 MC_SAG_CH0_0, MC_S AG_CH0_1, MC_SAG_CH0_2 MC_SAG_CH0_3, MC_SAG _CH0_4, MC_SAG_CH0_5 MC_SAG_CH0_6, MC_SAG _CH0_7, MC_SAG_CH1_0 MC_SAG_CH1_1, MC_SAG _CH1_2, MC_S.
Register Description 88 Datasheet 2.12 Integrated Memory Controller Channel Rank Registers 2.12.1 MC_RIR_LIMIT_CH0_0, MC_RIR_LIMIT_CH0_1 MC_RIR_LIMIT_CH0_2, MC_RIR_LIMIT_CH0_3 MC_RIR_LIMIT_CH0_4, MC_R.
Datasheet 89 Register Description 2.12.2 MC_RIR_WAY_CH0_0, MC_RIR_WAY_CH0_1 MC_RIR_WAY_CH0_2, MC_RIR_WAY_CH0_3 MC_RIR_WAY_CH0_4, MC_RIR_WAY_CH0_5 MC_RIR_WAY_CH0_6, MC_RIR_WAY_CH0_7 MC_RIR_WAY_CH0_8, M.
Register Description 90 Datasheet 2.12.3 MC_RIR_WAY_CH1_0, MC_RIR_WAY_CH1_1 MC_RIR_WAY_CH1_2, MC_RIR_WAY_CH1_3 MC_RIR_WAY_CH1_4, MC_RIR_WAY_CH1_5 MC_RIR_WAY_CH1_6, MC_RIR_WAY_CH1_7 MC_RIR_WAY_CH1_8, M.
Datasheet 91 Register Description 2.12.4 MC_RIR_WAY_CH2_0, MC_RIR_WAY_CH2_1 MC_RIR_WAY_CH2_2, MC_RIR_WAY_CH2_3 MC_RIR_WAY_CH2_4, MC_RIR_WAY_CH2_5 MC_RIR_WAY_CH2_6, MC_RIR_WAY_CH2_7 MC_RIR_WAY_CH2_8, M.
Register Description 92 Datasheet 2.13 Memory Thermal Control 2.13.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL1 MC_THERMAL_CONTROL2 Controls for the Integr ated Memory Controller thermal throttle logic for each channel. 2.13.2 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1 MC_THERMAL_STATUS2 Status registers for the thermal throttling logic for each channel.
Datasheet 93 Register Description 2.13.3 MC_THERMAL_DEFEATURE0 MC_THERMAL_DEFEATURE1 MC_THERMAL_DEFEATURE2 Thermal Throttle defeature register for each channel. 2.13.4 MC_THERMAL_PARAMS_A0 MC_THERMAL_PARAMS_A1 MC_THERMAL_PARAMS_A2 P arameters used by Open Loop Throughput Throttling (OL TT) and Closed Loop Thermal Throttling (CL T T).
Register Description 94 Datasheet 2.13.5 MC_THERMAL_PARAMS_B0 MC_THERMAL_PARAMS_B1 MC_THERMAL_PARAMS_B2 Par ameters used by the thermal throttling logic.
Datasheet 95 Register Description 2.13.7 MC_CLOSED_LOOP0 MC_CLOSED_LOOP1 MC_CLOSED_LOOP2 This register controls the closed loop ther mal response of the DRAM thermal throttle logic. It supports immediate thermal throttle an d 2X refresh. In addition, the register is used to configure the throttling duty cycle.
Register Description 96 Datasheet 2.13.9 MC_RANK_VIRTUAL_TEMP0 MC_RANK_VIRTUAL_TEMP1 MC_RANK_VIRTUAL_TEMP2 This register contains the 8 most significant bits [37:30] of the virtual temperature of each rank. The difference between the virtual temperature and the sensor temperature can be used to determine how fast fan speed should be increased.
Datasheet 97 Register Description 2.13.11 MC_DDR_THERM_STATUS0 MC_DDR_THERM_STATUS1 MC_DDR_THERM_STATUS2 This register contains the status portion of the DDR_THERM# functionality as described in the processor datasheet (i.e. , what is ha ppening or has happened with respect to the pin).
Register Description 98 Datasheet 2.14.2 MC_DIMM_CLK_RATIO This register is for the Re quested DIMM clock ratio (Qclk). Th is is the data rate going to the DIMM. The clock sent to the DIMM is 1/2 of QCLK r ate. § Device: 3 Function: 4 Offset: 54h Access as a Dword Bit Type Reset Value Description 4:0 RW 6 QCLK_RATIO.
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