Benutzeranleitung / Produktwartung Am79C930 des Produzenten AMD
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PRELIMINARY This document contains in f o r mation on a product under d e v elopment at Ad v anced Micro D e vice s . The in f o r mation is intended to help y ou e v aluate this product . AMD rese r v es the r ight to change or discontinue wo r k on this proposed product without notic e .
2 Am79C930 PRELIMINARY ORDERING INFORM A TION Standa r d P r oducts AMD standard products are a v aila b le in s e v e r al pa c kages and operating r ange s . The order number ( v alid combination) is f o r med b y a combination of the elements bel o w .
Am79C930 3 PRELIMINARY BLOCK DI A GRAM PCMCIA Mode JTAG Control Block TRST TMS/T3 TDI/T1 TDO/T2 RXCIN ANTSLT ANTSLT SAR6–0 ADIN2–1 ADREF RXDATA SDCLK SDDATA SDSEL3–1 TXCMD TXCMD TXMOD TXDATA TXD.
4 Am79C930 PRELIMINARY BLOCK DI A GRAM Bus Interface Unit A14–0 or LA23–17, SA16–0 D7–0 CLKIN Slave Control PCMCI A and IS A Memory and I/O Address Bu f fer Data Bu f fer SIR0 System Interrupt Generator SIR1 .
Am79C930 5 PRELIMINARY BLOCK DI A GRAM T ransceiver Atta c hment Interface Unit C R C MA[4:0] MD[7:0] CLKIN Slave Control Memory Interface Bus I/O and DMA TIR0 Interrupt Generator TCR31 TX FIFO 8 Bytes TXD RESET TCR.
AMD P R E L I M I N A R Y 6 Am79C930 TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GENERAL DESCRIPTION 1 . . . . . . . . . . . . . . . . .
P R E L I M I N A R Y AMD 7 Am79C930 Pin 3: USER4/LA17 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin 45: STSCHG/BALE 34 . . . . . . . . . . . . . . . . . . . . . . . . . .
AMD P R E L I M I N A R Y 8 Am79C930 Bus Interface Unit Interaction 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transceiver Attachment Interface Unit 47 . . . . . . . . . . . . . . . . . . . .
P R E L I M I N A R Y AMD 9 Am79C930 LED Support 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET Methods 73 . . . . . . . . . . . . . . . . . . . . . . . .
AMD P R E L I M I N A R Y 10 Am79C930 TIR10: TX FIFO Data Register 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIR11: Transmit Sequence Control 95 . . . . . . . . . . . . . . . . . . .
P R E L I M I N A R Y AMD 11 Am79C930 TCR24: RSSI Sample Start 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCR25: RSSI Configuration 118 . . . . . . . . . . . . . . . . . . . . . . .
AMD P R E L I M I N A R Y 12 Am79C930 TIMING WAVEFORMS 148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMCIA Bus Interface Waveforms 148 . . . . . . . . . . . . . . .
Am79C930 13 PRELIMINARY PCMCIA CONNECTION DI A GRAM Notes: Pin 1 is marked f or orientation. NC = No Connection 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 9.
1 4 Am79C930 PRELIMINARY PCMCIA PIN SUMMA R Y Listed b y Pin Number Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 USER2 37 MA10 73 D7 109 SAR1 2 USER3 38 MOE 74 D6 110 SAR2 3 U.
Am79C930 15 PRELIMINARY PCMCIA PIN LIST Listed b y Pin Name Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. A0 46 HFPE 120 OE 70 TXMOD 131 A1 47 INP ACK 50 PCMCIA 79 TXPE 129 A10 7.
1 6 Am79C930 PRELIMINARY PCMCIA PIN FUNCTION SUMMA R Y PCMCIA Pin Summary No . of Pins Pin Name Pin Function Pin Style 15 A14–A0 PCMCIA address b us lines I 8 D7–D0 PCMCIA data b us lines TS2 1 RE.
Am79C930 1 7 PRELIMINARY PCMCIA PIN FUNCTION SUMMA R Y (continued) PCMCIA Pin Summary (conti n ued) No . of Pins Pin Name Pin Function Pin Style 1 TDO T est Data Out—this is the data output signal f or IEEE 1149.1 testing TS1 1 TMS T est Mode Select—this is the test mode select f or IEEE 1149.
1 8 Am79C930 PRELIMINARY PCMCIA PIN FUNCTION SUMMA R Y (continued) PCMCIA Pin Summary (conti n ued) Output Drive r T ypes Inpu t T ypes No . of Pins Pin Name Pin Function Pin Style 2 ADIN1–2 Compara.
Am79C930 1 9 PRELIMINARY ISA PLUG AND PL A Y BLOCK DI A GRAM JTAG Control Block TRST TMS/T3 TDI/T1 TDO/T2 RXCIN ANTSLT ANTSLT SAR6–0 ADIN2–1 ADREF RXDATA SDCLK SDDATA SDSEL3–1 TXCMD TXCMD TXMOD TXDATA TXDATA RXPE TXPE HFPE HFCLK LFPE LFCLK FDET LNK ACT RXC IEEE 802.
20 Am79C930 PRELIMINARY ISA PLUG AND PL A Y CONNECTION DI A GRAM Notes: Pin 1 is marked f or orientation. NC = No Connection 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 .
Am79C930 21 PRELIMINARY ISA PLUG AND PL A Y PIN LIST Listed b y Pin Number Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 LA19 37 MA10 73 SD7 109 SAR1 2 SA16 38 MOE 74 SD6 110 S.
22 Am79C930 PRELIMINARY ISA PLUG AND PL A Y PIN LIST Listed b y Pin Name Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. A CT 98 MA11 6 SA1 47 SDSEL2 105 ADIN1 134 MA12 15 SA10 71 .
Am79C930 23 PRELIMINARY ISA PLUG AND PL A Y PIN SUMMA R Y No . of Pins Pin Name Pin Function Pin Style 7 LA23–LA17 ISA upper address b us lines I 17 SA16–SA0 ISA l o wer address b us lines I 8 SD7.
24 Am79C930 PRELIMINARY ISA PLUG AND PL A Y PIN SUMMA R Y (continued) Output Drive r T ypes Inpu t T ypes No . of Pins Pin Name Pin Function Pin Style 1 TXC T ransmit Clo c k—m a y be configured ei.
P R E L I M I N A R Y AMD 25 Am79C930 PIN DESCRIPTIONS Pins with Internal Pull Up or Pull Down Devices Several pins of the Am79C930 device include internal pull up or pull down devices. With the exception of the RESET pin, these pins are fully programmable as inputs or outputs when the PCMCIA mode has been selected.
AMD P R E L I M I N A R Y 26 Am79C930 The functionality of the following pins is determined, at least in part, by the connection of the PCMCIA pin: PCMCIA Mode ISA Plug and Play Mode Pin Name Pin Name.
P R E L I M I N A R Y AMD 27 Am79C930 Function Mode REG CE1 IORD IOWR A0 OE WE D7–0 Standby mode X H X X X X X High-Z Common Memory Read Even Byte H L H H L L H Even Byte Common Memory Read Odd Byte.
AMD P R E L I M I N A R Y 28 Am79C930 IOR I/O Read Input The IOR signal is made active by the ISA host in order to read data from the Am79C930 device’s I/O space. IOW I/O Write Input The IOW signal is made active by the ISA host in order to write data to the Am79C930 device’s I/O space.
P R E L I M I N A R Y AMD 29 Am79C930 Clock Pins CLKIN System Clock Input CLKIN is the clock input for the Am79C930 device’s logic functions. CLKIN is used to drive the CLKIN input of the embedded 80188 core. The BIU section uses the CLKOUT signal from the 80188 embedded core as a reference.
AMD P R E L I M I N A R Y 30 Am79C930 is deasserted when the RESET pin is issued or the CRC reset bit is set to 1 (SIR0); when the TXS bit is set to 1 (TIR8) or the RXS bit is set to 1 (TIR16); when TXRES bit set to 1 (TIR8), or the RXRES bit is set to 1 (TIR16), or the SRES bit is set to 1 (TIR0).
P R E L I M I N A R Y AMD 31 Am79C930 TXMOD Transmit Modulation Enable Output TXMOD is an active low output that is used to enable the transmit modulation function of the attached trans- ceiver. This pin is directly controlled by the transmit state machine in the TAI and the TXMOD bit of TIR11.
AMD P R E L I M I N A R Y 32 Am79C930 IEEE 1149.1 Test Access Port Pins TCK Test Clock Input TCK is the clock input for the boundary scan test mode operation. TCK frequency may be as high as 10 MHz. TCK does not have an internal pull-up resistor and must be connected to a valid TTL or CMOS level at all times.
P R E L I M I N A R Y AMD 33 Am79C930 VDDT, VDDU1, VDDU2, VDDP, Acceptable VCC VDDM AVDD, VDD5 Combination 5 V All at 5 V Both at 5 V Yes 3 V All at 5 V Both at 5 V Yes 3 V Any Combination Both at 5 V.
AMD P R E L I M I N A R Y 34 Am79C930 for an output function. This means that there are con- figurations for which a read of the pin data register bit will not reflect what has most recently been written to the pin data register bit ( i.
P R E L I M I N A R Y AMD 35 Am79C930 Note that a read of the USERDT[0] bit (TIR29[0]) will al- ways give the current USER0/RFRSH pin value, regard- less of pin configuration setting.
AMD P R E L I M I N A R Y 36 Am79C930 Pin 94: RXC/IRQ10/EXTA2DST The RXC/IRQ10 pin may be configured for input opera- tion, output operation, ISA IRQ10 operation, and as an output providing the RX clo.
P R E L I M I N A R Y AMD 37 Am79C930 ENXCHBSY bit of TCR28 and the CHBSYU bit of TIR5 and operates independently of the bits in the table below. In addition to the functionality listed above, the USER5/IRQ4/EXTCHBSY pin may be used as the source for CCA information, instead of relying on the in- ternal CCA logic of the Am79C930 device.
AMD P R E L I M I N A R Y 38 Am79C930 Pin 101: SDCLK The SDCLK pin may be configured for input or output operation. The output drive may be programmed for reg- ister-driven or auto-pulse generation. The auto-pulse may be programmed for either active low or active high operation.
P R E L I M I N A R Y AMD 39 Am79C930 Pin 115: TXC The TXC pin may be configured for input or output op- eration according to the table below: TXC input configuration is the reset default configura- tion. This configuration allows an external transceiver to control the clock that serves as the reference for the transmit data.
AMD P R E L I M I N A R Y 40 Am79C930 Pin 126: TXCMD The TXCMD pin may be configured to drive a trans- ceiver control reference signal, using one of two timing sources plus input from the TXCMD bit of.
P R E L I M I N A R Y AMD 41 Am79C930 some functionality is only available in PCMCIA mode. Pin functionality is programmed according to the follow- ing table: Note that a read of the ANTSLTD bit (TCR7[1]) will al- ways give the current ANTSLT /LA23 pin value without inversion, regardless of pin configuration setting.
AMD P R E L I M I N A R Y 42 Am79C930 LLOCKE/ LLOCKE/ PCMCIA LLOCKEN SA15 Pin SA15 Pin Pin Value TCR14[6] Direction Value 0 X I NA (SA15 input function) 10 I N A 1 1 O TIR11[4] FUNCTIONAL DESCRIPTION Basic Functions System Bus Interface Function The Am79C930 device is designed with a choice of two system bus interfaces.
P R E L I M I N A R Y AMD 43 Am79C930 PCMCIA Interface — The Am79C930 device fully sup- ports the PCMCIA standard, revision 2.1. The PCMCIA interface on the Am79C930 device sup- ports both memory and I/O cycles. The data bus is 8 bits in width. The address bus is 15 bits in width.
AMD P R E L I M I N A R Y 44 Am79C930 ISA (IEEE P996) Plug and Play Interface — The Am79C930 device fully supports the ISA Plug and Play specification, revision 1.0a. The ISA Plug and Play interface on the Am79C930 de- vice supports both memory and I/O cycles.
P R E L I M I N A R Y AMD 45 Am79C930 Memory Interface The memory interface is provided to support direct con- nection of both a non-volatile memory (typically Flash memory) and an SRAM and an additional peripheral de- vice. Separate chip enables for Flash, SRAM, and an extra peripheral device exist in the memory interface.
AMD P R E L I M I N A R Y 46 Am79C930 the media is considered busy and the MAC should defer to the existing message. This function is implemented in hardware in the TAI Unit. Additionally, each station is required to implement a Net Allocation Vector (NAV) in order to determine when the medium is expected to be busy.
P R E L I M I N A R Y AMD 47 Am79C930 accesses to use the memory interface bus during the T1 and T2 cycles of the 80188 access. The Memory Ad- dress Bus is internally shared between the 80188 core and the BIU. This bus also attaches to the Transceiver Attachment Unit as an input only.
AMD P R E L I M I N A R Y 48 Am79C930 Transceiver Attachment Interface Unit The TAI Unit includes the following subfunctions: TAI register set TX FIFO TX data serialization TX CRC32 generation TX CRC8.
P R E L I M I N A R Y AMD 49 Am79C930 T1 TXD A T A T2 T3 2 X TSCLK TGAP2 X TBCLK + 2 X TSCLK TGAP1 X TBCLK + 2 X TSCLK 1st Data Bit Last Data Bit 2 X TSCLK TXS 4 X TSCLK TSCLK = TCLKIN when CLKGT2.
AMD P R E L I M I N A R Y 50 Am79C930 Transceiver-Based TX Power Ramp Control — The CTS signal may be used to synchronize operations be- tween the Am79C930 device and transceivers that wish to perform their own transmit timing sequence.
P R E L I M I N A R Y AMD 51 Am79C930 values were found to be correct. These register values can be used to determine the end of a received frame. When good CRC values are found, these may be sig- naled to the 80188 core through interrupt bits in TIR5.
AMD P R E L I M I N A R Y 52 Am79C930 register of TCR4. ADIN2 becomes active after ADIN1 by the amount of delay specified in the RSSI Sample Start time of TCR24. ADIN2 remains active for the time pro- grammed in the A2DT register (TCR25). The converter output should be connected to the SAR pins, which act as inputs in this mode.
P R E L I M I N A R Y AMD 53 Am79C930 resolution is equal to twice the CLKIN period when the CLKGT20 bit of MIR9 is set to 1. (For a 1 MB data rate with CLKIN = 20 MHz and CLKGT20 = 0, resolution is 50 ns.
AMD P R E L I M I N A R Y 54 Am79C930 CCA Result UBDCS URSSI Baud Detect Carrier RSSI >= RSSI (CHBSY Bit TCR28:1 TCR28:0 Sense Decision Lower Limit of TIR26) 0 0 don’t care don’t care CHBSY = T.
P R E L I M I N A R Y AMD 55 Am79C930 Diversity decision logic for determining if a satisfactory antenna has been found. These inputs to the Stop Di- versity decision logic are enabled by specific bits of TCR28.
AMD P R E L I M I N A R Y 56 Am79C930 The following is a brief summary of the IEEE 1149.1 compatible test functions implemented in the Am79C930 device: Boundary Scan Circuit The boundary scan test circuit uses five pins: TRST, TCK, TMS, TDI, and TDO. These five pins are collec- tively labeled the TAP.
P R E L I M I N A R Y AMD 57 Am79C930 mode, the host requests a power down by writing to the Power Down bit (bit 2) of the PCMCIA Card Configura- tion and Status Register. In the ISA Plug and Play mode, the host requests a power down by writing to the ISA Power Down bit, bit 7 of SIR3.
AMD P R E L I M I N A R Y 58 Am79C930 Writing a 1 to the Power Down bit of the ISA Power Down bit of SIR3 will cause a request for a power down to be generated to the 80188 core via an interrupt bit in MIR0.
P R E L I M I N A R Y AMD 59 Am79C930 Am79C930 Device PCMCIA Mode Resource Requirements Common Common Attribute Attribute Memory Range Memory Size I/O Range I/O Size Memory Range Memory Size 0000h –.
AMD P R E L I M I N A R Y 60 Am79C930 Some of the Am79C930 device’s PCMCIA Common Memory locations have predefined uses and, therefore, are not freely available to the device driver.
P R E L I M I N A R Y AMD 61 Am79C930 The SRAM is intended to serve as a shared memory re- source between the driver operating through the system interface and the 80188 core operating through the Am79C930 memory interface bus.
AMD P R E L I M I N A R Y 62 Am79C930 Am79C930 Device PCMCIA Mode Attribute Memory Restricted Space PCMCIA Address in Attribute Memory SIR1[5:3] Size of Restricted Space Physical Memory and Descriptio.
P R E L I M I N A R Y AMD 63 Am79C930 The following table indicates the mapping of all I/O re- sources that are accessible through the Am79C930 PCMCIA system interface.
AMD P R E L I M I N A R Y 64 Am79C930 Am79C930 Device ISA Plug And Play Mode Memory And I/O Resource Requirements Memory Range Memory Size I/O Range I/O Size MBA*+0000h – 32 Kbytes IOBA**+0000h – .
P R E L I M I N A R Y AMD 65 Am79C930 address needs to be aligned to a 32K boundary in mem- ory space. This alignment requirement should be in- cluded in the Resource Data that is programmed into the Flash device and read by the Plug and Play configura- tion utility.
AMD P R E L I M I N A R Y 66 Am79C930 The SRAM is intended to serve as a shared memory re- source between the driver operating through the system interface and the 80188 core operating through the Am79C930 memory interface bus.
P R E L I M I N A R Y AMD 67 Am79C930 Am79C930 Device ISA Plug And Play Mode I/O MAP Physical ISA SIR1 Resource Location of Resource Name Mnemonic I/O address Bits [2:0] Size Resource SIR0: General SI.
AMD P R E L I M I N A R Y 68 Am79C930 ISA Plug and Play Register Set — The Am79C930 de- vice fully supports the ISA Plug and Play specification, revision 1.
P R E L I M I N A R Y AMD 69 Am79C930 Am79C930 Device ISA Plug And Play Mode Plug And Play Register Set ISA Plug and Play Plug and Play Port Register Name ADDRESS Physical Location Set READ_DATA port .
AMD P R E L I M I N A R Y 70 Am79C930 The Am79C930 device maps the Resource Data regis- ter accesses into 1K–16 of the upper 1 Kbytes of the Flash memory space so that Resource Data may be read from the Flash memory. Byte 0 of the Am79C930 device’s Resource Data is mapped to location 1 FC00h of the Flash memory.
P R E L I M I N A R Y AMD 71 Am79C930 80188 Core Memory Map Using Scheme “A”, LMCS=1FF8h, UMCS=E038h, MIR0[6]=0 Active 80188 Address Active 80188 Am79C930 Size of in Memory Chip Select Chip Select.
AMD P R E L I M I N A R Y 72 Am79C930 MAC (80188 core) Memory Resources Restrictions — Some of the Am79C930 device 80188 core’s memory locations have predefined uses and, therefore, are not freely available to the firmware.
P R E L I M I N A R Y AMD 73 Am79C930 to TIR10. It is also possible to use 80188 MOV instruc- tions to unload RX data from the RX FIFO. The RX FIFO may be unloaded by reading from TIR18.
AMD P R E L I M I N A R Y 74 Am79C930 The sleep state machine is returned to its idle state (i.e., awake). The memory bus arbitration state machine is re- turned to its idle state.
P R E L I M I N A R Y AMD 75 Am79C930 The sleep state machine is returned to its idle state (i.e., awake). The following registers and state machines are UNAFFECTED by assertion of the PCMCIA COR SRESET bit of COR[7]: All TIR registers are unaffected by COR SRESET.
AMD P R E L I M I N A R Y 76 Am79C930 The MIR space contains 16 registers which are used by the firmware to control allow communication between the firmware (MAC layer) and the device driver.
P R E L I M I N A R Y AMD 77 Am79C930 SIR0: General Configuration Register (GCR) This register is used to control general functions related to the Am79C930, particularly interrupts to and from the 80188 core and power down functions. Bit Name Reset Value Description 7 SWRESET 0 Software Reset.
AMD P R E L I M I N A R Y 78 Am79C930 2 INT2EC 0 Interrupt to Embedded Controller. When INT2EC is set to a 1, an interrupt is sent to the 80188 core. INT2EC will stay set at 1 until the 80188 core clears this bit by writing a 1 to bit 3 of the MIR0 register.
P R E L I M I N A R Y AMD 79 Am79C930 SIR2: Local Memory Address Register [7:0] (LMA) This register is the beginning address on the local bus for system interface I/O transfers that are made to the I/O Data Port. This register automatically increments by “1” following each read or write operation of any section of the I/O Data Port.
AMD P R E L I M I N A R Y 80 Am79C930 SIR5: I/O Data Port B (IODPB) This register is a system interface I/O address alias of I/O Data Port A. Bit Name Reset Value Description 7:0 IODPB[7:0] – Aliased to I/O Data Port A. SIR6: I/O Data Port C (IODPC) This register is a system interface I/O address alias of I/O Data Port A.
P R E L I M I N A R Y AMD 81 Am79C930 4 PDC 0 Power Down Command. When PDC is set to 1, the power down cy- cle of the BIU power down state machine will begin. PDC will auto- matically clear itself after completion of the power down operation. 3 SYSINT 0 System Interrupt.
AMD P R E L I M I N A R Y 82 Am79C930 MIR3: Power Down Length Count [15:8] (PDLC) This register is used to determine the length of power down cycles. Before execution of the power down se- quence, the 80188 core must load the PDLC counter.
P R E L I M I N A R Y AMD 83 Am79C930 MIR8: Flash Wait States This register gives the Flash Wait states. Bit Name Reset Value Description 7:4 Reserved – Reserved.
AMD P R E L I M I N A R Y 84 Am79C930 6 Reserved – Reserved. Must be written as a 0. Reads of this bit produce undefined data. 5:4 SRAMWAIT[1:0] 11b These bits must be set equal to or greater than t.
P R E L I M I N A R Y AMD 85 Am79C930 PCMCIA CCSR is RESET to a 0. If the STSCHGFN bit of TCR15 has been set to a 0, then the value that is written to this bit will be inverted and driven to the STSTCHG pin of the Am79C930 device.
AMD P R E L I M I N A R Y 86 Am79C930 Transceiver Attachment Interface Registers (TIR Space) The Transceiver Attachment Interface (TAI) Unit con- tains a total of 64 registers. Thirty-two of the registers are directly accessible from the 80188 embedded core and from the system interface through the BIU.
P R E L I M I N A R Y AMD 87 Am79C930 TIR mapping with SIR1 bit 2 (EIOW) set to “0” = normal TIR window mode. Note that EIOW = 0 is the only setting of EIOW that is allowed while operating in ISA PnP mode.
AMD P R E L I M I N A R Y 88 Am79C930 TIR mapping with SIR1 bit 2 (EIOW) set to “1” = Ex- panded TIR window mode. Note that the setting EIOW = 1 is only allowed while operating in PCMCIA mode.
P R E L I M I N A R Y AMD 89 Am79C930 TIR0: Network Control General control for the transceiver device attached to the transceiver interface pins. Bit Name Reset Value Description 7 LNK pin Link LED. The inverse of the LNK bit value is driven onto the LNK pin when the LNK pin has been enabled for output.
AMD P R E L I M I N A R Y 90 Am79C930 1 RXDRQ 0 Receive FIFO DMA Request. This bit represents the current value of the RXDRQ signal to the DRQ0 input of the 80188 embedded core. 0 TXDRQ 1 Transmit FIFO DMA Request. This bit represents the current value of the TXDRQ signal to the DRQ1 input of the 80188 embedded core.
P R E L I M I N A R Y AMD 91 Am79C930 The value read from SDD will always represent the current value of the SDDATA pin. The complete control of the function of the SDDATA pin is described in the Multi-Function Pin section.
AMD P R E L I M I N A R Y 92 Am79C930 5 MOREINT 1 MORE Interrupts. MOREINT will become set whenever there are interrupt bits set in Interrupt Register 3 (TCR11). Note that MOREINT bit does not reflect the state of interrupt status bits from Interrupt Register 2 (TIR5).
P R E L I M I N A R Y AMD 93 Am79C930 (Generated from the internal signal stop_d, which indicates that an- tenna diversity operation has selected an antenna.) Assertion of ALOKI indicates the cessation of antenna diversity activity so that the incoming network signal can be tracked and decoded by the DPLL.
AMD P R E L I M I N A R Y 94 Am79C930 TIR8: Transmit Control This register is the Transmitter Control register. Bit Name Reset Value Description 7 TXRES 0 Transmit Reset. When this bit is set to 1, the internal Transmit Re- set signal is asserted. When this bit is set to 0, the internal Transmit Reset signal is deasserted.
P R E L I M I N A R Y AMD 95 Am79C930 TIR9: Transmit Status Transmit Status register. Indicates the current status of the Transmit portion of the TAI. Writes to these bits have no effect. Bit Name Reset Value Description 7 TXCRC 0 Transmit CRC. TXCRC becomes set when the CRC is being ap- pended to the end of the transmit frame.
AMD P R E L I M I N A R Y 96 Am79C930 TIR11: Transmit Sequence Control This register is the Transmit Sequence Control. The bits in this register determine the function of the transmit sequence signals. Bit Name Reset Value Description 7 RXCD pin RXC/IRQ10 pin Data.
P R E L I M I N A R Y AMD 97 Am79C930 TIR12: Byte Count Register LSB This register is the Byte count register LSB. This register contains the lower 8 bits of the 12-bit byte count for receive and transmit messages. This is a working register; access by software is not needed for normal operation.
AMD P R E L I M I N A R Y 98 Am79C930 TIR15: Byte Count Limit MSB This register is the Byte Count Limit MSB register. Bit Name Reset Value Description 7–4 Reserved – Reserved. Must be written as a 0. Reads of this bit produce undefined data. 3–0 BCLT[11:8] 0h Byte Count Limit.
P R E L I M I N A R Y AMD 99 Am79C930 5 RXFOR 0 Receive FIFO Overrun. This bit is set whenever the RX FIFO expe- riences an overrun. This bit is cleared by resetting the RX FIFO. 4–1 RXFC[3:0] 0 Receive FIFO Count. These bits indicate the current count of the number of bytes contained in the RX FIFO.
AMD P R E L I M I N A R Y 100 Am79C930 TIR21: CRC32 Correct Byte Count MSB This register is the CRC32 Correct Byte Count MSB register. Bit Name Reset Value Description 7–4 Reserved – Reserved. Must be written as a 0. Reads of this bit produce undefined data.
P R E L I M I N A R Y AMD 101 Am79C930 TIR24: TCR Index Register This register is the TCR Index register. This register is used as an address into indirect TAI register space. The value in the TCR Index Register is used as an address that points at one of 64 registers that are accessed through the TCR Data Port.
AMD P R E L I M I N A R Y 102 Am79C930 2 ADDA 0 A/D D/A mode. ADDA is used with ENEXT (TCR25[6]), ENSAR (TCR25[5]), and UXA2DST (TCR25[7]) to determine the mode of operation of the A/D portion of the .
P R E L I M I N A R Y AMD 103 Am79C930 TIR28: RSSI Lower Limit This register is the RSSI Lower Limit register. The value in this register is compared against converted RSSI in- put values. When the converted RSSI value is equal to or exceeds the value in this register, then an indication will be sent to the clear channel assessment logic.
AMD P R E L I M I N A R Y 104 Am79C930 TIR31: TEST The TAI TEST register is a reserved location. Bit Name Reset Value Description 7 Reserved 0 These bit must be set to 0. Do not write to this register. 6–0 TC[6:0] 00h Test Command. The bits in this register are decoded to generate a test mode for the TAI.
P R E L I M I N A R Y AMD 105 Am79C930 Programmed SD[1:0] Start of Frame Detect Operation Register 00 Start of Frame Detect Off None 01 Search for 8 bit Start of Frame Delimiter TCR10 10 Search for 16.
AMD P R E L I M I N A R Y 106 Am79C930 TCR2: Clock Recovery This register is the Clock Recovery Configuration register. Bit Name Reset Value Description CONFIGURATION REGISTER INDEX: 02h 7 WNS2 0 Bit Stuffing Start. When WNS2 is set to a 1, then the bit stuffing op- eration on RX and TX frames will begin after the PHY header field has passed.
P R E L I M I N A R Y AMD 107 Am79C930 to delay the start of CRC8 and CRC32 and DC bias control calculation for both receive and transmit frames. The physical header field is assumed to begin after the Start of Frame Delimiter has been detected.
AMD P R E L I M I N A R Y 108 Am79C930 TCR6: TX Ramp Down Timing This register is the TX Ramp Down Timing register. This register determines the ramp down timing of the TX enable signals. CONFIGURATION REGISTER INDEX: 06h Bit Name Reset Value Description 7:4 TGAP3[3:0] 0h Transmit Timing Gap 3.
P R E L I M I N A R Y AMD 109 Am79C930 In addition, the USER5/IRQ4 pin may be used to produce interrupts to the 80188 embedded controller. This capability is controlled by the ENXCHBSY bit of TCR28 and the CHBSYCU bit of TIR5 and operates independently of the bits mentioned above.
AMD P R E L I M I N A R Y 110 Am79C930 has also been set to a 1 and the PCMCIA pin is set to 1. The value that is read from this bit represents the current value of the TXDATA pin of the Am79C930 device. A complete description of the control of the function of the TXDATA pin is described in the Multi-Function Pin section.
P R E L I M I N A R Y AMD 111 Am79C930 Delimiter may be used for start of frame recognition by appropriate settings of the SD[1:0] bits in the Network Configuration Register (TCR0).
AMD P R E L I M I N A R Y 112 Am79C930 TCR13: Pin Configuration A This register is the Pin Configuration A register. This register is used to set the state of various pins as outputs or as high impedance inputs. CONFIGURATION REGISTER INDEX: 0Dh Bit Name Reset Value Description 7 LNKEN 1 Link LED Enable.
P R E L I M I N A R Y AMD 113 Am79C930 value that is present on the LLOCKE pin, regardless of the setting of the PCMCIA pin. The control of the function of the LLOCKE/SA15 pin is described in the Multi-Function Pin section. 5 Reserved – Reserved. Must be written as a 0.
AMD P R E L I M I N A R Y 114 Am79C930 In addition to these bits, the USER6/IRQ5 pin may be used to pro- duce interrupts to the 80188 embedded controller. This capability is controlled by the ENXSDF bit of TCR28 and the SDFU bit of TIR5 and operates independently of the bits in the table above.
P R E L I M I N A R Y AMD 115 Am79C930 TCR17: Baud Detect Lower Limit This register is the Baud Detect Lower Limit register (TCR17). CONFIGURATION REGISTER INDEX: 11h Bit Name Reset Value Description 7–6 Reserved – Reserved. Must be written as a 0.
AMD P R E L I M I N A R Y 116 Am79C930 edge baud counter. This information should be used to appropri- ately program the Baud Detect Upper Limit register.
P R E L I M I N A R Y AMD 117 Am79C930 CONFIGURATION REGISTER INDEX: 15h Bit Name Reset Value Description 3–0 BDRN[3:0] 0h Baud Detect Ratio. These bits are used to set the ratio of good to bad baud detections which will be used as the minimum ratio to de- termine that a valid signal is present on the medium.
AMD P R E L I M I N A R Y 118 Am79C930 CONFIGURATION REGISTER INDEX: 18h Bit Name Reset Value Description 7:6 Reserved – Reserved. Must be written as a 0.
P R E L I M I N A R Y AMD 119 Am79C930 3–0 A2DT[3:0] 1010b A/D sampling Time[3:0]. The value in the A2DT[3:0] field deter- mines the duration of time required to convert the A/D input.
AMD P R E L I M I N A R Y 120 Am79C930 TCR26: Reserved This register is the TAI reserved location register. CONFIGURATION REGISTER INDEX: 1Ah Bit Name Reset Value Description 7–0 Reserved – Reserved. Must be written as a 0. Reads of this bit produce undefined data.
P R E L I M I N A R Y AMD 121 Am79C930 be high assert, such that when the TGAP2 counter expires, the TXMOD pin will be driven to a HIGH logic level. TCR28: Clear Channel Assessment Configuration This register is the Clear Channel Assessment Configuration register.
AMD P R E L I M I N A R Y 122 Am79C930 is set to a 0, the Baud Detect Count for Stop Diversity is not used in the stop diversity decision logic. 1 UBDCS 0 Use Baud Detect of Carrier Sense in CCA decision. When this bit is set to a 1, the Baud Detect Count for Carrier Sense becomes one input to the clear channel assessment logic.
P R E L I M I N A R Y AMD 123 Am79C930 then a 16-bit deep serial FIFO is inserted into the TX data path. This FIFO allows for some mismatch to be tolerated in the clock rates between the Am79C930 internal transmit clock and the external TXC clock that is connected to the TXC input.
AMD P R E L I M I N A R Y 124 Am79C930 PCMCIA CCR Registers and PCMCIA CIS Space Two bytes of attribute memory space have been used by the Am79C930 device for storage of two card configuration registers. These two registers are found at attribute memory locations 800h and 802h.
P R E L I M I N A R Y AMD 125 Am79C930 When written with a 1, the PWRDWN bit generates an interrupt to the 80188, requesting that the 80188 core place the Am79C930 de- vice into the power down state. The interrupt is signaled in MIR0, bit 5. If written with a 0 while in power down mode, power down mode is exited.
AMD P R E L I M I N A R Y 126 Am79C930 ABSOLUTE MAXIMUM RATINGS Storage Temperature: –65 to +150 ° C . . . . . . . . . . . . Ambient Temperature Under Bias: –65 to +125 ° C . . . Supply Voltage to AV SS or DV SS (AV DD , DV DD ): –0.3 to +6 V .
P R E L I M I N A R Y AMD 127 Am79C930 DC CHARACTERISTICS (continued) 5.0 V Am79C930 DC Characteristics Parameter Symbol Parameter Description Test Conditions Min Max Units I DDPD2 Power Supply Current Power Down mode 40 mA CLKIN = internally cutoff, PMX1 = 32.
AMD P R E L I M I N A R Y 128 Am79C930 ABSOLUTE MAXIMUM RATINGS Storage Temperature: –65 to +150 ° C . . . . . . . . . . . . Ambient Temperature Under Bias: –65 to +125 ° C . . . Supply Voltage to AV SS or DV SS (AV DD , DV DD ): –0.3 to +6 V .
P R E L I M I N A R Y AMD 129 Am79C930 DC CHARACTERISTICS (continued) 3.3 V Am79C930 DC Characteristics Parameter Symbol Parameter Description Test Conditions Min Max Units I DDPD2 Power Supply Current Power Down mode 5 mA CLKIN = internally cutoff, PMX1 = 32.
AMD P R E L I M I N A R Y 130 Am79C930 ABSOLUTE MAXIMUM RATINGS Storage Temperature: –65 to +150 ° C . . . . . . . . . . . . Ambient Temperature Under Bias: –65 to +125 ° C . . . Supply Voltage to AV SS or DV SS (AV DD , DV DD ): –0.3 to +6 V .
P R E L I M I N A R Y AMD 131 Am79C930 AC CHARACTERISTICS 5.0 AND 3.3 V PCMCIA INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature: –65 to +150*C . . . . . . . . . . . . Ambient Temperature Under Bias: –65 to +125*C . . . Supply Voltage to AV SS or DV SS (AV DD , DV DD ): –0.
AMD P R E L I M I N A R Y 132 Am79C930 PCMCIA MEMORY WRITE ACCESS Parameter Symbol Parameter Description Test Conditions Min Max Unit t AVWL Address setup to WE ↓ 20 ns t AVWH Address setup to WE .
P R E L I M I N A R Y AMD 133 Am79C930 PCMCIA I/O READ ACCESS Parameter Symbol Parameter Description Test Conditions Min Max Unit t AVIGL Address setup to IORD ↓ 70 ns t IGHAX Address hold from IORD.
AMD P R E L I M I N A R Y 134 Am79C930 PCMCIA I/O WRITE ACCESS Parameter Symbol Parameter Description Test Conditions Min Max Unit t AVIWL Address setup to IOWR ↓ 70 ns t IWHAX Address hold from IOW.
P R E L I M I N A R Y AMD 135 Am79C930 AC CHARACTERISTICS 5.0 AND 3.3 V ISA INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature: –65 to +150 ° C . . . . . . . . . . . . Ambient Temperature Under Bias: –65 to +125 ° C . . . Supply Voltage to AV SS or DV SS (AV DD , DV DD ): –0.
AMD P R E L I M I N A R Y 136 Am79C930 ISA ACCESS Parameter Symbol Parameter Description Test Conditions Min Max Unit t i 1 LA[23:17] valid setup to BALE ↓ 60 ns t i 2 BALE ↑ to BALE ↓ pulse wid.
P R E L I M I N A R Y AMD 137 Am79C930 AC CHARACTERISTICS 5.0 V MEMORY BUS INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature: –65 to +150 ° C . . . . . . . . . . . . Ambient Temperature Under Bias: –65 to +125 ° C . . . Supply Voltage to AV SS or DV SS (AV DD , DV DD ): –0.
AMD P R E L I M I N A R Y 138 Am79C930 MEMORY BUS WRITE ACCESS Parameter Symbol Parameter Description Test Conditions Min Max Unit t m AD MA[16:0] valid from CLKIN ↓ 26 0 n s t m CD CE active delay .
P R E L I M I N A R Y AMD 139 Am79C930 AC CHARACTERISTICS 3.3 V MEMORY BUS INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature: –65 to +150 ° C . . . . . . . . . . . . Ambient Temperature Under Bias: –65 to +125 ° C . . . Supply Voltage to AV SS or DV SS (AV DD , DV DD ): –0.
AMD P R E L I M I N A R Y 140 Am79C930 MEMORY BUS WRITE ACCESS Parameter Symbol Parameter Description Test Conditions Min Max Unit t m AD MA[16:0] valid from CLKIN ↓ 2 100 ns t m CD CE active delay .
P R E L I M I N A R Y AMD 141 Am79C930 AC CHARACTERISTICS 5.0 V TAI INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature: –65 to +150 ° C . . . . . . . . . . . . Ambient Temperature Under Bias: –65 to +125 ° C . . . Supply Voltage to AV SS or DV SS (AV DD , DV DD ): –0.
AMD P R E L I M I N A R Y 142 Am79C930 5.0 V TAI INTERFACE AC CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Max Unit T CLKIN CLKIN Period MIR9[7]=1 25 ns T CLIN CLKIN Low .
P R E L I M I N A R Y AMD 143 Am79C930 Notes: 1. Only applicable when TXC has been configured as an INPUT. 2. Only applicable when TXC has been configured as an OUTPUT. 3. MIN value not tested. 4. Parameter calculated from other parameters. 5. Clock period must correlate to data rate as specified in DR bits of TCR30.
AMD P R E L I M I N A R Y 144 Am79C930 AC CHARACTERISTICS 3.3 V TAI INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature: –65 to +150 ° C . . . . . . . . . . . . Ambient Temperature Under Bias: –65 to +125 ° C . . . Supply Voltage to AV SS or DV SS (AV DD , DV DD ): –0.
P R E L I M I N A R Y AMD 145 Am79C930 3.3 V TAI INTERFACE AC CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Max Unit t CLKIN CLKIN Period 50 ns t CLIN CLKIN Low time 22 ns.
AMD P R E L I M I N A R Y 146 Am79C930 AC CHARACTERISTICS 5.0 AND 3.3 V USER PROGRAMMABLE PINS ABSOLUTE MAXIMUM RATINGS Storage Temperature: –65 to +150 ° C . . . . . . . . . . . . Ambient Temperature Under Bias: –65 to +125 ° C . . . Supply Voltage to AV SS or DV SS (AV DD , DV DD ): –0.
P R E L I M I N A R Y AMD 147 Am79C930 AC CHARACTERISTICS 5.0 AND 3.3 V IEEE 1149.1 INTERFACE ABSOLUTE MAXIMUM RATINGS Storage Temperature: –65 to +150 ° C . . . . . . . . . . . . Ambient Temperature Under Bias: –65 to +125 ° C . . . Supply Voltage to AV SS or DV SS (AV DD , DV DD ): –0.
AMD P R E L I M I N A R Y 148 Am79C930 TIMING WAVEFORMS PCMCIA Bus Interface Waveforms A n , REG CE OE D o (Dout) t A VQV t ELQV t GLQV t GLQNZ t GHAX t GHQZ WE (high) W AIT t ELGL t AVG L t GHEH t GL WTV t WTL WTH t QVWTH 20138B-10 Figure 4.
P R E L I M I N A R Y AMD 149 Am79C930 20138B-12 A n REG IORD D o (Dout) W AIT t A VIGL CE t IGHRGH t RGLIGL t IGHAX t ELIGL t IGLIGH t IGL WTL t WTL WTH t IGHEH t WTHQV t IGHQX t IGLQV INP ACK t IGLIAL t IGHIAH t IGHQZ t IGQNZ Figure 6.
AMD P R E L I M I N A R Y 150 Am79C930 ISA Bus Interface Waveforms 20138B-14 ** CMD = one of: MEMR , MEMW , IOR , IOW LA n CMD** SD out (read) t i 1 t i 8 t i 34 t i 3 t i 14 IOCHRD Y t i 7 t i 4 t i .
P R E L I M I N A R Y AMD 151 Am79C930 Memory Bus Interface Waveforms 20138B-15 MA n FCE, SCE, XCE MOE MD i (Din) t m AA t m OE t m AD MWE (high) CLKIN t m RDSC t m ACS t m H data sampled at this point valid t m RI t m RDHC t m AD t m CD t m OD t m OLZ t m HZ CLKOUT (internal) t m CD t m OD t m AH t m CH Figure 9.
AMD P R E L I M I N A R Y 152 Am79C930 CLOCK WAVEFORMS 20138B-17 CLKIN 0.8 V 2.0 V t CLIN t INHL t CLKIN t INLH t CHIN 0.8 V TXC 0.8 V 2.0 V t CL TX t TXHL t TXC t TXLH t CHTX 0.
P R E L I M I N A R Y AMD 153 Am79C930 TAI WAVEFORMS 20138B-18 **ICO = Internally Controlled Output ICO* RCO** RCO** t n 1 CLKIN CLKOUT (internal) t n 2 RCO** t n 3 t n 4 Figure 12. TAI Timing Diagram 20138B-19 RXD t RXDS RXC t RXDS TXD t TXDD TXC (input) TXD t TXDV TXC (output) t TXDS t TXDH Figure 13.
AMD P R E L I M I N A R Y 154 Am79C930 PROGRAMMABLE INTERFACE WAVEFORMS 20138B-20 **RCO = Register Controlled Output W AIT or IOCHRD Y RCO** (data change) CLKOUT (internal) RCO** (drive change) t u 1 t u 2 RCO** (drive change) t u 3 CLKIN Figure 14.
P R E L I M I N A R Y AMD 155 Am79C930 IEEE 1149.1 INTERFACE WAVEFORMS 20138B-21 TCK TDI, TMS TDO t 31 Output Signals t 25 t 30 t 32 t 34 t 37 t 36 Input Signals t 35 Figure 15.
AMD P R E L I M I N A R Y 156 Am79C930 AC TEST REFERENCE WAVEFORMS 5.0 V PCMCIA AC Test Reference Waveform This waveform indicates the AC testing method em- ployed for all signals that are PCMCIA bus signals when the PCMCIA power supply pins are set to 5.
P R E L I M I N A R Y AMD 157 Am79C930 5.0 V NON-PCMCIA AC TEST REFERENCE WAVEFORM This waveform indicates the AC testing method em- ployed for all signals that are not PCMCIA bus signals when the appropriate power supply pins are set to 5.0 V (i.e., VDDT, VDDU1, VDDU2, VDDM pins = 5.
AMD P R E L I M I N A R Y 158 Am79C930 PHYSICAL DIMENSIONS PQT144 144-Pin Thin Quad Flat Pack (measured in millimeters) 1.00 REF. 1.60 MAX 11 ° – 13 ° 11 ° – 13 ° 0.50 BSC 144 1 1.35 1.45 21.80 22.20 19.80 20.20 21.80 22.20 19.80 20.
A-1 Am79C930 Typical Am79C930 System Application APPENDIX A Host Computer 128K Flash 128K SRAM Am79C930 Radio or IR Transceiver PCMCIA or ISA PnP Interface 20183A-1 Figure .
AMD A-2 Am79C930 1. Command and status communication 2. Data buffer areas 3. Am79C930 80188 core variable space After performing these functions, the device driver will enable the 80188 core by writing to a register to release the RESET of the Am79C930 80188 core.
T rademarks Copyright © 1998 Adv anced Micro De vices, Inc. All rights reser ved. AMD , the AMD logo, and combinations thereof are trademarks of Adv anced Micro De vices, Inc.
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